mv643xx_eth.c 71 KB

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  1. /*
  2. * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
  3. * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
  4. *
  5. * Based on the 64360 driver from:
  6. * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
  7. * Rabeeh Khoury <rabeeh@marvell.com>
  8. *
  9. * Copyright (C) 2003 PMC-Sierra, Inc.,
  10. * written by Manish Lachwani
  11. *
  12. * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
  13. *
  14. * Copyright (C) 2004-2006 MontaVista Software, Inc.
  15. * Dale Farnsworth <dale@farnsworth.org>
  16. *
  17. * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
  18. * <sjhill@realitydiluted.com>
  19. *
  20. * Copyright (C) 2007-2008 Marvell Semiconductor
  21. * Lennert Buytenhek <buytenh@marvell.com>
  22. *
  23. * This program is free software; you can redistribute it and/or
  24. * modify it under the terms of the GNU General Public License
  25. * as published by the Free Software Foundation; either version 2
  26. * of the License, or (at your option) any later version.
  27. *
  28. * This program is distributed in the hope that it will be useful,
  29. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  31. * GNU General Public License for more details.
  32. *
  33. * You should have received a copy of the GNU General Public License
  34. * along with this program; if not, write to the Free Software
  35. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  36. */
  37. #include <linux/init.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/in.h>
  40. #include <linux/ip.h>
  41. #include <linux/tcp.h>
  42. #include <linux/udp.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/delay.h>
  45. #include <linux/ethtool.h>
  46. #include <linux/platform_device.h>
  47. #include <linux/module.h>
  48. #include <linux/kernel.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/workqueue.h>
  51. #include <linux/phy.h>
  52. #include <linux/mv643xx_eth.h>
  53. #include <linux/io.h>
  54. #include <linux/types.h>
  55. #include <linux/inet_lro.h>
  56. #include <linux/slab.h>
  57. #include <asm/system.h>
  58. static char mv643xx_eth_driver_name[] = "mv643xx_eth";
  59. static char mv643xx_eth_driver_version[] = "1.4";
  60. /*
  61. * Registers shared between all ports.
  62. */
  63. #define PHY_ADDR 0x0000
  64. #define SMI_REG 0x0004
  65. #define SMI_BUSY 0x10000000
  66. #define SMI_READ_VALID 0x08000000
  67. #define SMI_OPCODE_READ 0x04000000
  68. #define SMI_OPCODE_WRITE 0x00000000
  69. #define ERR_INT_CAUSE 0x0080
  70. #define ERR_INT_SMI_DONE 0x00000010
  71. #define ERR_INT_MASK 0x0084
  72. #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
  73. #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
  74. #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
  75. #define WINDOW_BAR_ENABLE 0x0290
  76. #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
  77. /*
  78. * Main per-port registers. These live at offset 0x0400 for
  79. * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
  80. */
  81. #define PORT_CONFIG 0x0000
  82. #define UNICAST_PROMISCUOUS_MODE 0x00000001
  83. #define PORT_CONFIG_EXT 0x0004
  84. #define MAC_ADDR_LOW 0x0014
  85. #define MAC_ADDR_HIGH 0x0018
  86. #define SDMA_CONFIG 0x001c
  87. #define TX_BURST_SIZE_16_64BIT 0x01000000
  88. #define TX_BURST_SIZE_4_64BIT 0x00800000
  89. #define BLM_TX_NO_SWAP 0x00000020
  90. #define BLM_RX_NO_SWAP 0x00000010
  91. #define RX_BURST_SIZE_16_64BIT 0x00000008
  92. #define RX_BURST_SIZE_4_64BIT 0x00000004
  93. #define PORT_SERIAL_CONTROL 0x003c
  94. #define SET_MII_SPEED_TO_100 0x01000000
  95. #define SET_GMII_SPEED_TO_1000 0x00800000
  96. #define SET_FULL_DUPLEX_MODE 0x00200000
  97. #define MAX_RX_PACKET_9700BYTE 0x000a0000
  98. #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
  99. #define DO_NOT_FORCE_LINK_FAIL 0x00000400
  100. #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
  101. #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
  102. #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
  103. #define FORCE_LINK_PASS 0x00000002
  104. #define SERIAL_PORT_ENABLE 0x00000001
  105. #define PORT_STATUS 0x0044
  106. #define TX_FIFO_EMPTY 0x00000400
  107. #define TX_IN_PROGRESS 0x00000080
  108. #define PORT_SPEED_MASK 0x00000030
  109. #define PORT_SPEED_1000 0x00000010
  110. #define PORT_SPEED_100 0x00000020
  111. #define PORT_SPEED_10 0x00000000
  112. #define FLOW_CONTROL_ENABLED 0x00000008
  113. #define FULL_DUPLEX 0x00000004
  114. #define LINK_UP 0x00000002
  115. #define TXQ_COMMAND 0x0048
  116. #define TXQ_FIX_PRIO_CONF 0x004c
  117. #define TX_BW_RATE 0x0050
  118. #define TX_BW_MTU 0x0058
  119. #define TX_BW_BURST 0x005c
  120. #define INT_CAUSE 0x0060
  121. #define INT_TX_END 0x07f80000
  122. #define INT_TX_END_0 0x00080000
  123. #define INT_RX 0x000003fc
  124. #define INT_RX_0 0x00000004
  125. #define INT_EXT 0x00000002
  126. #define INT_CAUSE_EXT 0x0064
  127. #define INT_EXT_LINK_PHY 0x00110000
  128. #define INT_EXT_TX 0x000000ff
  129. #define INT_MASK 0x0068
  130. #define INT_MASK_EXT 0x006c
  131. #define TX_FIFO_URGENT_THRESHOLD 0x0074
  132. #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
  133. #define TX_BW_RATE_MOVED 0x00e0
  134. #define TX_BW_MTU_MOVED 0x00e8
  135. #define TX_BW_BURST_MOVED 0x00ec
  136. #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
  137. #define RXQ_COMMAND 0x0280
  138. #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
  139. #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
  140. #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
  141. #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
  142. /*
  143. * Misc per-port registers.
  144. */
  145. #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
  146. #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
  147. #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
  148. #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
  149. /*
  150. * SDMA configuration register default value.
  151. */
  152. #if defined(__BIG_ENDIAN)
  153. #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
  154. (RX_BURST_SIZE_4_64BIT | \
  155. TX_BURST_SIZE_4_64BIT)
  156. #elif defined(__LITTLE_ENDIAN)
  157. #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
  158. (RX_BURST_SIZE_4_64BIT | \
  159. BLM_RX_NO_SWAP | \
  160. BLM_TX_NO_SWAP | \
  161. TX_BURST_SIZE_4_64BIT)
  162. #else
  163. #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
  164. #endif
  165. /*
  166. * Misc definitions.
  167. */
  168. #define DEFAULT_RX_QUEUE_SIZE 128
  169. #define DEFAULT_TX_QUEUE_SIZE 256
  170. #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
  171. /*
  172. * RX/TX descriptors.
  173. */
  174. #if defined(__BIG_ENDIAN)
  175. struct rx_desc {
  176. u16 byte_cnt; /* Descriptor buffer byte count */
  177. u16 buf_size; /* Buffer size */
  178. u32 cmd_sts; /* Descriptor command status */
  179. u32 next_desc_ptr; /* Next descriptor pointer */
  180. u32 buf_ptr; /* Descriptor buffer pointer */
  181. };
  182. struct tx_desc {
  183. u16 byte_cnt; /* buffer byte count */
  184. u16 l4i_chk; /* CPU provided TCP checksum */
  185. u32 cmd_sts; /* Command/status field */
  186. u32 next_desc_ptr; /* Pointer to next descriptor */
  187. u32 buf_ptr; /* pointer to buffer for this descriptor*/
  188. };
  189. #elif defined(__LITTLE_ENDIAN)
  190. struct rx_desc {
  191. u32 cmd_sts; /* Descriptor command status */
  192. u16 buf_size; /* Buffer size */
  193. u16 byte_cnt; /* Descriptor buffer byte count */
  194. u32 buf_ptr; /* Descriptor buffer pointer */
  195. u32 next_desc_ptr; /* Next descriptor pointer */
  196. };
  197. struct tx_desc {
  198. u32 cmd_sts; /* Command/status field */
  199. u16 l4i_chk; /* CPU provided TCP checksum */
  200. u16 byte_cnt; /* buffer byte count */
  201. u32 buf_ptr; /* pointer to buffer for this descriptor*/
  202. u32 next_desc_ptr; /* Pointer to next descriptor */
  203. };
  204. #else
  205. #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
  206. #endif
  207. /* RX & TX descriptor command */
  208. #define BUFFER_OWNED_BY_DMA 0x80000000
  209. /* RX & TX descriptor status */
  210. #define ERROR_SUMMARY 0x00000001
  211. /* RX descriptor status */
  212. #define LAYER_4_CHECKSUM_OK 0x40000000
  213. #define RX_ENABLE_INTERRUPT 0x20000000
  214. #define RX_FIRST_DESC 0x08000000
  215. #define RX_LAST_DESC 0x04000000
  216. #define RX_IP_HDR_OK 0x02000000
  217. #define RX_PKT_IS_IPV4 0x01000000
  218. #define RX_PKT_IS_ETHERNETV2 0x00800000
  219. #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
  220. #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
  221. #define RX_PKT_IS_VLAN_TAGGED 0x00080000
  222. /* TX descriptor command */
  223. #define TX_ENABLE_INTERRUPT 0x00800000
  224. #define GEN_CRC 0x00400000
  225. #define TX_FIRST_DESC 0x00200000
  226. #define TX_LAST_DESC 0x00100000
  227. #define ZERO_PADDING 0x00080000
  228. #define GEN_IP_V4_CHECKSUM 0x00040000
  229. #define GEN_TCP_UDP_CHECKSUM 0x00020000
  230. #define UDP_FRAME 0x00010000
  231. #define MAC_HDR_EXTRA_4_BYTES 0x00008000
  232. #define MAC_HDR_EXTRA_8_BYTES 0x00000200
  233. #define TX_IHL_SHIFT 11
  234. /* global *******************************************************************/
  235. struct mv643xx_eth_shared_private {
  236. /*
  237. * Ethernet controller base address.
  238. */
  239. void __iomem *base;
  240. /*
  241. * Points at the right SMI instance to use.
  242. */
  243. struct mv643xx_eth_shared_private *smi;
  244. /*
  245. * Provides access to local SMI interface.
  246. */
  247. struct mii_bus *smi_bus;
  248. /*
  249. * If we have access to the error interrupt pin (which is
  250. * somewhat misnamed as it not only reflects internal errors
  251. * but also reflects SMI completion), use that to wait for
  252. * SMI access completion instead of polling the SMI busy bit.
  253. */
  254. int err_interrupt;
  255. wait_queue_head_t smi_busy_wait;
  256. /*
  257. * Per-port MBUS window access register value.
  258. */
  259. u32 win_protect;
  260. /*
  261. * Hardware-specific parameters.
  262. */
  263. unsigned int t_clk;
  264. int extended_rx_coal_limit;
  265. int tx_bw_control;
  266. int tx_csum_limit;
  267. };
  268. #define TX_BW_CONTROL_ABSENT 0
  269. #define TX_BW_CONTROL_OLD_LAYOUT 1
  270. #define TX_BW_CONTROL_NEW_LAYOUT 2
  271. static int mv643xx_eth_open(struct net_device *dev);
  272. static int mv643xx_eth_stop(struct net_device *dev);
  273. /* per-port *****************************************************************/
  274. struct mib_counters {
  275. u64 good_octets_received;
  276. u32 bad_octets_received;
  277. u32 internal_mac_transmit_err;
  278. u32 good_frames_received;
  279. u32 bad_frames_received;
  280. u32 broadcast_frames_received;
  281. u32 multicast_frames_received;
  282. u32 frames_64_octets;
  283. u32 frames_65_to_127_octets;
  284. u32 frames_128_to_255_octets;
  285. u32 frames_256_to_511_octets;
  286. u32 frames_512_to_1023_octets;
  287. u32 frames_1024_to_max_octets;
  288. u64 good_octets_sent;
  289. u32 good_frames_sent;
  290. u32 excessive_collision;
  291. u32 multicast_frames_sent;
  292. u32 broadcast_frames_sent;
  293. u32 unrec_mac_control_received;
  294. u32 fc_sent;
  295. u32 good_fc_received;
  296. u32 bad_fc_received;
  297. u32 undersize_received;
  298. u32 fragments_received;
  299. u32 oversize_received;
  300. u32 jabber_received;
  301. u32 mac_receive_error;
  302. u32 bad_crc_event;
  303. u32 collision;
  304. u32 late_collision;
  305. };
  306. struct lro_counters {
  307. u32 lro_aggregated;
  308. u32 lro_flushed;
  309. u32 lro_no_desc;
  310. };
  311. struct rx_queue {
  312. int index;
  313. int rx_ring_size;
  314. int rx_desc_count;
  315. int rx_curr_desc;
  316. int rx_used_desc;
  317. struct rx_desc *rx_desc_area;
  318. dma_addr_t rx_desc_dma;
  319. int rx_desc_area_size;
  320. struct sk_buff **rx_skb;
  321. struct net_lro_mgr lro_mgr;
  322. struct net_lro_desc lro_arr[8];
  323. };
  324. struct tx_queue {
  325. int index;
  326. int tx_ring_size;
  327. int tx_desc_count;
  328. int tx_curr_desc;
  329. int tx_used_desc;
  330. struct tx_desc *tx_desc_area;
  331. dma_addr_t tx_desc_dma;
  332. int tx_desc_area_size;
  333. struct sk_buff_head tx_skb;
  334. unsigned long tx_packets;
  335. unsigned long tx_bytes;
  336. unsigned long tx_dropped;
  337. };
  338. struct mv643xx_eth_private {
  339. struct mv643xx_eth_shared_private *shared;
  340. void __iomem *base;
  341. int port_num;
  342. struct net_device *dev;
  343. struct phy_device *phy;
  344. struct timer_list mib_counters_timer;
  345. spinlock_t mib_counters_lock;
  346. struct mib_counters mib_counters;
  347. struct lro_counters lro_counters;
  348. struct work_struct tx_timeout_task;
  349. struct napi_struct napi;
  350. u32 int_mask;
  351. u8 oom;
  352. u8 work_link;
  353. u8 work_tx;
  354. u8 work_tx_end;
  355. u8 work_rx;
  356. u8 work_rx_refill;
  357. int skb_size;
  358. struct sk_buff_head rx_recycle;
  359. /*
  360. * RX state.
  361. */
  362. int rx_ring_size;
  363. unsigned long rx_desc_sram_addr;
  364. int rx_desc_sram_size;
  365. int rxq_count;
  366. struct timer_list rx_oom;
  367. struct rx_queue rxq[8];
  368. /*
  369. * TX state.
  370. */
  371. int tx_ring_size;
  372. unsigned long tx_desc_sram_addr;
  373. int tx_desc_sram_size;
  374. int txq_count;
  375. struct tx_queue txq[8];
  376. };
  377. /* port register accessors **************************************************/
  378. static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
  379. {
  380. return readl(mp->shared->base + offset);
  381. }
  382. static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
  383. {
  384. return readl(mp->base + offset);
  385. }
  386. static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
  387. {
  388. writel(data, mp->shared->base + offset);
  389. }
  390. static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
  391. {
  392. writel(data, mp->base + offset);
  393. }
  394. /* rxq/txq helper functions *************************************************/
  395. static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
  396. {
  397. return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
  398. }
  399. static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
  400. {
  401. return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
  402. }
  403. static void rxq_enable(struct rx_queue *rxq)
  404. {
  405. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  406. wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
  407. }
  408. static void rxq_disable(struct rx_queue *rxq)
  409. {
  410. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  411. u8 mask = 1 << rxq->index;
  412. wrlp(mp, RXQ_COMMAND, mask << 8);
  413. while (rdlp(mp, RXQ_COMMAND) & mask)
  414. udelay(10);
  415. }
  416. static void txq_reset_hw_ptr(struct tx_queue *txq)
  417. {
  418. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  419. u32 addr;
  420. addr = (u32)txq->tx_desc_dma;
  421. addr += txq->tx_curr_desc * sizeof(struct tx_desc);
  422. wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
  423. }
  424. static void txq_enable(struct tx_queue *txq)
  425. {
  426. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  427. wrlp(mp, TXQ_COMMAND, 1 << txq->index);
  428. }
  429. static void txq_disable(struct tx_queue *txq)
  430. {
  431. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  432. u8 mask = 1 << txq->index;
  433. wrlp(mp, TXQ_COMMAND, mask << 8);
  434. while (rdlp(mp, TXQ_COMMAND) & mask)
  435. udelay(10);
  436. }
  437. static void txq_maybe_wake(struct tx_queue *txq)
  438. {
  439. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  440. struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
  441. if (netif_tx_queue_stopped(nq)) {
  442. __netif_tx_lock(nq, smp_processor_id());
  443. if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
  444. netif_tx_wake_queue(nq);
  445. __netif_tx_unlock(nq);
  446. }
  447. }
  448. /* rx napi ******************************************************************/
  449. static int
  450. mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
  451. u64 *hdr_flags, void *priv)
  452. {
  453. unsigned long cmd_sts = (unsigned long)priv;
  454. /*
  455. * Make sure that this packet is Ethernet II, is not VLAN
  456. * tagged, is IPv4, has a valid IP header, and is TCP.
  457. */
  458. if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
  459. RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
  460. RX_PKT_IS_VLAN_TAGGED)) !=
  461. (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
  462. RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
  463. return -1;
  464. skb_reset_network_header(skb);
  465. skb_set_transport_header(skb, ip_hdrlen(skb));
  466. *iphdr = ip_hdr(skb);
  467. *tcph = tcp_hdr(skb);
  468. *hdr_flags = LRO_IPV4 | LRO_TCP;
  469. return 0;
  470. }
  471. static int rxq_process(struct rx_queue *rxq, int budget)
  472. {
  473. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  474. struct net_device_stats *stats = &mp->dev->stats;
  475. int lro_flush_needed;
  476. int rx;
  477. lro_flush_needed = 0;
  478. rx = 0;
  479. while (rx < budget && rxq->rx_desc_count) {
  480. struct rx_desc *rx_desc;
  481. unsigned int cmd_sts;
  482. struct sk_buff *skb;
  483. u16 byte_cnt;
  484. rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
  485. cmd_sts = rx_desc->cmd_sts;
  486. if (cmd_sts & BUFFER_OWNED_BY_DMA)
  487. break;
  488. rmb();
  489. skb = rxq->rx_skb[rxq->rx_curr_desc];
  490. rxq->rx_skb[rxq->rx_curr_desc] = NULL;
  491. rxq->rx_curr_desc++;
  492. if (rxq->rx_curr_desc == rxq->rx_ring_size)
  493. rxq->rx_curr_desc = 0;
  494. dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
  495. rx_desc->buf_size, DMA_FROM_DEVICE);
  496. rxq->rx_desc_count--;
  497. rx++;
  498. mp->work_rx_refill |= 1 << rxq->index;
  499. byte_cnt = rx_desc->byte_cnt;
  500. /*
  501. * Update statistics.
  502. *
  503. * Note that the descriptor byte count includes 2 dummy
  504. * bytes automatically inserted by the hardware at the
  505. * start of the packet (which we don't count), and a 4
  506. * byte CRC at the end of the packet (which we do count).
  507. */
  508. stats->rx_packets++;
  509. stats->rx_bytes += byte_cnt - 2;
  510. /*
  511. * In case we received a packet without first / last bits
  512. * on, or the error summary bit is set, the packet needs
  513. * to be dropped.
  514. */
  515. if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
  516. != (RX_FIRST_DESC | RX_LAST_DESC))
  517. goto err;
  518. /*
  519. * The -4 is for the CRC in the trailer of the
  520. * received packet
  521. */
  522. skb_put(skb, byte_cnt - 2 - 4);
  523. if (cmd_sts & LAYER_4_CHECKSUM_OK)
  524. skb->ip_summed = CHECKSUM_UNNECESSARY;
  525. skb->protocol = eth_type_trans(skb, mp->dev);
  526. if (skb->dev->features & NETIF_F_LRO &&
  527. skb->ip_summed == CHECKSUM_UNNECESSARY) {
  528. lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
  529. lro_flush_needed = 1;
  530. } else
  531. netif_receive_skb(skb);
  532. continue;
  533. err:
  534. stats->rx_dropped++;
  535. if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
  536. (RX_FIRST_DESC | RX_LAST_DESC)) {
  537. if (net_ratelimit())
  538. dev_printk(KERN_ERR, &mp->dev->dev,
  539. "received packet spanning "
  540. "multiple descriptors\n");
  541. }
  542. if (cmd_sts & ERROR_SUMMARY)
  543. stats->rx_errors++;
  544. dev_kfree_skb(skb);
  545. }
  546. if (lro_flush_needed)
  547. lro_flush_all(&rxq->lro_mgr);
  548. if (rx < budget)
  549. mp->work_rx &= ~(1 << rxq->index);
  550. return rx;
  551. }
  552. static int rxq_refill(struct rx_queue *rxq, int budget)
  553. {
  554. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  555. int refilled;
  556. refilled = 0;
  557. while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
  558. struct sk_buff *skb;
  559. int rx;
  560. struct rx_desc *rx_desc;
  561. int size;
  562. skb = __skb_dequeue(&mp->rx_recycle);
  563. if (skb == NULL)
  564. skb = dev_alloc_skb(mp->skb_size);
  565. if (skb == NULL) {
  566. mp->oom = 1;
  567. goto oom;
  568. }
  569. if (SKB_DMA_REALIGN)
  570. skb_reserve(skb, SKB_DMA_REALIGN);
  571. refilled++;
  572. rxq->rx_desc_count++;
  573. rx = rxq->rx_used_desc++;
  574. if (rxq->rx_used_desc == rxq->rx_ring_size)
  575. rxq->rx_used_desc = 0;
  576. rx_desc = rxq->rx_desc_area + rx;
  577. size = skb->end - skb->data;
  578. rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
  579. skb->data, size,
  580. DMA_FROM_DEVICE);
  581. rx_desc->buf_size = size;
  582. rxq->rx_skb[rx] = skb;
  583. wmb();
  584. rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
  585. wmb();
  586. /*
  587. * The hardware automatically prepends 2 bytes of
  588. * dummy data to each received packet, so that the
  589. * IP header ends up 16-byte aligned.
  590. */
  591. skb_reserve(skb, 2);
  592. }
  593. if (refilled < budget)
  594. mp->work_rx_refill &= ~(1 << rxq->index);
  595. oom:
  596. return refilled;
  597. }
  598. /* tx ***********************************************************************/
  599. static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
  600. {
  601. int frag;
  602. for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
  603. skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
  604. if (fragp->size <= 8 && fragp->page_offset & 7)
  605. return 1;
  606. }
  607. return 0;
  608. }
  609. static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
  610. {
  611. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  612. int nr_frags = skb_shinfo(skb)->nr_frags;
  613. int frag;
  614. for (frag = 0; frag < nr_frags; frag++) {
  615. skb_frag_t *this_frag;
  616. int tx_index;
  617. struct tx_desc *desc;
  618. this_frag = &skb_shinfo(skb)->frags[frag];
  619. tx_index = txq->tx_curr_desc++;
  620. if (txq->tx_curr_desc == txq->tx_ring_size)
  621. txq->tx_curr_desc = 0;
  622. desc = &txq->tx_desc_area[tx_index];
  623. /*
  624. * The last fragment will generate an interrupt
  625. * which will free the skb on TX completion.
  626. */
  627. if (frag == nr_frags - 1) {
  628. desc->cmd_sts = BUFFER_OWNED_BY_DMA |
  629. ZERO_PADDING | TX_LAST_DESC |
  630. TX_ENABLE_INTERRUPT;
  631. } else {
  632. desc->cmd_sts = BUFFER_OWNED_BY_DMA;
  633. }
  634. desc->l4i_chk = 0;
  635. desc->byte_cnt = this_frag->size;
  636. desc->buf_ptr = dma_map_page(mp->dev->dev.parent,
  637. this_frag->page,
  638. this_frag->page_offset,
  639. this_frag->size, DMA_TO_DEVICE);
  640. }
  641. }
  642. static inline __be16 sum16_as_be(__sum16 sum)
  643. {
  644. return (__force __be16)sum;
  645. }
  646. static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
  647. {
  648. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  649. int nr_frags = skb_shinfo(skb)->nr_frags;
  650. int tx_index;
  651. struct tx_desc *desc;
  652. u32 cmd_sts;
  653. u16 l4i_chk;
  654. int length;
  655. cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
  656. l4i_chk = 0;
  657. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  658. int hdr_len;
  659. int tag_bytes;
  660. BUG_ON(skb->protocol != htons(ETH_P_IP) &&
  661. skb->protocol != htons(ETH_P_8021Q));
  662. hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
  663. tag_bytes = hdr_len - ETH_HLEN;
  664. if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
  665. unlikely(tag_bytes & ~12)) {
  666. if (skb_checksum_help(skb) == 0)
  667. goto no_csum;
  668. kfree_skb(skb);
  669. return 1;
  670. }
  671. if (tag_bytes & 4)
  672. cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
  673. if (tag_bytes & 8)
  674. cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
  675. cmd_sts |= GEN_TCP_UDP_CHECKSUM |
  676. GEN_IP_V4_CHECKSUM |
  677. ip_hdr(skb)->ihl << TX_IHL_SHIFT;
  678. switch (ip_hdr(skb)->protocol) {
  679. case IPPROTO_UDP:
  680. cmd_sts |= UDP_FRAME;
  681. l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
  682. break;
  683. case IPPROTO_TCP:
  684. l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
  685. break;
  686. default:
  687. BUG();
  688. }
  689. } else {
  690. no_csum:
  691. /* Errata BTS #50, IHL must be 5 if no HW checksum */
  692. cmd_sts |= 5 << TX_IHL_SHIFT;
  693. }
  694. tx_index = txq->tx_curr_desc++;
  695. if (txq->tx_curr_desc == txq->tx_ring_size)
  696. txq->tx_curr_desc = 0;
  697. desc = &txq->tx_desc_area[tx_index];
  698. if (nr_frags) {
  699. txq_submit_frag_skb(txq, skb);
  700. length = skb_headlen(skb);
  701. } else {
  702. cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
  703. length = skb->len;
  704. }
  705. desc->l4i_chk = l4i_chk;
  706. desc->byte_cnt = length;
  707. desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
  708. length, DMA_TO_DEVICE);
  709. __skb_queue_tail(&txq->tx_skb, skb);
  710. /* ensure all other descriptors are written before first cmd_sts */
  711. wmb();
  712. desc->cmd_sts = cmd_sts;
  713. /* clear TX_END status */
  714. mp->work_tx_end &= ~(1 << txq->index);
  715. /* ensure all descriptors are written before poking hardware */
  716. wmb();
  717. txq_enable(txq);
  718. txq->tx_desc_count += nr_frags + 1;
  719. return 0;
  720. }
  721. static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
  722. {
  723. struct mv643xx_eth_private *mp = netdev_priv(dev);
  724. int queue;
  725. struct tx_queue *txq;
  726. struct netdev_queue *nq;
  727. queue = skb_get_queue_mapping(skb);
  728. txq = mp->txq + queue;
  729. nq = netdev_get_tx_queue(dev, queue);
  730. if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
  731. txq->tx_dropped++;
  732. dev_printk(KERN_DEBUG, &dev->dev,
  733. "failed to linearize skb with tiny "
  734. "unaligned fragment\n");
  735. return NETDEV_TX_BUSY;
  736. }
  737. if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
  738. if (net_ratelimit())
  739. dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
  740. kfree_skb(skb);
  741. return NETDEV_TX_OK;
  742. }
  743. if (!txq_submit_skb(txq, skb)) {
  744. int entries_left;
  745. txq->tx_bytes += skb->len;
  746. txq->tx_packets++;
  747. entries_left = txq->tx_ring_size - txq->tx_desc_count;
  748. if (entries_left < MAX_SKB_FRAGS + 1)
  749. netif_tx_stop_queue(nq);
  750. }
  751. return NETDEV_TX_OK;
  752. }
  753. /* tx napi ******************************************************************/
  754. static void txq_kick(struct tx_queue *txq)
  755. {
  756. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  757. struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
  758. u32 hw_desc_ptr;
  759. u32 expected_ptr;
  760. __netif_tx_lock(nq, smp_processor_id());
  761. if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
  762. goto out;
  763. hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
  764. expected_ptr = (u32)txq->tx_desc_dma +
  765. txq->tx_curr_desc * sizeof(struct tx_desc);
  766. if (hw_desc_ptr != expected_ptr)
  767. txq_enable(txq);
  768. out:
  769. __netif_tx_unlock(nq);
  770. mp->work_tx_end &= ~(1 << txq->index);
  771. }
  772. static int txq_reclaim(struct tx_queue *txq, int budget, int force)
  773. {
  774. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  775. struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
  776. int reclaimed;
  777. __netif_tx_lock(nq, smp_processor_id());
  778. reclaimed = 0;
  779. while (reclaimed < budget && txq->tx_desc_count > 0) {
  780. int tx_index;
  781. struct tx_desc *desc;
  782. u32 cmd_sts;
  783. struct sk_buff *skb;
  784. tx_index = txq->tx_used_desc;
  785. desc = &txq->tx_desc_area[tx_index];
  786. cmd_sts = desc->cmd_sts;
  787. if (cmd_sts & BUFFER_OWNED_BY_DMA) {
  788. if (!force)
  789. break;
  790. desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
  791. }
  792. txq->tx_used_desc = tx_index + 1;
  793. if (txq->tx_used_desc == txq->tx_ring_size)
  794. txq->tx_used_desc = 0;
  795. reclaimed++;
  796. txq->tx_desc_count--;
  797. skb = NULL;
  798. if (cmd_sts & TX_LAST_DESC)
  799. skb = __skb_dequeue(&txq->tx_skb);
  800. if (cmd_sts & ERROR_SUMMARY) {
  801. dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
  802. mp->dev->stats.tx_errors++;
  803. }
  804. if (cmd_sts & TX_FIRST_DESC) {
  805. dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
  806. desc->byte_cnt, DMA_TO_DEVICE);
  807. } else {
  808. dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
  809. desc->byte_cnt, DMA_TO_DEVICE);
  810. }
  811. if (skb != NULL) {
  812. if (skb_queue_len(&mp->rx_recycle) <
  813. mp->rx_ring_size &&
  814. skb_recycle_check(skb, mp->skb_size))
  815. __skb_queue_head(&mp->rx_recycle, skb);
  816. else
  817. dev_kfree_skb(skb);
  818. }
  819. }
  820. __netif_tx_unlock(nq);
  821. if (reclaimed < budget)
  822. mp->work_tx &= ~(1 << txq->index);
  823. return reclaimed;
  824. }
  825. /* tx rate control **********************************************************/
  826. /*
  827. * Set total maximum TX rate (shared by all TX queues for this port)
  828. * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
  829. */
  830. static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
  831. {
  832. int token_rate;
  833. int mtu;
  834. int bucket_size;
  835. token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
  836. if (token_rate > 1023)
  837. token_rate = 1023;
  838. mtu = (mp->dev->mtu + 255) >> 8;
  839. if (mtu > 63)
  840. mtu = 63;
  841. bucket_size = (burst + 255) >> 8;
  842. if (bucket_size > 65535)
  843. bucket_size = 65535;
  844. switch (mp->shared->tx_bw_control) {
  845. case TX_BW_CONTROL_OLD_LAYOUT:
  846. wrlp(mp, TX_BW_RATE, token_rate);
  847. wrlp(mp, TX_BW_MTU, mtu);
  848. wrlp(mp, TX_BW_BURST, bucket_size);
  849. break;
  850. case TX_BW_CONTROL_NEW_LAYOUT:
  851. wrlp(mp, TX_BW_RATE_MOVED, token_rate);
  852. wrlp(mp, TX_BW_MTU_MOVED, mtu);
  853. wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
  854. break;
  855. }
  856. }
  857. static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
  858. {
  859. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  860. int token_rate;
  861. int bucket_size;
  862. token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
  863. if (token_rate > 1023)
  864. token_rate = 1023;
  865. bucket_size = (burst + 255) >> 8;
  866. if (bucket_size > 65535)
  867. bucket_size = 65535;
  868. wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
  869. wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
  870. }
  871. static void txq_set_fixed_prio_mode(struct tx_queue *txq)
  872. {
  873. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  874. int off;
  875. u32 val;
  876. /*
  877. * Turn on fixed priority mode.
  878. */
  879. off = 0;
  880. switch (mp->shared->tx_bw_control) {
  881. case TX_BW_CONTROL_OLD_LAYOUT:
  882. off = TXQ_FIX_PRIO_CONF;
  883. break;
  884. case TX_BW_CONTROL_NEW_LAYOUT:
  885. off = TXQ_FIX_PRIO_CONF_MOVED;
  886. break;
  887. }
  888. if (off) {
  889. val = rdlp(mp, off);
  890. val |= 1 << txq->index;
  891. wrlp(mp, off, val);
  892. }
  893. }
  894. /* mii management interface *************************************************/
  895. static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
  896. {
  897. struct mv643xx_eth_shared_private *msp = dev_id;
  898. if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
  899. writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
  900. wake_up(&msp->smi_busy_wait);
  901. return IRQ_HANDLED;
  902. }
  903. return IRQ_NONE;
  904. }
  905. static int smi_is_done(struct mv643xx_eth_shared_private *msp)
  906. {
  907. return !(readl(msp->base + SMI_REG) & SMI_BUSY);
  908. }
  909. static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
  910. {
  911. if (msp->err_interrupt == NO_IRQ) {
  912. int i;
  913. for (i = 0; !smi_is_done(msp); i++) {
  914. if (i == 10)
  915. return -ETIMEDOUT;
  916. msleep(10);
  917. }
  918. return 0;
  919. }
  920. if (!smi_is_done(msp)) {
  921. wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
  922. msecs_to_jiffies(100));
  923. if (!smi_is_done(msp))
  924. return -ETIMEDOUT;
  925. }
  926. return 0;
  927. }
  928. static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
  929. {
  930. struct mv643xx_eth_shared_private *msp = bus->priv;
  931. void __iomem *smi_reg = msp->base + SMI_REG;
  932. int ret;
  933. if (smi_wait_ready(msp)) {
  934. printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
  935. return -ETIMEDOUT;
  936. }
  937. writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
  938. if (smi_wait_ready(msp)) {
  939. printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
  940. return -ETIMEDOUT;
  941. }
  942. ret = readl(smi_reg);
  943. if (!(ret & SMI_READ_VALID)) {
  944. printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
  945. return -ENODEV;
  946. }
  947. return ret & 0xffff;
  948. }
  949. static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
  950. {
  951. struct mv643xx_eth_shared_private *msp = bus->priv;
  952. void __iomem *smi_reg = msp->base + SMI_REG;
  953. if (smi_wait_ready(msp)) {
  954. printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
  955. return -ETIMEDOUT;
  956. }
  957. writel(SMI_OPCODE_WRITE | (reg << 21) |
  958. (addr << 16) | (val & 0xffff), smi_reg);
  959. if (smi_wait_ready(msp)) {
  960. printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
  961. return -ETIMEDOUT;
  962. }
  963. return 0;
  964. }
  965. /* statistics ***************************************************************/
  966. static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
  967. {
  968. struct mv643xx_eth_private *mp = netdev_priv(dev);
  969. struct net_device_stats *stats = &dev->stats;
  970. unsigned long tx_packets = 0;
  971. unsigned long tx_bytes = 0;
  972. unsigned long tx_dropped = 0;
  973. int i;
  974. for (i = 0; i < mp->txq_count; i++) {
  975. struct tx_queue *txq = mp->txq + i;
  976. tx_packets += txq->tx_packets;
  977. tx_bytes += txq->tx_bytes;
  978. tx_dropped += txq->tx_dropped;
  979. }
  980. stats->tx_packets = tx_packets;
  981. stats->tx_bytes = tx_bytes;
  982. stats->tx_dropped = tx_dropped;
  983. return stats;
  984. }
  985. static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
  986. {
  987. u32 lro_aggregated = 0;
  988. u32 lro_flushed = 0;
  989. u32 lro_no_desc = 0;
  990. int i;
  991. for (i = 0; i < mp->rxq_count; i++) {
  992. struct rx_queue *rxq = mp->rxq + i;
  993. lro_aggregated += rxq->lro_mgr.stats.aggregated;
  994. lro_flushed += rxq->lro_mgr.stats.flushed;
  995. lro_no_desc += rxq->lro_mgr.stats.no_desc;
  996. }
  997. mp->lro_counters.lro_aggregated = lro_aggregated;
  998. mp->lro_counters.lro_flushed = lro_flushed;
  999. mp->lro_counters.lro_no_desc = lro_no_desc;
  1000. }
  1001. static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
  1002. {
  1003. return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
  1004. }
  1005. static void mib_counters_clear(struct mv643xx_eth_private *mp)
  1006. {
  1007. int i;
  1008. for (i = 0; i < 0x80; i += 4)
  1009. mib_read(mp, i);
  1010. }
  1011. static void mib_counters_update(struct mv643xx_eth_private *mp)
  1012. {
  1013. struct mib_counters *p = &mp->mib_counters;
  1014. spin_lock_bh(&mp->mib_counters_lock);
  1015. p->good_octets_received += mib_read(mp, 0x00);
  1016. p->bad_octets_received += mib_read(mp, 0x08);
  1017. p->internal_mac_transmit_err += mib_read(mp, 0x0c);
  1018. p->good_frames_received += mib_read(mp, 0x10);
  1019. p->bad_frames_received += mib_read(mp, 0x14);
  1020. p->broadcast_frames_received += mib_read(mp, 0x18);
  1021. p->multicast_frames_received += mib_read(mp, 0x1c);
  1022. p->frames_64_octets += mib_read(mp, 0x20);
  1023. p->frames_65_to_127_octets += mib_read(mp, 0x24);
  1024. p->frames_128_to_255_octets += mib_read(mp, 0x28);
  1025. p->frames_256_to_511_octets += mib_read(mp, 0x2c);
  1026. p->frames_512_to_1023_octets += mib_read(mp, 0x30);
  1027. p->frames_1024_to_max_octets += mib_read(mp, 0x34);
  1028. p->good_octets_sent += mib_read(mp, 0x38);
  1029. p->good_frames_sent += mib_read(mp, 0x40);
  1030. p->excessive_collision += mib_read(mp, 0x44);
  1031. p->multicast_frames_sent += mib_read(mp, 0x48);
  1032. p->broadcast_frames_sent += mib_read(mp, 0x4c);
  1033. p->unrec_mac_control_received += mib_read(mp, 0x50);
  1034. p->fc_sent += mib_read(mp, 0x54);
  1035. p->good_fc_received += mib_read(mp, 0x58);
  1036. p->bad_fc_received += mib_read(mp, 0x5c);
  1037. p->undersize_received += mib_read(mp, 0x60);
  1038. p->fragments_received += mib_read(mp, 0x64);
  1039. p->oversize_received += mib_read(mp, 0x68);
  1040. p->jabber_received += mib_read(mp, 0x6c);
  1041. p->mac_receive_error += mib_read(mp, 0x70);
  1042. p->bad_crc_event += mib_read(mp, 0x74);
  1043. p->collision += mib_read(mp, 0x78);
  1044. p->late_collision += mib_read(mp, 0x7c);
  1045. spin_unlock_bh(&mp->mib_counters_lock);
  1046. mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
  1047. }
  1048. static void mib_counters_timer_wrapper(unsigned long _mp)
  1049. {
  1050. struct mv643xx_eth_private *mp = (void *)_mp;
  1051. mib_counters_update(mp);
  1052. }
  1053. /* interrupt coalescing *****************************************************/
  1054. /*
  1055. * Hardware coalescing parameters are set in units of 64 t_clk
  1056. * cycles. I.e.:
  1057. *
  1058. * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
  1059. *
  1060. * register_value = coal_delay_in_usec * t_clk_rate / 64000000
  1061. *
  1062. * In the ->set*() methods, we round the computed register value
  1063. * to the nearest integer.
  1064. */
  1065. static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
  1066. {
  1067. u32 val = rdlp(mp, SDMA_CONFIG);
  1068. u64 temp;
  1069. if (mp->shared->extended_rx_coal_limit)
  1070. temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
  1071. else
  1072. temp = (val & 0x003fff00) >> 8;
  1073. temp *= 64000000;
  1074. do_div(temp, mp->shared->t_clk);
  1075. return (unsigned int)temp;
  1076. }
  1077. static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
  1078. {
  1079. u64 temp;
  1080. u32 val;
  1081. temp = (u64)usec * mp->shared->t_clk;
  1082. temp += 31999999;
  1083. do_div(temp, 64000000);
  1084. val = rdlp(mp, SDMA_CONFIG);
  1085. if (mp->shared->extended_rx_coal_limit) {
  1086. if (temp > 0xffff)
  1087. temp = 0xffff;
  1088. val &= ~0x023fff80;
  1089. val |= (temp & 0x8000) << 10;
  1090. val |= (temp & 0x7fff) << 7;
  1091. } else {
  1092. if (temp > 0x3fff)
  1093. temp = 0x3fff;
  1094. val &= ~0x003fff00;
  1095. val |= (temp & 0x3fff) << 8;
  1096. }
  1097. wrlp(mp, SDMA_CONFIG, val);
  1098. }
  1099. static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
  1100. {
  1101. u64 temp;
  1102. temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
  1103. temp *= 64000000;
  1104. do_div(temp, mp->shared->t_clk);
  1105. return (unsigned int)temp;
  1106. }
  1107. static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
  1108. {
  1109. u64 temp;
  1110. temp = (u64)usec * mp->shared->t_clk;
  1111. temp += 31999999;
  1112. do_div(temp, 64000000);
  1113. if (temp > 0x3fff)
  1114. temp = 0x3fff;
  1115. wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
  1116. }
  1117. /* ethtool ******************************************************************/
  1118. struct mv643xx_eth_stats {
  1119. char stat_string[ETH_GSTRING_LEN];
  1120. int sizeof_stat;
  1121. int netdev_off;
  1122. int mp_off;
  1123. };
  1124. #define SSTAT(m) \
  1125. { #m, FIELD_SIZEOF(struct net_device_stats, m), \
  1126. offsetof(struct net_device, stats.m), -1 }
  1127. #define MIBSTAT(m) \
  1128. { #m, FIELD_SIZEOF(struct mib_counters, m), \
  1129. -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
  1130. #define LROSTAT(m) \
  1131. { #m, FIELD_SIZEOF(struct lro_counters, m), \
  1132. -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
  1133. static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
  1134. SSTAT(rx_packets),
  1135. SSTAT(tx_packets),
  1136. SSTAT(rx_bytes),
  1137. SSTAT(tx_bytes),
  1138. SSTAT(rx_errors),
  1139. SSTAT(tx_errors),
  1140. SSTAT(rx_dropped),
  1141. SSTAT(tx_dropped),
  1142. MIBSTAT(good_octets_received),
  1143. MIBSTAT(bad_octets_received),
  1144. MIBSTAT(internal_mac_transmit_err),
  1145. MIBSTAT(good_frames_received),
  1146. MIBSTAT(bad_frames_received),
  1147. MIBSTAT(broadcast_frames_received),
  1148. MIBSTAT(multicast_frames_received),
  1149. MIBSTAT(frames_64_octets),
  1150. MIBSTAT(frames_65_to_127_octets),
  1151. MIBSTAT(frames_128_to_255_octets),
  1152. MIBSTAT(frames_256_to_511_octets),
  1153. MIBSTAT(frames_512_to_1023_octets),
  1154. MIBSTAT(frames_1024_to_max_octets),
  1155. MIBSTAT(good_octets_sent),
  1156. MIBSTAT(good_frames_sent),
  1157. MIBSTAT(excessive_collision),
  1158. MIBSTAT(multicast_frames_sent),
  1159. MIBSTAT(broadcast_frames_sent),
  1160. MIBSTAT(unrec_mac_control_received),
  1161. MIBSTAT(fc_sent),
  1162. MIBSTAT(good_fc_received),
  1163. MIBSTAT(bad_fc_received),
  1164. MIBSTAT(undersize_received),
  1165. MIBSTAT(fragments_received),
  1166. MIBSTAT(oversize_received),
  1167. MIBSTAT(jabber_received),
  1168. MIBSTAT(mac_receive_error),
  1169. MIBSTAT(bad_crc_event),
  1170. MIBSTAT(collision),
  1171. MIBSTAT(late_collision),
  1172. LROSTAT(lro_aggregated),
  1173. LROSTAT(lro_flushed),
  1174. LROSTAT(lro_no_desc),
  1175. };
  1176. static int
  1177. mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
  1178. struct ethtool_cmd *cmd)
  1179. {
  1180. int err;
  1181. err = phy_read_status(mp->phy);
  1182. if (err == 0)
  1183. err = phy_ethtool_gset(mp->phy, cmd);
  1184. /*
  1185. * The MAC does not support 1000baseT_Half.
  1186. */
  1187. cmd->supported &= ~SUPPORTED_1000baseT_Half;
  1188. cmd->advertising &= ~ADVERTISED_1000baseT_Half;
  1189. return err;
  1190. }
  1191. static int
  1192. mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
  1193. struct ethtool_cmd *cmd)
  1194. {
  1195. u32 port_status;
  1196. port_status = rdlp(mp, PORT_STATUS);
  1197. cmd->supported = SUPPORTED_MII;
  1198. cmd->advertising = ADVERTISED_MII;
  1199. switch (port_status & PORT_SPEED_MASK) {
  1200. case PORT_SPEED_10:
  1201. cmd->speed = SPEED_10;
  1202. break;
  1203. case PORT_SPEED_100:
  1204. cmd->speed = SPEED_100;
  1205. break;
  1206. case PORT_SPEED_1000:
  1207. cmd->speed = SPEED_1000;
  1208. break;
  1209. default:
  1210. cmd->speed = -1;
  1211. break;
  1212. }
  1213. cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
  1214. cmd->port = PORT_MII;
  1215. cmd->phy_address = 0;
  1216. cmd->transceiver = XCVR_INTERNAL;
  1217. cmd->autoneg = AUTONEG_DISABLE;
  1218. cmd->maxtxpkt = 1;
  1219. cmd->maxrxpkt = 1;
  1220. return 0;
  1221. }
  1222. static int
  1223. mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1224. {
  1225. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1226. if (mp->phy != NULL)
  1227. return mv643xx_eth_get_settings_phy(mp, cmd);
  1228. else
  1229. return mv643xx_eth_get_settings_phyless(mp, cmd);
  1230. }
  1231. static int
  1232. mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1233. {
  1234. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1235. if (mp->phy == NULL)
  1236. return -EINVAL;
  1237. /*
  1238. * The MAC does not support 1000baseT_Half.
  1239. */
  1240. cmd->advertising &= ~ADVERTISED_1000baseT_Half;
  1241. return phy_ethtool_sset(mp->phy, cmd);
  1242. }
  1243. static void mv643xx_eth_get_drvinfo(struct net_device *dev,
  1244. struct ethtool_drvinfo *drvinfo)
  1245. {
  1246. strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
  1247. strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
  1248. strncpy(drvinfo->fw_version, "N/A", 32);
  1249. strncpy(drvinfo->bus_info, "platform", 32);
  1250. drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
  1251. }
  1252. static int mv643xx_eth_nway_reset(struct net_device *dev)
  1253. {
  1254. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1255. if (mp->phy == NULL)
  1256. return -EINVAL;
  1257. return genphy_restart_aneg(mp->phy);
  1258. }
  1259. static u32 mv643xx_eth_get_link(struct net_device *dev)
  1260. {
  1261. return !!netif_carrier_ok(dev);
  1262. }
  1263. static int
  1264. mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  1265. {
  1266. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1267. ec->rx_coalesce_usecs = get_rx_coal(mp);
  1268. ec->tx_coalesce_usecs = get_tx_coal(mp);
  1269. return 0;
  1270. }
  1271. static int
  1272. mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  1273. {
  1274. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1275. set_rx_coal(mp, ec->rx_coalesce_usecs);
  1276. set_tx_coal(mp, ec->tx_coalesce_usecs);
  1277. return 0;
  1278. }
  1279. static void
  1280. mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
  1281. {
  1282. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1283. er->rx_max_pending = 4096;
  1284. er->tx_max_pending = 4096;
  1285. er->rx_mini_max_pending = 0;
  1286. er->rx_jumbo_max_pending = 0;
  1287. er->rx_pending = mp->rx_ring_size;
  1288. er->tx_pending = mp->tx_ring_size;
  1289. er->rx_mini_pending = 0;
  1290. er->rx_jumbo_pending = 0;
  1291. }
  1292. static int
  1293. mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
  1294. {
  1295. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1296. if (er->rx_mini_pending || er->rx_jumbo_pending)
  1297. return -EINVAL;
  1298. mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
  1299. mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
  1300. if (netif_running(dev)) {
  1301. mv643xx_eth_stop(dev);
  1302. if (mv643xx_eth_open(dev)) {
  1303. dev_printk(KERN_ERR, &dev->dev,
  1304. "fatal error on re-opening device after "
  1305. "ring param change\n");
  1306. return -ENOMEM;
  1307. }
  1308. }
  1309. return 0;
  1310. }
  1311. static u32
  1312. mv643xx_eth_get_rx_csum(struct net_device *dev)
  1313. {
  1314. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1315. return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
  1316. }
  1317. static int
  1318. mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
  1319. {
  1320. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1321. wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
  1322. return 0;
  1323. }
  1324. static void mv643xx_eth_get_strings(struct net_device *dev,
  1325. uint32_t stringset, uint8_t *data)
  1326. {
  1327. int i;
  1328. if (stringset == ETH_SS_STATS) {
  1329. for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
  1330. memcpy(data + i * ETH_GSTRING_LEN,
  1331. mv643xx_eth_stats[i].stat_string,
  1332. ETH_GSTRING_LEN);
  1333. }
  1334. }
  1335. }
  1336. static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
  1337. struct ethtool_stats *stats,
  1338. uint64_t *data)
  1339. {
  1340. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1341. int i;
  1342. mv643xx_eth_get_stats(dev);
  1343. mib_counters_update(mp);
  1344. mv643xx_eth_grab_lro_stats(mp);
  1345. for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
  1346. const struct mv643xx_eth_stats *stat;
  1347. void *p;
  1348. stat = mv643xx_eth_stats + i;
  1349. if (stat->netdev_off >= 0)
  1350. p = ((void *)mp->dev) + stat->netdev_off;
  1351. else
  1352. p = ((void *)mp) + stat->mp_off;
  1353. data[i] = (stat->sizeof_stat == 8) ?
  1354. *(uint64_t *)p : *(uint32_t *)p;
  1355. }
  1356. }
  1357. static int mv643xx_eth_set_flags(struct net_device *dev, u32 data)
  1358. {
  1359. return ethtool_op_set_flags(dev, data, ETH_FLAG_LRO);
  1360. }
  1361. static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
  1362. {
  1363. if (sset == ETH_SS_STATS)
  1364. return ARRAY_SIZE(mv643xx_eth_stats);
  1365. return -EOPNOTSUPP;
  1366. }
  1367. static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
  1368. .get_settings = mv643xx_eth_get_settings,
  1369. .set_settings = mv643xx_eth_set_settings,
  1370. .get_drvinfo = mv643xx_eth_get_drvinfo,
  1371. .nway_reset = mv643xx_eth_nway_reset,
  1372. .get_link = mv643xx_eth_get_link,
  1373. .get_coalesce = mv643xx_eth_get_coalesce,
  1374. .set_coalesce = mv643xx_eth_set_coalesce,
  1375. .get_ringparam = mv643xx_eth_get_ringparam,
  1376. .set_ringparam = mv643xx_eth_set_ringparam,
  1377. .get_rx_csum = mv643xx_eth_get_rx_csum,
  1378. .set_rx_csum = mv643xx_eth_set_rx_csum,
  1379. .set_tx_csum = ethtool_op_set_tx_csum,
  1380. .set_sg = ethtool_op_set_sg,
  1381. .get_strings = mv643xx_eth_get_strings,
  1382. .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
  1383. .get_flags = ethtool_op_get_flags,
  1384. .set_flags = mv643xx_eth_set_flags,
  1385. .get_sset_count = mv643xx_eth_get_sset_count,
  1386. };
  1387. /* address handling *********************************************************/
  1388. static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
  1389. {
  1390. unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
  1391. unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
  1392. addr[0] = (mac_h >> 24) & 0xff;
  1393. addr[1] = (mac_h >> 16) & 0xff;
  1394. addr[2] = (mac_h >> 8) & 0xff;
  1395. addr[3] = mac_h & 0xff;
  1396. addr[4] = (mac_l >> 8) & 0xff;
  1397. addr[5] = mac_l & 0xff;
  1398. }
  1399. static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
  1400. {
  1401. wrlp(mp, MAC_ADDR_HIGH,
  1402. (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
  1403. wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
  1404. }
  1405. static u32 uc_addr_filter_mask(struct net_device *dev)
  1406. {
  1407. struct netdev_hw_addr *ha;
  1408. u32 nibbles;
  1409. if (dev->flags & IFF_PROMISC)
  1410. return 0;
  1411. nibbles = 1 << (dev->dev_addr[5] & 0x0f);
  1412. netdev_for_each_uc_addr(ha, dev) {
  1413. if (memcmp(dev->dev_addr, ha->addr, 5))
  1414. return 0;
  1415. if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
  1416. return 0;
  1417. nibbles |= 1 << (ha->addr[5] & 0x0f);
  1418. }
  1419. return nibbles;
  1420. }
  1421. static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
  1422. {
  1423. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1424. u32 port_config;
  1425. u32 nibbles;
  1426. int i;
  1427. uc_addr_set(mp, dev->dev_addr);
  1428. port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
  1429. nibbles = uc_addr_filter_mask(dev);
  1430. if (!nibbles) {
  1431. port_config |= UNICAST_PROMISCUOUS_MODE;
  1432. nibbles = 0xffff;
  1433. }
  1434. for (i = 0; i < 16; i += 4) {
  1435. int off = UNICAST_TABLE(mp->port_num) + i;
  1436. u32 v;
  1437. v = 0;
  1438. if (nibbles & 1)
  1439. v |= 0x00000001;
  1440. if (nibbles & 2)
  1441. v |= 0x00000100;
  1442. if (nibbles & 4)
  1443. v |= 0x00010000;
  1444. if (nibbles & 8)
  1445. v |= 0x01000000;
  1446. nibbles >>= 4;
  1447. wrl(mp, off, v);
  1448. }
  1449. wrlp(mp, PORT_CONFIG, port_config);
  1450. }
  1451. static int addr_crc(unsigned char *addr)
  1452. {
  1453. int crc = 0;
  1454. int i;
  1455. for (i = 0; i < 6; i++) {
  1456. int j;
  1457. crc = (crc ^ addr[i]) << 8;
  1458. for (j = 7; j >= 0; j--) {
  1459. if (crc & (0x100 << j))
  1460. crc ^= 0x107 << j;
  1461. }
  1462. }
  1463. return crc;
  1464. }
  1465. static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
  1466. {
  1467. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1468. u32 *mc_spec;
  1469. u32 *mc_other;
  1470. struct netdev_hw_addr *ha;
  1471. int i;
  1472. if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
  1473. int port_num;
  1474. u32 accept;
  1475. oom:
  1476. port_num = mp->port_num;
  1477. accept = 0x01010101;
  1478. for (i = 0; i < 0x100; i += 4) {
  1479. wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
  1480. wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
  1481. }
  1482. return;
  1483. }
  1484. mc_spec = kmalloc(0x200, GFP_ATOMIC);
  1485. if (mc_spec == NULL)
  1486. goto oom;
  1487. mc_other = mc_spec + (0x100 >> 2);
  1488. memset(mc_spec, 0, 0x100);
  1489. memset(mc_other, 0, 0x100);
  1490. netdev_for_each_mc_addr(ha, dev) {
  1491. u8 *a = ha->addr;
  1492. u32 *table;
  1493. int entry;
  1494. if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
  1495. table = mc_spec;
  1496. entry = a[5];
  1497. } else {
  1498. table = mc_other;
  1499. entry = addr_crc(a);
  1500. }
  1501. table[entry >> 2] |= 1 << (8 * (entry & 3));
  1502. }
  1503. for (i = 0; i < 0x100; i += 4) {
  1504. wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
  1505. wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
  1506. }
  1507. kfree(mc_spec);
  1508. }
  1509. static void mv643xx_eth_set_rx_mode(struct net_device *dev)
  1510. {
  1511. mv643xx_eth_program_unicast_filter(dev);
  1512. mv643xx_eth_program_multicast_filter(dev);
  1513. }
  1514. static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
  1515. {
  1516. struct sockaddr *sa = addr;
  1517. if (!is_valid_ether_addr(sa->sa_data))
  1518. return -EINVAL;
  1519. memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
  1520. netif_addr_lock_bh(dev);
  1521. mv643xx_eth_program_unicast_filter(dev);
  1522. netif_addr_unlock_bh(dev);
  1523. return 0;
  1524. }
  1525. /* rx/tx queue initialisation ***********************************************/
  1526. static int rxq_init(struct mv643xx_eth_private *mp, int index)
  1527. {
  1528. struct rx_queue *rxq = mp->rxq + index;
  1529. struct rx_desc *rx_desc;
  1530. int size;
  1531. int i;
  1532. rxq->index = index;
  1533. rxq->rx_ring_size = mp->rx_ring_size;
  1534. rxq->rx_desc_count = 0;
  1535. rxq->rx_curr_desc = 0;
  1536. rxq->rx_used_desc = 0;
  1537. size = rxq->rx_ring_size * sizeof(struct rx_desc);
  1538. if (index == 0 && size <= mp->rx_desc_sram_size) {
  1539. rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
  1540. mp->rx_desc_sram_size);
  1541. rxq->rx_desc_dma = mp->rx_desc_sram_addr;
  1542. } else {
  1543. rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
  1544. size, &rxq->rx_desc_dma,
  1545. GFP_KERNEL);
  1546. }
  1547. if (rxq->rx_desc_area == NULL) {
  1548. dev_printk(KERN_ERR, &mp->dev->dev,
  1549. "can't allocate rx ring (%d bytes)\n", size);
  1550. goto out;
  1551. }
  1552. memset(rxq->rx_desc_area, 0, size);
  1553. rxq->rx_desc_area_size = size;
  1554. rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
  1555. GFP_KERNEL);
  1556. if (rxq->rx_skb == NULL) {
  1557. dev_printk(KERN_ERR, &mp->dev->dev,
  1558. "can't allocate rx skb ring\n");
  1559. goto out_free;
  1560. }
  1561. rx_desc = (struct rx_desc *)rxq->rx_desc_area;
  1562. for (i = 0; i < rxq->rx_ring_size; i++) {
  1563. int nexti;
  1564. nexti = i + 1;
  1565. if (nexti == rxq->rx_ring_size)
  1566. nexti = 0;
  1567. rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
  1568. nexti * sizeof(struct rx_desc);
  1569. }
  1570. rxq->lro_mgr.dev = mp->dev;
  1571. memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
  1572. rxq->lro_mgr.features = LRO_F_NAPI;
  1573. rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
  1574. rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
  1575. rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
  1576. rxq->lro_mgr.max_aggr = 32;
  1577. rxq->lro_mgr.frag_align_pad = 0;
  1578. rxq->lro_mgr.lro_arr = rxq->lro_arr;
  1579. rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
  1580. memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
  1581. return 0;
  1582. out_free:
  1583. if (index == 0 && size <= mp->rx_desc_sram_size)
  1584. iounmap(rxq->rx_desc_area);
  1585. else
  1586. dma_free_coherent(mp->dev->dev.parent, size,
  1587. rxq->rx_desc_area,
  1588. rxq->rx_desc_dma);
  1589. out:
  1590. return -ENOMEM;
  1591. }
  1592. static void rxq_deinit(struct rx_queue *rxq)
  1593. {
  1594. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  1595. int i;
  1596. rxq_disable(rxq);
  1597. for (i = 0; i < rxq->rx_ring_size; i++) {
  1598. if (rxq->rx_skb[i]) {
  1599. dev_kfree_skb(rxq->rx_skb[i]);
  1600. rxq->rx_desc_count--;
  1601. }
  1602. }
  1603. if (rxq->rx_desc_count) {
  1604. dev_printk(KERN_ERR, &mp->dev->dev,
  1605. "error freeing rx ring -- %d skbs stuck\n",
  1606. rxq->rx_desc_count);
  1607. }
  1608. if (rxq->index == 0 &&
  1609. rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
  1610. iounmap(rxq->rx_desc_area);
  1611. else
  1612. dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
  1613. rxq->rx_desc_area, rxq->rx_desc_dma);
  1614. kfree(rxq->rx_skb);
  1615. }
  1616. static int txq_init(struct mv643xx_eth_private *mp, int index)
  1617. {
  1618. struct tx_queue *txq = mp->txq + index;
  1619. struct tx_desc *tx_desc;
  1620. int size;
  1621. int i;
  1622. txq->index = index;
  1623. txq->tx_ring_size = mp->tx_ring_size;
  1624. txq->tx_desc_count = 0;
  1625. txq->tx_curr_desc = 0;
  1626. txq->tx_used_desc = 0;
  1627. size = txq->tx_ring_size * sizeof(struct tx_desc);
  1628. if (index == 0 && size <= mp->tx_desc_sram_size) {
  1629. txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
  1630. mp->tx_desc_sram_size);
  1631. txq->tx_desc_dma = mp->tx_desc_sram_addr;
  1632. } else {
  1633. txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
  1634. size, &txq->tx_desc_dma,
  1635. GFP_KERNEL);
  1636. }
  1637. if (txq->tx_desc_area == NULL) {
  1638. dev_printk(KERN_ERR, &mp->dev->dev,
  1639. "can't allocate tx ring (%d bytes)\n", size);
  1640. return -ENOMEM;
  1641. }
  1642. memset(txq->tx_desc_area, 0, size);
  1643. txq->tx_desc_area_size = size;
  1644. tx_desc = (struct tx_desc *)txq->tx_desc_area;
  1645. for (i = 0; i < txq->tx_ring_size; i++) {
  1646. struct tx_desc *txd = tx_desc + i;
  1647. int nexti;
  1648. nexti = i + 1;
  1649. if (nexti == txq->tx_ring_size)
  1650. nexti = 0;
  1651. txd->cmd_sts = 0;
  1652. txd->next_desc_ptr = txq->tx_desc_dma +
  1653. nexti * sizeof(struct tx_desc);
  1654. }
  1655. skb_queue_head_init(&txq->tx_skb);
  1656. return 0;
  1657. }
  1658. static void txq_deinit(struct tx_queue *txq)
  1659. {
  1660. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  1661. txq_disable(txq);
  1662. txq_reclaim(txq, txq->tx_ring_size, 1);
  1663. BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
  1664. if (txq->index == 0 &&
  1665. txq->tx_desc_area_size <= mp->tx_desc_sram_size)
  1666. iounmap(txq->tx_desc_area);
  1667. else
  1668. dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
  1669. txq->tx_desc_area, txq->tx_desc_dma);
  1670. }
  1671. /* netdev ops and related ***************************************************/
  1672. static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
  1673. {
  1674. u32 int_cause;
  1675. u32 int_cause_ext;
  1676. int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
  1677. if (int_cause == 0)
  1678. return 0;
  1679. int_cause_ext = 0;
  1680. if (int_cause & INT_EXT) {
  1681. int_cause &= ~INT_EXT;
  1682. int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
  1683. }
  1684. if (int_cause) {
  1685. wrlp(mp, INT_CAUSE, ~int_cause);
  1686. mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
  1687. ~(rdlp(mp, TXQ_COMMAND) & 0xff);
  1688. mp->work_rx |= (int_cause & INT_RX) >> 2;
  1689. }
  1690. int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
  1691. if (int_cause_ext) {
  1692. wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
  1693. if (int_cause_ext & INT_EXT_LINK_PHY)
  1694. mp->work_link = 1;
  1695. mp->work_tx |= int_cause_ext & INT_EXT_TX;
  1696. }
  1697. return 1;
  1698. }
  1699. static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
  1700. {
  1701. struct net_device *dev = (struct net_device *)dev_id;
  1702. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1703. if (unlikely(!mv643xx_eth_collect_events(mp)))
  1704. return IRQ_NONE;
  1705. wrlp(mp, INT_MASK, 0);
  1706. napi_schedule(&mp->napi);
  1707. return IRQ_HANDLED;
  1708. }
  1709. static void handle_link_event(struct mv643xx_eth_private *mp)
  1710. {
  1711. struct net_device *dev = mp->dev;
  1712. u32 port_status;
  1713. int speed;
  1714. int duplex;
  1715. int fc;
  1716. port_status = rdlp(mp, PORT_STATUS);
  1717. if (!(port_status & LINK_UP)) {
  1718. if (netif_carrier_ok(dev)) {
  1719. int i;
  1720. printk(KERN_INFO "%s: link down\n", dev->name);
  1721. netif_carrier_off(dev);
  1722. for (i = 0; i < mp->txq_count; i++) {
  1723. struct tx_queue *txq = mp->txq + i;
  1724. txq_reclaim(txq, txq->tx_ring_size, 1);
  1725. txq_reset_hw_ptr(txq);
  1726. }
  1727. }
  1728. return;
  1729. }
  1730. switch (port_status & PORT_SPEED_MASK) {
  1731. case PORT_SPEED_10:
  1732. speed = 10;
  1733. break;
  1734. case PORT_SPEED_100:
  1735. speed = 100;
  1736. break;
  1737. case PORT_SPEED_1000:
  1738. speed = 1000;
  1739. break;
  1740. default:
  1741. speed = -1;
  1742. break;
  1743. }
  1744. duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
  1745. fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
  1746. printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
  1747. "flow control %sabled\n", dev->name,
  1748. speed, duplex ? "full" : "half",
  1749. fc ? "en" : "dis");
  1750. if (!netif_carrier_ok(dev))
  1751. netif_carrier_on(dev);
  1752. }
  1753. static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
  1754. {
  1755. struct mv643xx_eth_private *mp;
  1756. int work_done;
  1757. mp = container_of(napi, struct mv643xx_eth_private, napi);
  1758. if (unlikely(mp->oom)) {
  1759. mp->oom = 0;
  1760. del_timer(&mp->rx_oom);
  1761. }
  1762. work_done = 0;
  1763. while (work_done < budget) {
  1764. u8 queue_mask;
  1765. int queue;
  1766. int work_tbd;
  1767. if (mp->work_link) {
  1768. mp->work_link = 0;
  1769. handle_link_event(mp);
  1770. work_done++;
  1771. continue;
  1772. }
  1773. queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
  1774. if (likely(!mp->oom))
  1775. queue_mask |= mp->work_rx_refill;
  1776. if (!queue_mask) {
  1777. if (mv643xx_eth_collect_events(mp))
  1778. continue;
  1779. break;
  1780. }
  1781. queue = fls(queue_mask) - 1;
  1782. queue_mask = 1 << queue;
  1783. work_tbd = budget - work_done;
  1784. if (work_tbd > 16)
  1785. work_tbd = 16;
  1786. if (mp->work_tx_end & queue_mask) {
  1787. txq_kick(mp->txq + queue);
  1788. } else if (mp->work_tx & queue_mask) {
  1789. work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
  1790. txq_maybe_wake(mp->txq + queue);
  1791. } else if (mp->work_rx & queue_mask) {
  1792. work_done += rxq_process(mp->rxq + queue, work_tbd);
  1793. } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
  1794. work_done += rxq_refill(mp->rxq + queue, work_tbd);
  1795. } else {
  1796. BUG();
  1797. }
  1798. }
  1799. if (work_done < budget) {
  1800. if (mp->oom)
  1801. mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
  1802. napi_complete(napi);
  1803. wrlp(mp, INT_MASK, mp->int_mask);
  1804. }
  1805. return work_done;
  1806. }
  1807. static inline void oom_timer_wrapper(unsigned long data)
  1808. {
  1809. struct mv643xx_eth_private *mp = (void *)data;
  1810. napi_schedule(&mp->napi);
  1811. }
  1812. static void phy_reset(struct mv643xx_eth_private *mp)
  1813. {
  1814. int data;
  1815. data = phy_read(mp->phy, MII_BMCR);
  1816. if (data < 0)
  1817. return;
  1818. data |= BMCR_RESET;
  1819. if (phy_write(mp->phy, MII_BMCR, data) < 0)
  1820. return;
  1821. do {
  1822. data = phy_read(mp->phy, MII_BMCR);
  1823. } while (data >= 0 && data & BMCR_RESET);
  1824. }
  1825. static void port_start(struct mv643xx_eth_private *mp)
  1826. {
  1827. u32 pscr;
  1828. int i;
  1829. /*
  1830. * Perform PHY reset, if there is a PHY.
  1831. */
  1832. if (mp->phy != NULL) {
  1833. struct ethtool_cmd cmd;
  1834. mv643xx_eth_get_settings(mp->dev, &cmd);
  1835. phy_reset(mp);
  1836. mv643xx_eth_set_settings(mp->dev, &cmd);
  1837. }
  1838. /*
  1839. * Configure basic link parameters.
  1840. */
  1841. pscr = rdlp(mp, PORT_SERIAL_CONTROL);
  1842. pscr |= SERIAL_PORT_ENABLE;
  1843. wrlp(mp, PORT_SERIAL_CONTROL, pscr);
  1844. pscr |= DO_NOT_FORCE_LINK_FAIL;
  1845. if (mp->phy == NULL)
  1846. pscr |= FORCE_LINK_PASS;
  1847. wrlp(mp, PORT_SERIAL_CONTROL, pscr);
  1848. /*
  1849. * Configure TX path and queues.
  1850. */
  1851. tx_set_rate(mp, 1000000000, 16777216);
  1852. for (i = 0; i < mp->txq_count; i++) {
  1853. struct tx_queue *txq = mp->txq + i;
  1854. txq_reset_hw_ptr(txq);
  1855. txq_set_rate(txq, 1000000000, 16777216);
  1856. txq_set_fixed_prio_mode(txq);
  1857. }
  1858. /*
  1859. * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
  1860. * frames to RX queue #0, and include the pseudo-header when
  1861. * calculating receive checksums.
  1862. */
  1863. wrlp(mp, PORT_CONFIG, 0x02000000);
  1864. /*
  1865. * Treat BPDUs as normal multicasts, and disable partition mode.
  1866. */
  1867. wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
  1868. /*
  1869. * Add configured unicast addresses to address filter table.
  1870. */
  1871. mv643xx_eth_program_unicast_filter(mp->dev);
  1872. /*
  1873. * Enable the receive queues.
  1874. */
  1875. for (i = 0; i < mp->rxq_count; i++) {
  1876. struct rx_queue *rxq = mp->rxq + i;
  1877. u32 addr;
  1878. addr = (u32)rxq->rx_desc_dma;
  1879. addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
  1880. wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
  1881. rxq_enable(rxq);
  1882. }
  1883. }
  1884. static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
  1885. {
  1886. int skb_size;
  1887. /*
  1888. * Reserve 2+14 bytes for an ethernet header (the hardware
  1889. * automatically prepends 2 bytes of dummy data to each
  1890. * received packet), 16 bytes for up to four VLAN tags, and
  1891. * 4 bytes for the trailing FCS -- 36 bytes total.
  1892. */
  1893. skb_size = mp->dev->mtu + 36;
  1894. /*
  1895. * Make sure that the skb size is a multiple of 8 bytes, as
  1896. * the lower three bits of the receive descriptor's buffer
  1897. * size field are ignored by the hardware.
  1898. */
  1899. mp->skb_size = (skb_size + 7) & ~7;
  1900. /*
  1901. * If NET_SKB_PAD is smaller than a cache line,
  1902. * netdev_alloc_skb() will cause skb->data to be misaligned
  1903. * to a cache line boundary. If this is the case, include
  1904. * some extra space to allow re-aligning the data area.
  1905. */
  1906. mp->skb_size += SKB_DMA_REALIGN;
  1907. }
  1908. static int mv643xx_eth_open(struct net_device *dev)
  1909. {
  1910. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1911. int err;
  1912. int i;
  1913. wrlp(mp, INT_CAUSE, 0);
  1914. wrlp(mp, INT_CAUSE_EXT, 0);
  1915. rdlp(mp, INT_CAUSE_EXT);
  1916. err = request_irq(dev->irq, mv643xx_eth_irq,
  1917. IRQF_SHARED, dev->name, dev);
  1918. if (err) {
  1919. dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
  1920. return -EAGAIN;
  1921. }
  1922. mv643xx_eth_recalc_skb_size(mp);
  1923. napi_enable(&mp->napi);
  1924. skb_queue_head_init(&mp->rx_recycle);
  1925. mp->int_mask = INT_EXT;
  1926. for (i = 0; i < mp->rxq_count; i++) {
  1927. err = rxq_init(mp, i);
  1928. if (err) {
  1929. while (--i >= 0)
  1930. rxq_deinit(mp->rxq + i);
  1931. goto out;
  1932. }
  1933. rxq_refill(mp->rxq + i, INT_MAX);
  1934. mp->int_mask |= INT_RX_0 << i;
  1935. }
  1936. if (mp->oom) {
  1937. mp->rx_oom.expires = jiffies + (HZ / 10);
  1938. add_timer(&mp->rx_oom);
  1939. }
  1940. for (i = 0; i < mp->txq_count; i++) {
  1941. err = txq_init(mp, i);
  1942. if (err) {
  1943. while (--i >= 0)
  1944. txq_deinit(mp->txq + i);
  1945. goto out_free;
  1946. }
  1947. mp->int_mask |= INT_TX_END_0 << i;
  1948. }
  1949. port_start(mp);
  1950. wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
  1951. wrlp(mp, INT_MASK, mp->int_mask);
  1952. return 0;
  1953. out_free:
  1954. for (i = 0; i < mp->rxq_count; i++)
  1955. rxq_deinit(mp->rxq + i);
  1956. out:
  1957. free_irq(dev->irq, dev);
  1958. return err;
  1959. }
  1960. static void port_reset(struct mv643xx_eth_private *mp)
  1961. {
  1962. unsigned int data;
  1963. int i;
  1964. for (i = 0; i < mp->rxq_count; i++)
  1965. rxq_disable(mp->rxq + i);
  1966. for (i = 0; i < mp->txq_count; i++)
  1967. txq_disable(mp->txq + i);
  1968. while (1) {
  1969. u32 ps = rdlp(mp, PORT_STATUS);
  1970. if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
  1971. break;
  1972. udelay(10);
  1973. }
  1974. /* Reset the Enable bit in the Configuration Register */
  1975. data = rdlp(mp, PORT_SERIAL_CONTROL);
  1976. data &= ~(SERIAL_PORT_ENABLE |
  1977. DO_NOT_FORCE_LINK_FAIL |
  1978. FORCE_LINK_PASS);
  1979. wrlp(mp, PORT_SERIAL_CONTROL, data);
  1980. }
  1981. static int mv643xx_eth_stop(struct net_device *dev)
  1982. {
  1983. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1984. int i;
  1985. wrlp(mp, INT_MASK_EXT, 0x00000000);
  1986. wrlp(mp, INT_MASK, 0x00000000);
  1987. rdlp(mp, INT_MASK);
  1988. napi_disable(&mp->napi);
  1989. del_timer_sync(&mp->rx_oom);
  1990. netif_carrier_off(dev);
  1991. free_irq(dev->irq, dev);
  1992. port_reset(mp);
  1993. mv643xx_eth_get_stats(dev);
  1994. mib_counters_update(mp);
  1995. del_timer_sync(&mp->mib_counters_timer);
  1996. skb_queue_purge(&mp->rx_recycle);
  1997. for (i = 0; i < mp->rxq_count; i++)
  1998. rxq_deinit(mp->rxq + i);
  1999. for (i = 0; i < mp->txq_count; i++)
  2000. txq_deinit(mp->txq + i);
  2001. return 0;
  2002. }
  2003. static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  2004. {
  2005. struct mv643xx_eth_private *mp = netdev_priv(dev);
  2006. if (mp->phy != NULL)
  2007. return phy_mii_ioctl(mp->phy, ifr, cmd);
  2008. return -EOPNOTSUPP;
  2009. }
  2010. static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
  2011. {
  2012. struct mv643xx_eth_private *mp = netdev_priv(dev);
  2013. if (new_mtu < 64 || new_mtu > 9500)
  2014. return -EINVAL;
  2015. dev->mtu = new_mtu;
  2016. mv643xx_eth_recalc_skb_size(mp);
  2017. tx_set_rate(mp, 1000000000, 16777216);
  2018. if (!netif_running(dev))
  2019. return 0;
  2020. /*
  2021. * Stop and then re-open the interface. This will allocate RX
  2022. * skbs of the new MTU.
  2023. * There is a possible danger that the open will not succeed,
  2024. * due to memory being full.
  2025. */
  2026. mv643xx_eth_stop(dev);
  2027. if (mv643xx_eth_open(dev)) {
  2028. dev_printk(KERN_ERR, &dev->dev,
  2029. "fatal error on re-opening device after "
  2030. "MTU change\n");
  2031. }
  2032. return 0;
  2033. }
  2034. static void tx_timeout_task(struct work_struct *ugly)
  2035. {
  2036. struct mv643xx_eth_private *mp;
  2037. mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
  2038. if (netif_running(mp->dev)) {
  2039. netif_tx_stop_all_queues(mp->dev);
  2040. port_reset(mp);
  2041. port_start(mp);
  2042. netif_tx_wake_all_queues(mp->dev);
  2043. }
  2044. }
  2045. static void mv643xx_eth_tx_timeout(struct net_device *dev)
  2046. {
  2047. struct mv643xx_eth_private *mp = netdev_priv(dev);
  2048. dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
  2049. schedule_work(&mp->tx_timeout_task);
  2050. }
  2051. #ifdef CONFIG_NET_POLL_CONTROLLER
  2052. static void mv643xx_eth_netpoll(struct net_device *dev)
  2053. {
  2054. struct mv643xx_eth_private *mp = netdev_priv(dev);
  2055. wrlp(mp, INT_MASK, 0x00000000);
  2056. rdlp(mp, INT_MASK);
  2057. mv643xx_eth_irq(dev->irq, dev);
  2058. wrlp(mp, INT_MASK, mp->int_mask);
  2059. }
  2060. #endif
  2061. /* platform glue ************************************************************/
  2062. static void
  2063. mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
  2064. struct mbus_dram_target_info *dram)
  2065. {
  2066. void __iomem *base = msp->base;
  2067. u32 win_enable;
  2068. u32 win_protect;
  2069. int i;
  2070. for (i = 0; i < 6; i++) {
  2071. writel(0, base + WINDOW_BASE(i));
  2072. writel(0, base + WINDOW_SIZE(i));
  2073. if (i < 4)
  2074. writel(0, base + WINDOW_REMAP_HIGH(i));
  2075. }
  2076. win_enable = 0x3f;
  2077. win_protect = 0;
  2078. for (i = 0; i < dram->num_cs; i++) {
  2079. struct mbus_dram_window *cs = dram->cs + i;
  2080. writel((cs->base & 0xffff0000) |
  2081. (cs->mbus_attr << 8) |
  2082. dram->mbus_dram_target_id, base + WINDOW_BASE(i));
  2083. writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
  2084. win_enable &= ~(1 << i);
  2085. win_protect |= 3 << (2 * i);
  2086. }
  2087. writel(win_enable, base + WINDOW_BAR_ENABLE);
  2088. msp->win_protect = win_protect;
  2089. }
  2090. static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
  2091. {
  2092. /*
  2093. * Check whether we have a 14-bit coal limit field in bits
  2094. * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
  2095. * SDMA config register.
  2096. */
  2097. writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
  2098. if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
  2099. msp->extended_rx_coal_limit = 1;
  2100. else
  2101. msp->extended_rx_coal_limit = 0;
  2102. /*
  2103. * Check whether the MAC supports TX rate control, and if
  2104. * yes, whether its associated registers are in the old or
  2105. * the new place.
  2106. */
  2107. writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
  2108. if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
  2109. msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
  2110. } else {
  2111. writel(7, msp->base + 0x0400 + TX_BW_RATE);
  2112. if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
  2113. msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
  2114. else
  2115. msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
  2116. }
  2117. }
  2118. static int mv643xx_eth_shared_probe(struct platform_device *pdev)
  2119. {
  2120. static int mv643xx_eth_version_printed;
  2121. struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
  2122. struct mv643xx_eth_shared_private *msp;
  2123. struct resource *res;
  2124. int ret;
  2125. if (!mv643xx_eth_version_printed++)
  2126. printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
  2127. "driver version %s\n", mv643xx_eth_driver_version);
  2128. ret = -EINVAL;
  2129. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2130. if (res == NULL)
  2131. goto out;
  2132. ret = -ENOMEM;
  2133. msp = kzalloc(sizeof(*msp), GFP_KERNEL);
  2134. if (msp == NULL)
  2135. goto out;
  2136. msp->base = ioremap(res->start, res->end - res->start + 1);
  2137. if (msp->base == NULL)
  2138. goto out_free;
  2139. /*
  2140. * Set up and register SMI bus.
  2141. */
  2142. if (pd == NULL || pd->shared_smi == NULL) {
  2143. msp->smi_bus = mdiobus_alloc();
  2144. if (msp->smi_bus == NULL)
  2145. goto out_unmap;
  2146. msp->smi_bus->priv = msp;
  2147. msp->smi_bus->name = "mv643xx_eth smi";
  2148. msp->smi_bus->read = smi_bus_read;
  2149. msp->smi_bus->write = smi_bus_write,
  2150. snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
  2151. msp->smi_bus->parent = &pdev->dev;
  2152. msp->smi_bus->phy_mask = 0xffffffff;
  2153. if (mdiobus_register(msp->smi_bus) < 0)
  2154. goto out_free_mii_bus;
  2155. msp->smi = msp;
  2156. } else {
  2157. msp->smi = platform_get_drvdata(pd->shared_smi);
  2158. }
  2159. msp->err_interrupt = NO_IRQ;
  2160. init_waitqueue_head(&msp->smi_busy_wait);
  2161. /*
  2162. * Check whether the error interrupt is hooked up.
  2163. */
  2164. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  2165. if (res != NULL) {
  2166. int err;
  2167. err = request_irq(res->start, mv643xx_eth_err_irq,
  2168. IRQF_SHARED, "mv643xx_eth", msp);
  2169. if (!err) {
  2170. writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
  2171. msp->err_interrupt = res->start;
  2172. }
  2173. }
  2174. /*
  2175. * (Re-)program MBUS remapping windows if we are asked to.
  2176. */
  2177. if (pd != NULL && pd->dram != NULL)
  2178. mv643xx_eth_conf_mbus_windows(msp, pd->dram);
  2179. /*
  2180. * Detect hardware parameters.
  2181. */
  2182. msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
  2183. msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
  2184. pd->tx_csum_limit : 9 * 1024;
  2185. infer_hw_params(msp);
  2186. platform_set_drvdata(pdev, msp);
  2187. return 0;
  2188. out_free_mii_bus:
  2189. mdiobus_free(msp->smi_bus);
  2190. out_unmap:
  2191. iounmap(msp->base);
  2192. out_free:
  2193. kfree(msp);
  2194. out:
  2195. return ret;
  2196. }
  2197. static int mv643xx_eth_shared_remove(struct platform_device *pdev)
  2198. {
  2199. struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
  2200. struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
  2201. if (pd == NULL || pd->shared_smi == NULL) {
  2202. mdiobus_unregister(msp->smi_bus);
  2203. mdiobus_free(msp->smi_bus);
  2204. }
  2205. if (msp->err_interrupt != NO_IRQ)
  2206. free_irq(msp->err_interrupt, msp);
  2207. iounmap(msp->base);
  2208. kfree(msp);
  2209. return 0;
  2210. }
  2211. static struct platform_driver mv643xx_eth_shared_driver = {
  2212. .probe = mv643xx_eth_shared_probe,
  2213. .remove = mv643xx_eth_shared_remove,
  2214. .driver = {
  2215. .name = MV643XX_ETH_SHARED_NAME,
  2216. .owner = THIS_MODULE,
  2217. },
  2218. };
  2219. static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
  2220. {
  2221. int addr_shift = 5 * mp->port_num;
  2222. u32 data;
  2223. data = rdl(mp, PHY_ADDR);
  2224. data &= ~(0x1f << addr_shift);
  2225. data |= (phy_addr & 0x1f) << addr_shift;
  2226. wrl(mp, PHY_ADDR, data);
  2227. }
  2228. static int phy_addr_get(struct mv643xx_eth_private *mp)
  2229. {
  2230. unsigned int data;
  2231. data = rdl(mp, PHY_ADDR);
  2232. return (data >> (5 * mp->port_num)) & 0x1f;
  2233. }
  2234. static void set_params(struct mv643xx_eth_private *mp,
  2235. struct mv643xx_eth_platform_data *pd)
  2236. {
  2237. struct net_device *dev = mp->dev;
  2238. if (is_valid_ether_addr(pd->mac_addr))
  2239. memcpy(dev->dev_addr, pd->mac_addr, 6);
  2240. else
  2241. uc_addr_get(mp, dev->dev_addr);
  2242. mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
  2243. if (pd->rx_queue_size)
  2244. mp->rx_ring_size = pd->rx_queue_size;
  2245. mp->rx_desc_sram_addr = pd->rx_sram_addr;
  2246. mp->rx_desc_sram_size = pd->rx_sram_size;
  2247. mp->rxq_count = pd->rx_queue_count ? : 1;
  2248. mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
  2249. if (pd->tx_queue_size)
  2250. mp->tx_ring_size = pd->tx_queue_size;
  2251. mp->tx_desc_sram_addr = pd->tx_sram_addr;
  2252. mp->tx_desc_sram_size = pd->tx_sram_size;
  2253. mp->txq_count = pd->tx_queue_count ? : 1;
  2254. }
  2255. static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
  2256. int phy_addr)
  2257. {
  2258. struct mii_bus *bus = mp->shared->smi->smi_bus;
  2259. struct phy_device *phydev;
  2260. int start;
  2261. int num;
  2262. int i;
  2263. if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
  2264. start = phy_addr_get(mp) & 0x1f;
  2265. num = 32;
  2266. } else {
  2267. start = phy_addr & 0x1f;
  2268. num = 1;
  2269. }
  2270. phydev = NULL;
  2271. for (i = 0; i < num; i++) {
  2272. int addr = (start + i) & 0x1f;
  2273. if (bus->phy_map[addr] == NULL)
  2274. mdiobus_scan(bus, addr);
  2275. if (phydev == NULL) {
  2276. phydev = bus->phy_map[addr];
  2277. if (phydev != NULL)
  2278. phy_addr_set(mp, addr);
  2279. }
  2280. }
  2281. return phydev;
  2282. }
  2283. static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
  2284. {
  2285. struct phy_device *phy = mp->phy;
  2286. phy_reset(mp);
  2287. phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
  2288. if (speed == 0) {
  2289. phy->autoneg = AUTONEG_ENABLE;
  2290. phy->speed = 0;
  2291. phy->duplex = 0;
  2292. phy->advertising = phy->supported | ADVERTISED_Autoneg;
  2293. } else {
  2294. phy->autoneg = AUTONEG_DISABLE;
  2295. phy->advertising = 0;
  2296. phy->speed = speed;
  2297. phy->duplex = duplex;
  2298. }
  2299. phy_start_aneg(phy);
  2300. }
  2301. static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
  2302. {
  2303. u32 pscr;
  2304. pscr = rdlp(mp, PORT_SERIAL_CONTROL);
  2305. if (pscr & SERIAL_PORT_ENABLE) {
  2306. pscr &= ~SERIAL_PORT_ENABLE;
  2307. wrlp(mp, PORT_SERIAL_CONTROL, pscr);
  2308. }
  2309. pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
  2310. if (mp->phy == NULL) {
  2311. pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
  2312. if (speed == SPEED_1000)
  2313. pscr |= SET_GMII_SPEED_TO_1000;
  2314. else if (speed == SPEED_100)
  2315. pscr |= SET_MII_SPEED_TO_100;
  2316. pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
  2317. pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
  2318. if (duplex == DUPLEX_FULL)
  2319. pscr |= SET_FULL_DUPLEX_MODE;
  2320. }
  2321. wrlp(mp, PORT_SERIAL_CONTROL, pscr);
  2322. }
  2323. static const struct net_device_ops mv643xx_eth_netdev_ops = {
  2324. .ndo_open = mv643xx_eth_open,
  2325. .ndo_stop = mv643xx_eth_stop,
  2326. .ndo_start_xmit = mv643xx_eth_xmit,
  2327. .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
  2328. .ndo_set_mac_address = mv643xx_eth_set_mac_address,
  2329. .ndo_validate_addr = eth_validate_addr,
  2330. .ndo_do_ioctl = mv643xx_eth_ioctl,
  2331. .ndo_change_mtu = mv643xx_eth_change_mtu,
  2332. .ndo_tx_timeout = mv643xx_eth_tx_timeout,
  2333. .ndo_get_stats = mv643xx_eth_get_stats,
  2334. #ifdef CONFIG_NET_POLL_CONTROLLER
  2335. .ndo_poll_controller = mv643xx_eth_netpoll,
  2336. #endif
  2337. };
  2338. static int mv643xx_eth_probe(struct platform_device *pdev)
  2339. {
  2340. struct mv643xx_eth_platform_data *pd;
  2341. struct mv643xx_eth_private *mp;
  2342. struct net_device *dev;
  2343. struct resource *res;
  2344. int err;
  2345. pd = pdev->dev.platform_data;
  2346. if (pd == NULL) {
  2347. dev_printk(KERN_ERR, &pdev->dev,
  2348. "no mv643xx_eth_platform_data\n");
  2349. return -ENODEV;
  2350. }
  2351. if (pd->shared == NULL) {
  2352. dev_printk(KERN_ERR, &pdev->dev,
  2353. "no mv643xx_eth_platform_data->shared\n");
  2354. return -ENODEV;
  2355. }
  2356. dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
  2357. if (!dev)
  2358. return -ENOMEM;
  2359. mp = netdev_priv(dev);
  2360. platform_set_drvdata(pdev, mp);
  2361. mp->shared = platform_get_drvdata(pd->shared);
  2362. mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
  2363. mp->port_num = pd->port_number;
  2364. mp->dev = dev;
  2365. set_params(mp, pd);
  2366. dev->real_num_tx_queues = mp->txq_count;
  2367. if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
  2368. mp->phy = phy_scan(mp, pd->phy_addr);
  2369. if (mp->phy != NULL)
  2370. phy_init(mp, pd->speed, pd->duplex);
  2371. SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
  2372. init_pscr(mp, pd->speed, pd->duplex);
  2373. mib_counters_clear(mp);
  2374. init_timer(&mp->mib_counters_timer);
  2375. mp->mib_counters_timer.data = (unsigned long)mp;
  2376. mp->mib_counters_timer.function = mib_counters_timer_wrapper;
  2377. mp->mib_counters_timer.expires = jiffies + 30 * HZ;
  2378. add_timer(&mp->mib_counters_timer);
  2379. spin_lock_init(&mp->mib_counters_lock);
  2380. INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
  2381. netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
  2382. init_timer(&mp->rx_oom);
  2383. mp->rx_oom.data = (unsigned long)mp;
  2384. mp->rx_oom.function = oom_timer_wrapper;
  2385. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  2386. BUG_ON(!res);
  2387. dev->irq = res->start;
  2388. dev->netdev_ops = &mv643xx_eth_netdev_ops;
  2389. dev->watchdog_timeo = 2 * HZ;
  2390. dev->base_addr = 0;
  2391. dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
  2392. dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
  2393. SET_NETDEV_DEV(dev, &pdev->dev);
  2394. if (mp->shared->win_protect)
  2395. wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
  2396. netif_carrier_off(dev);
  2397. wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
  2398. set_rx_coal(mp, 250);
  2399. set_tx_coal(mp, 0);
  2400. err = register_netdev(dev);
  2401. if (err)
  2402. goto out;
  2403. dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
  2404. mp->port_num, dev->dev_addr);
  2405. if (mp->tx_desc_sram_size > 0)
  2406. dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
  2407. return 0;
  2408. out:
  2409. free_netdev(dev);
  2410. return err;
  2411. }
  2412. static int mv643xx_eth_remove(struct platform_device *pdev)
  2413. {
  2414. struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
  2415. unregister_netdev(mp->dev);
  2416. if (mp->phy != NULL)
  2417. phy_detach(mp->phy);
  2418. flush_scheduled_work();
  2419. free_netdev(mp->dev);
  2420. platform_set_drvdata(pdev, NULL);
  2421. return 0;
  2422. }
  2423. static void mv643xx_eth_shutdown(struct platform_device *pdev)
  2424. {
  2425. struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
  2426. /* Mask all interrupts on ethernet port */
  2427. wrlp(mp, INT_MASK, 0);
  2428. rdlp(mp, INT_MASK);
  2429. if (netif_running(mp->dev))
  2430. port_reset(mp);
  2431. }
  2432. static struct platform_driver mv643xx_eth_driver = {
  2433. .probe = mv643xx_eth_probe,
  2434. .remove = mv643xx_eth_remove,
  2435. .shutdown = mv643xx_eth_shutdown,
  2436. .driver = {
  2437. .name = MV643XX_ETH_NAME,
  2438. .owner = THIS_MODULE,
  2439. },
  2440. };
  2441. static int __init mv643xx_eth_init_module(void)
  2442. {
  2443. int rc;
  2444. rc = platform_driver_register(&mv643xx_eth_shared_driver);
  2445. if (!rc) {
  2446. rc = platform_driver_register(&mv643xx_eth_driver);
  2447. if (rc)
  2448. platform_driver_unregister(&mv643xx_eth_shared_driver);
  2449. }
  2450. return rc;
  2451. }
  2452. module_init(mv643xx_eth_init_module);
  2453. static void __exit mv643xx_eth_cleanup_module(void)
  2454. {
  2455. platform_driver_unregister(&mv643xx_eth_driver);
  2456. platform_driver_unregister(&mv643xx_eth_shared_driver);
  2457. }
  2458. module_exit(mv643xx_eth_cleanup_module);
  2459. MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
  2460. "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
  2461. MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
  2462. MODULE_LICENSE("GPL");
  2463. MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
  2464. MODULE_ALIAS("platform:" MV643XX_ETH_NAME);