forcedeth.c 189 KB

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  1. /*
  2. * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
  3. *
  4. * Note: This driver is a cleanroom reimplementation based on reverse
  5. * engineered documentation written by Carl-Daniel Hailfinger
  6. * and Andrew de Quincey.
  7. *
  8. * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  9. * trademarks of NVIDIA Corporation in the United States and other
  10. * countries.
  11. *
  12. * Copyright (C) 2003,4,5 Manfred Spraul
  13. * Copyright (C) 2004 Andrew de Quincey (wol support)
  14. * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15. * IRQ rate fixes, bigendian fixes, cleanups, verification)
  16. * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. * Known bugs:
  33. * We suspect that on some hardware no TX done interrupts are generated.
  34. * This means recovery from netif_stop_queue only happens if the hw timer
  35. * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36. * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37. * If your hardware reliably generates tx done interrupts, then you can remove
  38. * DEV_NEED_TIMERIRQ from the driver_data flags.
  39. * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40. * superfluous timer interrupts from the nic.
  41. */
  42. #define FORCEDETH_VERSION "0.64"
  43. #define DRV_NAME "forcedeth"
  44. #include <linux/module.h>
  45. #include <linux/types.h>
  46. #include <linux/pci.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/netdevice.h>
  49. #include <linux/etherdevice.h>
  50. #include <linux/delay.h>
  51. #include <linux/sched.h>
  52. #include <linux/spinlock.h>
  53. #include <linux/ethtool.h>
  54. #include <linux/timer.h>
  55. #include <linux/skbuff.h>
  56. #include <linux/mii.h>
  57. #include <linux/random.h>
  58. #include <linux/init.h>
  59. #include <linux/if_vlan.h>
  60. #include <linux/dma-mapping.h>
  61. #include <linux/slab.h>
  62. #include <asm/irq.h>
  63. #include <asm/io.h>
  64. #include <asm/uaccess.h>
  65. #include <asm/system.h>
  66. #if 0
  67. #define dprintk printk
  68. #else
  69. #define dprintk(x...) do { } while (0)
  70. #endif
  71. #define TX_WORK_PER_LOOP 64
  72. #define RX_WORK_PER_LOOP 64
  73. /*
  74. * Hardware access:
  75. */
  76. #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
  77. #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
  78. #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
  79. #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
  80. #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
  81. #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
  82. #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
  83. #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
  84. #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
  85. #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
  86. #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
  87. #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
  88. #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
  89. #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
  90. #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
  91. #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
  92. #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
  93. #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
  94. #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
  95. #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
  96. #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
  97. #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
  98. #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
  99. #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
  100. #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
  101. #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
  102. #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
  103. enum {
  104. NvRegIrqStatus = 0x000,
  105. #define NVREG_IRQSTAT_MIIEVENT 0x040
  106. #define NVREG_IRQSTAT_MASK 0x83ff
  107. NvRegIrqMask = 0x004,
  108. #define NVREG_IRQ_RX_ERROR 0x0001
  109. #define NVREG_IRQ_RX 0x0002
  110. #define NVREG_IRQ_RX_NOBUF 0x0004
  111. #define NVREG_IRQ_TX_ERR 0x0008
  112. #define NVREG_IRQ_TX_OK 0x0010
  113. #define NVREG_IRQ_TIMER 0x0020
  114. #define NVREG_IRQ_LINK 0x0040
  115. #define NVREG_IRQ_RX_FORCED 0x0080
  116. #define NVREG_IRQ_TX_FORCED 0x0100
  117. #define NVREG_IRQ_RECOVER_ERROR 0x8200
  118. #define NVREG_IRQMASK_THROUGHPUT 0x00df
  119. #define NVREG_IRQMASK_CPU 0x0060
  120. #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
  121. #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
  122. #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
  123. NvRegUnknownSetupReg6 = 0x008,
  124. #define NVREG_UNKSETUP6_VAL 3
  125. /*
  126. * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
  127. * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
  128. */
  129. NvRegPollingInterval = 0x00c,
  130. #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
  131. #define NVREG_POLL_DEFAULT_CPU 13
  132. NvRegMSIMap0 = 0x020,
  133. NvRegMSIMap1 = 0x024,
  134. NvRegMSIIrqMask = 0x030,
  135. #define NVREG_MSI_VECTOR_0_ENABLED 0x01
  136. NvRegMisc1 = 0x080,
  137. #define NVREG_MISC1_PAUSE_TX 0x01
  138. #define NVREG_MISC1_HD 0x02
  139. #define NVREG_MISC1_FORCE 0x3b0f3c
  140. NvRegMacReset = 0x34,
  141. #define NVREG_MAC_RESET_ASSERT 0x0F3
  142. NvRegTransmitterControl = 0x084,
  143. #define NVREG_XMITCTL_START 0x01
  144. #define NVREG_XMITCTL_MGMT_ST 0x40000000
  145. #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
  146. #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
  147. #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
  148. #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
  149. #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
  150. #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
  151. #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
  152. #define NVREG_XMITCTL_HOST_LOADED 0x00004000
  153. #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
  154. #define NVREG_XMITCTL_DATA_START 0x00100000
  155. #define NVREG_XMITCTL_DATA_READY 0x00010000
  156. #define NVREG_XMITCTL_DATA_ERROR 0x00020000
  157. NvRegTransmitterStatus = 0x088,
  158. #define NVREG_XMITSTAT_BUSY 0x01
  159. NvRegPacketFilterFlags = 0x8c,
  160. #define NVREG_PFF_PAUSE_RX 0x08
  161. #define NVREG_PFF_ALWAYS 0x7F0000
  162. #define NVREG_PFF_PROMISC 0x80
  163. #define NVREG_PFF_MYADDR 0x20
  164. #define NVREG_PFF_LOOPBACK 0x10
  165. NvRegOffloadConfig = 0x90,
  166. #define NVREG_OFFLOAD_HOMEPHY 0x601
  167. #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
  168. NvRegReceiverControl = 0x094,
  169. #define NVREG_RCVCTL_START 0x01
  170. #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
  171. NvRegReceiverStatus = 0x98,
  172. #define NVREG_RCVSTAT_BUSY 0x01
  173. NvRegSlotTime = 0x9c,
  174. #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
  175. #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
  176. #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
  177. #define NVREG_SLOTTIME_HALF 0x0000ff00
  178. #define NVREG_SLOTTIME_DEFAULT 0x00007f00
  179. #define NVREG_SLOTTIME_MASK 0x000000ff
  180. NvRegTxDeferral = 0xA0,
  181. #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
  182. #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
  183. #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
  184. #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
  185. #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
  186. #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
  187. NvRegRxDeferral = 0xA4,
  188. #define NVREG_RX_DEFERRAL_DEFAULT 0x16
  189. NvRegMacAddrA = 0xA8,
  190. NvRegMacAddrB = 0xAC,
  191. NvRegMulticastAddrA = 0xB0,
  192. #define NVREG_MCASTADDRA_FORCE 0x01
  193. NvRegMulticastAddrB = 0xB4,
  194. NvRegMulticastMaskA = 0xB8,
  195. #define NVREG_MCASTMASKA_NONE 0xffffffff
  196. NvRegMulticastMaskB = 0xBC,
  197. #define NVREG_MCASTMASKB_NONE 0xffff
  198. NvRegPhyInterface = 0xC0,
  199. #define PHY_RGMII 0x10000000
  200. NvRegBackOffControl = 0xC4,
  201. #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
  202. #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
  203. #define NVREG_BKOFFCTRL_SELECT 24
  204. #define NVREG_BKOFFCTRL_GEAR 12
  205. NvRegTxRingPhysAddr = 0x100,
  206. NvRegRxRingPhysAddr = 0x104,
  207. NvRegRingSizes = 0x108,
  208. #define NVREG_RINGSZ_TXSHIFT 0
  209. #define NVREG_RINGSZ_RXSHIFT 16
  210. NvRegTransmitPoll = 0x10c,
  211. #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
  212. NvRegLinkSpeed = 0x110,
  213. #define NVREG_LINKSPEED_FORCE 0x10000
  214. #define NVREG_LINKSPEED_10 1000
  215. #define NVREG_LINKSPEED_100 100
  216. #define NVREG_LINKSPEED_1000 50
  217. #define NVREG_LINKSPEED_MASK (0xFFF)
  218. NvRegUnknownSetupReg5 = 0x130,
  219. #define NVREG_UNKSETUP5_BIT31 (1<<31)
  220. NvRegTxWatermark = 0x13c,
  221. #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
  222. #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
  223. #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
  224. NvRegTxRxControl = 0x144,
  225. #define NVREG_TXRXCTL_KICK 0x0001
  226. #define NVREG_TXRXCTL_BIT1 0x0002
  227. #define NVREG_TXRXCTL_BIT2 0x0004
  228. #define NVREG_TXRXCTL_IDLE 0x0008
  229. #define NVREG_TXRXCTL_RESET 0x0010
  230. #define NVREG_TXRXCTL_RXCHECK 0x0400
  231. #define NVREG_TXRXCTL_DESC_1 0
  232. #define NVREG_TXRXCTL_DESC_2 0x002100
  233. #define NVREG_TXRXCTL_DESC_3 0xc02200
  234. #define NVREG_TXRXCTL_VLANSTRIP 0x00040
  235. #define NVREG_TXRXCTL_VLANINS 0x00080
  236. NvRegTxRingPhysAddrHigh = 0x148,
  237. NvRegRxRingPhysAddrHigh = 0x14C,
  238. NvRegTxPauseFrame = 0x170,
  239. #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
  240. #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
  241. #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
  242. #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
  243. NvRegTxPauseFrameLimit = 0x174,
  244. #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
  245. NvRegMIIStatus = 0x180,
  246. #define NVREG_MIISTAT_ERROR 0x0001
  247. #define NVREG_MIISTAT_LINKCHANGE 0x0008
  248. #define NVREG_MIISTAT_MASK_RW 0x0007
  249. #define NVREG_MIISTAT_MASK_ALL 0x000f
  250. NvRegMIIMask = 0x184,
  251. #define NVREG_MII_LINKCHANGE 0x0008
  252. NvRegAdapterControl = 0x188,
  253. #define NVREG_ADAPTCTL_START 0x02
  254. #define NVREG_ADAPTCTL_LINKUP 0x04
  255. #define NVREG_ADAPTCTL_PHYVALID 0x40000
  256. #define NVREG_ADAPTCTL_RUNNING 0x100000
  257. #define NVREG_ADAPTCTL_PHYSHIFT 24
  258. NvRegMIISpeed = 0x18c,
  259. #define NVREG_MIISPEED_BIT8 (1<<8)
  260. #define NVREG_MIIDELAY 5
  261. NvRegMIIControl = 0x190,
  262. #define NVREG_MIICTL_INUSE 0x08000
  263. #define NVREG_MIICTL_WRITE 0x00400
  264. #define NVREG_MIICTL_ADDRSHIFT 5
  265. NvRegMIIData = 0x194,
  266. NvRegTxUnicast = 0x1a0,
  267. NvRegTxMulticast = 0x1a4,
  268. NvRegTxBroadcast = 0x1a8,
  269. NvRegWakeUpFlags = 0x200,
  270. #define NVREG_WAKEUPFLAGS_VAL 0x7770
  271. #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
  272. #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
  273. #define NVREG_WAKEUPFLAGS_D3SHIFT 12
  274. #define NVREG_WAKEUPFLAGS_D2SHIFT 8
  275. #define NVREG_WAKEUPFLAGS_D1SHIFT 4
  276. #define NVREG_WAKEUPFLAGS_D0SHIFT 0
  277. #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
  278. #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
  279. #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
  280. #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
  281. NvRegMgmtUnitGetVersion = 0x204,
  282. #define NVREG_MGMTUNITGETVERSION 0x01
  283. NvRegMgmtUnitVersion = 0x208,
  284. #define NVREG_MGMTUNITVERSION 0x08
  285. NvRegPowerCap = 0x268,
  286. #define NVREG_POWERCAP_D3SUPP (1<<30)
  287. #define NVREG_POWERCAP_D2SUPP (1<<26)
  288. #define NVREG_POWERCAP_D1SUPP (1<<25)
  289. NvRegPowerState = 0x26c,
  290. #define NVREG_POWERSTATE_POWEREDUP 0x8000
  291. #define NVREG_POWERSTATE_VALID 0x0100
  292. #define NVREG_POWERSTATE_MASK 0x0003
  293. #define NVREG_POWERSTATE_D0 0x0000
  294. #define NVREG_POWERSTATE_D1 0x0001
  295. #define NVREG_POWERSTATE_D2 0x0002
  296. #define NVREG_POWERSTATE_D3 0x0003
  297. NvRegMgmtUnitControl = 0x278,
  298. #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
  299. NvRegTxCnt = 0x280,
  300. NvRegTxZeroReXmt = 0x284,
  301. NvRegTxOneReXmt = 0x288,
  302. NvRegTxManyReXmt = 0x28c,
  303. NvRegTxLateCol = 0x290,
  304. NvRegTxUnderflow = 0x294,
  305. NvRegTxLossCarrier = 0x298,
  306. NvRegTxExcessDef = 0x29c,
  307. NvRegTxRetryErr = 0x2a0,
  308. NvRegRxFrameErr = 0x2a4,
  309. NvRegRxExtraByte = 0x2a8,
  310. NvRegRxLateCol = 0x2ac,
  311. NvRegRxRunt = 0x2b0,
  312. NvRegRxFrameTooLong = 0x2b4,
  313. NvRegRxOverflow = 0x2b8,
  314. NvRegRxFCSErr = 0x2bc,
  315. NvRegRxFrameAlignErr = 0x2c0,
  316. NvRegRxLenErr = 0x2c4,
  317. NvRegRxUnicast = 0x2c8,
  318. NvRegRxMulticast = 0x2cc,
  319. NvRegRxBroadcast = 0x2d0,
  320. NvRegTxDef = 0x2d4,
  321. NvRegTxFrame = 0x2d8,
  322. NvRegRxCnt = 0x2dc,
  323. NvRegTxPause = 0x2e0,
  324. NvRegRxPause = 0x2e4,
  325. NvRegRxDropFrame = 0x2e8,
  326. NvRegVlanControl = 0x300,
  327. #define NVREG_VLANCONTROL_ENABLE 0x2000
  328. NvRegMSIXMap0 = 0x3e0,
  329. NvRegMSIXMap1 = 0x3e4,
  330. NvRegMSIXIrqStatus = 0x3f0,
  331. NvRegPowerState2 = 0x600,
  332. #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
  333. #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
  334. #define NVREG_POWERSTATE2_PHY_RESET 0x0004
  335. #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
  336. };
  337. /* Big endian: should work, but is untested */
  338. struct ring_desc {
  339. __le32 buf;
  340. __le32 flaglen;
  341. };
  342. struct ring_desc_ex {
  343. __le32 bufhigh;
  344. __le32 buflow;
  345. __le32 txvlan;
  346. __le32 flaglen;
  347. };
  348. union ring_type {
  349. struct ring_desc* orig;
  350. struct ring_desc_ex* ex;
  351. };
  352. #define FLAG_MASK_V1 0xffff0000
  353. #define FLAG_MASK_V2 0xffffc000
  354. #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
  355. #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
  356. #define NV_TX_LASTPACKET (1<<16)
  357. #define NV_TX_RETRYERROR (1<<19)
  358. #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
  359. #define NV_TX_FORCED_INTERRUPT (1<<24)
  360. #define NV_TX_DEFERRED (1<<26)
  361. #define NV_TX_CARRIERLOST (1<<27)
  362. #define NV_TX_LATECOLLISION (1<<28)
  363. #define NV_TX_UNDERFLOW (1<<29)
  364. #define NV_TX_ERROR (1<<30)
  365. #define NV_TX_VALID (1<<31)
  366. #define NV_TX2_LASTPACKET (1<<29)
  367. #define NV_TX2_RETRYERROR (1<<18)
  368. #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
  369. #define NV_TX2_FORCED_INTERRUPT (1<<30)
  370. #define NV_TX2_DEFERRED (1<<25)
  371. #define NV_TX2_CARRIERLOST (1<<26)
  372. #define NV_TX2_LATECOLLISION (1<<27)
  373. #define NV_TX2_UNDERFLOW (1<<28)
  374. /* error and valid are the same for both */
  375. #define NV_TX2_ERROR (1<<30)
  376. #define NV_TX2_VALID (1<<31)
  377. #define NV_TX2_TSO (1<<28)
  378. #define NV_TX2_TSO_SHIFT 14
  379. #define NV_TX2_TSO_MAX_SHIFT 14
  380. #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
  381. #define NV_TX2_CHECKSUM_L3 (1<<27)
  382. #define NV_TX2_CHECKSUM_L4 (1<<26)
  383. #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
  384. #define NV_RX_DESCRIPTORVALID (1<<16)
  385. #define NV_RX_MISSEDFRAME (1<<17)
  386. #define NV_RX_SUBSTRACT1 (1<<18)
  387. #define NV_RX_ERROR1 (1<<23)
  388. #define NV_RX_ERROR2 (1<<24)
  389. #define NV_RX_ERROR3 (1<<25)
  390. #define NV_RX_ERROR4 (1<<26)
  391. #define NV_RX_CRCERR (1<<27)
  392. #define NV_RX_OVERFLOW (1<<28)
  393. #define NV_RX_FRAMINGERR (1<<29)
  394. #define NV_RX_ERROR (1<<30)
  395. #define NV_RX_AVAIL (1<<31)
  396. #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
  397. #define NV_RX2_CHECKSUMMASK (0x1C000000)
  398. #define NV_RX2_CHECKSUM_IP (0x10000000)
  399. #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
  400. #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
  401. #define NV_RX2_DESCRIPTORVALID (1<<29)
  402. #define NV_RX2_SUBSTRACT1 (1<<25)
  403. #define NV_RX2_ERROR1 (1<<18)
  404. #define NV_RX2_ERROR2 (1<<19)
  405. #define NV_RX2_ERROR3 (1<<20)
  406. #define NV_RX2_ERROR4 (1<<21)
  407. #define NV_RX2_CRCERR (1<<22)
  408. #define NV_RX2_OVERFLOW (1<<23)
  409. #define NV_RX2_FRAMINGERR (1<<24)
  410. /* error and avail are the same for both */
  411. #define NV_RX2_ERROR (1<<30)
  412. #define NV_RX2_AVAIL (1<<31)
  413. #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
  414. #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
  415. #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
  416. /* Miscelaneous hardware related defines: */
  417. #define NV_PCI_REGSZ_VER1 0x270
  418. #define NV_PCI_REGSZ_VER2 0x2d4
  419. #define NV_PCI_REGSZ_VER3 0x604
  420. #define NV_PCI_REGSZ_MAX 0x604
  421. /* various timeout delays: all in usec */
  422. #define NV_TXRX_RESET_DELAY 4
  423. #define NV_TXSTOP_DELAY1 10
  424. #define NV_TXSTOP_DELAY1MAX 500000
  425. #define NV_TXSTOP_DELAY2 100
  426. #define NV_RXSTOP_DELAY1 10
  427. #define NV_RXSTOP_DELAY1MAX 500000
  428. #define NV_RXSTOP_DELAY2 100
  429. #define NV_SETUP5_DELAY 5
  430. #define NV_SETUP5_DELAYMAX 50000
  431. #define NV_POWERUP_DELAY 5
  432. #define NV_POWERUP_DELAYMAX 5000
  433. #define NV_MIIBUSY_DELAY 50
  434. #define NV_MIIPHY_DELAY 10
  435. #define NV_MIIPHY_DELAYMAX 10000
  436. #define NV_MAC_RESET_DELAY 64
  437. #define NV_WAKEUPPATTERNS 5
  438. #define NV_WAKEUPMASKENTRIES 4
  439. /* General driver defaults */
  440. #define NV_WATCHDOG_TIMEO (5*HZ)
  441. #define RX_RING_DEFAULT 512
  442. #define TX_RING_DEFAULT 256
  443. #define RX_RING_MIN 128
  444. #define TX_RING_MIN 64
  445. #define RING_MAX_DESC_VER_1 1024
  446. #define RING_MAX_DESC_VER_2_3 16384
  447. /* rx/tx mac addr + type + vlan + align + slack*/
  448. #define NV_RX_HEADERS (64)
  449. /* even more slack. */
  450. #define NV_RX_ALLOC_PAD (64)
  451. /* maximum mtu size */
  452. #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
  453. #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
  454. #define OOM_REFILL (1+HZ/20)
  455. #define POLL_WAIT (1+HZ/100)
  456. #define LINK_TIMEOUT (3*HZ)
  457. #define STATS_INTERVAL (10*HZ)
  458. /*
  459. * desc_ver values:
  460. * The nic supports three different descriptor types:
  461. * - DESC_VER_1: Original
  462. * - DESC_VER_2: support for jumbo frames.
  463. * - DESC_VER_3: 64-bit format.
  464. */
  465. #define DESC_VER_1 1
  466. #define DESC_VER_2 2
  467. #define DESC_VER_3 3
  468. /* PHY defines */
  469. #define PHY_OUI_MARVELL 0x5043
  470. #define PHY_OUI_CICADA 0x03f1
  471. #define PHY_OUI_VITESSE 0x01c1
  472. #define PHY_OUI_REALTEK 0x0732
  473. #define PHY_OUI_REALTEK2 0x0020
  474. #define PHYID1_OUI_MASK 0x03ff
  475. #define PHYID1_OUI_SHFT 6
  476. #define PHYID2_OUI_MASK 0xfc00
  477. #define PHYID2_OUI_SHFT 10
  478. #define PHYID2_MODEL_MASK 0x03f0
  479. #define PHY_MODEL_REALTEK_8211 0x0110
  480. #define PHY_REV_MASK 0x0001
  481. #define PHY_REV_REALTEK_8211B 0x0000
  482. #define PHY_REV_REALTEK_8211C 0x0001
  483. #define PHY_MODEL_REALTEK_8201 0x0200
  484. #define PHY_MODEL_MARVELL_E3016 0x0220
  485. #define PHY_MARVELL_E3016_INITMASK 0x0300
  486. #define PHY_CICADA_INIT1 0x0f000
  487. #define PHY_CICADA_INIT2 0x0e00
  488. #define PHY_CICADA_INIT3 0x01000
  489. #define PHY_CICADA_INIT4 0x0200
  490. #define PHY_CICADA_INIT5 0x0004
  491. #define PHY_CICADA_INIT6 0x02000
  492. #define PHY_VITESSE_INIT_REG1 0x1f
  493. #define PHY_VITESSE_INIT_REG2 0x10
  494. #define PHY_VITESSE_INIT_REG3 0x11
  495. #define PHY_VITESSE_INIT_REG4 0x12
  496. #define PHY_VITESSE_INIT_MSK1 0xc
  497. #define PHY_VITESSE_INIT_MSK2 0x0180
  498. #define PHY_VITESSE_INIT1 0x52b5
  499. #define PHY_VITESSE_INIT2 0xaf8a
  500. #define PHY_VITESSE_INIT3 0x8
  501. #define PHY_VITESSE_INIT4 0x8f8a
  502. #define PHY_VITESSE_INIT5 0xaf86
  503. #define PHY_VITESSE_INIT6 0x8f86
  504. #define PHY_VITESSE_INIT7 0xaf82
  505. #define PHY_VITESSE_INIT8 0x0100
  506. #define PHY_VITESSE_INIT9 0x8f82
  507. #define PHY_VITESSE_INIT10 0x0
  508. #define PHY_REALTEK_INIT_REG1 0x1f
  509. #define PHY_REALTEK_INIT_REG2 0x19
  510. #define PHY_REALTEK_INIT_REG3 0x13
  511. #define PHY_REALTEK_INIT_REG4 0x14
  512. #define PHY_REALTEK_INIT_REG5 0x18
  513. #define PHY_REALTEK_INIT_REG6 0x11
  514. #define PHY_REALTEK_INIT_REG7 0x01
  515. #define PHY_REALTEK_INIT1 0x0000
  516. #define PHY_REALTEK_INIT2 0x8e00
  517. #define PHY_REALTEK_INIT3 0x0001
  518. #define PHY_REALTEK_INIT4 0xad17
  519. #define PHY_REALTEK_INIT5 0xfb54
  520. #define PHY_REALTEK_INIT6 0xf5c7
  521. #define PHY_REALTEK_INIT7 0x1000
  522. #define PHY_REALTEK_INIT8 0x0003
  523. #define PHY_REALTEK_INIT9 0x0008
  524. #define PHY_REALTEK_INIT10 0x0005
  525. #define PHY_REALTEK_INIT11 0x0200
  526. #define PHY_REALTEK_INIT_MSK1 0x0003
  527. #define PHY_GIGABIT 0x0100
  528. #define PHY_TIMEOUT 0x1
  529. #define PHY_ERROR 0x2
  530. #define PHY_100 0x1
  531. #define PHY_1000 0x2
  532. #define PHY_HALF 0x100
  533. #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
  534. #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
  535. #define NV_PAUSEFRAME_RX_ENABLE 0x0004
  536. #define NV_PAUSEFRAME_TX_ENABLE 0x0008
  537. #define NV_PAUSEFRAME_RX_REQ 0x0010
  538. #define NV_PAUSEFRAME_TX_REQ 0x0020
  539. #define NV_PAUSEFRAME_AUTONEG 0x0040
  540. /* MSI/MSI-X defines */
  541. #define NV_MSI_X_MAX_VECTORS 8
  542. #define NV_MSI_X_VECTORS_MASK 0x000f
  543. #define NV_MSI_CAPABLE 0x0010
  544. #define NV_MSI_X_CAPABLE 0x0020
  545. #define NV_MSI_ENABLED 0x0040
  546. #define NV_MSI_X_ENABLED 0x0080
  547. #define NV_MSI_X_VECTOR_ALL 0x0
  548. #define NV_MSI_X_VECTOR_RX 0x0
  549. #define NV_MSI_X_VECTOR_TX 0x1
  550. #define NV_MSI_X_VECTOR_OTHER 0x2
  551. #define NV_MSI_PRIV_OFFSET 0x68
  552. #define NV_MSI_PRIV_VALUE 0xffffffff
  553. #define NV_RESTART_TX 0x1
  554. #define NV_RESTART_RX 0x2
  555. #define NV_TX_LIMIT_COUNT 16
  556. #define NV_DYNAMIC_THRESHOLD 4
  557. #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
  558. /* statistics */
  559. struct nv_ethtool_str {
  560. char name[ETH_GSTRING_LEN];
  561. };
  562. static const struct nv_ethtool_str nv_estats_str[] = {
  563. { "tx_bytes" },
  564. { "tx_zero_rexmt" },
  565. { "tx_one_rexmt" },
  566. { "tx_many_rexmt" },
  567. { "tx_late_collision" },
  568. { "tx_fifo_errors" },
  569. { "tx_carrier_errors" },
  570. { "tx_excess_deferral" },
  571. { "tx_retry_error" },
  572. { "rx_frame_error" },
  573. { "rx_extra_byte" },
  574. { "rx_late_collision" },
  575. { "rx_runt" },
  576. { "rx_frame_too_long" },
  577. { "rx_over_errors" },
  578. { "rx_crc_errors" },
  579. { "rx_frame_align_error" },
  580. { "rx_length_error" },
  581. { "rx_unicast" },
  582. { "rx_multicast" },
  583. { "rx_broadcast" },
  584. { "rx_packets" },
  585. { "rx_errors_total" },
  586. { "tx_errors_total" },
  587. /* version 2 stats */
  588. { "tx_deferral" },
  589. { "tx_packets" },
  590. { "rx_bytes" },
  591. { "tx_pause" },
  592. { "rx_pause" },
  593. { "rx_drop_frame" },
  594. /* version 3 stats */
  595. { "tx_unicast" },
  596. { "tx_multicast" },
  597. { "tx_broadcast" }
  598. };
  599. struct nv_ethtool_stats {
  600. u64 tx_bytes;
  601. u64 tx_zero_rexmt;
  602. u64 tx_one_rexmt;
  603. u64 tx_many_rexmt;
  604. u64 tx_late_collision;
  605. u64 tx_fifo_errors;
  606. u64 tx_carrier_errors;
  607. u64 tx_excess_deferral;
  608. u64 tx_retry_error;
  609. u64 rx_frame_error;
  610. u64 rx_extra_byte;
  611. u64 rx_late_collision;
  612. u64 rx_runt;
  613. u64 rx_frame_too_long;
  614. u64 rx_over_errors;
  615. u64 rx_crc_errors;
  616. u64 rx_frame_align_error;
  617. u64 rx_length_error;
  618. u64 rx_unicast;
  619. u64 rx_multicast;
  620. u64 rx_broadcast;
  621. u64 rx_packets;
  622. u64 rx_errors_total;
  623. u64 tx_errors_total;
  624. /* version 2 stats */
  625. u64 tx_deferral;
  626. u64 tx_packets;
  627. u64 rx_bytes;
  628. u64 tx_pause;
  629. u64 rx_pause;
  630. u64 rx_drop_frame;
  631. /* version 3 stats */
  632. u64 tx_unicast;
  633. u64 tx_multicast;
  634. u64 tx_broadcast;
  635. };
  636. #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
  637. #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
  638. #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
  639. /* diagnostics */
  640. #define NV_TEST_COUNT_BASE 3
  641. #define NV_TEST_COUNT_EXTENDED 4
  642. static const struct nv_ethtool_str nv_etests_str[] = {
  643. { "link (online/offline)" },
  644. { "register (offline) " },
  645. { "interrupt (offline) " },
  646. { "loopback (offline) " }
  647. };
  648. struct register_test {
  649. __u32 reg;
  650. __u32 mask;
  651. };
  652. static const struct register_test nv_registers_test[] = {
  653. { NvRegUnknownSetupReg6, 0x01 },
  654. { NvRegMisc1, 0x03c },
  655. { NvRegOffloadConfig, 0x03ff },
  656. { NvRegMulticastAddrA, 0xffffffff },
  657. { NvRegTxWatermark, 0x0ff },
  658. { NvRegWakeUpFlags, 0x07777 },
  659. { 0,0 }
  660. };
  661. struct nv_skb_map {
  662. struct sk_buff *skb;
  663. dma_addr_t dma;
  664. unsigned int dma_len:31;
  665. unsigned int dma_single:1;
  666. struct ring_desc_ex *first_tx_desc;
  667. struct nv_skb_map *next_tx_ctx;
  668. };
  669. /*
  670. * SMP locking:
  671. * All hardware access under netdev_priv(dev)->lock, except the performance
  672. * critical parts:
  673. * - rx is (pseudo-) lockless: it relies on the single-threading provided
  674. * by the arch code for interrupts.
  675. * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
  676. * needs netdev_priv(dev)->lock :-(
  677. * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
  678. */
  679. /* in dev: base, irq */
  680. struct fe_priv {
  681. spinlock_t lock;
  682. struct net_device *dev;
  683. struct napi_struct napi;
  684. /* General data:
  685. * Locking: spin_lock(&np->lock); */
  686. struct nv_ethtool_stats estats;
  687. int in_shutdown;
  688. u32 linkspeed;
  689. int duplex;
  690. int autoneg;
  691. int fixed_mode;
  692. int phyaddr;
  693. int wolenabled;
  694. unsigned int phy_oui;
  695. unsigned int phy_model;
  696. unsigned int phy_rev;
  697. u16 gigabit;
  698. int intr_test;
  699. int recover_error;
  700. int quiet_count;
  701. /* General data: RO fields */
  702. dma_addr_t ring_addr;
  703. struct pci_dev *pci_dev;
  704. u32 orig_mac[2];
  705. u32 events;
  706. u32 irqmask;
  707. u32 desc_ver;
  708. u32 txrxctl_bits;
  709. u32 vlanctl_bits;
  710. u32 driver_data;
  711. u32 device_id;
  712. u32 register_size;
  713. int rx_csum;
  714. u32 mac_in_use;
  715. int mgmt_version;
  716. int mgmt_sema;
  717. void __iomem *base;
  718. /* rx specific fields.
  719. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  720. */
  721. union ring_type get_rx, put_rx, first_rx, last_rx;
  722. struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
  723. struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
  724. struct nv_skb_map *rx_skb;
  725. union ring_type rx_ring;
  726. unsigned int rx_buf_sz;
  727. unsigned int pkt_limit;
  728. struct timer_list oom_kick;
  729. struct timer_list nic_poll;
  730. struct timer_list stats_poll;
  731. u32 nic_poll_irq;
  732. int rx_ring_size;
  733. /* media detection workaround.
  734. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  735. */
  736. int need_linktimer;
  737. unsigned long link_timeout;
  738. /*
  739. * tx specific fields.
  740. */
  741. union ring_type get_tx, put_tx, first_tx, last_tx;
  742. struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
  743. struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
  744. struct nv_skb_map *tx_skb;
  745. union ring_type tx_ring;
  746. u32 tx_flags;
  747. int tx_ring_size;
  748. int tx_limit;
  749. u32 tx_pkts_in_progress;
  750. struct nv_skb_map *tx_change_owner;
  751. struct nv_skb_map *tx_end_flip;
  752. int tx_stop;
  753. /* vlan fields */
  754. struct vlan_group *vlangrp;
  755. /* msi/msi-x fields */
  756. u32 msi_flags;
  757. struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
  758. /* flow control */
  759. u32 pause_flags;
  760. /* power saved state */
  761. u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
  762. /* for different msi-x irq type */
  763. char name_rx[IFNAMSIZ + 3]; /* -rx */
  764. char name_tx[IFNAMSIZ + 3]; /* -tx */
  765. char name_other[IFNAMSIZ + 6]; /* -other */
  766. };
  767. /*
  768. * Maximum number of loops until we assume that a bit in the irq mask
  769. * is stuck. Overridable with module param.
  770. */
  771. static int max_interrupt_work = 4;
  772. /*
  773. * Optimization can be either throuput mode or cpu mode
  774. *
  775. * Throughput Mode: Every tx and rx packet will generate an interrupt.
  776. * CPU Mode: Interrupts are controlled by a timer.
  777. */
  778. enum {
  779. NV_OPTIMIZATION_MODE_THROUGHPUT,
  780. NV_OPTIMIZATION_MODE_CPU,
  781. NV_OPTIMIZATION_MODE_DYNAMIC
  782. };
  783. static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
  784. /*
  785. * Poll interval for timer irq
  786. *
  787. * This interval determines how frequent an interrupt is generated.
  788. * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
  789. * Min = 0, and Max = 65535
  790. */
  791. static int poll_interval = -1;
  792. /*
  793. * MSI interrupts
  794. */
  795. enum {
  796. NV_MSI_INT_DISABLED,
  797. NV_MSI_INT_ENABLED
  798. };
  799. static int msi = NV_MSI_INT_ENABLED;
  800. /*
  801. * MSIX interrupts
  802. */
  803. enum {
  804. NV_MSIX_INT_DISABLED,
  805. NV_MSIX_INT_ENABLED
  806. };
  807. static int msix = NV_MSIX_INT_ENABLED;
  808. /*
  809. * DMA 64bit
  810. */
  811. enum {
  812. NV_DMA_64BIT_DISABLED,
  813. NV_DMA_64BIT_ENABLED
  814. };
  815. static int dma_64bit = NV_DMA_64BIT_ENABLED;
  816. /*
  817. * Crossover Detection
  818. * Realtek 8201 phy + some OEM boards do not work properly.
  819. */
  820. enum {
  821. NV_CROSSOVER_DETECTION_DISABLED,
  822. NV_CROSSOVER_DETECTION_ENABLED
  823. };
  824. static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
  825. /*
  826. * Power down phy when interface is down (persists through reboot;
  827. * older Linux and other OSes may not power it up again)
  828. */
  829. static int phy_power_down = 0;
  830. static inline struct fe_priv *get_nvpriv(struct net_device *dev)
  831. {
  832. return netdev_priv(dev);
  833. }
  834. static inline u8 __iomem *get_hwbase(struct net_device *dev)
  835. {
  836. return ((struct fe_priv *)netdev_priv(dev))->base;
  837. }
  838. static inline void pci_push(u8 __iomem *base)
  839. {
  840. /* force out pending posted writes */
  841. readl(base);
  842. }
  843. static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
  844. {
  845. return le32_to_cpu(prd->flaglen)
  846. & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
  847. }
  848. static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
  849. {
  850. return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
  851. }
  852. static bool nv_optimized(struct fe_priv *np)
  853. {
  854. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  855. return false;
  856. return true;
  857. }
  858. static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
  859. int delay, int delaymax, const char *msg)
  860. {
  861. u8 __iomem *base = get_hwbase(dev);
  862. pci_push(base);
  863. do {
  864. udelay(delay);
  865. delaymax -= delay;
  866. if (delaymax < 0) {
  867. if (msg)
  868. printk("%s", msg);
  869. return 1;
  870. }
  871. } while ((readl(base + offset) & mask) != target);
  872. return 0;
  873. }
  874. #define NV_SETUP_RX_RING 0x01
  875. #define NV_SETUP_TX_RING 0x02
  876. static inline u32 dma_low(dma_addr_t addr)
  877. {
  878. return addr;
  879. }
  880. static inline u32 dma_high(dma_addr_t addr)
  881. {
  882. return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
  883. }
  884. static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
  885. {
  886. struct fe_priv *np = get_nvpriv(dev);
  887. u8 __iomem *base = get_hwbase(dev);
  888. if (!nv_optimized(np)) {
  889. if (rxtx_flags & NV_SETUP_RX_RING) {
  890. writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
  891. }
  892. if (rxtx_flags & NV_SETUP_TX_RING) {
  893. writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
  894. }
  895. } else {
  896. if (rxtx_flags & NV_SETUP_RX_RING) {
  897. writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
  898. writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
  899. }
  900. if (rxtx_flags & NV_SETUP_TX_RING) {
  901. writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
  902. writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
  903. }
  904. }
  905. }
  906. static void free_rings(struct net_device *dev)
  907. {
  908. struct fe_priv *np = get_nvpriv(dev);
  909. if (!nv_optimized(np)) {
  910. if (np->rx_ring.orig)
  911. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
  912. np->rx_ring.orig, np->ring_addr);
  913. } else {
  914. if (np->rx_ring.ex)
  915. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
  916. np->rx_ring.ex, np->ring_addr);
  917. }
  918. if (np->rx_skb)
  919. kfree(np->rx_skb);
  920. if (np->tx_skb)
  921. kfree(np->tx_skb);
  922. }
  923. static int using_multi_irqs(struct net_device *dev)
  924. {
  925. struct fe_priv *np = get_nvpriv(dev);
  926. if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
  927. ((np->msi_flags & NV_MSI_X_ENABLED) &&
  928. ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
  929. return 0;
  930. else
  931. return 1;
  932. }
  933. static void nv_txrx_gate(struct net_device *dev, bool gate)
  934. {
  935. struct fe_priv *np = get_nvpriv(dev);
  936. u8 __iomem *base = get_hwbase(dev);
  937. u32 powerstate;
  938. if (!np->mac_in_use &&
  939. (np->driver_data & DEV_HAS_POWER_CNTRL)) {
  940. powerstate = readl(base + NvRegPowerState2);
  941. if (gate)
  942. powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
  943. else
  944. powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
  945. writel(powerstate, base + NvRegPowerState2);
  946. }
  947. }
  948. static void nv_enable_irq(struct net_device *dev)
  949. {
  950. struct fe_priv *np = get_nvpriv(dev);
  951. if (!using_multi_irqs(dev)) {
  952. if (np->msi_flags & NV_MSI_X_ENABLED)
  953. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  954. else
  955. enable_irq(np->pci_dev->irq);
  956. } else {
  957. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  958. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  959. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  960. }
  961. }
  962. static void nv_disable_irq(struct net_device *dev)
  963. {
  964. struct fe_priv *np = get_nvpriv(dev);
  965. if (!using_multi_irqs(dev)) {
  966. if (np->msi_flags & NV_MSI_X_ENABLED)
  967. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  968. else
  969. disable_irq(np->pci_dev->irq);
  970. } else {
  971. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  972. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  973. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  974. }
  975. }
  976. /* In MSIX mode, a write to irqmask behaves as XOR */
  977. static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
  978. {
  979. u8 __iomem *base = get_hwbase(dev);
  980. writel(mask, base + NvRegIrqMask);
  981. }
  982. static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
  983. {
  984. struct fe_priv *np = get_nvpriv(dev);
  985. u8 __iomem *base = get_hwbase(dev);
  986. if (np->msi_flags & NV_MSI_X_ENABLED) {
  987. writel(mask, base + NvRegIrqMask);
  988. } else {
  989. if (np->msi_flags & NV_MSI_ENABLED)
  990. writel(0, base + NvRegMSIIrqMask);
  991. writel(0, base + NvRegIrqMask);
  992. }
  993. }
  994. static void nv_napi_enable(struct net_device *dev)
  995. {
  996. struct fe_priv *np = get_nvpriv(dev);
  997. napi_enable(&np->napi);
  998. }
  999. static void nv_napi_disable(struct net_device *dev)
  1000. {
  1001. struct fe_priv *np = get_nvpriv(dev);
  1002. napi_disable(&np->napi);
  1003. }
  1004. #define MII_READ (-1)
  1005. /* mii_rw: read/write a register on the PHY.
  1006. *
  1007. * Caller must guarantee serialization
  1008. */
  1009. static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
  1010. {
  1011. u8 __iomem *base = get_hwbase(dev);
  1012. u32 reg;
  1013. int retval;
  1014. writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
  1015. reg = readl(base + NvRegMIIControl);
  1016. if (reg & NVREG_MIICTL_INUSE) {
  1017. writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
  1018. udelay(NV_MIIBUSY_DELAY);
  1019. }
  1020. reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
  1021. if (value != MII_READ) {
  1022. writel(value, base + NvRegMIIData);
  1023. reg |= NVREG_MIICTL_WRITE;
  1024. }
  1025. writel(reg, base + NvRegMIIControl);
  1026. if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
  1027. NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
  1028. dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
  1029. dev->name, miireg, addr);
  1030. retval = -1;
  1031. } else if (value != MII_READ) {
  1032. /* it was a write operation - fewer failures are detectable */
  1033. dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
  1034. dev->name, value, miireg, addr);
  1035. retval = 0;
  1036. } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
  1037. dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
  1038. dev->name, miireg, addr);
  1039. retval = -1;
  1040. } else {
  1041. retval = readl(base + NvRegMIIData);
  1042. dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
  1043. dev->name, miireg, addr, retval);
  1044. }
  1045. return retval;
  1046. }
  1047. static int phy_reset(struct net_device *dev, u32 bmcr_setup)
  1048. {
  1049. struct fe_priv *np = netdev_priv(dev);
  1050. u32 miicontrol;
  1051. unsigned int tries = 0;
  1052. miicontrol = BMCR_RESET | bmcr_setup;
  1053. if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
  1054. return -1;
  1055. }
  1056. /* wait for 500ms */
  1057. msleep(500);
  1058. /* must wait till reset is deasserted */
  1059. while (miicontrol & BMCR_RESET) {
  1060. msleep(10);
  1061. miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1062. /* FIXME: 100 tries seem excessive */
  1063. if (tries++ > 100)
  1064. return -1;
  1065. }
  1066. return 0;
  1067. }
  1068. static int phy_init(struct net_device *dev)
  1069. {
  1070. struct fe_priv *np = get_nvpriv(dev);
  1071. u8 __iomem *base = get_hwbase(dev);
  1072. u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
  1073. /* phy errata for E3016 phy */
  1074. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  1075. reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  1076. reg &= ~PHY_MARVELL_E3016_INITMASK;
  1077. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
  1078. printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
  1079. return PHY_ERROR;
  1080. }
  1081. }
  1082. if (np->phy_oui == PHY_OUI_REALTEK) {
  1083. if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1084. np->phy_rev == PHY_REV_REALTEK_8211B) {
  1085. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
  1086. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1087. return PHY_ERROR;
  1088. }
  1089. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
  1090. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1091. return PHY_ERROR;
  1092. }
  1093. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
  1094. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1095. return PHY_ERROR;
  1096. }
  1097. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
  1098. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1099. return PHY_ERROR;
  1100. }
  1101. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
  1102. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1103. return PHY_ERROR;
  1104. }
  1105. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
  1106. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1107. return PHY_ERROR;
  1108. }
  1109. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
  1110. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1111. return PHY_ERROR;
  1112. }
  1113. }
  1114. if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1115. np->phy_rev == PHY_REV_REALTEK_8211C) {
  1116. u32 powerstate = readl(base + NvRegPowerState2);
  1117. /* need to perform hw phy reset */
  1118. powerstate |= NVREG_POWERSTATE2_PHY_RESET;
  1119. writel(powerstate, base + NvRegPowerState2);
  1120. msleep(25);
  1121. powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
  1122. writel(powerstate, base + NvRegPowerState2);
  1123. msleep(25);
  1124. reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
  1125. reg |= PHY_REALTEK_INIT9;
  1126. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
  1127. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1128. return PHY_ERROR;
  1129. }
  1130. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
  1131. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1132. return PHY_ERROR;
  1133. }
  1134. reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
  1135. if (!(reg & PHY_REALTEK_INIT11)) {
  1136. reg |= PHY_REALTEK_INIT11;
  1137. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
  1138. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1139. return PHY_ERROR;
  1140. }
  1141. }
  1142. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
  1143. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1144. return PHY_ERROR;
  1145. }
  1146. }
  1147. if (np->phy_model == PHY_MODEL_REALTEK_8201) {
  1148. if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
  1149. phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
  1150. phy_reserved |= PHY_REALTEK_INIT7;
  1151. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
  1152. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1153. return PHY_ERROR;
  1154. }
  1155. }
  1156. }
  1157. }
  1158. /* set advertise register */
  1159. reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  1160. reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
  1161. if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
  1162. printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
  1163. return PHY_ERROR;
  1164. }
  1165. /* get phy interface type */
  1166. phyinterface = readl(base + NvRegPhyInterface);
  1167. /* see if gigabit phy */
  1168. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  1169. if (mii_status & PHY_GIGABIT) {
  1170. np->gigabit = PHY_GIGABIT;
  1171. mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  1172. mii_control_1000 &= ~ADVERTISE_1000HALF;
  1173. if (phyinterface & PHY_RGMII)
  1174. mii_control_1000 |= ADVERTISE_1000FULL;
  1175. else
  1176. mii_control_1000 &= ~ADVERTISE_1000FULL;
  1177. if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
  1178. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1179. return PHY_ERROR;
  1180. }
  1181. }
  1182. else
  1183. np->gigabit = 0;
  1184. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1185. mii_control |= BMCR_ANENABLE;
  1186. if (np->phy_oui == PHY_OUI_REALTEK &&
  1187. np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1188. np->phy_rev == PHY_REV_REALTEK_8211C) {
  1189. /* start autoneg since we already performed hw reset above */
  1190. mii_control |= BMCR_ANRESTART;
  1191. if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
  1192. printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
  1193. return PHY_ERROR;
  1194. }
  1195. } else {
  1196. /* reset the phy
  1197. * (certain phys need bmcr to be setup with reset)
  1198. */
  1199. if (phy_reset(dev, mii_control)) {
  1200. printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
  1201. return PHY_ERROR;
  1202. }
  1203. }
  1204. /* phy vendor specific configuration */
  1205. if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
  1206. phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
  1207. phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
  1208. phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
  1209. if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
  1210. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1211. return PHY_ERROR;
  1212. }
  1213. phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  1214. phy_reserved |= PHY_CICADA_INIT5;
  1215. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
  1216. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1217. return PHY_ERROR;
  1218. }
  1219. }
  1220. if (np->phy_oui == PHY_OUI_CICADA) {
  1221. phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
  1222. phy_reserved |= PHY_CICADA_INIT6;
  1223. if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
  1224. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1225. return PHY_ERROR;
  1226. }
  1227. }
  1228. if (np->phy_oui == PHY_OUI_VITESSE) {
  1229. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
  1230. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1231. return PHY_ERROR;
  1232. }
  1233. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
  1234. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1235. return PHY_ERROR;
  1236. }
  1237. phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
  1238. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
  1239. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1240. return PHY_ERROR;
  1241. }
  1242. phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
  1243. phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
  1244. phy_reserved |= PHY_VITESSE_INIT3;
  1245. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
  1246. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1247. return PHY_ERROR;
  1248. }
  1249. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
  1250. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1251. return PHY_ERROR;
  1252. }
  1253. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
  1254. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1255. return PHY_ERROR;
  1256. }
  1257. phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
  1258. phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
  1259. phy_reserved |= PHY_VITESSE_INIT3;
  1260. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
  1261. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1262. return PHY_ERROR;
  1263. }
  1264. phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
  1265. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
  1266. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1267. return PHY_ERROR;
  1268. }
  1269. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
  1270. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1271. return PHY_ERROR;
  1272. }
  1273. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
  1274. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1275. return PHY_ERROR;
  1276. }
  1277. phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
  1278. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
  1279. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1280. return PHY_ERROR;
  1281. }
  1282. phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
  1283. phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
  1284. phy_reserved |= PHY_VITESSE_INIT8;
  1285. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
  1286. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1287. return PHY_ERROR;
  1288. }
  1289. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
  1290. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1291. return PHY_ERROR;
  1292. }
  1293. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
  1294. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1295. return PHY_ERROR;
  1296. }
  1297. }
  1298. if (np->phy_oui == PHY_OUI_REALTEK) {
  1299. if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1300. np->phy_rev == PHY_REV_REALTEK_8211B) {
  1301. /* reset could have cleared these out, set them back */
  1302. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
  1303. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1304. return PHY_ERROR;
  1305. }
  1306. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
  1307. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1308. return PHY_ERROR;
  1309. }
  1310. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
  1311. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1312. return PHY_ERROR;
  1313. }
  1314. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
  1315. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1316. return PHY_ERROR;
  1317. }
  1318. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
  1319. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1320. return PHY_ERROR;
  1321. }
  1322. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
  1323. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1324. return PHY_ERROR;
  1325. }
  1326. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
  1327. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1328. return PHY_ERROR;
  1329. }
  1330. }
  1331. if (np->phy_model == PHY_MODEL_REALTEK_8201) {
  1332. if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
  1333. phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
  1334. phy_reserved |= PHY_REALTEK_INIT7;
  1335. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
  1336. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1337. return PHY_ERROR;
  1338. }
  1339. }
  1340. if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
  1341. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
  1342. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1343. return PHY_ERROR;
  1344. }
  1345. phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
  1346. phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
  1347. phy_reserved |= PHY_REALTEK_INIT3;
  1348. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
  1349. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1350. return PHY_ERROR;
  1351. }
  1352. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
  1353. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1354. return PHY_ERROR;
  1355. }
  1356. }
  1357. }
  1358. }
  1359. /* some phys clear out pause advertisment on reset, set it back */
  1360. mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
  1361. /* restart auto negotiation, power down phy */
  1362. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1363. mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
  1364. if (phy_power_down) {
  1365. mii_control |= BMCR_PDOWN;
  1366. }
  1367. if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
  1368. return PHY_ERROR;
  1369. }
  1370. return 0;
  1371. }
  1372. static void nv_start_rx(struct net_device *dev)
  1373. {
  1374. struct fe_priv *np = netdev_priv(dev);
  1375. u8 __iomem *base = get_hwbase(dev);
  1376. u32 rx_ctrl = readl(base + NvRegReceiverControl);
  1377. dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
  1378. /* Already running? Stop it. */
  1379. if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
  1380. rx_ctrl &= ~NVREG_RCVCTL_START;
  1381. writel(rx_ctrl, base + NvRegReceiverControl);
  1382. pci_push(base);
  1383. }
  1384. writel(np->linkspeed, base + NvRegLinkSpeed);
  1385. pci_push(base);
  1386. rx_ctrl |= NVREG_RCVCTL_START;
  1387. if (np->mac_in_use)
  1388. rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
  1389. writel(rx_ctrl, base + NvRegReceiverControl);
  1390. dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
  1391. dev->name, np->duplex, np->linkspeed);
  1392. pci_push(base);
  1393. }
  1394. static void nv_stop_rx(struct net_device *dev)
  1395. {
  1396. struct fe_priv *np = netdev_priv(dev);
  1397. u8 __iomem *base = get_hwbase(dev);
  1398. u32 rx_ctrl = readl(base + NvRegReceiverControl);
  1399. dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
  1400. if (!np->mac_in_use)
  1401. rx_ctrl &= ~NVREG_RCVCTL_START;
  1402. else
  1403. rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
  1404. writel(rx_ctrl, base + NvRegReceiverControl);
  1405. reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
  1406. NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
  1407. KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
  1408. udelay(NV_RXSTOP_DELAY2);
  1409. if (!np->mac_in_use)
  1410. writel(0, base + NvRegLinkSpeed);
  1411. }
  1412. static void nv_start_tx(struct net_device *dev)
  1413. {
  1414. struct fe_priv *np = netdev_priv(dev);
  1415. u8 __iomem *base = get_hwbase(dev);
  1416. u32 tx_ctrl = readl(base + NvRegTransmitterControl);
  1417. dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
  1418. tx_ctrl |= NVREG_XMITCTL_START;
  1419. if (np->mac_in_use)
  1420. tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
  1421. writel(tx_ctrl, base + NvRegTransmitterControl);
  1422. pci_push(base);
  1423. }
  1424. static void nv_stop_tx(struct net_device *dev)
  1425. {
  1426. struct fe_priv *np = netdev_priv(dev);
  1427. u8 __iomem *base = get_hwbase(dev);
  1428. u32 tx_ctrl = readl(base + NvRegTransmitterControl);
  1429. dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
  1430. if (!np->mac_in_use)
  1431. tx_ctrl &= ~NVREG_XMITCTL_START;
  1432. else
  1433. tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
  1434. writel(tx_ctrl, base + NvRegTransmitterControl);
  1435. reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
  1436. NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
  1437. KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
  1438. udelay(NV_TXSTOP_DELAY2);
  1439. if (!np->mac_in_use)
  1440. writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
  1441. base + NvRegTransmitPoll);
  1442. }
  1443. static void nv_start_rxtx(struct net_device *dev)
  1444. {
  1445. nv_start_rx(dev);
  1446. nv_start_tx(dev);
  1447. }
  1448. static void nv_stop_rxtx(struct net_device *dev)
  1449. {
  1450. nv_stop_rx(dev);
  1451. nv_stop_tx(dev);
  1452. }
  1453. static void nv_txrx_reset(struct net_device *dev)
  1454. {
  1455. struct fe_priv *np = netdev_priv(dev);
  1456. u8 __iomem *base = get_hwbase(dev);
  1457. dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
  1458. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
  1459. pci_push(base);
  1460. udelay(NV_TXRX_RESET_DELAY);
  1461. writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
  1462. pci_push(base);
  1463. }
  1464. static void nv_mac_reset(struct net_device *dev)
  1465. {
  1466. struct fe_priv *np = netdev_priv(dev);
  1467. u8 __iomem *base = get_hwbase(dev);
  1468. u32 temp1, temp2, temp3;
  1469. dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
  1470. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
  1471. pci_push(base);
  1472. /* save registers since they will be cleared on reset */
  1473. temp1 = readl(base + NvRegMacAddrA);
  1474. temp2 = readl(base + NvRegMacAddrB);
  1475. temp3 = readl(base + NvRegTransmitPoll);
  1476. writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
  1477. pci_push(base);
  1478. udelay(NV_MAC_RESET_DELAY);
  1479. writel(0, base + NvRegMacReset);
  1480. pci_push(base);
  1481. udelay(NV_MAC_RESET_DELAY);
  1482. /* restore saved registers */
  1483. writel(temp1, base + NvRegMacAddrA);
  1484. writel(temp2, base + NvRegMacAddrB);
  1485. writel(temp3, base + NvRegTransmitPoll);
  1486. writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
  1487. pci_push(base);
  1488. }
  1489. static void nv_get_hw_stats(struct net_device *dev)
  1490. {
  1491. struct fe_priv *np = netdev_priv(dev);
  1492. u8 __iomem *base = get_hwbase(dev);
  1493. np->estats.tx_bytes += readl(base + NvRegTxCnt);
  1494. np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
  1495. np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
  1496. np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
  1497. np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
  1498. np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
  1499. np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
  1500. np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
  1501. np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
  1502. np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
  1503. np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
  1504. np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
  1505. np->estats.rx_runt += readl(base + NvRegRxRunt);
  1506. np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
  1507. np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
  1508. np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
  1509. np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
  1510. np->estats.rx_length_error += readl(base + NvRegRxLenErr);
  1511. np->estats.rx_unicast += readl(base + NvRegRxUnicast);
  1512. np->estats.rx_multicast += readl(base + NvRegRxMulticast);
  1513. np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
  1514. np->estats.rx_packets =
  1515. np->estats.rx_unicast +
  1516. np->estats.rx_multicast +
  1517. np->estats.rx_broadcast;
  1518. np->estats.rx_errors_total =
  1519. np->estats.rx_crc_errors +
  1520. np->estats.rx_over_errors +
  1521. np->estats.rx_frame_error +
  1522. (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
  1523. np->estats.rx_late_collision +
  1524. np->estats.rx_runt +
  1525. np->estats.rx_frame_too_long;
  1526. np->estats.tx_errors_total =
  1527. np->estats.tx_late_collision +
  1528. np->estats.tx_fifo_errors +
  1529. np->estats.tx_carrier_errors +
  1530. np->estats.tx_excess_deferral +
  1531. np->estats.tx_retry_error;
  1532. if (np->driver_data & DEV_HAS_STATISTICS_V2) {
  1533. np->estats.tx_deferral += readl(base + NvRegTxDef);
  1534. np->estats.tx_packets += readl(base + NvRegTxFrame);
  1535. np->estats.rx_bytes += readl(base + NvRegRxCnt);
  1536. np->estats.tx_pause += readl(base + NvRegTxPause);
  1537. np->estats.rx_pause += readl(base + NvRegRxPause);
  1538. np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
  1539. }
  1540. if (np->driver_data & DEV_HAS_STATISTICS_V3) {
  1541. np->estats.tx_unicast += readl(base + NvRegTxUnicast);
  1542. np->estats.tx_multicast += readl(base + NvRegTxMulticast);
  1543. np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
  1544. }
  1545. }
  1546. /*
  1547. * nv_get_stats: dev->get_stats function
  1548. * Get latest stats value from the nic.
  1549. * Called with read_lock(&dev_base_lock) held for read -
  1550. * only synchronized against unregister_netdevice.
  1551. */
  1552. static struct net_device_stats *nv_get_stats(struct net_device *dev)
  1553. {
  1554. struct fe_priv *np = netdev_priv(dev);
  1555. /* If the nic supports hw counters then retrieve latest values */
  1556. if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
  1557. nv_get_hw_stats(dev);
  1558. /* copy to net_device stats */
  1559. dev->stats.tx_bytes = np->estats.tx_bytes;
  1560. dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
  1561. dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
  1562. dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
  1563. dev->stats.rx_over_errors = np->estats.rx_over_errors;
  1564. dev->stats.rx_errors = np->estats.rx_errors_total;
  1565. dev->stats.tx_errors = np->estats.tx_errors_total;
  1566. }
  1567. return &dev->stats;
  1568. }
  1569. /*
  1570. * nv_alloc_rx: fill rx ring entries.
  1571. * Return 1 if the allocations for the skbs failed and the
  1572. * rx engine is without Available descriptors
  1573. */
  1574. static int nv_alloc_rx(struct net_device *dev)
  1575. {
  1576. struct fe_priv *np = netdev_priv(dev);
  1577. struct ring_desc* less_rx;
  1578. less_rx = np->get_rx.orig;
  1579. if (less_rx-- == np->first_rx.orig)
  1580. less_rx = np->last_rx.orig;
  1581. while (np->put_rx.orig != less_rx) {
  1582. struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  1583. if (skb) {
  1584. np->put_rx_ctx->skb = skb;
  1585. np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
  1586. skb->data,
  1587. skb_tailroom(skb),
  1588. PCI_DMA_FROMDEVICE);
  1589. np->put_rx_ctx->dma_len = skb_tailroom(skb);
  1590. np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
  1591. wmb();
  1592. np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
  1593. if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
  1594. np->put_rx.orig = np->first_rx.orig;
  1595. if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
  1596. np->put_rx_ctx = np->first_rx_ctx;
  1597. } else {
  1598. return 1;
  1599. }
  1600. }
  1601. return 0;
  1602. }
  1603. static int nv_alloc_rx_optimized(struct net_device *dev)
  1604. {
  1605. struct fe_priv *np = netdev_priv(dev);
  1606. struct ring_desc_ex* less_rx;
  1607. less_rx = np->get_rx.ex;
  1608. if (less_rx-- == np->first_rx.ex)
  1609. less_rx = np->last_rx.ex;
  1610. while (np->put_rx.ex != less_rx) {
  1611. struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  1612. if (skb) {
  1613. np->put_rx_ctx->skb = skb;
  1614. np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
  1615. skb->data,
  1616. skb_tailroom(skb),
  1617. PCI_DMA_FROMDEVICE);
  1618. np->put_rx_ctx->dma_len = skb_tailroom(skb);
  1619. np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
  1620. np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
  1621. wmb();
  1622. np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
  1623. if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
  1624. np->put_rx.ex = np->first_rx.ex;
  1625. if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
  1626. np->put_rx_ctx = np->first_rx_ctx;
  1627. } else {
  1628. return 1;
  1629. }
  1630. }
  1631. return 0;
  1632. }
  1633. /* If rx bufs are exhausted called after 50ms to attempt to refresh */
  1634. static void nv_do_rx_refill(unsigned long data)
  1635. {
  1636. struct net_device *dev = (struct net_device *) data;
  1637. struct fe_priv *np = netdev_priv(dev);
  1638. /* Just reschedule NAPI rx processing */
  1639. napi_schedule(&np->napi);
  1640. }
  1641. static void nv_init_rx(struct net_device *dev)
  1642. {
  1643. struct fe_priv *np = netdev_priv(dev);
  1644. int i;
  1645. np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
  1646. if (!nv_optimized(np))
  1647. np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
  1648. else
  1649. np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
  1650. np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
  1651. np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
  1652. for (i = 0; i < np->rx_ring_size; i++) {
  1653. if (!nv_optimized(np)) {
  1654. np->rx_ring.orig[i].flaglen = 0;
  1655. np->rx_ring.orig[i].buf = 0;
  1656. } else {
  1657. np->rx_ring.ex[i].flaglen = 0;
  1658. np->rx_ring.ex[i].txvlan = 0;
  1659. np->rx_ring.ex[i].bufhigh = 0;
  1660. np->rx_ring.ex[i].buflow = 0;
  1661. }
  1662. np->rx_skb[i].skb = NULL;
  1663. np->rx_skb[i].dma = 0;
  1664. }
  1665. }
  1666. static void nv_init_tx(struct net_device *dev)
  1667. {
  1668. struct fe_priv *np = netdev_priv(dev);
  1669. int i;
  1670. np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
  1671. if (!nv_optimized(np))
  1672. np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
  1673. else
  1674. np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
  1675. np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
  1676. np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
  1677. np->tx_pkts_in_progress = 0;
  1678. np->tx_change_owner = NULL;
  1679. np->tx_end_flip = NULL;
  1680. np->tx_stop = 0;
  1681. for (i = 0; i < np->tx_ring_size; i++) {
  1682. if (!nv_optimized(np)) {
  1683. np->tx_ring.orig[i].flaglen = 0;
  1684. np->tx_ring.orig[i].buf = 0;
  1685. } else {
  1686. np->tx_ring.ex[i].flaglen = 0;
  1687. np->tx_ring.ex[i].txvlan = 0;
  1688. np->tx_ring.ex[i].bufhigh = 0;
  1689. np->tx_ring.ex[i].buflow = 0;
  1690. }
  1691. np->tx_skb[i].skb = NULL;
  1692. np->tx_skb[i].dma = 0;
  1693. np->tx_skb[i].dma_len = 0;
  1694. np->tx_skb[i].dma_single = 0;
  1695. np->tx_skb[i].first_tx_desc = NULL;
  1696. np->tx_skb[i].next_tx_ctx = NULL;
  1697. }
  1698. }
  1699. static int nv_init_ring(struct net_device *dev)
  1700. {
  1701. struct fe_priv *np = netdev_priv(dev);
  1702. nv_init_tx(dev);
  1703. nv_init_rx(dev);
  1704. if (!nv_optimized(np))
  1705. return nv_alloc_rx(dev);
  1706. else
  1707. return nv_alloc_rx_optimized(dev);
  1708. }
  1709. static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
  1710. {
  1711. if (tx_skb->dma) {
  1712. if (tx_skb->dma_single)
  1713. pci_unmap_single(np->pci_dev, tx_skb->dma,
  1714. tx_skb->dma_len,
  1715. PCI_DMA_TODEVICE);
  1716. else
  1717. pci_unmap_page(np->pci_dev, tx_skb->dma,
  1718. tx_skb->dma_len,
  1719. PCI_DMA_TODEVICE);
  1720. tx_skb->dma = 0;
  1721. }
  1722. }
  1723. static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
  1724. {
  1725. nv_unmap_txskb(np, tx_skb);
  1726. if (tx_skb->skb) {
  1727. dev_kfree_skb_any(tx_skb->skb);
  1728. tx_skb->skb = NULL;
  1729. return 1;
  1730. }
  1731. return 0;
  1732. }
  1733. static void nv_drain_tx(struct net_device *dev)
  1734. {
  1735. struct fe_priv *np = netdev_priv(dev);
  1736. unsigned int i;
  1737. for (i = 0; i < np->tx_ring_size; i++) {
  1738. if (!nv_optimized(np)) {
  1739. np->tx_ring.orig[i].flaglen = 0;
  1740. np->tx_ring.orig[i].buf = 0;
  1741. } else {
  1742. np->tx_ring.ex[i].flaglen = 0;
  1743. np->tx_ring.ex[i].txvlan = 0;
  1744. np->tx_ring.ex[i].bufhigh = 0;
  1745. np->tx_ring.ex[i].buflow = 0;
  1746. }
  1747. if (nv_release_txskb(np, &np->tx_skb[i]))
  1748. dev->stats.tx_dropped++;
  1749. np->tx_skb[i].dma = 0;
  1750. np->tx_skb[i].dma_len = 0;
  1751. np->tx_skb[i].dma_single = 0;
  1752. np->tx_skb[i].first_tx_desc = NULL;
  1753. np->tx_skb[i].next_tx_ctx = NULL;
  1754. }
  1755. np->tx_pkts_in_progress = 0;
  1756. np->tx_change_owner = NULL;
  1757. np->tx_end_flip = NULL;
  1758. }
  1759. static void nv_drain_rx(struct net_device *dev)
  1760. {
  1761. struct fe_priv *np = netdev_priv(dev);
  1762. int i;
  1763. for (i = 0; i < np->rx_ring_size; i++) {
  1764. if (!nv_optimized(np)) {
  1765. np->rx_ring.orig[i].flaglen = 0;
  1766. np->rx_ring.orig[i].buf = 0;
  1767. } else {
  1768. np->rx_ring.ex[i].flaglen = 0;
  1769. np->rx_ring.ex[i].txvlan = 0;
  1770. np->rx_ring.ex[i].bufhigh = 0;
  1771. np->rx_ring.ex[i].buflow = 0;
  1772. }
  1773. wmb();
  1774. if (np->rx_skb[i].skb) {
  1775. pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
  1776. (skb_end_pointer(np->rx_skb[i].skb) -
  1777. np->rx_skb[i].skb->data),
  1778. PCI_DMA_FROMDEVICE);
  1779. dev_kfree_skb(np->rx_skb[i].skb);
  1780. np->rx_skb[i].skb = NULL;
  1781. }
  1782. }
  1783. }
  1784. static void nv_drain_rxtx(struct net_device *dev)
  1785. {
  1786. nv_drain_tx(dev);
  1787. nv_drain_rx(dev);
  1788. }
  1789. static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
  1790. {
  1791. return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
  1792. }
  1793. static void nv_legacybackoff_reseed(struct net_device *dev)
  1794. {
  1795. u8 __iomem *base = get_hwbase(dev);
  1796. u32 reg;
  1797. u32 low;
  1798. int tx_status = 0;
  1799. reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
  1800. get_random_bytes(&low, sizeof(low));
  1801. reg |= low & NVREG_SLOTTIME_MASK;
  1802. /* Need to stop tx before change takes effect.
  1803. * Caller has already gained np->lock.
  1804. */
  1805. tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
  1806. if (tx_status)
  1807. nv_stop_tx(dev);
  1808. nv_stop_rx(dev);
  1809. writel(reg, base + NvRegSlotTime);
  1810. if (tx_status)
  1811. nv_start_tx(dev);
  1812. nv_start_rx(dev);
  1813. }
  1814. /* Gear Backoff Seeds */
  1815. #define BACKOFF_SEEDSET_ROWS 8
  1816. #define BACKOFF_SEEDSET_LFSRS 15
  1817. /* Known Good seed sets */
  1818. static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
  1819. {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
  1820. {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
  1821. {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
  1822. {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
  1823. {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
  1824. {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
  1825. {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
  1826. {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
  1827. static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
  1828. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1829. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1830. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
  1831. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1832. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1833. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1834. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1835. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
  1836. static void nv_gear_backoff_reseed(struct net_device *dev)
  1837. {
  1838. u8 __iomem *base = get_hwbase(dev);
  1839. u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
  1840. u32 temp, seedset, combinedSeed;
  1841. int i;
  1842. /* Setup seed for free running LFSR */
  1843. /* We are going to read the time stamp counter 3 times
  1844. and swizzle bits around to increase randomness */
  1845. get_random_bytes(&miniseed1, sizeof(miniseed1));
  1846. miniseed1 &= 0x0fff;
  1847. if (miniseed1 == 0)
  1848. miniseed1 = 0xabc;
  1849. get_random_bytes(&miniseed2, sizeof(miniseed2));
  1850. miniseed2 &= 0x0fff;
  1851. if (miniseed2 == 0)
  1852. miniseed2 = 0xabc;
  1853. miniseed2_reversed =
  1854. ((miniseed2 & 0xF00) >> 8) |
  1855. (miniseed2 & 0x0F0) |
  1856. ((miniseed2 & 0x00F) << 8);
  1857. get_random_bytes(&miniseed3, sizeof(miniseed3));
  1858. miniseed3 &= 0x0fff;
  1859. if (miniseed3 == 0)
  1860. miniseed3 = 0xabc;
  1861. miniseed3_reversed =
  1862. ((miniseed3 & 0xF00) >> 8) |
  1863. (miniseed3 & 0x0F0) |
  1864. ((miniseed3 & 0x00F) << 8);
  1865. combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
  1866. (miniseed2 ^ miniseed3_reversed);
  1867. /* Seeds can not be zero */
  1868. if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
  1869. combinedSeed |= 0x08;
  1870. if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
  1871. combinedSeed |= 0x8000;
  1872. /* No need to disable tx here */
  1873. temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
  1874. temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
  1875. temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
  1876. writel(temp,base + NvRegBackOffControl);
  1877. /* Setup seeds for all gear LFSRs. */
  1878. get_random_bytes(&seedset, sizeof(seedset));
  1879. seedset = seedset % BACKOFF_SEEDSET_ROWS;
  1880. for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
  1881. {
  1882. temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
  1883. temp |= main_seedset[seedset][i-1] & 0x3ff;
  1884. temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
  1885. writel(temp, base + NvRegBackOffControl);
  1886. }
  1887. }
  1888. /*
  1889. * nv_start_xmit: dev->hard_start_xmit function
  1890. * Called with netif_tx_lock held.
  1891. */
  1892. static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1893. {
  1894. struct fe_priv *np = netdev_priv(dev);
  1895. u32 tx_flags = 0;
  1896. u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
  1897. unsigned int fragments = skb_shinfo(skb)->nr_frags;
  1898. unsigned int i;
  1899. u32 offset = 0;
  1900. u32 bcnt;
  1901. u32 size = skb_headlen(skb);
  1902. u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1903. u32 empty_slots;
  1904. struct ring_desc* put_tx;
  1905. struct ring_desc* start_tx;
  1906. struct ring_desc* prev_tx;
  1907. struct nv_skb_map* prev_tx_ctx;
  1908. unsigned long flags;
  1909. /* add fragments to entries count */
  1910. for (i = 0; i < fragments; i++) {
  1911. entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
  1912. ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1913. }
  1914. spin_lock_irqsave(&np->lock, flags);
  1915. empty_slots = nv_get_empty_tx_slots(np);
  1916. if (unlikely(empty_slots <= entries)) {
  1917. netif_stop_queue(dev);
  1918. np->tx_stop = 1;
  1919. spin_unlock_irqrestore(&np->lock, flags);
  1920. return NETDEV_TX_BUSY;
  1921. }
  1922. spin_unlock_irqrestore(&np->lock, flags);
  1923. start_tx = put_tx = np->put_tx.orig;
  1924. /* setup the header buffer */
  1925. do {
  1926. prev_tx = put_tx;
  1927. prev_tx_ctx = np->put_tx_ctx;
  1928. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1929. np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
  1930. PCI_DMA_TODEVICE);
  1931. np->put_tx_ctx->dma_len = bcnt;
  1932. np->put_tx_ctx->dma_single = 1;
  1933. put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
  1934. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1935. tx_flags = np->tx_flags;
  1936. offset += bcnt;
  1937. size -= bcnt;
  1938. if (unlikely(put_tx++ == np->last_tx.orig))
  1939. put_tx = np->first_tx.orig;
  1940. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1941. np->put_tx_ctx = np->first_tx_ctx;
  1942. } while (size);
  1943. /* setup the fragments */
  1944. for (i = 0; i < fragments; i++) {
  1945. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1946. u32 size = frag->size;
  1947. offset = 0;
  1948. do {
  1949. prev_tx = put_tx;
  1950. prev_tx_ctx = np->put_tx_ctx;
  1951. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1952. np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
  1953. PCI_DMA_TODEVICE);
  1954. np->put_tx_ctx->dma_len = bcnt;
  1955. np->put_tx_ctx->dma_single = 0;
  1956. put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
  1957. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1958. offset += bcnt;
  1959. size -= bcnt;
  1960. if (unlikely(put_tx++ == np->last_tx.orig))
  1961. put_tx = np->first_tx.orig;
  1962. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1963. np->put_tx_ctx = np->first_tx_ctx;
  1964. } while (size);
  1965. }
  1966. /* set last fragment flag */
  1967. prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
  1968. /* save skb in this slot's context area */
  1969. prev_tx_ctx->skb = skb;
  1970. if (skb_is_gso(skb))
  1971. tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
  1972. else
  1973. tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
  1974. NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
  1975. spin_lock_irqsave(&np->lock, flags);
  1976. /* set tx flags */
  1977. start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
  1978. np->put_tx.orig = put_tx;
  1979. spin_unlock_irqrestore(&np->lock, flags);
  1980. dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
  1981. dev->name, entries, tx_flags_extra);
  1982. {
  1983. int j;
  1984. for (j=0; j<64; j++) {
  1985. if ((j%16) == 0)
  1986. dprintk("\n%03x:", j);
  1987. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  1988. }
  1989. dprintk("\n");
  1990. }
  1991. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  1992. return NETDEV_TX_OK;
  1993. }
  1994. static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
  1995. struct net_device *dev)
  1996. {
  1997. struct fe_priv *np = netdev_priv(dev);
  1998. u32 tx_flags = 0;
  1999. u32 tx_flags_extra;
  2000. unsigned int fragments = skb_shinfo(skb)->nr_frags;
  2001. unsigned int i;
  2002. u32 offset = 0;
  2003. u32 bcnt;
  2004. u32 size = skb_headlen(skb);
  2005. u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  2006. u32 empty_slots;
  2007. struct ring_desc_ex* put_tx;
  2008. struct ring_desc_ex* start_tx;
  2009. struct ring_desc_ex* prev_tx;
  2010. struct nv_skb_map* prev_tx_ctx;
  2011. struct nv_skb_map* start_tx_ctx;
  2012. unsigned long flags;
  2013. /* add fragments to entries count */
  2014. for (i = 0; i < fragments; i++) {
  2015. entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
  2016. ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  2017. }
  2018. spin_lock_irqsave(&np->lock, flags);
  2019. empty_slots = nv_get_empty_tx_slots(np);
  2020. if (unlikely(empty_slots <= entries)) {
  2021. netif_stop_queue(dev);
  2022. np->tx_stop = 1;
  2023. spin_unlock_irqrestore(&np->lock, flags);
  2024. return NETDEV_TX_BUSY;
  2025. }
  2026. spin_unlock_irqrestore(&np->lock, flags);
  2027. start_tx = put_tx = np->put_tx.ex;
  2028. start_tx_ctx = np->put_tx_ctx;
  2029. /* setup the header buffer */
  2030. do {
  2031. prev_tx = put_tx;
  2032. prev_tx_ctx = np->put_tx_ctx;
  2033. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  2034. np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
  2035. PCI_DMA_TODEVICE);
  2036. np->put_tx_ctx->dma_len = bcnt;
  2037. np->put_tx_ctx->dma_single = 1;
  2038. put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
  2039. put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
  2040. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  2041. tx_flags = NV_TX2_VALID;
  2042. offset += bcnt;
  2043. size -= bcnt;
  2044. if (unlikely(put_tx++ == np->last_tx.ex))
  2045. put_tx = np->first_tx.ex;
  2046. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  2047. np->put_tx_ctx = np->first_tx_ctx;
  2048. } while (size);
  2049. /* setup the fragments */
  2050. for (i = 0; i < fragments; i++) {
  2051. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2052. u32 size = frag->size;
  2053. offset = 0;
  2054. do {
  2055. prev_tx = put_tx;
  2056. prev_tx_ctx = np->put_tx_ctx;
  2057. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  2058. np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
  2059. PCI_DMA_TODEVICE);
  2060. np->put_tx_ctx->dma_len = bcnt;
  2061. np->put_tx_ctx->dma_single = 0;
  2062. put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
  2063. put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
  2064. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  2065. offset += bcnt;
  2066. size -= bcnt;
  2067. if (unlikely(put_tx++ == np->last_tx.ex))
  2068. put_tx = np->first_tx.ex;
  2069. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  2070. np->put_tx_ctx = np->first_tx_ctx;
  2071. } while (size);
  2072. }
  2073. /* set last fragment flag */
  2074. prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
  2075. /* save skb in this slot's context area */
  2076. prev_tx_ctx->skb = skb;
  2077. if (skb_is_gso(skb))
  2078. tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
  2079. else
  2080. tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
  2081. NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
  2082. /* vlan tag */
  2083. if (likely(!np->vlangrp)) {
  2084. start_tx->txvlan = 0;
  2085. } else {
  2086. if (vlan_tx_tag_present(skb))
  2087. start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
  2088. else
  2089. start_tx->txvlan = 0;
  2090. }
  2091. spin_lock_irqsave(&np->lock, flags);
  2092. if (np->tx_limit) {
  2093. /* Limit the number of outstanding tx. Setup all fragments, but
  2094. * do not set the VALID bit on the first descriptor. Save a pointer
  2095. * to that descriptor and also for next skb_map element.
  2096. */
  2097. if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
  2098. if (!np->tx_change_owner)
  2099. np->tx_change_owner = start_tx_ctx;
  2100. /* remove VALID bit */
  2101. tx_flags &= ~NV_TX2_VALID;
  2102. start_tx_ctx->first_tx_desc = start_tx;
  2103. start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
  2104. np->tx_end_flip = np->put_tx_ctx;
  2105. } else {
  2106. np->tx_pkts_in_progress++;
  2107. }
  2108. }
  2109. /* set tx flags */
  2110. start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
  2111. np->put_tx.ex = put_tx;
  2112. spin_unlock_irqrestore(&np->lock, flags);
  2113. dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
  2114. dev->name, entries, tx_flags_extra);
  2115. {
  2116. int j;
  2117. for (j=0; j<64; j++) {
  2118. if ((j%16) == 0)
  2119. dprintk("\n%03x:", j);
  2120. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  2121. }
  2122. dprintk("\n");
  2123. }
  2124. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2125. return NETDEV_TX_OK;
  2126. }
  2127. static inline void nv_tx_flip_ownership(struct net_device *dev)
  2128. {
  2129. struct fe_priv *np = netdev_priv(dev);
  2130. np->tx_pkts_in_progress--;
  2131. if (np->tx_change_owner) {
  2132. np->tx_change_owner->first_tx_desc->flaglen |=
  2133. cpu_to_le32(NV_TX2_VALID);
  2134. np->tx_pkts_in_progress++;
  2135. np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
  2136. if (np->tx_change_owner == np->tx_end_flip)
  2137. np->tx_change_owner = NULL;
  2138. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2139. }
  2140. }
  2141. /*
  2142. * nv_tx_done: check for completed packets, release the skbs.
  2143. *
  2144. * Caller must own np->lock.
  2145. */
  2146. static int nv_tx_done(struct net_device *dev, int limit)
  2147. {
  2148. struct fe_priv *np = netdev_priv(dev);
  2149. u32 flags;
  2150. int tx_work = 0;
  2151. struct ring_desc* orig_get_tx = np->get_tx.orig;
  2152. while ((np->get_tx.orig != np->put_tx.orig) &&
  2153. !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
  2154. (tx_work < limit)) {
  2155. dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
  2156. dev->name, flags);
  2157. nv_unmap_txskb(np, np->get_tx_ctx);
  2158. if (np->desc_ver == DESC_VER_1) {
  2159. if (flags & NV_TX_LASTPACKET) {
  2160. if (flags & NV_TX_ERROR) {
  2161. if (flags & NV_TX_UNDERFLOW)
  2162. dev->stats.tx_fifo_errors++;
  2163. if (flags & NV_TX_CARRIERLOST)
  2164. dev->stats.tx_carrier_errors++;
  2165. if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
  2166. nv_legacybackoff_reseed(dev);
  2167. dev->stats.tx_errors++;
  2168. } else {
  2169. dev->stats.tx_packets++;
  2170. dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
  2171. }
  2172. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2173. np->get_tx_ctx->skb = NULL;
  2174. tx_work++;
  2175. }
  2176. } else {
  2177. if (flags & NV_TX2_LASTPACKET) {
  2178. if (flags & NV_TX2_ERROR) {
  2179. if (flags & NV_TX2_UNDERFLOW)
  2180. dev->stats.tx_fifo_errors++;
  2181. if (flags & NV_TX2_CARRIERLOST)
  2182. dev->stats.tx_carrier_errors++;
  2183. if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
  2184. nv_legacybackoff_reseed(dev);
  2185. dev->stats.tx_errors++;
  2186. } else {
  2187. dev->stats.tx_packets++;
  2188. dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
  2189. }
  2190. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2191. np->get_tx_ctx->skb = NULL;
  2192. tx_work++;
  2193. }
  2194. }
  2195. if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
  2196. np->get_tx.orig = np->first_tx.orig;
  2197. if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
  2198. np->get_tx_ctx = np->first_tx_ctx;
  2199. }
  2200. if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
  2201. np->tx_stop = 0;
  2202. netif_wake_queue(dev);
  2203. }
  2204. return tx_work;
  2205. }
  2206. static int nv_tx_done_optimized(struct net_device *dev, int limit)
  2207. {
  2208. struct fe_priv *np = netdev_priv(dev);
  2209. u32 flags;
  2210. int tx_work = 0;
  2211. struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
  2212. while ((np->get_tx.ex != np->put_tx.ex) &&
  2213. !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
  2214. (tx_work < limit)) {
  2215. dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
  2216. dev->name, flags);
  2217. nv_unmap_txskb(np, np->get_tx_ctx);
  2218. if (flags & NV_TX2_LASTPACKET) {
  2219. if (!(flags & NV_TX2_ERROR))
  2220. dev->stats.tx_packets++;
  2221. else {
  2222. if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
  2223. if (np->driver_data & DEV_HAS_GEAR_MODE)
  2224. nv_gear_backoff_reseed(dev);
  2225. else
  2226. nv_legacybackoff_reseed(dev);
  2227. }
  2228. }
  2229. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2230. np->get_tx_ctx->skb = NULL;
  2231. tx_work++;
  2232. if (np->tx_limit) {
  2233. nv_tx_flip_ownership(dev);
  2234. }
  2235. }
  2236. if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
  2237. np->get_tx.ex = np->first_tx.ex;
  2238. if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
  2239. np->get_tx_ctx = np->first_tx_ctx;
  2240. }
  2241. if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
  2242. np->tx_stop = 0;
  2243. netif_wake_queue(dev);
  2244. }
  2245. return tx_work;
  2246. }
  2247. /*
  2248. * nv_tx_timeout: dev->tx_timeout function
  2249. * Called with netif_tx_lock held.
  2250. */
  2251. static void nv_tx_timeout(struct net_device *dev)
  2252. {
  2253. struct fe_priv *np = netdev_priv(dev);
  2254. u8 __iomem *base = get_hwbase(dev);
  2255. u32 status;
  2256. union ring_type put_tx;
  2257. int saved_tx_limit;
  2258. if (np->msi_flags & NV_MSI_X_ENABLED)
  2259. status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  2260. else
  2261. status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  2262. printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
  2263. {
  2264. int i;
  2265. printk(KERN_INFO "%s: Ring at %lx\n",
  2266. dev->name, (unsigned long)np->ring_addr);
  2267. printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
  2268. for (i=0;i<=np->register_size;i+= 32) {
  2269. printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
  2270. i,
  2271. readl(base + i + 0), readl(base + i + 4),
  2272. readl(base + i + 8), readl(base + i + 12),
  2273. readl(base + i + 16), readl(base + i + 20),
  2274. readl(base + i + 24), readl(base + i + 28));
  2275. }
  2276. printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
  2277. for (i=0;i<np->tx_ring_size;i+= 4) {
  2278. if (!nv_optimized(np)) {
  2279. printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
  2280. i,
  2281. le32_to_cpu(np->tx_ring.orig[i].buf),
  2282. le32_to_cpu(np->tx_ring.orig[i].flaglen),
  2283. le32_to_cpu(np->tx_ring.orig[i+1].buf),
  2284. le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
  2285. le32_to_cpu(np->tx_ring.orig[i+2].buf),
  2286. le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
  2287. le32_to_cpu(np->tx_ring.orig[i+3].buf),
  2288. le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
  2289. } else {
  2290. printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
  2291. i,
  2292. le32_to_cpu(np->tx_ring.ex[i].bufhigh),
  2293. le32_to_cpu(np->tx_ring.ex[i].buflow),
  2294. le32_to_cpu(np->tx_ring.ex[i].flaglen),
  2295. le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
  2296. le32_to_cpu(np->tx_ring.ex[i+1].buflow),
  2297. le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
  2298. le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
  2299. le32_to_cpu(np->tx_ring.ex[i+2].buflow),
  2300. le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
  2301. le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
  2302. le32_to_cpu(np->tx_ring.ex[i+3].buflow),
  2303. le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
  2304. }
  2305. }
  2306. }
  2307. spin_lock_irq(&np->lock);
  2308. /* 1) stop tx engine */
  2309. nv_stop_tx(dev);
  2310. /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
  2311. saved_tx_limit = np->tx_limit;
  2312. np->tx_limit = 0; /* prevent giving HW any limited pkts */
  2313. np->tx_stop = 0; /* prevent waking tx queue */
  2314. if (!nv_optimized(np))
  2315. nv_tx_done(dev, np->tx_ring_size);
  2316. else
  2317. nv_tx_done_optimized(dev, np->tx_ring_size);
  2318. /* save current HW postion */
  2319. if (np->tx_change_owner)
  2320. put_tx.ex = np->tx_change_owner->first_tx_desc;
  2321. else
  2322. put_tx = np->put_tx;
  2323. /* 3) clear all tx state */
  2324. nv_drain_tx(dev);
  2325. nv_init_tx(dev);
  2326. /* 4) restore state to current HW position */
  2327. np->get_tx = np->put_tx = put_tx;
  2328. np->tx_limit = saved_tx_limit;
  2329. /* 5) restart tx engine */
  2330. nv_start_tx(dev);
  2331. netif_wake_queue(dev);
  2332. spin_unlock_irq(&np->lock);
  2333. }
  2334. /*
  2335. * Called when the nic notices a mismatch between the actual data len on the
  2336. * wire and the len indicated in the 802 header
  2337. */
  2338. static int nv_getlen(struct net_device *dev, void *packet, int datalen)
  2339. {
  2340. int hdrlen; /* length of the 802 header */
  2341. int protolen; /* length as stored in the proto field */
  2342. /* 1) calculate len according to header */
  2343. if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
  2344. protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
  2345. hdrlen = VLAN_HLEN;
  2346. } else {
  2347. protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
  2348. hdrlen = ETH_HLEN;
  2349. }
  2350. dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
  2351. dev->name, datalen, protolen, hdrlen);
  2352. if (protolen > ETH_DATA_LEN)
  2353. return datalen; /* Value in proto field not a len, no checks possible */
  2354. protolen += hdrlen;
  2355. /* consistency checks: */
  2356. if (datalen > ETH_ZLEN) {
  2357. if (datalen >= protolen) {
  2358. /* more data on wire than in 802 header, trim of
  2359. * additional data.
  2360. */
  2361. dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
  2362. dev->name, protolen);
  2363. return protolen;
  2364. } else {
  2365. /* less data on wire than mentioned in header.
  2366. * Discard the packet.
  2367. */
  2368. dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
  2369. dev->name);
  2370. return -1;
  2371. }
  2372. } else {
  2373. /* short packet. Accept only if 802 values are also short */
  2374. if (protolen > ETH_ZLEN) {
  2375. dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
  2376. dev->name);
  2377. return -1;
  2378. }
  2379. dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
  2380. dev->name, datalen);
  2381. return datalen;
  2382. }
  2383. }
  2384. static int nv_rx_process(struct net_device *dev, int limit)
  2385. {
  2386. struct fe_priv *np = netdev_priv(dev);
  2387. u32 flags;
  2388. int rx_work = 0;
  2389. struct sk_buff *skb;
  2390. int len;
  2391. while((np->get_rx.orig != np->put_rx.orig) &&
  2392. !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
  2393. (rx_work < limit)) {
  2394. dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
  2395. dev->name, flags);
  2396. /*
  2397. * the packet is for us - immediately tear down the pci mapping.
  2398. * TODO: check if a prefetch of the first cacheline improves
  2399. * the performance.
  2400. */
  2401. pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
  2402. np->get_rx_ctx->dma_len,
  2403. PCI_DMA_FROMDEVICE);
  2404. skb = np->get_rx_ctx->skb;
  2405. np->get_rx_ctx->skb = NULL;
  2406. {
  2407. int j;
  2408. dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
  2409. for (j=0; j<64; j++) {
  2410. if ((j%16) == 0)
  2411. dprintk("\n%03x:", j);
  2412. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  2413. }
  2414. dprintk("\n");
  2415. }
  2416. /* look at what we actually got: */
  2417. if (np->desc_ver == DESC_VER_1) {
  2418. if (likely(flags & NV_RX_DESCRIPTORVALID)) {
  2419. len = flags & LEN_MASK_V1;
  2420. if (unlikely(flags & NV_RX_ERROR)) {
  2421. if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
  2422. len = nv_getlen(dev, skb->data, len);
  2423. if (len < 0) {
  2424. dev->stats.rx_errors++;
  2425. dev_kfree_skb(skb);
  2426. goto next_pkt;
  2427. }
  2428. }
  2429. /* framing errors are soft errors */
  2430. else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
  2431. if (flags & NV_RX_SUBSTRACT1) {
  2432. len--;
  2433. }
  2434. }
  2435. /* the rest are hard errors */
  2436. else {
  2437. if (flags & NV_RX_MISSEDFRAME)
  2438. dev->stats.rx_missed_errors++;
  2439. if (flags & NV_RX_CRCERR)
  2440. dev->stats.rx_crc_errors++;
  2441. if (flags & NV_RX_OVERFLOW)
  2442. dev->stats.rx_over_errors++;
  2443. dev->stats.rx_errors++;
  2444. dev_kfree_skb(skb);
  2445. goto next_pkt;
  2446. }
  2447. }
  2448. } else {
  2449. dev_kfree_skb(skb);
  2450. goto next_pkt;
  2451. }
  2452. } else {
  2453. if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
  2454. len = flags & LEN_MASK_V2;
  2455. if (unlikely(flags & NV_RX2_ERROR)) {
  2456. if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
  2457. len = nv_getlen(dev, skb->data, len);
  2458. if (len < 0) {
  2459. dev->stats.rx_errors++;
  2460. dev_kfree_skb(skb);
  2461. goto next_pkt;
  2462. }
  2463. }
  2464. /* framing errors are soft errors */
  2465. else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
  2466. if (flags & NV_RX2_SUBSTRACT1) {
  2467. len--;
  2468. }
  2469. }
  2470. /* the rest are hard errors */
  2471. else {
  2472. if (flags & NV_RX2_CRCERR)
  2473. dev->stats.rx_crc_errors++;
  2474. if (flags & NV_RX2_OVERFLOW)
  2475. dev->stats.rx_over_errors++;
  2476. dev->stats.rx_errors++;
  2477. dev_kfree_skb(skb);
  2478. goto next_pkt;
  2479. }
  2480. }
  2481. if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
  2482. ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
  2483. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2484. } else {
  2485. dev_kfree_skb(skb);
  2486. goto next_pkt;
  2487. }
  2488. }
  2489. /* got a valid packet - forward it to the network core */
  2490. skb_put(skb, len);
  2491. skb->protocol = eth_type_trans(skb, dev);
  2492. dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
  2493. dev->name, len, skb->protocol);
  2494. napi_gro_receive(&np->napi, skb);
  2495. dev->stats.rx_packets++;
  2496. dev->stats.rx_bytes += len;
  2497. next_pkt:
  2498. if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
  2499. np->get_rx.orig = np->first_rx.orig;
  2500. if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
  2501. np->get_rx_ctx = np->first_rx_ctx;
  2502. rx_work++;
  2503. }
  2504. return rx_work;
  2505. }
  2506. static int nv_rx_process_optimized(struct net_device *dev, int limit)
  2507. {
  2508. struct fe_priv *np = netdev_priv(dev);
  2509. u32 flags;
  2510. u32 vlanflags = 0;
  2511. int rx_work = 0;
  2512. struct sk_buff *skb;
  2513. int len;
  2514. while((np->get_rx.ex != np->put_rx.ex) &&
  2515. !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
  2516. (rx_work < limit)) {
  2517. dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
  2518. dev->name, flags);
  2519. /*
  2520. * the packet is for us - immediately tear down the pci mapping.
  2521. * TODO: check if a prefetch of the first cacheline improves
  2522. * the performance.
  2523. */
  2524. pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
  2525. np->get_rx_ctx->dma_len,
  2526. PCI_DMA_FROMDEVICE);
  2527. skb = np->get_rx_ctx->skb;
  2528. np->get_rx_ctx->skb = NULL;
  2529. {
  2530. int j;
  2531. dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
  2532. for (j=0; j<64; j++) {
  2533. if ((j%16) == 0)
  2534. dprintk("\n%03x:", j);
  2535. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  2536. }
  2537. dprintk("\n");
  2538. }
  2539. /* look at what we actually got: */
  2540. if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
  2541. len = flags & LEN_MASK_V2;
  2542. if (unlikely(flags & NV_RX2_ERROR)) {
  2543. if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
  2544. len = nv_getlen(dev, skb->data, len);
  2545. if (len < 0) {
  2546. dev_kfree_skb(skb);
  2547. goto next_pkt;
  2548. }
  2549. }
  2550. /* framing errors are soft errors */
  2551. else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
  2552. if (flags & NV_RX2_SUBSTRACT1) {
  2553. len--;
  2554. }
  2555. }
  2556. /* the rest are hard errors */
  2557. else {
  2558. dev_kfree_skb(skb);
  2559. goto next_pkt;
  2560. }
  2561. }
  2562. if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
  2563. ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
  2564. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2565. /* got a valid packet - forward it to the network core */
  2566. skb_put(skb, len);
  2567. skb->protocol = eth_type_trans(skb, dev);
  2568. prefetch(skb->data);
  2569. dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
  2570. dev->name, len, skb->protocol);
  2571. if (likely(!np->vlangrp)) {
  2572. napi_gro_receive(&np->napi, skb);
  2573. } else {
  2574. vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
  2575. if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
  2576. vlan_gro_receive(&np->napi, np->vlangrp,
  2577. vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
  2578. } else {
  2579. napi_gro_receive(&np->napi, skb);
  2580. }
  2581. }
  2582. dev->stats.rx_packets++;
  2583. dev->stats.rx_bytes += len;
  2584. } else {
  2585. dev_kfree_skb(skb);
  2586. }
  2587. next_pkt:
  2588. if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
  2589. np->get_rx.ex = np->first_rx.ex;
  2590. if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
  2591. np->get_rx_ctx = np->first_rx_ctx;
  2592. rx_work++;
  2593. }
  2594. return rx_work;
  2595. }
  2596. static void set_bufsize(struct net_device *dev)
  2597. {
  2598. struct fe_priv *np = netdev_priv(dev);
  2599. if (dev->mtu <= ETH_DATA_LEN)
  2600. np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
  2601. else
  2602. np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
  2603. }
  2604. /*
  2605. * nv_change_mtu: dev->change_mtu function
  2606. * Called with dev_base_lock held for read.
  2607. */
  2608. static int nv_change_mtu(struct net_device *dev, int new_mtu)
  2609. {
  2610. struct fe_priv *np = netdev_priv(dev);
  2611. int old_mtu;
  2612. if (new_mtu < 64 || new_mtu > np->pkt_limit)
  2613. return -EINVAL;
  2614. old_mtu = dev->mtu;
  2615. dev->mtu = new_mtu;
  2616. /* return early if the buffer sizes will not change */
  2617. if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
  2618. return 0;
  2619. if (old_mtu == new_mtu)
  2620. return 0;
  2621. /* synchronized against open : rtnl_lock() held by caller */
  2622. if (netif_running(dev)) {
  2623. u8 __iomem *base = get_hwbase(dev);
  2624. /*
  2625. * It seems that the nic preloads valid ring entries into an
  2626. * internal buffer. The procedure for flushing everything is
  2627. * guessed, there is probably a simpler approach.
  2628. * Changing the MTU is a rare event, it shouldn't matter.
  2629. */
  2630. nv_disable_irq(dev);
  2631. nv_napi_disable(dev);
  2632. netif_tx_lock_bh(dev);
  2633. netif_addr_lock(dev);
  2634. spin_lock(&np->lock);
  2635. /* stop engines */
  2636. nv_stop_rxtx(dev);
  2637. nv_txrx_reset(dev);
  2638. /* drain rx queue */
  2639. nv_drain_rxtx(dev);
  2640. /* reinit driver view of the rx queue */
  2641. set_bufsize(dev);
  2642. if (nv_init_ring(dev)) {
  2643. if (!np->in_shutdown)
  2644. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  2645. }
  2646. /* reinit nic view of the rx queue */
  2647. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  2648. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  2649. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  2650. base + NvRegRingSizes);
  2651. pci_push(base);
  2652. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2653. pci_push(base);
  2654. /* restart rx engine */
  2655. nv_start_rxtx(dev);
  2656. spin_unlock(&np->lock);
  2657. netif_addr_unlock(dev);
  2658. netif_tx_unlock_bh(dev);
  2659. nv_napi_enable(dev);
  2660. nv_enable_irq(dev);
  2661. }
  2662. return 0;
  2663. }
  2664. static void nv_copy_mac_to_hw(struct net_device *dev)
  2665. {
  2666. u8 __iomem *base = get_hwbase(dev);
  2667. u32 mac[2];
  2668. mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
  2669. (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
  2670. mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
  2671. writel(mac[0], base + NvRegMacAddrA);
  2672. writel(mac[1], base + NvRegMacAddrB);
  2673. }
  2674. /*
  2675. * nv_set_mac_address: dev->set_mac_address function
  2676. * Called with rtnl_lock() held.
  2677. */
  2678. static int nv_set_mac_address(struct net_device *dev, void *addr)
  2679. {
  2680. struct fe_priv *np = netdev_priv(dev);
  2681. struct sockaddr *macaddr = (struct sockaddr*)addr;
  2682. if (!is_valid_ether_addr(macaddr->sa_data))
  2683. return -EADDRNOTAVAIL;
  2684. /* synchronized against open : rtnl_lock() held by caller */
  2685. memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
  2686. if (netif_running(dev)) {
  2687. netif_tx_lock_bh(dev);
  2688. netif_addr_lock(dev);
  2689. spin_lock_irq(&np->lock);
  2690. /* stop rx engine */
  2691. nv_stop_rx(dev);
  2692. /* set mac address */
  2693. nv_copy_mac_to_hw(dev);
  2694. /* restart rx engine */
  2695. nv_start_rx(dev);
  2696. spin_unlock_irq(&np->lock);
  2697. netif_addr_unlock(dev);
  2698. netif_tx_unlock_bh(dev);
  2699. } else {
  2700. nv_copy_mac_to_hw(dev);
  2701. }
  2702. return 0;
  2703. }
  2704. /*
  2705. * nv_set_multicast: dev->set_multicast function
  2706. * Called with netif_tx_lock held.
  2707. */
  2708. static void nv_set_multicast(struct net_device *dev)
  2709. {
  2710. struct fe_priv *np = netdev_priv(dev);
  2711. u8 __iomem *base = get_hwbase(dev);
  2712. u32 addr[2];
  2713. u32 mask[2];
  2714. u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
  2715. memset(addr, 0, sizeof(addr));
  2716. memset(mask, 0, sizeof(mask));
  2717. if (dev->flags & IFF_PROMISC) {
  2718. pff |= NVREG_PFF_PROMISC;
  2719. } else {
  2720. pff |= NVREG_PFF_MYADDR;
  2721. if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
  2722. u32 alwaysOff[2];
  2723. u32 alwaysOn[2];
  2724. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
  2725. if (dev->flags & IFF_ALLMULTI) {
  2726. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
  2727. } else {
  2728. struct netdev_hw_addr *ha;
  2729. netdev_for_each_mc_addr(ha, dev) {
  2730. unsigned char *addr = ha->addr;
  2731. u32 a, b;
  2732. a = le32_to_cpu(*(__le32 *) addr);
  2733. b = le16_to_cpu(*(__le16 *) (&addr[4]));
  2734. alwaysOn[0] &= a;
  2735. alwaysOff[0] &= ~a;
  2736. alwaysOn[1] &= b;
  2737. alwaysOff[1] &= ~b;
  2738. }
  2739. }
  2740. addr[0] = alwaysOn[0];
  2741. addr[1] = alwaysOn[1];
  2742. mask[0] = alwaysOn[0] | alwaysOff[0];
  2743. mask[1] = alwaysOn[1] | alwaysOff[1];
  2744. } else {
  2745. mask[0] = NVREG_MCASTMASKA_NONE;
  2746. mask[1] = NVREG_MCASTMASKB_NONE;
  2747. }
  2748. }
  2749. addr[0] |= NVREG_MCASTADDRA_FORCE;
  2750. pff |= NVREG_PFF_ALWAYS;
  2751. spin_lock_irq(&np->lock);
  2752. nv_stop_rx(dev);
  2753. writel(addr[0], base + NvRegMulticastAddrA);
  2754. writel(addr[1], base + NvRegMulticastAddrB);
  2755. writel(mask[0], base + NvRegMulticastMaskA);
  2756. writel(mask[1], base + NvRegMulticastMaskB);
  2757. writel(pff, base + NvRegPacketFilterFlags);
  2758. dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
  2759. dev->name);
  2760. nv_start_rx(dev);
  2761. spin_unlock_irq(&np->lock);
  2762. }
  2763. static void nv_update_pause(struct net_device *dev, u32 pause_flags)
  2764. {
  2765. struct fe_priv *np = netdev_priv(dev);
  2766. u8 __iomem *base = get_hwbase(dev);
  2767. np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
  2768. if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
  2769. u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
  2770. if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
  2771. writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
  2772. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2773. } else {
  2774. writel(pff, base + NvRegPacketFilterFlags);
  2775. }
  2776. }
  2777. if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
  2778. u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
  2779. if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
  2780. u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
  2781. if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
  2782. pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
  2783. if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
  2784. pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
  2785. /* limit the number of tx pause frames to a default of 8 */
  2786. writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
  2787. }
  2788. writel(pause_enable, base + NvRegTxPauseFrame);
  2789. writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
  2790. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2791. } else {
  2792. writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
  2793. writel(regmisc, base + NvRegMisc1);
  2794. }
  2795. }
  2796. }
  2797. /**
  2798. * nv_update_linkspeed: Setup the MAC according to the link partner
  2799. * @dev: Network device to be configured
  2800. *
  2801. * The function queries the PHY and checks if there is a link partner.
  2802. * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
  2803. * set to 10 MBit HD.
  2804. *
  2805. * The function returns 0 if there is no link partner and 1 if there is
  2806. * a good link partner.
  2807. */
  2808. static int nv_update_linkspeed(struct net_device *dev)
  2809. {
  2810. struct fe_priv *np = netdev_priv(dev);
  2811. u8 __iomem *base = get_hwbase(dev);
  2812. int adv = 0;
  2813. int lpa = 0;
  2814. int adv_lpa, adv_pause, lpa_pause;
  2815. int newls = np->linkspeed;
  2816. int newdup = np->duplex;
  2817. int mii_status;
  2818. int retval = 0;
  2819. u32 control_1000, status_1000, phyreg, pause_flags, txreg;
  2820. u32 txrxFlags = 0;
  2821. u32 phy_exp;
  2822. /* BMSR_LSTATUS is latched, read it twice:
  2823. * we want the current value.
  2824. */
  2825. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  2826. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  2827. if (!(mii_status & BMSR_LSTATUS)) {
  2828. dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
  2829. dev->name);
  2830. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2831. newdup = 0;
  2832. retval = 0;
  2833. goto set_speed;
  2834. }
  2835. if (np->autoneg == 0) {
  2836. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
  2837. dev->name, np->fixed_mode);
  2838. if (np->fixed_mode & LPA_100FULL) {
  2839. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2840. newdup = 1;
  2841. } else if (np->fixed_mode & LPA_100HALF) {
  2842. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2843. newdup = 0;
  2844. } else if (np->fixed_mode & LPA_10FULL) {
  2845. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2846. newdup = 1;
  2847. } else {
  2848. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2849. newdup = 0;
  2850. }
  2851. retval = 1;
  2852. goto set_speed;
  2853. }
  2854. /* check auto negotiation is complete */
  2855. if (!(mii_status & BMSR_ANEGCOMPLETE)) {
  2856. /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
  2857. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2858. newdup = 0;
  2859. retval = 0;
  2860. dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
  2861. goto set_speed;
  2862. }
  2863. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  2864. lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
  2865. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
  2866. dev->name, adv, lpa);
  2867. retval = 1;
  2868. if (np->gigabit == PHY_GIGABIT) {
  2869. control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  2870. status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
  2871. if ((control_1000 & ADVERTISE_1000FULL) &&
  2872. (status_1000 & LPA_1000FULL)) {
  2873. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
  2874. dev->name);
  2875. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
  2876. newdup = 1;
  2877. goto set_speed;
  2878. }
  2879. }
  2880. /* FIXME: handle parallel detection properly */
  2881. adv_lpa = lpa & adv;
  2882. if (adv_lpa & LPA_100FULL) {
  2883. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2884. newdup = 1;
  2885. } else if (adv_lpa & LPA_100HALF) {
  2886. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2887. newdup = 0;
  2888. } else if (adv_lpa & LPA_10FULL) {
  2889. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2890. newdup = 1;
  2891. } else if (adv_lpa & LPA_10HALF) {
  2892. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2893. newdup = 0;
  2894. } else {
  2895. dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
  2896. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2897. newdup = 0;
  2898. }
  2899. set_speed:
  2900. if (np->duplex == newdup && np->linkspeed == newls)
  2901. return retval;
  2902. dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
  2903. dev->name, np->linkspeed, np->duplex, newls, newdup);
  2904. np->duplex = newdup;
  2905. np->linkspeed = newls;
  2906. /* The transmitter and receiver must be restarted for safe update */
  2907. if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
  2908. txrxFlags |= NV_RESTART_TX;
  2909. nv_stop_tx(dev);
  2910. }
  2911. if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
  2912. txrxFlags |= NV_RESTART_RX;
  2913. nv_stop_rx(dev);
  2914. }
  2915. if (np->gigabit == PHY_GIGABIT) {
  2916. phyreg = readl(base + NvRegSlotTime);
  2917. phyreg &= ~(0x3FF00);
  2918. if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
  2919. ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
  2920. phyreg |= NVREG_SLOTTIME_10_100_FULL;
  2921. else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
  2922. phyreg |= NVREG_SLOTTIME_1000_FULL;
  2923. writel(phyreg, base + NvRegSlotTime);
  2924. }
  2925. phyreg = readl(base + NvRegPhyInterface);
  2926. phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
  2927. if (np->duplex == 0)
  2928. phyreg |= PHY_HALF;
  2929. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
  2930. phyreg |= PHY_100;
  2931. else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2932. phyreg |= PHY_1000;
  2933. writel(phyreg, base + NvRegPhyInterface);
  2934. phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
  2935. if (phyreg & PHY_RGMII) {
  2936. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
  2937. txreg = NVREG_TX_DEFERRAL_RGMII_1000;
  2938. } else {
  2939. if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
  2940. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
  2941. txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
  2942. else
  2943. txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
  2944. } else {
  2945. txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
  2946. }
  2947. }
  2948. } else {
  2949. if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
  2950. txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
  2951. else
  2952. txreg = NVREG_TX_DEFERRAL_DEFAULT;
  2953. }
  2954. writel(txreg, base + NvRegTxDeferral);
  2955. if (np->desc_ver == DESC_VER_1) {
  2956. txreg = NVREG_TX_WM_DESC1_DEFAULT;
  2957. } else {
  2958. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2959. txreg = NVREG_TX_WM_DESC2_3_1000;
  2960. else
  2961. txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
  2962. }
  2963. writel(txreg, base + NvRegTxWatermark);
  2964. writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
  2965. base + NvRegMisc1);
  2966. pci_push(base);
  2967. writel(np->linkspeed, base + NvRegLinkSpeed);
  2968. pci_push(base);
  2969. pause_flags = 0;
  2970. /* setup pause frame */
  2971. if (np->duplex != 0) {
  2972. if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
  2973. adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
  2974. lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
  2975. switch (adv_pause) {
  2976. case ADVERTISE_PAUSE_CAP:
  2977. if (lpa_pause & LPA_PAUSE_CAP) {
  2978. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2979. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  2980. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2981. }
  2982. break;
  2983. case ADVERTISE_PAUSE_ASYM:
  2984. if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
  2985. {
  2986. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2987. }
  2988. break;
  2989. case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
  2990. if (lpa_pause & LPA_PAUSE_CAP)
  2991. {
  2992. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2993. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  2994. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2995. }
  2996. if (lpa_pause == LPA_PAUSE_ASYM)
  2997. {
  2998. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2999. }
  3000. break;
  3001. }
  3002. } else {
  3003. pause_flags = np->pause_flags;
  3004. }
  3005. }
  3006. nv_update_pause(dev, pause_flags);
  3007. if (txrxFlags & NV_RESTART_TX)
  3008. nv_start_tx(dev);
  3009. if (txrxFlags & NV_RESTART_RX)
  3010. nv_start_rx(dev);
  3011. return retval;
  3012. }
  3013. static void nv_linkchange(struct net_device *dev)
  3014. {
  3015. if (nv_update_linkspeed(dev)) {
  3016. if (!netif_carrier_ok(dev)) {
  3017. netif_carrier_on(dev);
  3018. printk(KERN_INFO "%s: link up.\n", dev->name);
  3019. nv_txrx_gate(dev, false);
  3020. nv_start_rx(dev);
  3021. }
  3022. } else {
  3023. if (netif_carrier_ok(dev)) {
  3024. netif_carrier_off(dev);
  3025. printk(KERN_INFO "%s: link down.\n", dev->name);
  3026. nv_txrx_gate(dev, true);
  3027. nv_stop_rx(dev);
  3028. }
  3029. }
  3030. }
  3031. static void nv_link_irq(struct net_device *dev)
  3032. {
  3033. u8 __iomem *base = get_hwbase(dev);
  3034. u32 miistat;
  3035. miistat = readl(base + NvRegMIIStatus);
  3036. writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
  3037. dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
  3038. if (miistat & (NVREG_MIISTAT_LINKCHANGE))
  3039. nv_linkchange(dev);
  3040. dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
  3041. }
  3042. static void nv_msi_workaround(struct fe_priv *np)
  3043. {
  3044. /* Need to toggle the msi irq mask within the ethernet device,
  3045. * otherwise, future interrupts will not be detected.
  3046. */
  3047. if (np->msi_flags & NV_MSI_ENABLED) {
  3048. u8 __iomem *base = np->base;
  3049. writel(0, base + NvRegMSIIrqMask);
  3050. writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
  3051. }
  3052. }
  3053. static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
  3054. {
  3055. struct fe_priv *np = netdev_priv(dev);
  3056. if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
  3057. if (total_work > NV_DYNAMIC_THRESHOLD) {
  3058. /* transition to poll based interrupts */
  3059. np->quiet_count = 0;
  3060. if (np->irqmask != NVREG_IRQMASK_CPU) {
  3061. np->irqmask = NVREG_IRQMASK_CPU;
  3062. return 1;
  3063. }
  3064. } else {
  3065. if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
  3066. np->quiet_count++;
  3067. } else {
  3068. /* reached a period of low activity, switch
  3069. to per tx/rx packet interrupts */
  3070. if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
  3071. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  3072. return 1;
  3073. }
  3074. }
  3075. }
  3076. }
  3077. return 0;
  3078. }
  3079. static irqreturn_t nv_nic_irq(int foo, void *data)
  3080. {
  3081. struct net_device *dev = (struct net_device *) data;
  3082. struct fe_priv *np = netdev_priv(dev);
  3083. u8 __iomem *base = get_hwbase(dev);
  3084. dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
  3085. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  3086. np->events = readl(base + NvRegIrqStatus);
  3087. writel(np->events, base + NvRegIrqStatus);
  3088. } else {
  3089. np->events = readl(base + NvRegMSIXIrqStatus);
  3090. writel(np->events, base + NvRegMSIXIrqStatus);
  3091. }
  3092. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
  3093. if (!(np->events & np->irqmask))
  3094. return IRQ_NONE;
  3095. nv_msi_workaround(np);
  3096. if (napi_schedule_prep(&np->napi)) {
  3097. /*
  3098. * Disable further irq's (msix not enabled with napi)
  3099. */
  3100. writel(0, base + NvRegIrqMask);
  3101. __napi_schedule(&np->napi);
  3102. }
  3103. dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
  3104. return IRQ_HANDLED;
  3105. }
  3106. /**
  3107. * All _optimized functions are used to help increase performance
  3108. * (reduce CPU and increase throughput). They use descripter version 3,
  3109. * compiler directives, and reduce memory accesses.
  3110. */
  3111. static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
  3112. {
  3113. struct net_device *dev = (struct net_device *) data;
  3114. struct fe_priv *np = netdev_priv(dev);
  3115. u8 __iomem *base = get_hwbase(dev);
  3116. dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
  3117. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  3118. np->events = readl(base + NvRegIrqStatus);
  3119. writel(np->events, base + NvRegIrqStatus);
  3120. } else {
  3121. np->events = readl(base + NvRegMSIXIrqStatus);
  3122. writel(np->events, base + NvRegMSIXIrqStatus);
  3123. }
  3124. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
  3125. if (!(np->events & np->irqmask))
  3126. return IRQ_NONE;
  3127. nv_msi_workaround(np);
  3128. if (napi_schedule_prep(&np->napi)) {
  3129. /*
  3130. * Disable further irq's (msix not enabled with napi)
  3131. */
  3132. writel(0, base + NvRegIrqMask);
  3133. __napi_schedule(&np->napi);
  3134. }
  3135. dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
  3136. return IRQ_HANDLED;
  3137. }
  3138. static irqreturn_t nv_nic_irq_tx(int foo, void *data)
  3139. {
  3140. struct net_device *dev = (struct net_device *) data;
  3141. struct fe_priv *np = netdev_priv(dev);
  3142. u8 __iomem *base = get_hwbase(dev);
  3143. u32 events;
  3144. int i;
  3145. unsigned long flags;
  3146. dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
  3147. for (i=0; ; i++) {
  3148. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
  3149. writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
  3150. dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
  3151. if (!(events & np->irqmask))
  3152. break;
  3153. spin_lock_irqsave(&np->lock, flags);
  3154. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  3155. spin_unlock_irqrestore(&np->lock, flags);
  3156. if (unlikely(i > max_interrupt_work)) {
  3157. spin_lock_irqsave(&np->lock, flags);
  3158. /* disable interrupts on the nic */
  3159. writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
  3160. pci_push(base);
  3161. if (!np->in_shutdown) {
  3162. np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
  3163. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3164. }
  3165. spin_unlock_irqrestore(&np->lock, flags);
  3166. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
  3167. break;
  3168. }
  3169. }
  3170. dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
  3171. return IRQ_RETVAL(i);
  3172. }
  3173. static int nv_napi_poll(struct napi_struct *napi, int budget)
  3174. {
  3175. struct fe_priv *np = container_of(napi, struct fe_priv, napi);
  3176. struct net_device *dev = np->dev;
  3177. u8 __iomem *base = get_hwbase(dev);
  3178. unsigned long flags;
  3179. int retcode;
  3180. int rx_count, tx_work=0, rx_work=0;
  3181. do {
  3182. if (!nv_optimized(np)) {
  3183. spin_lock_irqsave(&np->lock, flags);
  3184. tx_work += nv_tx_done(dev, np->tx_ring_size);
  3185. spin_unlock_irqrestore(&np->lock, flags);
  3186. rx_count = nv_rx_process(dev, budget - rx_work);
  3187. retcode = nv_alloc_rx(dev);
  3188. } else {
  3189. spin_lock_irqsave(&np->lock, flags);
  3190. tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
  3191. spin_unlock_irqrestore(&np->lock, flags);
  3192. rx_count = nv_rx_process_optimized(dev,
  3193. budget - rx_work);
  3194. retcode = nv_alloc_rx_optimized(dev);
  3195. }
  3196. } while (retcode == 0 &&
  3197. rx_count > 0 && (rx_work += rx_count) < budget);
  3198. if (retcode) {
  3199. spin_lock_irqsave(&np->lock, flags);
  3200. if (!np->in_shutdown)
  3201. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3202. spin_unlock_irqrestore(&np->lock, flags);
  3203. }
  3204. nv_change_interrupt_mode(dev, tx_work + rx_work);
  3205. if (unlikely(np->events & NVREG_IRQ_LINK)) {
  3206. spin_lock_irqsave(&np->lock, flags);
  3207. nv_link_irq(dev);
  3208. spin_unlock_irqrestore(&np->lock, flags);
  3209. }
  3210. if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
  3211. spin_lock_irqsave(&np->lock, flags);
  3212. nv_linkchange(dev);
  3213. spin_unlock_irqrestore(&np->lock, flags);
  3214. np->link_timeout = jiffies + LINK_TIMEOUT;
  3215. }
  3216. if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
  3217. spin_lock_irqsave(&np->lock, flags);
  3218. if (!np->in_shutdown) {
  3219. np->nic_poll_irq = np->irqmask;
  3220. np->recover_error = 1;
  3221. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3222. }
  3223. spin_unlock_irqrestore(&np->lock, flags);
  3224. napi_complete(napi);
  3225. return rx_work;
  3226. }
  3227. if (rx_work < budget) {
  3228. /* re-enable interrupts
  3229. (msix not enabled in napi) */
  3230. napi_complete(napi);
  3231. writel(np->irqmask, base + NvRegIrqMask);
  3232. }
  3233. return rx_work;
  3234. }
  3235. static irqreturn_t nv_nic_irq_rx(int foo, void *data)
  3236. {
  3237. struct net_device *dev = (struct net_device *) data;
  3238. struct fe_priv *np = netdev_priv(dev);
  3239. u8 __iomem *base = get_hwbase(dev);
  3240. u32 events;
  3241. int i;
  3242. unsigned long flags;
  3243. dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
  3244. for (i=0; ; i++) {
  3245. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
  3246. writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
  3247. dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
  3248. if (!(events & np->irqmask))
  3249. break;
  3250. if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
  3251. if (unlikely(nv_alloc_rx_optimized(dev))) {
  3252. spin_lock_irqsave(&np->lock, flags);
  3253. if (!np->in_shutdown)
  3254. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3255. spin_unlock_irqrestore(&np->lock, flags);
  3256. }
  3257. }
  3258. if (unlikely(i > max_interrupt_work)) {
  3259. spin_lock_irqsave(&np->lock, flags);
  3260. /* disable interrupts on the nic */
  3261. writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
  3262. pci_push(base);
  3263. if (!np->in_shutdown) {
  3264. np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
  3265. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3266. }
  3267. spin_unlock_irqrestore(&np->lock, flags);
  3268. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
  3269. break;
  3270. }
  3271. }
  3272. dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
  3273. return IRQ_RETVAL(i);
  3274. }
  3275. static irqreturn_t nv_nic_irq_other(int foo, void *data)
  3276. {
  3277. struct net_device *dev = (struct net_device *) data;
  3278. struct fe_priv *np = netdev_priv(dev);
  3279. u8 __iomem *base = get_hwbase(dev);
  3280. u32 events;
  3281. int i;
  3282. unsigned long flags;
  3283. dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
  3284. for (i=0; ; i++) {
  3285. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
  3286. writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
  3287. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
  3288. if (!(events & np->irqmask))
  3289. break;
  3290. /* check tx in case we reached max loop limit in tx isr */
  3291. spin_lock_irqsave(&np->lock, flags);
  3292. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  3293. spin_unlock_irqrestore(&np->lock, flags);
  3294. if (events & NVREG_IRQ_LINK) {
  3295. spin_lock_irqsave(&np->lock, flags);
  3296. nv_link_irq(dev);
  3297. spin_unlock_irqrestore(&np->lock, flags);
  3298. }
  3299. if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
  3300. spin_lock_irqsave(&np->lock, flags);
  3301. nv_linkchange(dev);
  3302. spin_unlock_irqrestore(&np->lock, flags);
  3303. np->link_timeout = jiffies + LINK_TIMEOUT;
  3304. }
  3305. if (events & NVREG_IRQ_RECOVER_ERROR) {
  3306. spin_lock_irq(&np->lock);
  3307. /* disable interrupts on the nic */
  3308. writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
  3309. pci_push(base);
  3310. if (!np->in_shutdown) {
  3311. np->nic_poll_irq |= NVREG_IRQ_OTHER;
  3312. np->recover_error = 1;
  3313. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3314. }
  3315. spin_unlock_irq(&np->lock);
  3316. break;
  3317. }
  3318. if (unlikely(i > max_interrupt_work)) {
  3319. spin_lock_irqsave(&np->lock, flags);
  3320. /* disable interrupts on the nic */
  3321. writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
  3322. pci_push(base);
  3323. if (!np->in_shutdown) {
  3324. np->nic_poll_irq |= NVREG_IRQ_OTHER;
  3325. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3326. }
  3327. spin_unlock_irqrestore(&np->lock, flags);
  3328. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
  3329. break;
  3330. }
  3331. }
  3332. dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
  3333. return IRQ_RETVAL(i);
  3334. }
  3335. static irqreturn_t nv_nic_irq_test(int foo, void *data)
  3336. {
  3337. struct net_device *dev = (struct net_device *) data;
  3338. struct fe_priv *np = netdev_priv(dev);
  3339. u8 __iomem *base = get_hwbase(dev);
  3340. u32 events;
  3341. dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
  3342. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  3343. events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  3344. writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
  3345. } else {
  3346. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  3347. writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
  3348. }
  3349. pci_push(base);
  3350. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
  3351. if (!(events & NVREG_IRQ_TIMER))
  3352. return IRQ_RETVAL(0);
  3353. nv_msi_workaround(np);
  3354. spin_lock(&np->lock);
  3355. np->intr_test = 1;
  3356. spin_unlock(&np->lock);
  3357. dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
  3358. return IRQ_RETVAL(1);
  3359. }
  3360. static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
  3361. {
  3362. u8 __iomem *base = get_hwbase(dev);
  3363. int i;
  3364. u32 msixmap = 0;
  3365. /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
  3366. * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
  3367. * the remaining 8 interrupts.
  3368. */
  3369. for (i = 0; i < 8; i++) {
  3370. if ((irqmask >> i) & 0x1) {
  3371. msixmap |= vector << (i << 2);
  3372. }
  3373. }
  3374. writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
  3375. msixmap = 0;
  3376. for (i = 0; i < 8; i++) {
  3377. if ((irqmask >> (i + 8)) & 0x1) {
  3378. msixmap |= vector << (i << 2);
  3379. }
  3380. }
  3381. writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
  3382. }
  3383. static int nv_request_irq(struct net_device *dev, int intr_test)
  3384. {
  3385. struct fe_priv *np = get_nvpriv(dev);
  3386. u8 __iomem *base = get_hwbase(dev);
  3387. int ret = 1;
  3388. int i;
  3389. irqreturn_t (*handler)(int foo, void *data);
  3390. if (intr_test) {
  3391. handler = nv_nic_irq_test;
  3392. } else {
  3393. if (nv_optimized(np))
  3394. handler = nv_nic_irq_optimized;
  3395. else
  3396. handler = nv_nic_irq;
  3397. }
  3398. if (np->msi_flags & NV_MSI_X_CAPABLE) {
  3399. for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
  3400. np->msi_x_entry[i].entry = i;
  3401. }
  3402. if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
  3403. np->msi_flags |= NV_MSI_X_ENABLED;
  3404. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
  3405. /* Request irq for rx handling */
  3406. sprintf(np->name_rx, "%s-rx", dev->name);
  3407. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
  3408. nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
  3409. printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
  3410. pci_disable_msix(np->pci_dev);
  3411. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3412. goto out_err;
  3413. }
  3414. /* Request irq for tx handling */
  3415. sprintf(np->name_tx, "%s-tx", dev->name);
  3416. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
  3417. nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
  3418. printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
  3419. pci_disable_msix(np->pci_dev);
  3420. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3421. goto out_free_rx;
  3422. }
  3423. /* Request irq for link and timer handling */
  3424. sprintf(np->name_other, "%s-other", dev->name);
  3425. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
  3426. nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
  3427. printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
  3428. pci_disable_msix(np->pci_dev);
  3429. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3430. goto out_free_tx;
  3431. }
  3432. /* map interrupts to their respective vector */
  3433. writel(0, base + NvRegMSIXMap0);
  3434. writel(0, base + NvRegMSIXMap1);
  3435. set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
  3436. set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
  3437. set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
  3438. } else {
  3439. /* Request irq for all interrupts */
  3440. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
  3441. printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
  3442. pci_disable_msix(np->pci_dev);
  3443. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3444. goto out_err;
  3445. }
  3446. /* map interrupts to vector 0 */
  3447. writel(0, base + NvRegMSIXMap0);
  3448. writel(0, base + NvRegMSIXMap1);
  3449. }
  3450. }
  3451. }
  3452. if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
  3453. if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
  3454. np->msi_flags |= NV_MSI_ENABLED;
  3455. dev->irq = np->pci_dev->irq;
  3456. if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
  3457. printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
  3458. pci_disable_msi(np->pci_dev);
  3459. np->msi_flags &= ~NV_MSI_ENABLED;
  3460. dev->irq = np->pci_dev->irq;
  3461. goto out_err;
  3462. }
  3463. /* map interrupts to vector 0 */
  3464. writel(0, base + NvRegMSIMap0);
  3465. writel(0, base + NvRegMSIMap1);
  3466. /* enable msi vector 0 */
  3467. writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
  3468. }
  3469. }
  3470. if (ret != 0) {
  3471. if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
  3472. goto out_err;
  3473. }
  3474. return 0;
  3475. out_free_tx:
  3476. free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
  3477. out_free_rx:
  3478. free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
  3479. out_err:
  3480. return 1;
  3481. }
  3482. static void nv_free_irq(struct net_device *dev)
  3483. {
  3484. struct fe_priv *np = get_nvpriv(dev);
  3485. int i;
  3486. if (np->msi_flags & NV_MSI_X_ENABLED) {
  3487. for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
  3488. free_irq(np->msi_x_entry[i].vector, dev);
  3489. }
  3490. pci_disable_msix(np->pci_dev);
  3491. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3492. } else {
  3493. free_irq(np->pci_dev->irq, dev);
  3494. if (np->msi_flags & NV_MSI_ENABLED) {
  3495. pci_disable_msi(np->pci_dev);
  3496. np->msi_flags &= ~NV_MSI_ENABLED;
  3497. }
  3498. }
  3499. }
  3500. static void nv_do_nic_poll(unsigned long data)
  3501. {
  3502. struct net_device *dev = (struct net_device *) data;
  3503. struct fe_priv *np = netdev_priv(dev);
  3504. u8 __iomem *base = get_hwbase(dev);
  3505. u32 mask = 0;
  3506. /*
  3507. * First disable irq(s) and then
  3508. * reenable interrupts on the nic, we have to do this before calling
  3509. * nv_nic_irq because that may decide to do otherwise
  3510. */
  3511. if (!using_multi_irqs(dev)) {
  3512. if (np->msi_flags & NV_MSI_X_ENABLED)
  3513. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  3514. else
  3515. disable_irq_lockdep(np->pci_dev->irq);
  3516. mask = np->irqmask;
  3517. } else {
  3518. if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
  3519. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  3520. mask |= NVREG_IRQ_RX_ALL;
  3521. }
  3522. if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
  3523. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  3524. mask |= NVREG_IRQ_TX_ALL;
  3525. }
  3526. if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
  3527. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  3528. mask |= NVREG_IRQ_OTHER;
  3529. }
  3530. }
  3531. /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
  3532. if (np->recover_error) {
  3533. np->recover_error = 0;
  3534. printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
  3535. if (netif_running(dev)) {
  3536. netif_tx_lock_bh(dev);
  3537. netif_addr_lock(dev);
  3538. spin_lock(&np->lock);
  3539. /* stop engines */
  3540. nv_stop_rxtx(dev);
  3541. if (np->driver_data & DEV_HAS_POWER_CNTRL)
  3542. nv_mac_reset(dev);
  3543. nv_txrx_reset(dev);
  3544. /* drain rx queue */
  3545. nv_drain_rxtx(dev);
  3546. /* reinit driver view of the rx queue */
  3547. set_bufsize(dev);
  3548. if (nv_init_ring(dev)) {
  3549. if (!np->in_shutdown)
  3550. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3551. }
  3552. /* reinit nic view of the rx queue */
  3553. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  3554. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  3555. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  3556. base + NvRegRingSizes);
  3557. pci_push(base);
  3558. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  3559. pci_push(base);
  3560. /* clear interrupts */
  3561. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  3562. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  3563. else
  3564. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  3565. /* restart rx engine */
  3566. nv_start_rxtx(dev);
  3567. spin_unlock(&np->lock);
  3568. netif_addr_unlock(dev);
  3569. netif_tx_unlock_bh(dev);
  3570. }
  3571. }
  3572. writel(mask, base + NvRegIrqMask);
  3573. pci_push(base);
  3574. if (!using_multi_irqs(dev)) {
  3575. np->nic_poll_irq = 0;
  3576. if (nv_optimized(np))
  3577. nv_nic_irq_optimized(0, dev);
  3578. else
  3579. nv_nic_irq(0, dev);
  3580. if (np->msi_flags & NV_MSI_X_ENABLED)
  3581. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  3582. else
  3583. enable_irq_lockdep(np->pci_dev->irq);
  3584. } else {
  3585. if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
  3586. np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
  3587. nv_nic_irq_rx(0, dev);
  3588. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  3589. }
  3590. if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
  3591. np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
  3592. nv_nic_irq_tx(0, dev);
  3593. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  3594. }
  3595. if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
  3596. np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
  3597. nv_nic_irq_other(0, dev);
  3598. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  3599. }
  3600. }
  3601. }
  3602. #ifdef CONFIG_NET_POLL_CONTROLLER
  3603. static void nv_poll_controller(struct net_device *dev)
  3604. {
  3605. nv_do_nic_poll((unsigned long) dev);
  3606. }
  3607. #endif
  3608. static void nv_do_stats_poll(unsigned long data)
  3609. {
  3610. struct net_device *dev = (struct net_device *) data;
  3611. struct fe_priv *np = netdev_priv(dev);
  3612. nv_get_hw_stats(dev);
  3613. if (!np->in_shutdown)
  3614. mod_timer(&np->stats_poll,
  3615. round_jiffies(jiffies + STATS_INTERVAL));
  3616. }
  3617. static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  3618. {
  3619. struct fe_priv *np = netdev_priv(dev);
  3620. strcpy(info->driver, DRV_NAME);
  3621. strcpy(info->version, FORCEDETH_VERSION);
  3622. strcpy(info->bus_info, pci_name(np->pci_dev));
  3623. }
  3624. static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  3625. {
  3626. struct fe_priv *np = netdev_priv(dev);
  3627. wolinfo->supported = WAKE_MAGIC;
  3628. spin_lock_irq(&np->lock);
  3629. if (np->wolenabled)
  3630. wolinfo->wolopts = WAKE_MAGIC;
  3631. spin_unlock_irq(&np->lock);
  3632. }
  3633. static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  3634. {
  3635. struct fe_priv *np = netdev_priv(dev);
  3636. u8 __iomem *base = get_hwbase(dev);
  3637. u32 flags = 0;
  3638. if (wolinfo->wolopts == 0) {
  3639. np->wolenabled = 0;
  3640. } else if (wolinfo->wolopts & WAKE_MAGIC) {
  3641. np->wolenabled = 1;
  3642. flags = NVREG_WAKEUPFLAGS_ENABLE;
  3643. }
  3644. if (netif_running(dev)) {
  3645. spin_lock_irq(&np->lock);
  3646. writel(flags, base + NvRegWakeUpFlags);
  3647. spin_unlock_irq(&np->lock);
  3648. }
  3649. return 0;
  3650. }
  3651. static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  3652. {
  3653. struct fe_priv *np = netdev_priv(dev);
  3654. int adv;
  3655. spin_lock_irq(&np->lock);
  3656. ecmd->port = PORT_MII;
  3657. if (!netif_running(dev)) {
  3658. /* We do not track link speed / duplex setting if the
  3659. * interface is disabled. Force a link check */
  3660. if (nv_update_linkspeed(dev)) {
  3661. if (!netif_carrier_ok(dev))
  3662. netif_carrier_on(dev);
  3663. } else {
  3664. if (netif_carrier_ok(dev))
  3665. netif_carrier_off(dev);
  3666. }
  3667. }
  3668. if (netif_carrier_ok(dev)) {
  3669. switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
  3670. case NVREG_LINKSPEED_10:
  3671. ecmd->speed = SPEED_10;
  3672. break;
  3673. case NVREG_LINKSPEED_100:
  3674. ecmd->speed = SPEED_100;
  3675. break;
  3676. case NVREG_LINKSPEED_1000:
  3677. ecmd->speed = SPEED_1000;
  3678. break;
  3679. }
  3680. ecmd->duplex = DUPLEX_HALF;
  3681. if (np->duplex)
  3682. ecmd->duplex = DUPLEX_FULL;
  3683. } else {
  3684. ecmd->speed = -1;
  3685. ecmd->duplex = -1;
  3686. }
  3687. ecmd->autoneg = np->autoneg;
  3688. ecmd->advertising = ADVERTISED_MII;
  3689. if (np->autoneg) {
  3690. ecmd->advertising |= ADVERTISED_Autoneg;
  3691. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3692. if (adv & ADVERTISE_10HALF)
  3693. ecmd->advertising |= ADVERTISED_10baseT_Half;
  3694. if (adv & ADVERTISE_10FULL)
  3695. ecmd->advertising |= ADVERTISED_10baseT_Full;
  3696. if (adv & ADVERTISE_100HALF)
  3697. ecmd->advertising |= ADVERTISED_100baseT_Half;
  3698. if (adv & ADVERTISE_100FULL)
  3699. ecmd->advertising |= ADVERTISED_100baseT_Full;
  3700. if (np->gigabit == PHY_GIGABIT) {
  3701. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3702. if (adv & ADVERTISE_1000FULL)
  3703. ecmd->advertising |= ADVERTISED_1000baseT_Full;
  3704. }
  3705. }
  3706. ecmd->supported = (SUPPORTED_Autoneg |
  3707. SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  3708. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  3709. SUPPORTED_MII);
  3710. if (np->gigabit == PHY_GIGABIT)
  3711. ecmd->supported |= SUPPORTED_1000baseT_Full;
  3712. ecmd->phy_address = np->phyaddr;
  3713. ecmd->transceiver = XCVR_EXTERNAL;
  3714. /* ignore maxtxpkt, maxrxpkt for now */
  3715. spin_unlock_irq(&np->lock);
  3716. return 0;
  3717. }
  3718. static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  3719. {
  3720. struct fe_priv *np = netdev_priv(dev);
  3721. if (ecmd->port != PORT_MII)
  3722. return -EINVAL;
  3723. if (ecmd->transceiver != XCVR_EXTERNAL)
  3724. return -EINVAL;
  3725. if (ecmd->phy_address != np->phyaddr) {
  3726. /* TODO: support switching between multiple phys. Should be
  3727. * trivial, but not enabled due to lack of test hardware. */
  3728. return -EINVAL;
  3729. }
  3730. if (ecmd->autoneg == AUTONEG_ENABLE) {
  3731. u32 mask;
  3732. mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3733. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  3734. if (np->gigabit == PHY_GIGABIT)
  3735. mask |= ADVERTISED_1000baseT_Full;
  3736. if ((ecmd->advertising & mask) == 0)
  3737. return -EINVAL;
  3738. } else if (ecmd->autoneg == AUTONEG_DISABLE) {
  3739. /* Note: autonegotiation disable, speed 1000 intentionally
  3740. * forbidden - noone should need that. */
  3741. if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
  3742. return -EINVAL;
  3743. if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
  3744. return -EINVAL;
  3745. } else {
  3746. return -EINVAL;
  3747. }
  3748. netif_carrier_off(dev);
  3749. if (netif_running(dev)) {
  3750. unsigned long flags;
  3751. nv_disable_irq(dev);
  3752. netif_tx_lock_bh(dev);
  3753. netif_addr_lock(dev);
  3754. /* with plain spinlock lockdep complains */
  3755. spin_lock_irqsave(&np->lock, flags);
  3756. /* stop engines */
  3757. /* FIXME:
  3758. * this can take some time, and interrupts are disabled
  3759. * due to spin_lock_irqsave, but let's hope no daemon
  3760. * is going to change the settings very often...
  3761. * Worst case:
  3762. * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
  3763. * + some minor delays, which is up to a second approximately
  3764. */
  3765. nv_stop_rxtx(dev);
  3766. spin_unlock_irqrestore(&np->lock, flags);
  3767. netif_addr_unlock(dev);
  3768. netif_tx_unlock_bh(dev);
  3769. }
  3770. if (ecmd->autoneg == AUTONEG_ENABLE) {
  3771. int adv, bmcr;
  3772. np->autoneg = 1;
  3773. /* advertise only what has been requested */
  3774. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3775. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3776. if (ecmd->advertising & ADVERTISED_10baseT_Half)
  3777. adv |= ADVERTISE_10HALF;
  3778. if (ecmd->advertising & ADVERTISED_10baseT_Full)
  3779. adv |= ADVERTISE_10FULL;
  3780. if (ecmd->advertising & ADVERTISED_100baseT_Half)
  3781. adv |= ADVERTISE_100HALF;
  3782. if (ecmd->advertising & ADVERTISED_100baseT_Full)
  3783. adv |= ADVERTISE_100FULL;
  3784. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
  3785. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3786. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  3787. adv |= ADVERTISE_PAUSE_ASYM;
  3788. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3789. if (np->gigabit == PHY_GIGABIT) {
  3790. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3791. adv &= ~ADVERTISE_1000FULL;
  3792. if (ecmd->advertising & ADVERTISED_1000baseT_Full)
  3793. adv |= ADVERTISE_1000FULL;
  3794. mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
  3795. }
  3796. if (netif_running(dev))
  3797. printk(KERN_INFO "%s: link down.\n", dev->name);
  3798. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3799. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  3800. bmcr |= BMCR_ANENABLE;
  3801. /* reset the phy in order for settings to stick,
  3802. * and cause autoneg to start */
  3803. if (phy_reset(dev, bmcr)) {
  3804. printk(KERN_INFO "%s: phy reset failed\n", dev->name);
  3805. return -EINVAL;
  3806. }
  3807. } else {
  3808. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3809. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3810. }
  3811. } else {
  3812. int adv, bmcr;
  3813. np->autoneg = 0;
  3814. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3815. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3816. if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
  3817. adv |= ADVERTISE_10HALF;
  3818. if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
  3819. adv |= ADVERTISE_10FULL;
  3820. if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
  3821. adv |= ADVERTISE_100HALF;
  3822. if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
  3823. adv |= ADVERTISE_100FULL;
  3824. np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
  3825. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
  3826. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3827. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  3828. }
  3829. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
  3830. adv |= ADVERTISE_PAUSE_ASYM;
  3831. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  3832. }
  3833. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3834. np->fixed_mode = adv;
  3835. if (np->gigabit == PHY_GIGABIT) {
  3836. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3837. adv &= ~ADVERTISE_1000FULL;
  3838. mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
  3839. }
  3840. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3841. bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
  3842. if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
  3843. bmcr |= BMCR_FULLDPLX;
  3844. if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
  3845. bmcr |= BMCR_SPEED100;
  3846. if (np->phy_oui == PHY_OUI_MARVELL) {
  3847. /* reset the phy in order for forced mode settings to stick */
  3848. if (phy_reset(dev, bmcr)) {
  3849. printk(KERN_INFO "%s: phy reset failed\n", dev->name);
  3850. return -EINVAL;
  3851. }
  3852. } else {
  3853. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3854. if (netif_running(dev)) {
  3855. /* Wait a bit and then reconfigure the nic. */
  3856. udelay(10);
  3857. nv_linkchange(dev);
  3858. }
  3859. }
  3860. }
  3861. if (netif_running(dev)) {
  3862. nv_start_rxtx(dev);
  3863. nv_enable_irq(dev);
  3864. }
  3865. return 0;
  3866. }
  3867. #define FORCEDETH_REGS_VER 1
  3868. static int nv_get_regs_len(struct net_device *dev)
  3869. {
  3870. struct fe_priv *np = netdev_priv(dev);
  3871. return np->register_size;
  3872. }
  3873. static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
  3874. {
  3875. struct fe_priv *np = netdev_priv(dev);
  3876. u8 __iomem *base = get_hwbase(dev);
  3877. u32 *rbuf = buf;
  3878. int i;
  3879. regs->version = FORCEDETH_REGS_VER;
  3880. spin_lock_irq(&np->lock);
  3881. for (i = 0;i <= np->register_size/sizeof(u32); i++)
  3882. rbuf[i] = readl(base + i*sizeof(u32));
  3883. spin_unlock_irq(&np->lock);
  3884. }
  3885. static int nv_nway_reset(struct net_device *dev)
  3886. {
  3887. struct fe_priv *np = netdev_priv(dev);
  3888. int ret;
  3889. if (np->autoneg) {
  3890. int bmcr;
  3891. netif_carrier_off(dev);
  3892. if (netif_running(dev)) {
  3893. nv_disable_irq(dev);
  3894. netif_tx_lock_bh(dev);
  3895. netif_addr_lock(dev);
  3896. spin_lock(&np->lock);
  3897. /* stop engines */
  3898. nv_stop_rxtx(dev);
  3899. spin_unlock(&np->lock);
  3900. netif_addr_unlock(dev);
  3901. netif_tx_unlock_bh(dev);
  3902. printk(KERN_INFO "%s: link down.\n", dev->name);
  3903. }
  3904. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3905. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  3906. bmcr |= BMCR_ANENABLE;
  3907. /* reset the phy in order for settings to stick*/
  3908. if (phy_reset(dev, bmcr)) {
  3909. printk(KERN_INFO "%s: phy reset failed\n", dev->name);
  3910. return -EINVAL;
  3911. }
  3912. } else {
  3913. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3914. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3915. }
  3916. if (netif_running(dev)) {
  3917. nv_start_rxtx(dev);
  3918. nv_enable_irq(dev);
  3919. }
  3920. ret = 0;
  3921. } else {
  3922. ret = -EINVAL;
  3923. }
  3924. return ret;
  3925. }
  3926. static int nv_set_tso(struct net_device *dev, u32 value)
  3927. {
  3928. struct fe_priv *np = netdev_priv(dev);
  3929. if ((np->driver_data & DEV_HAS_CHECKSUM))
  3930. return ethtool_op_set_tso(dev, value);
  3931. else
  3932. return -EOPNOTSUPP;
  3933. }
  3934. static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  3935. {
  3936. struct fe_priv *np = netdev_priv(dev);
  3937. ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
  3938. ring->rx_mini_max_pending = 0;
  3939. ring->rx_jumbo_max_pending = 0;
  3940. ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
  3941. ring->rx_pending = np->rx_ring_size;
  3942. ring->rx_mini_pending = 0;
  3943. ring->rx_jumbo_pending = 0;
  3944. ring->tx_pending = np->tx_ring_size;
  3945. }
  3946. static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  3947. {
  3948. struct fe_priv *np = netdev_priv(dev);
  3949. u8 __iomem *base = get_hwbase(dev);
  3950. u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
  3951. dma_addr_t ring_addr;
  3952. if (ring->rx_pending < RX_RING_MIN ||
  3953. ring->tx_pending < TX_RING_MIN ||
  3954. ring->rx_mini_pending != 0 ||
  3955. ring->rx_jumbo_pending != 0 ||
  3956. (np->desc_ver == DESC_VER_1 &&
  3957. (ring->rx_pending > RING_MAX_DESC_VER_1 ||
  3958. ring->tx_pending > RING_MAX_DESC_VER_1)) ||
  3959. (np->desc_ver != DESC_VER_1 &&
  3960. (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
  3961. ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
  3962. return -EINVAL;
  3963. }
  3964. /* allocate new rings */
  3965. if (!nv_optimized(np)) {
  3966. rxtx_ring = pci_alloc_consistent(np->pci_dev,
  3967. sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
  3968. &ring_addr);
  3969. } else {
  3970. rxtx_ring = pci_alloc_consistent(np->pci_dev,
  3971. sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
  3972. &ring_addr);
  3973. }
  3974. rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
  3975. tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
  3976. if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
  3977. /* fall back to old rings */
  3978. if (!nv_optimized(np)) {
  3979. if (rxtx_ring)
  3980. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
  3981. rxtx_ring, ring_addr);
  3982. } else {
  3983. if (rxtx_ring)
  3984. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
  3985. rxtx_ring, ring_addr);
  3986. }
  3987. if (rx_skbuff)
  3988. kfree(rx_skbuff);
  3989. if (tx_skbuff)
  3990. kfree(tx_skbuff);
  3991. goto exit;
  3992. }
  3993. if (netif_running(dev)) {
  3994. nv_disable_irq(dev);
  3995. nv_napi_disable(dev);
  3996. netif_tx_lock_bh(dev);
  3997. netif_addr_lock(dev);
  3998. spin_lock(&np->lock);
  3999. /* stop engines */
  4000. nv_stop_rxtx(dev);
  4001. nv_txrx_reset(dev);
  4002. /* drain queues */
  4003. nv_drain_rxtx(dev);
  4004. /* delete queues */
  4005. free_rings(dev);
  4006. }
  4007. /* set new values */
  4008. np->rx_ring_size = ring->rx_pending;
  4009. np->tx_ring_size = ring->tx_pending;
  4010. if (!nv_optimized(np)) {
  4011. np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
  4012. np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
  4013. } else {
  4014. np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
  4015. np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
  4016. }
  4017. np->rx_skb = (struct nv_skb_map*)rx_skbuff;
  4018. np->tx_skb = (struct nv_skb_map*)tx_skbuff;
  4019. np->ring_addr = ring_addr;
  4020. memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
  4021. memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
  4022. if (netif_running(dev)) {
  4023. /* reinit driver view of the queues */
  4024. set_bufsize(dev);
  4025. if (nv_init_ring(dev)) {
  4026. if (!np->in_shutdown)
  4027. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4028. }
  4029. /* reinit nic view of the queues */
  4030. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4031. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4032. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4033. base + NvRegRingSizes);
  4034. pci_push(base);
  4035. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4036. pci_push(base);
  4037. /* restart engines */
  4038. nv_start_rxtx(dev);
  4039. spin_unlock(&np->lock);
  4040. netif_addr_unlock(dev);
  4041. netif_tx_unlock_bh(dev);
  4042. nv_napi_enable(dev);
  4043. nv_enable_irq(dev);
  4044. }
  4045. return 0;
  4046. exit:
  4047. return -ENOMEM;
  4048. }
  4049. static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
  4050. {
  4051. struct fe_priv *np = netdev_priv(dev);
  4052. pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
  4053. pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
  4054. pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
  4055. }
  4056. static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
  4057. {
  4058. struct fe_priv *np = netdev_priv(dev);
  4059. int adv, bmcr;
  4060. if ((!np->autoneg && np->duplex == 0) ||
  4061. (np->autoneg && !pause->autoneg && np->duplex == 0)) {
  4062. printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
  4063. dev->name);
  4064. return -EINVAL;
  4065. }
  4066. if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
  4067. printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
  4068. return -EINVAL;
  4069. }
  4070. netif_carrier_off(dev);
  4071. if (netif_running(dev)) {
  4072. nv_disable_irq(dev);
  4073. netif_tx_lock_bh(dev);
  4074. netif_addr_lock(dev);
  4075. spin_lock(&np->lock);
  4076. /* stop engines */
  4077. nv_stop_rxtx(dev);
  4078. spin_unlock(&np->lock);
  4079. netif_addr_unlock(dev);
  4080. netif_tx_unlock_bh(dev);
  4081. }
  4082. np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
  4083. if (pause->rx_pause)
  4084. np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
  4085. if (pause->tx_pause)
  4086. np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
  4087. if (np->autoneg && pause->autoneg) {
  4088. np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
  4089. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  4090. adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  4091. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
  4092. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  4093. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  4094. adv |= ADVERTISE_PAUSE_ASYM;
  4095. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  4096. if (netif_running(dev))
  4097. printk(KERN_INFO "%s: link down.\n", dev->name);
  4098. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  4099. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  4100. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  4101. } else {
  4102. np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
  4103. if (pause->rx_pause)
  4104. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  4105. if (pause->tx_pause)
  4106. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  4107. if (!netif_running(dev))
  4108. nv_update_linkspeed(dev);
  4109. else
  4110. nv_update_pause(dev, np->pause_flags);
  4111. }
  4112. if (netif_running(dev)) {
  4113. nv_start_rxtx(dev);
  4114. nv_enable_irq(dev);
  4115. }
  4116. return 0;
  4117. }
  4118. static u32 nv_get_rx_csum(struct net_device *dev)
  4119. {
  4120. struct fe_priv *np = netdev_priv(dev);
  4121. return (np->rx_csum) != 0;
  4122. }
  4123. static int nv_set_rx_csum(struct net_device *dev, u32 data)
  4124. {
  4125. struct fe_priv *np = netdev_priv(dev);
  4126. u8 __iomem *base = get_hwbase(dev);
  4127. int retcode = 0;
  4128. if (np->driver_data & DEV_HAS_CHECKSUM) {
  4129. if (data) {
  4130. np->rx_csum = 1;
  4131. np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
  4132. } else {
  4133. np->rx_csum = 0;
  4134. /* vlan is dependent on rx checksum offload */
  4135. if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
  4136. np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
  4137. }
  4138. if (netif_running(dev)) {
  4139. spin_lock_irq(&np->lock);
  4140. writel(np->txrxctl_bits, base + NvRegTxRxControl);
  4141. spin_unlock_irq(&np->lock);
  4142. }
  4143. } else {
  4144. return -EINVAL;
  4145. }
  4146. return retcode;
  4147. }
  4148. static int nv_set_tx_csum(struct net_device *dev, u32 data)
  4149. {
  4150. struct fe_priv *np = netdev_priv(dev);
  4151. if (np->driver_data & DEV_HAS_CHECKSUM)
  4152. return ethtool_op_set_tx_csum(dev, data);
  4153. else
  4154. return -EOPNOTSUPP;
  4155. }
  4156. static int nv_set_sg(struct net_device *dev, u32 data)
  4157. {
  4158. struct fe_priv *np = netdev_priv(dev);
  4159. if (np->driver_data & DEV_HAS_CHECKSUM)
  4160. return ethtool_op_set_sg(dev, data);
  4161. else
  4162. return -EOPNOTSUPP;
  4163. }
  4164. static int nv_get_sset_count(struct net_device *dev, int sset)
  4165. {
  4166. struct fe_priv *np = netdev_priv(dev);
  4167. switch (sset) {
  4168. case ETH_SS_TEST:
  4169. if (np->driver_data & DEV_HAS_TEST_EXTENDED)
  4170. return NV_TEST_COUNT_EXTENDED;
  4171. else
  4172. return NV_TEST_COUNT_BASE;
  4173. case ETH_SS_STATS:
  4174. if (np->driver_data & DEV_HAS_STATISTICS_V3)
  4175. return NV_DEV_STATISTICS_V3_COUNT;
  4176. else if (np->driver_data & DEV_HAS_STATISTICS_V2)
  4177. return NV_DEV_STATISTICS_V2_COUNT;
  4178. else if (np->driver_data & DEV_HAS_STATISTICS_V1)
  4179. return NV_DEV_STATISTICS_V1_COUNT;
  4180. else
  4181. return 0;
  4182. default:
  4183. return -EOPNOTSUPP;
  4184. }
  4185. }
  4186. static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
  4187. {
  4188. struct fe_priv *np = netdev_priv(dev);
  4189. /* update stats */
  4190. nv_do_stats_poll((unsigned long)dev);
  4191. memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
  4192. }
  4193. static int nv_link_test(struct net_device *dev)
  4194. {
  4195. struct fe_priv *np = netdev_priv(dev);
  4196. int mii_status;
  4197. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4198. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4199. /* check phy link status */
  4200. if (!(mii_status & BMSR_LSTATUS))
  4201. return 0;
  4202. else
  4203. return 1;
  4204. }
  4205. static int nv_register_test(struct net_device *dev)
  4206. {
  4207. u8 __iomem *base = get_hwbase(dev);
  4208. int i = 0;
  4209. u32 orig_read, new_read;
  4210. do {
  4211. orig_read = readl(base + nv_registers_test[i].reg);
  4212. /* xor with mask to toggle bits */
  4213. orig_read ^= nv_registers_test[i].mask;
  4214. writel(orig_read, base + nv_registers_test[i].reg);
  4215. new_read = readl(base + nv_registers_test[i].reg);
  4216. if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
  4217. return 0;
  4218. /* restore original value */
  4219. orig_read ^= nv_registers_test[i].mask;
  4220. writel(orig_read, base + nv_registers_test[i].reg);
  4221. } while (nv_registers_test[++i].reg != 0);
  4222. return 1;
  4223. }
  4224. static int nv_interrupt_test(struct net_device *dev)
  4225. {
  4226. struct fe_priv *np = netdev_priv(dev);
  4227. u8 __iomem *base = get_hwbase(dev);
  4228. int ret = 1;
  4229. int testcnt;
  4230. u32 save_msi_flags, save_poll_interval = 0;
  4231. if (netif_running(dev)) {
  4232. /* free current irq */
  4233. nv_free_irq(dev);
  4234. save_poll_interval = readl(base+NvRegPollingInterval);
  4235. }
  4236. /* flag to test interrupt handler */
  4237. np->intr_test = 0;
  4238. /* setup test irq */
  4239. save_msi_flags = np->msi_flags;
  4240. np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
  4241. np->msi_flags |= 0x001; /* setup 1 vector */
  4242. if (nv_request_irq(dev, 1))
  4243. return 0;
  4244. /* setup timer interrupt */
  4245. writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
  4246. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4247. nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
  4248. /* wait for at least one interrupt */
  4249. msleep(100);
  4250. spin_lock_irq(&np->lock);
  4251. /* flag should be set within ISR */
  4252. testcnt = np->intr_test;
  4253. if (!testcnt)
  4254. ret = 2;
  4255. nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
  4256. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  4257. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4258. else
  4259. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  4260. spin_unlock_irq(&np->lock);
  4261. nv_free_irq(dev);
  4262. np->msi_flags = save_msi_flags;
  4263. if (netif_running(dev)) {
  4264. writel(save_poll_interval, base + NvRegPollingInterval);
  4265. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4266. /* restore original irq */
  4267. if (nv_request_irq(dev, 0))
  4268. return 0;
  4269. }
  4270. return ret;
  4271. }
  4272. static int nv_loopback_test(struct net_device *dev)
  4273. {
  4274. struct fe_priv *np = netdev_priv(dev);
  4275. u8 __iomem *base = get_hwbase(dev);
  4276. struct sk_buff *tx_skb, *rx_skb;
  4277. dma_addr_t test_dma_addr;
  4278. u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
  4279. u32 flags;
  4280. int len, i, pkt_len;
  4281. u8 *pkt_data;
  4282. u32 filter_flags = 0;
  4283. u32 misc1_flags = 0;
  4284. int ret = 1;
  4285. if (netif_running(dev)) {
  4286. nv_disable_irq(dev);
  4287. filter_flags = readl(base + NvRegPacketFilterFlags);
  4288. misc1_flags = readl(base + NvRegMisc1);
  4289. } else {
  4290. nv_txrx_reset(dev);
  4291. }
  4292. /* reinit driver view of the rx queue */
  4293. set_bufsize(dev);
  4294. nv_init_ring(dev);
  4295. /* setup hardware for loopback */
  4296. writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
  4297. writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
  4298. /* reinit nic view of the rx queue */
  4299. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4300. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4301. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4302. base + NvRegRingSizes);
  4303. pci_push(base);
  4304. /* restart rx engine */
  4305. nv_start_rxtx(dev);
  4306. /* setup packet for tx */
  4307. pkt_len = ETH_DATA_LEN;
  4308. tx_skb = dev_alloc_skb(pkt_len);
  4309. if (!tx_skb) {
  4310. printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
  4311. " of %s\n", dev->name);
  4312. ret = 0;
  4313. goto out;
  4314. }
  4315. test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
  4316. skb_tailroom(tx_skb),
  4317. PCI_DMA_FROMDEVICE);
  4318. pkt_data = skb_put(tx_skb, pkt_len);
  4319. for (i = 0; i < pkt_len; i++)
  4320. pkt_data[i] = (u8)(i & 0xff);
  4321. if (!nv_optimized(np)) {
  4322. np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
  4323. np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
  4324. } else {
  4325. np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
  4326. np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
  4327. np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
  4328. }
  4329. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4330. pci_push(get_hwbase(dev));
  4331. msleep(500);
  4332. /* check for rx of the packet */
  4333. if (!nv_optimized(np)) {
  4334. flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
  4335. len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
  4336. } else {
  4337. flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
  4338. len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
  4339. }
  4340. if (flags & NV_RX_AVAIL) {
  4341. ret = 0;
  4342. } else if (np->desc_ver == DESC_VER_1) {
  4343. if (flags & NV_RX_ERROR)
  4344. ret = 0;
  4345. } else {
  4346. if (flags & NV_RX2_ERROR) {
  4347. ret = 0;
  4348. }
  4349. }
  4350. if (ret) {
  4351. if (len != pkt_len) {
  4352. ret = 0;
  4353. dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
  4354. dev->name, len, pkt_len);
  4355. } else {
  4356. rx_skb = np->rx_skb[0].skb;
  4357. for (i = 0; i < pkt_len; i++) {
  4358. if (rx_skb->data[i] != (u8)(i & 0xff)) {
  4359. ret = 0;
  4360. dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
  4361. dev->name, i);
  4362. break;
  4363. }
  4364. }
  4365. }
  4366. } else {
  4367. dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
  4368. }
  4369. pci_unmap_single(np->pci_dev, test_dma_addr,
  4370. (skb_end_pointer(tx_skb) - tx_skb->data),
  4371. PCI_DMA_TODEVICE);
  4372. dev_kfree_skb_any(tx_skb);
  4373. out:
  4374. /* stop engines */
  4375. nv_stop_rxtx(dev);
  4376. nv_txrx_reset(dev);
  4377. /* drain rx queue */
  4378. nv_drain_rxtx(dev);
  4379. if (netif_running(dev)) {
  4380. writel(misc1_flags, base + NvRegMisc1);
  4381. writel(filter_flags, base + NvRegPacketFilterFlags);
  4382. nv_enable_irq(dev);
  4383. }
  4384. return ret;
  4385. }
  4386. static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
  4387. {
  4388. struct fe_priv *np = netdev_priv(dev);
  4389. u8 __iomem *base = get_hwbase(dev);
  4390. int result;
  4391. memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
  4392. if (!nv_link_test(dev)) {
  4393. test->flags |= ETH_TEST_FL_FAILED;
  4394. buffer[0] = 1;
  4395. }
  4396. if (test->flags & ETH_TEST_FL_OFFLINE) {
  4397. if (netif_running(dev)) {
  4398. netif_stop_queue(dev);
  4399. nv_napi_disable(dev);
  4400. netif_tx_lock_bh(dev);
  4401. netif_addr_lock(dev);
  4402. spin_lock_irq(&np->lock);
  4403. nv_disable_hw_interrupts(dev, np->irqmask);
  4404. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  4405. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4406. } else {
  4407. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  4408. }
  4409. /* stop engines */
  4410. nv_stop_rxtx(dev);
  4411. nv_txrx_reset(dev);
  4412. /* drain rx queue */
  4413. nv_drain_rxtx(dev);
  4414. spin_unlock_irq(&np->lock);
  4415. netif_addr_unlock(dev);
  4416. netif_tx_unlock_bh(dev);
  4417. }
  4418. if (!nv_register_test(dev)) {
  4419. test->flags |= ETH_TEST_FL_FAILED;
  4420. buffer[1] = 1;
  4421. }
  4422. result = nv_interrupt_test(dev);
  4423. if (result != 1) {
  4424. test->flags |= ETH_TEST_FL_FAILED;
  4425. buffer[2] = 1;
  4426. }
  4427. if (result == 0) {
  4428. /* bail out */
  4429. return;
  4430. }
  4431. if (!nv_loopback_test(dev)) {
  4432. test->flags |= ETH_TEST_FL_FAILED;
  4433. buffer[3] = 1;
  4434. }
  4435. if (netif_running(dev)) {
  4436. /* reinit driver view of the rx queue */
  4437. set_bufsize(dev);
  4438. if (nv_init_ring(dev)) {
  4439. if (!np->in_shutdown)
  4440. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4441. }
  4442. /* reinit nic view of the rx queue */
  4443. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4444. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4445. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4446. base + NvRegRingSizes);
  4447. pci_push(base);
  4448. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4449. pci_push(base);
  4450. /* restart rx engine */
  4451. nv_start_rxtx(dev);
  4452. netif_start_queue(dev);
  4453. nv_napi_enable(dev);
  4454. nv_enable_hw_interrupts(dev, np->irqmask);
  4455. }
  4456. }
  4457. }
  4458. static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
  4459. {
  4460. switch (stringset) {
  4461. case ETH_SS_STATS:
  4462. memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
  4463. break;
  4464. case ETH_SS_TEST:
  4465. memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
  4466. break;
  4467. }
  4468. }
  4469. static const struct ethtool_ops ops = {
  4470. .get_drvinfo = nv_get_drvinfo,
  4471. .get_link = ethtool_op_get_link,
  4472. .get_wol = nv_get_wol,
  4473. .set_wol = nv_set_wol,
  4474. .get_settings = nv_get_settings,
  4475. .set_settings = nv_set_settings,
  4476. .get_regs_len = nv_get_regs_len,
  4477. .get_regs = nv_get_regs,
  4478. .nway_reset = nv_nway_reset,
  4479. .set_tso = nv_set_tso,
  4480. .get_ringparam = nv_get_ringparam,
  4481. .set_ringparam = nv_set_ringparam,
  4482. .get_pauseparam = nv_get_pauseparam,
  4483. .set_pauseparam = nv_set_pauseparam,
  4484. .get_rx_csum = nv_get_rx_csum,
  4485. .set_rx_csum = nv_set_rx_csum,
  4486. .set_tx_csum = nv_set_tx_csum,
  4487. .set_sg = nv_set_sg,
  4488. .get_strings = nv_get_strings,
  4489. .get_ethtool_stats = nv_get_ethtool_stats,
  4490. .get_sset_count = nv_get_sset_count,
  4491. .self_test = nv_self_test,
  4492. };
  4493. static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  4494. {
  4495. struct fe_priv *np = get_nvpriv(dev);
  4496. spin_lock_irq(&np->lock);
  4497. /* save vlan group */
  4498. np->vlangrp = grp;
  4499. if (grp) {
  4500. /* enable vlan on MAC */
  4501. np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
  4502. } else {
  4503. /* disable vlan on MAC */
  4504. np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
  4505. np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
  4506. }
  4507. writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4508. spin_unlock_irq(&np->lock);
  4509. }
  4510. /* The mgmt unit and driver use a semaphore to access the phy during init */
  4511. static int nv_mgmt_acquire_sema(struct net_device *dev)
  4512. {
  4513. struct fe_priv *np = netdev_priv(dev);
  4514. u8 __iomem *base = get_hwbase(dev);
  4515. int i;
  4516. u32 tx_ctrl, mgmt_sema;
  4517. for (i = 0; i < 10; i++) {
  4518. mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
  4519. if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
  4520. break;
  4521. msleep(500);
  4522. }
  4523. if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
  4524. return 0;
  4525. for (i = 0; i < 2; i++) {
  4526. tx_ctrl = readl(base + NvRegTransmitterControl);
  4527. tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
  4528. writel(tx_ctrl, base + NvRegTransmitterControl);
  4529. /* verify that semaphore was acquired */
  4530. tx_ctrl = readl(base + NvRegTransmitterControl);
  4531. if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
  4532. ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
  4533. np->mgmt_sema = 1;
  4534. return 1;
  4535. }
  4536. else
  4537. udelay(50);
  4538. }
  4539. return 0;
  4540. }
  4541. static void nv_mgmt_release_sema(struct net_device *dev)
  4542. {
  4543. struct fe_priv *np = netdev_priv(dev);
  4544. u8 __iomem *base = get_hwbase(dev);
  4545. u32 tx_ctrl;
  4546. if (np->driver_data & DEV_HAS_MGMT_UNIT) {
  4547. if (np->mgmt_sema) {
  4548. tx_ctrl = readl(base + NvRegTransmitterControl);
  4549. tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
  4550. writel(tx_ctrl, base + NvRegTransmitterControl);
  4551. }
  4552. }
  4553. }
  4554. static int nv_mgmt_get_version(struct net_device *dev)
  4555. {
  4556. struct fe_priv *np = netdev_priv(dev);
  4557. u8 __iomem *base = get_hwbase(dev);
  4558. u32 data_ready = readl(base + NvRegTransmitterControl);
  4559. u32 data_ready2 = 0;
  4560. unsigned long start;
  4561. int ready = 0;
  4562. writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
  4563. writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
  4564. start = jiffies;
  4565. while (time_before(jiffies, start + 5*HZ)) {
  4566. data_ready2 = readl(base + NvRegTransmitterControl);
  4567. if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
  4568. ready = 1;
  4569. break;
  4570. }
  4571. schedule_timeout_uninterruptible(1);
  4572. }
  4573. if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
  4574. return 0;
  4575. np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
  4576. return 1;
  4577. }
  4578. static int nv_open(struct net_device *dev)
  4579. {
  4580. struct fe_priv *np = netdev_priv(dev);
  4581. u8 __iomem *base = get_hwbase(dev);
  4582. int ret = 1;
  4583. int oom, i;
  4584. u32 low;
  4585. dprintk(KERN_DEBUG "nv_open: begin\n");
  4586. /* power up phy */
  4587. mii_rw(dev, np->phyaddr, MII_BMCR,
  4588. mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
  4589. nv_txrx_gate(dev, false);
  4590. /* erase previous misconfiguration */
  4591. if (np->driver_data & DEV_HAS_POWER_CNTRL)
  4592. nv_mac_reset(dev);
  4593. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  4594. writel(0, base + NvRegMulticastAddrB);
  4595. writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
  4596. writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
  4597. writel(0, base + NvRegPacketFilterFlags);
  4598. writel(0, base + NvRegTransmitterControl);
  4599. writel(0, base + NvRegReceiverControl);
  4600. writel(0, base + NvRegAdapterControl);
  4601. if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
  4602. writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
  4603. /* initialize descriptor rings */
  4604. set_bufsize(dev);
  4605. oom = nv_init_ring(dev);
  4606. writel(0, base + NvRegLinkSpeed);
  4607. writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
  4608. nv_txrx_reset(dev);
  4609. writel(0, base + NvRegUnknownSetupReg6);
  4610. np->in_shutdown = 0;
  4611. /* give hw rings */
  4612. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4613. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4614. base + NvRegRingSizes);
  4615. writel(np->linkspeed, base + NvRegLinkSpeed);
  4616. if (np->desc_ver == DESC_VER_1)
  4617. writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
  4618. else
  4619. writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
  4620. writel(np->txrxctl_bits, base + NvRegTxRxControl);
  4621. writel(np->vlanctl_bits, base + NvRegVlanControl);
  4622. pci_push(base);
  4623. writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
  4624. reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
  4625. NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
  4626. KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
  4627. writel(0, base + NvRegMIIMask);
  4628. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4629. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4630. writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
  4631. writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
  4632. writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
  4633. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4634. writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
  4635. get_random_bytes(&low, sizeof(low));
  4636. low &= NVREG_SLOTTIME_MASK;
  4637. if (np->desc_ver == DESC_VER_1) {
  4638. writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
  4639. } else {
  4640. if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
  4641. /* setup legacy backoff */
  4642. writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
  4643. } else {
  4644. writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
  4645. nv_gear_backoff_reseed(dev);
  4646. }
  4647. }
  4648. writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
  4649. writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
  4650. if (poll_interval == -1) {
  4651. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
  4652. writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
  4653. else
  4654. writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
  4655. }
  4656. else
  4657. writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
  4658. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4659. writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
  4660. base + NvRegAdapterControl);
  4661. writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
  4662. writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
  4663. if (np->wolenabled)
  4664. writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
  4665. i = readl(base + NvRegPowerState);
  4666. if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
  4667. writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
  4668. pci_push(base);
  4669. udelay(10);
  4670. writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
  4671. nv_disable_hw_interrupts(dev, np->irqmask);
  4672. pci_push(base);
  4673. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4674. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4675. pci_push(base);
  4676. if (nv_request_irq(dev, 0)) {
  4677. goto out_drain;
  4678. }
  4679. /* ask for interrupts */
  4680. nv_enable_hw_interrupts(dev, np->irqmask);
  4681. spin_lock_irq(&np->lock);
  4682. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  4683. writel(0, base + NvRegMulticastAddrB);
  4684. writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
  4685. writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
  4686. writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
  4687. /* One manual link speed update: Interrupts are enabled, future link
  4688. * speed changes cause interrupts and are handled by nv_link_irq().
  4689. */
  4690. {
  4691. u32 miistat;
  4692. miistat = readl(base + NvRegMIIStatus);
  4693. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4694. dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
  4695. }
  4696. /* set linkspeed to invalid value, thus force nv_update_linkspeed
  4697. * to init hw */
  4698. np->linkspeed = 0;
  4699. ret = nv_update_linkspeed(dev);
  4700. nv_start_rxtx(dev);
  4701. netif_start_queue(dev);
  4702. nv_napi_enable(dev);
  4703. if (ret) {
  4704. netif_carrier_on(dev);
  4705. } else {
  4706. printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
  4707. netif_carrier_off(dev);
  4708. }
  4709. if (oom)
  4710. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4711. /* start statistics timer */
  4712. if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
  4713. mod_timer(&np->stats_poll,
  4714. round_jiffies(jiffies + STATS_INTERVAL));
  4715. spin_unlock_irq(&np->lock);
  4716. return 0;
  4717. out_drain:
  4718. nv_drain_rxtx(dev);
  4719. return ret;
  4720. }
  4721. static int nv_close(struct net_device *dev)
  4722. {
  4723. struct fe_priv *np = netdev_priv(dev);
  4724. u8 __iomem *base;
  4725. spin_lock_irq(&np->lock);
  4726. np->in_shutdown = 1;
  4727. spin_unlock_irq(&np->lock);
  4728. nv_napi_disable(dev);
  4729. synchronize_irq(np->pci_dev->irq);
  4730. del_timer_sync(&np->oom_kick);
  4731. del_timer_sync(&np->nic_poll);
  4732. del_timer_sync(&np->stats_poll);
  4733. netif_stop_queue(dev);
  4734. spin_lock_irq(&np->lock);
  4735. nv_stop_rxtx(dev);
  4736. nv_txrx_reset(dev);
  4737. /* disable interrupts on the nic or we will lock up */
  4738. base = get_hwbase(dev);
  4739. nv_disable_hw_interrupts(dev, np->irqmask);
  4740. pci_push(base);
  4741. dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
  4742. spin_unlock_irq(&np->lock);
  4743. nv_free_irq(dev);
  4744. nv_drain_rxtx(dev);
  4745. if (np->wolenabled || !phy_power_down) {
  4746. nv_txrx_gate(dev, false);
  4747. writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
  4748. nv_start_rx(dev);
  4749. } else {
  4750. /* power down phy */
  4751. mii_rw(dev, np->phyaddr, MII_BMCR,
  4752. mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
  4753. nv_txrx_gate(dev, true);
  4754. }
  4755. /* FIXME: power down nic */
  4756. return 0;
  4757. }
  4758. static const struct net_device_ops nv_netdev_ops = {
  4759. .ndo_open = nv_open,
  4760. .ndo_stop = nv_close,
  4761. .ndo_get_stats = nv_get_stats,
  4762. .ndo_start_xmit = nv_start_xmit,
  4763. .ndo_tx_timeout = nv_tx_timeout,
  4764. .ndo_change_mtu = nv_change_mtu,
  4765. .ndo_validate_addr = eth_validate_addr,
  4766. .ndo_set_mac_address = nv_set_mac_address,
  4767. .ndo_set_multicast_list = nv_set_multicast,
  4768. .ndo_vlan_rx_register = nv_vlan_rx_register,
  4769. #ifdef CONFIG_NET_POLL_CONTROLLER
  4770. .ndo_poll_controller = nv_poll_controller,
  4771. #endif
  4772. };
  4773. static const struct net_device_ops nv_netdev_ops_optimized = {
  4774. .ndo_open = nv_open,
  4775. .ndo_stop = nv_close,
  4776. .ndo_get_stats = nv_get_stats,
  4777. .ndo_start_xmit = nv_start_xmit_optimized,
  4778. .ndo_tx_timeout = nv_tx_timeout,
  4779. .ndo_change_mtu = nv_change_mtu,
  4780. .ndo_validate_addr = eth_validate_addr,
  4781. .ndo_set_mac_address = nv_set_mac_address,
  4782. .ndo_set_multicast_list = nv_set_multicast,
  4783. .ndo_vlan_rx_register = nv_vlan_rx_register,
  4784. #ifdef CONFIG_NET_POLL_CONTROLLER
  4785. .ndo_poll_controller = nv_poll_controller,
  4786. #endif
  4787. };
  4788. static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  4789. {
  4790. struct net_device *dev;
  4791. struct fe_priv *np;
  4792. unsigned long addr;
  4793. u8 __iomem *base;
  4794. int err, i;
  4795. u32 powerstate, txreg;
  4796. u32 phystate_orig = 0, phystate;
  4797. int phyinitialized = 0;
  4798. static int printed_version;
  4799. if (!printed_version++)
  4800. printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
  4801. " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
  4802. dev = alloc_etherdev(sizeof(struct fe_priv));
  4803. err = -ENOMEM;
  4804. if (!dev)
  4805. goto out;
  4806. np = netdev_priv(dev);
  4807. np->dev = dev;
  4808. np->pci_dev = pci_dev;
  4809. spin_lock_init(&np->lock);
  4810. SET_NETDEV_DEV(dev, &pci_dev->dev);
  4811. init_timer(&np->oom_kick);
  4812. np->oom_kick.data = (unsigned long) dev;
  4813. np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
  4814. init_timer(&np->nic_poll);
  4815. np->nic_poll.data = (unsigned long) dev;
  4816. np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
  4817. init_timer(&np->stats_poll);
  4818. np->stats_poll.data = (unsigned long) dev;
  4819. np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
  4820. err = pci_enable_device(pci_dev);
  4821. if (err)
  4822. goto out_free;
  4823. pci_set_master(pci_dev);
  4824. err = pci_request_regions(pci_dev, DRV_NAME);
  4825. if (err < 0)
  4826. goto out_disable;
  4827. if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
  4828. np->register_size = NV_PCI_REGSZ_VER3;
  4829. else if (id->driver_data & DEV_HAS_STATISTICS_V1)
  4830. np->register_size = NV_PCI_REGSZ_VER2;
  4831. else
  4832. np->register_size = NV_PCI_REGSZ_VER1;
  4833. err = -EINVAL;
  4834. addr = 0;
  4835. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  4836. dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
  4837. pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
  4838. pci_resource_len(pci_dev, i),
  4839. pci_resource_flags(pci_dev, i));
  4840. if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
  4841. pci_resource_len(pci_dev, i) >= np->register_size) {
  4842. addr = pci_resource_start(pci_dev, i);
  4843. break;
  4844. }
  4845. }
  4846. if (i == DEVICE_COUNT_RESOURCE) {
  4847. dev_printk(KERN_INFO, &pci_dev->dev,
  4848. "Couldn't find register window\n");
  4849. goto out_relreg;
  4850. }
  4851. /* copy of driver data */
  4852. np->driver_data = id->driver_data;
  4853. /* copy of device id */
  4854. np->device_id = id->device;
  4855. /* handle different descriptor versions */
  4856. if (id->driver_data & DEV_HAS_HIGH_DMA) {
  4857. /* packet format 3: supports 40-bit addressing */
  4858. np->desc_ver = DESC_VER_3;
  4859. np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
  4860. if (dma_64bit) {
  4861. if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
  4862. dev_printk(KERN_INFO, &pci_dev->dev,
  4863. "64-bit DMA failed, using 32-bit addressing\n");
  4864. else
  4865. dev->features |= NETIF_F_HIGHDMA;
  4866. if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
  4867. dev_printk(KERN_INFO, &pci_dev->dev,
  4868. "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
  4869. }
  4870. }
  4871. } else if (id->driver_data & DEV_HAS_LARGEDESC) {
  4872. /* packet format 2: supports jumbo frames */
  4873. np->desc_ver = DESC_VER_2;
  4874. np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
  4875. } else {
  4876. /* original packet format */
  4877. np->desc_ver = DESC_VER_1;
  4878. np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
  4879. }
  4880. np->pkt_limit = NV_PKTLIMIT_1;
  4881. if (id->driver_data & DEV_HAS_LARGEDESC)
  4882. np->pkt_limit = NV_PKTLIMIT_2;
  4883. if (id->driver_data & DEV_HAS_CHECKSUM) {
  4884. np->rx_csum = 1;
  4885. np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
  4886. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  4887. dev->features |= NETIF_F_TSO;
  4888. dev->features |= NETIF_F_GRO;
  4889. }
  4890. np->vlanctl_bits = 0;
  4891. if (id->driver_data & DEV_HAS_VLAN) {
  4892. np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
  4893. dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
  4894. }
  4895. np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
  4896. if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
  4897. (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
  4898. (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
  4899. np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
  4900. }
  4901. err = -ENOMEM;
  4902. np->base = ioremap(addr, np->register_size);
  4903. if (!np->base)
  4904. goto out_relreg;
  4905. dev->base_addr = (unsigned long)np->base;
  4906. dev->irq = pci_dev->irq;
  4907. np->rx_ring_size = RX_RING_DEFAULT;
  4908. np->tx_ring_size = TX_RING_DEFAULT;
  4909. if (!nv_optimized(np)) {
  4910. np->rx_ring.orig = pci_alloc_consistent(pci_dev,
  4911. sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
  4912. &np->ring_addr);
  4913. if (!np->rx_ring.orig)
  4914. goto out_unmap;
  4915. np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
  4916. } else {
  4917. np->rx_ring.ex = pci_alloc_consistent(pci_dev,
  4918. sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
  4919. &np->ring_addr);
  4920. if (!np->rx_ring.ex)
  4921. goto out_unmap;
  4922. np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
  4923. }
  4924. np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
  4925. np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
  4926. if (!np->rx_skb || !np->tx_skb)
  4927. goto out_freering;
  4928. if (!nv_optimized(np))
  4929. dev->netdev_ops = &nv_netdev_ops;
  4930. else
  4931. dev->netdev_ops = &nv_netdev_ops_optimized;
  4932. netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
  4933. SET_ETHTOOL_OPS(dev, &ops);
  4934. dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
  4935. pci_set_drvdata(pci_dev, dev);
  4936. /* read the mac address */
  4937. base = get_hwbase(dev);
  4938. np->orig_mac[0] = readl(base + NvRegMacAddrA);
  4939. np->orig_mac[1] = readl(base + NvRegMacAddrB);
  4940. /* check the workaround bit for correct mac address order */
  4941. txreg = readl(base + NvRegTransmitPoll);
  4942. if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
  4943. /* mac address is already in correct order */
  4944. dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
  4945. dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
  4946. dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
  4947. dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
  4948. dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
  4949. dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
  4950. } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
  4951. /* mac address is already in correct order */
  4952. dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
  4953. dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
  4954. dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
  4955. dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
  4956. dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
  4957. dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
  4958. /*
  4959. * Set orig mac address back to the reversed version.
  4960. * This flag will be cleared during low power transition.
  4961. * Therefore, we should always put back the reversed address.
  4962. */
  4963. np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
  4964. (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
  4965. np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
  4966. } else {
  4967. /* need to reverse mac address to correct order */
  4968. dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
  4969. dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
  4970. dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
  4971. dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
  4972. dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
  4973. dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
  4974. writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
  4975. printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
  4976. }
  4977. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  4978. if (!is_valid_ether_addr(dev->perm_addr)) {
  4979. /*
  4980. * Bad mac address. At least one bios sets the mac address
  4981. * to 01:23:45:67:89:ab
  4982. */
  4983. dev_printk(KERN_ERR, &pci_dev->dev,
  4984. "Invalid Mac address detected: %pM\n",
  4985. dev->dev_addr);
  4986. dev_printk(KERN_ERR, &pci_dev->dev,
  4987. "Please complain to your hardware vendor. Switching to a random MAC.\n");
  4988. random_ether_addr(dev->dev_addr);
  4989. }
  4990. dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
  4991. pci_name(pci_dev), dev->dev_addr);
  4992. /* set mac address */
  4993. nv_copy_mac_to_hw(dev);
  4994. /* Workaround current PCI init glitch: wakeup bits aren't
  4995. * being set from PCI PM capability.
  4996. */
  4997. device_init_wakeup(&pci_dev->dev, 1);
  4998. /* disable WOL */
  4999. writel(0, base + NvRegWakeUpFlags);
  5000. np->wolenabled = 0;
  5001. if (id->driver_data & DEV_HAS_POWER_CNTRL) {
  5002. /* take phy and nic out of low power mode */
  5003. powerstate = readl(base + NvRegPowerState2);
  5004. powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
  5005. if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
  5006. pci_dev->revision >= 0xA3)
  5007. powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
  5008. writel(powerstate, base + NvRegPowerState2);
  5009. }
  5010. if (np->desc_ver == DESC_VER_1) {
  5011. np->tx_flags = NV_TX_VALID;
  5012. } else {
  5013. np->tx_flags = NV_TX2_VALID;
  5014. }
  5015. np->msi_flags = 0;
  5016. if ((id->driver_data & DEV_HAS_MSI) && msi) {
  5017. np->msi_flags |= NV_MSI_CAPABLE;
  5018. }
  5019. if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
  5020. /* msix has had reported issues when modifying irqmask
  5021. as in the case of napi, therefore, disable for now
  5022. */
  5023. #if 0
  5024. np->msi_flags |= NV_MSI_X_CAPABLE;
  5025. #endif
  5026. }
  5027. if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
  5028. np->irqmask = NVREG_IRQMASK_CPU;
  5029. if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
  5030. np->msi_flags |= 0x0001;
  5031. } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
  5032. !(id->driver_data & DEV_NEED_TIMERIRQ)) {
  5033. /* start off in throughput mode */
  5034. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  5035. /* remove support for msix mode */
  5036. np->msi_flags &= ~NV_MSI_X_CAPABLE;
  5037. } else {
  5038. optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
  5039. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  5040. if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
  5041. np->msi_flags |= 0x0003;
  5042. }
  5043. if (id->driver_data & DEV_NEED_TIMERIRQ)
  5044. np->irqmask |= NVREG_IRQ_TIMER;
  5045. if (id->driver_data & DEV_NEED_LINKTIMER) {
  5046. dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
  5047. np->need_linktimer = 1;
  5048. np->link_timeout = jiffies + LINK_TIMEOUT;
  5049. } else {
  5050. dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
  5051. np->need_linktimer = 0;
  5052. }
  5053. /* Limit the number of tx's outstanding for hw bug */
  5054. if (id->driver_data & DEV_NEED_TX_LIMIT) {
  5055. np->tx_limit = 1;
  5056. if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
  5057. pci_dev->revision >= 0xA2)
  5058. np->tx_limit = 0;
  5059. }
  5060. /* clear phy state and temporarily halt phy interrupts */
  5061. writel(0, base + NvRegMIIMask);
  5062. phystate = readl(base + NvRegAdapterControl);
  5063. if (phystate & NVREG_ADAPTCTL_RUNNING) {
  5064. phystate_orig = 1;
  5065. phystate &= ~NVREG_ADAPTCTL_RUNNING;
  5066. writel(phystate, base + NvRegAdapterControl);
  5067. }
  5068. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  5069. if (id->driver_data & DEV_HAS_MGMT_UNIT) {
  5070. /* management unit running on the mac? */
  5071. if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
  5072. (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
  5073. nv_mgmt_acquire_sema(dev) &&
  5074. nv_mgmt_get_version(dev)) {
  5075. np->mac_in_use = 1;
  5076. if (np->mgmt_version > 0) {
  5077. np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
  5078. }
  5079. dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
  5080. pci_name(pci_dev), np->mac_in_use);
  5081. /* management unit setup the phy already? */
  5082. if (np->mac_in_use &&
  5083. ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
  5084. NVREG_XMITCTL_SYNC_PHY_INIT)) {
  5085. /* phy is inited by mgmt unit */
  5086. phyinitialized = 1;
  5087. dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
  5088. pci_name(pci_dev));
  5089. } else {
  5090. /* we need to init the phy */
  5091. }
  5092. }
  5093. }
  5094. /* find a suitable phy */
  5095. for (i = 1; i <= 32; i++) {
  5096. int id1, id2;
  5097. int phyaddr = i & 0x1F;
  5098. spin_lock_irq(&np->lock);
  5099. id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
  5100. spin_unlock_irq(&np->lock);
  5101. if (id1 < 0 || id1 == 0xffff)
  5102. continue;
  5103. spin_lock_irq(&np->lock);
  5104. id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
  5105. spin_unlock_irq(&np->lock);
  5106. if (id2 < 0 || id2 == 0xffff)
  5107. continue;
  5108. np->phy_model = id2 & PHYID2_MODEL_MASK;
  5109. id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
  5110. id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
  5111. dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
  5112. pci_name(pci_dev), id1, id2, phyaddr);
  5113. np->phyaddr = phyaddr;
  5114. np->phy_oui = id1 | id2;
  5115. /* Realtek hardcoded phy id1 to all zero's on certain phys */
  5116. if (np->phy_oui == PHY_OUI_REALTEK2)
  5117. np->phy_oui = PHY_OUI_REALTEK;
  5118. /* Setup phy revision for Realtek */
  5119. if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
  5120. np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
  5121. break;
  5122. }
  5123. if (i == 33) {
  5124. dev_printk(KERN_INFO, &pci_dev->dev,
  5125. "open: Could not find a valid PHY.\n");
  5126. goto out_error;
  5127. }
  5128. if (!phyinitialized) {
  5129. /* reset it */
  5130. phy_init(dev);
  5131. } else {
  5132. /* see if it is a gigabit phy */
  5133. u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  5134. if (mii_status & PHY_GIGABIT) {
  5135. np->gigabit = PHY_GIGABIT;
  5136. }
  5137. }
  5138. /* set default link speed settings */
  5139. np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  5140. np->duplex = 0;
  5141. np->autoneg = 1;
  5142. err = register_netdev(dev);
  5143. if (err) {
  5144. dev_printk(KERN_INFO, &pci_dev->dev,
  5145. "unable to register netdev: %d\n", err);
  5146. goto out_error;
  5147. }
  5148. dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
  5149. "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
  5150. dev->name,
  5151. np->phy_oui,
  5152. np->phyaddr,
  5153. dev->dev_addr[0],
  5154. dev->dev_addr[1],
  5155. dev->dev_addr[2],
  5156. dev->dev_addr[3],
  5157. dev->dev_addr[4],
  5158. dev->dev_addr[5]);
  5159. dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
  5160. dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
  5161. dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
  5162. "csum " : "",
  5163. dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
  5164. "vlan " : "",
  5165. id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
  5166. id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
  5167. id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
  5168. np->gigabit == PHY_GIGABIT ? "gbit " : "",
  5169. np->need_linktimer ? "lnktim " : "",
  5170. np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
  5171. np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
  5172. np->desc_ver);
  5173. return 0;
  5174. out_error:
  5175. if (phystate_orig)
  5176. writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
  5177. pci_set_drvdata(pci_dev, NULL);
  5178. out_freering:
  5179. free_rings(dev);
  5180. out_unmap:
  5181. iounmap(get_hwbase(dev));
  5182. out_relreg:
  5183. pci_release_regions(pci_dev);
  5184. out_disable:
  5185. pci_disable_device(pci_dev);
  5186. out_free:
  5187. free_netdev(dev);
  5188. out:
  5189. return err;
  5190. }
  5191. static void nv_restore_phy(struct net_device *dev)
  5192. {
  5193. struct fe_priv *np = netdev_priv(dev);
  5194. u16 phy_reserved, mii_control;
  5195. if (np->phy_oui == PHY_OUI_REALTEK &&
  5196. np->phy_model == PHY_MODEL_REALTEK_8201 &&
  5197. phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
  5198. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
  5199. phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
  5200. phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
  5201. phy_reserved |= PHY_REALTEK_INIT8;
  5202. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
  5203. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
  5204. /* restart auto negotiation */
  5205. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  5206. mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
  5207. mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
  5208. }
  5209. }
  5210. static void nv_restore_mac_addr(struct pci_dev *pci_dev)
  5211. {
  5212. struct net_device *dev = pci_get_drvdata(pci_dev);
  5213. struct fe_priv *np = netdev_priv(dev);
  5214. u8 __iomem *base = get_hwbase(dev);
  5215. /* special op: write back the misordered MAC address - otherwise
  5216. * the next nv_probe would see a wrong address.
  5217. */
  5218. writel(np->orig_mac[0], base + NvRegMacAddrA);
  5219. writel(np->orig_mac[1], base + NvRegMacAddrB);
  5220. writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
  5221. base + NvRegTransmitPoll);
  5222. }
  5223. static void __devexit nv_remove(struct pci_dev *pci_dev)
  5224. {
  5225. struct net_device *dev = pci_get_drvdata(pci_dev);
  5226. unregister_netdev(dev);
  5227. nv_restore_mac_addr(pci_dev);
  5228. /* restore any phy related changes */
  5229. nv_restore_phy(dev);
  5230. nv_mgmt_release_sema(dev);
  5231. /* free all structures */
  5232. free_rings(dev);
  5233. iounmap(get_hwbase(dev));
  5234. pci_release_regions(pci_dev);
  5235. pci_disable_device(pci_dev);
  5236. free_netdev(dev);
  5237. pci_set_drvdata(pci_dev, NULL);
  5238. }
  5239. #ifdef CONFIG_PM
  5240. static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
  5241. {
  5242. struct net_device *dev = pci_get_drvdata(pdev);
  5243. struct fe_priv *np = netdev_priv(dev);
  5244. u8 __iomem *base = get_hwbase(dev);
  5245. int i;
  5246. if (netif_running(dev)) {
  5247. // Gross.
  5248. nv_close(dev);
  5249. }
  5250. netif_device_detach(dev);
  5251. /* save non-pci configuration space */
  5252. for (i = 0;i <= np->register_size/sizeof(u32); i++)
  5253. np->saved_config_space[i] = readl(base + i*sizeof(u32));
  5254. pci_save_state(pdev);
  5255. pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
  5256. pci_disable_device(pdev);
  5257. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  5258. return 0;
  5259. }
  5260. static int nv_resume(struct pci_dev *pdev)
  5261. {
  5262. struct net_device *dev = pci_get_drvdata(pdev);
  5263. struct fe_priv *np = netdev_priv(dev);
  5264. u8 __iomem *base = get_hwbase(dev);
  5265. int i, rc = 0;
  5266. pci_set_power_state(pdev, PCI_D0);
  5267. pci_restore_state(pdev);
  5268. /* ack any pending wake events, disable PME */
  5269. pci_enable_wake(pdev, PCI_D0, 0);
  5270. /* restore non-pci configuration space */
  5271. for (i = 0;i <= np->register_size/sizeof(u32); i++)
  5272. writel(np->saved_config_space[i], base+i*sizeof(u32));
  5273. if (np->driver_data & DEV_NEED_MSI_FIX)
  5274. pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
  5275. /* restore phy state, including autoneg */
  5276. phy_init(dev);
  5277. netif_device_attach(dev);
  5278. if (netif_running(dev)) {
  5279. rc = nv_open(dev);
  5280. nv_set_multicast(dev);
  5281. }
  5282. return rc;
  5283. }
  5284. static void nv_shutdown(struct pci_dev *pdev)
  5285. {
  5286. struct net_device *dev = pci_get_drvdata(pdev);
  5287. struct fe_priv *np = netdev_priv(dev);
  5288. if (netif_running(dev))
  5289. nv_close(dev);
  5290. /*
  5291. * Restore the MAC so a kernel started by kexec won't get confused.
  5292. * If we really go for poweroff, we must not restore the MAC,
  5293. * otherwise the MAC for WOL will be reversed at least on some boards.
  5294. */
  5295. if (system_state != SYSTEM_POWER_OFF) {
  5296. nv_restore_mac_addr(pdev);
  5297. }
  5298. pci_disable_device(pdev);
  5299. /*
  5300. * Apparently it is not possible to reinitialise from D3 hot,
  5301. * only put the device into D3 if we really go for poweroff.
  5302. */
  5303. if (system_state == SYSTEM_POWER_OFF) {
  5304. if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
  5305. pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
  5306. pci_set_power_state(pdev, PCI_D3hot);
  5307. }
  5308. }
  5309. #else
  5310. #define nv_suspend NULL
  5311. #define nv_shutdown NULL
  5312. #define nv_resume NULL
  5313. #endif /* CONFIG_PM */
  5314. static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
  5315. { /* nForce Ethernet Controller */
  5316. PCI_DEVICE(0x10DE, 0x01C3),
  5317. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5318. },
  5319. { /* nForce2 Ethernet Controller */
  5320. PCI_DEVICE(0x10DE, 0x0066),
  5321. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5322. },
  5323. { /* nForce3 Ethernet Controller */
  5324. PCI_DEVICE(0x10DE, 0x00D6),
  5325. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5326. },
  5327. { /* nForce3 Ethernet Controller */
  5328. PCI_DEVICE(0x10DE, 0x0086),
  5329. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5330. },
  5331. { /* nForce3 Ethernet Controller */
  5332. PCI_DEVICE(0x10DE, 0x008C),
  5333. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5334. },
  5335. { /* nForce3 Ethernet Controller */
  5336. PCI_DEVICE(0x10DE, 0x00E6),
  5337. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5338. },
  5339. { /* nForce3 Ethernet Controller */
  5340. PCI_DEVICE(0x10DE, 0x00DF),
  5341. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5342. },
  5343. { /* CK804 Ethernet Controller */
  5344. PCI_DEVICE(0x10DE, 0x0056),
  5345. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5346. },
  5347. { /* CK804 Ethernet Controller */
  5348. PCI_DEVICE(0x10DE, 0x0057),
  5349. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5350. },
  5351. { /* MCP04 Ethernet Controller */
  5352. PCI_DEVICE(0x10DE, 0x0037),
  5353. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5354. },
  5355. { /* MCP04 Ethernet Controller */
  5356. PCI_DEVICE(0x10DE, 0x0038),
  5357. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5358. },
  5359. { /* MCP51 Ethernet Controller */
  5360. PCI_DEVICE(0x10DE, 0x0268),
  5361. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
  5362. },
  5363. { /* MCP51 Ethernet Controller */
  5364. PCI_DEVICE(0x10DE, 0x0269),
  5365. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
  5366. },
  5367. { /* MCP55 Ethernet Controller */
  5368. PCI_DEVICE(0x10DE, 0x0372),
  5369. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
  5370. },
  5371. { /* MCP55 Ethernet Controller */
  5372. PCI_DEVICE(0x10DE, 0x0373),
  5373. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
  5374. },
  5375. { /* MCP61 Ethernet Controller */
  5376. PCI_DEVICE(0x10DE, 0x03E5),
  5377. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5378. },
  5379. { /* MCP61 Ethernet Controller */
  5380. PCI_DEVICE(0x10DE, 0x03E6),
  5381. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5382. },
  5383. { /* MCP61 Ethernet Controller */
  5384. PCI_DEVICE(0x10DE, 0x03EE),
  5385. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5386. },
  5387. { /* MCP61 Ethernet Controller */
  5388. PCI_DEVICE(0x10DE, 0x03EF),
  5389. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5390. },
  5391. { /* MCP65 Ethernet Controller */
  5392. PCI_DEVICE(0x10DE, 0x0450),
  5393. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5394. },
  5395. { /* MCP65 Ethernet Controller */
  5396. PCI_DEVICE(0x10DE, 0x0451),
  5397. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5398. },
  5399. { /* MCP65 Ethernet Controller */
  5400. PCI_DEVICE(0x10DE, 0x0452),
  5401. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5402. },
  5403. { /* MCP65 Ethernet Controller */
  5404. PCI_DEVICE(0x10DE, 0x0453),
  5405. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5406. },
  5407. { /* MCP67 Ethernet Controller */
  5408. PCI_DEVICE(0x10DE, 0x054C),
  5409. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5410. },
  5411. { /* MCP67 Ethernet Controller */
  5412. PCI_DEVICE(0x10DE, 0x054D),
  5413. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5414. },
  5415. { /* MCP67 Ethernet Controller */
  5416. PCI_DEVICE(0x10DE, 0x054E),
  5417. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5418. },
  5419. { /* MCP67 Ethernet Controller */
  5420. PCI_DEVICE(0x10DE, 0x054F),
  5421. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5422. },
  5423. { /* MCP73 Ethernet Controller */
  5424. PCI_DEVICE(0x10DE, 0x07DC),
  5425. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5426. },
  5427. { /* MCP73 Ethernet Controller */
  5428. PCI_DEVICE(0x10DE, 0x07DD),
  5429. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5430. },
  5431. { /* MCP73 Ethernet Controller */
  5432. PCI_DEVICE(0x10DE, 0x07DE),
  5433. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5434. },
  5435. { /* MCP73 Ethernet Controller */
  5436. PCI_DEVICE(0x10DE, 0x07DF),
  5437. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5438. },
  5439. { /* MCP77 Ethernet Controller */
  5440. PCI_DEVICE(0x10DE, 0x0760),
  5441. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5442. },
  5443. { /* MCP77 Ethernet Controller */
  5444. PCI_DEVICE(0x10DE, 0x0761),
  5445. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5446. },
  5447. { /* MCP77 Ethernet Controller */
  5448. PCI_DEVICE(0x10DE, 0x0762),
  5449. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5450. },
  5451. { /* MCP77 Ethernet Controller */
  5452. PCI_DEVICE(0x10DE, 0x0763),
  5453. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5454. },
  5455. { /* MCP79 Ethernet Controller */
  5456. PCI_DEVICE(0x10DE, 0x0AB0),
  5457. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5458. },
  5459. { /* MCP79 Ethernet Controller */
  5460. PCI_DEVICE(0x10DE, 0x0AB1),
  5461. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5462. },
  5463. { /* MCP79 Ethernet Controller */
  5464. PCI_DEVICE(0x10DE, 0x0AB2),
  5465. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5466. },
  5467. { /* MCP79 Ethernet Controller */
  5468. PCI_DEVICE(0x10DE, 0x0AB3),
  5469. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5470. },
  5471. { /* MCP89 Ethernet Controller */
  5472. PCI_DEVICE(0x10DE, 0x0D7D),
  5473. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
  5474. },
  5475. {0,},
  5476. };
  5477. static struct pci_driver driver = {
  5478. .name = DRV_NAME,
  5479. .id_table = pci_tbl,
  5480. .probe = nv_probe,
  5481. .remove = __devexit_p(nv_remove),
  5482. .suspend = nv_suspend,
  5483. .resume = nv_resume,
  5484. .shutdown = nv_shutdown,
  5485. };
  5486. static int __init init_nic(void)
  5487. {
  5488. return pci_register_driver(&driver);
  5489. }
  5490. static void __exit exit_nic(void)
  5491. {
  5492. pci_unregister_driver(&driver);
  5493. }
  5494. module_param(max_interrupt_work, int, 0);
  5495. MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
  5496. module_param(optimization_mode, int, 0);
  5497. MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
  5498. module_param(poll_interval, int, 0);
  5499. MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
  5500. module_param(msi, int, 0);
  5501. MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
  5502. module_param(msix, int, 0);
  5503. MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
  5504. module_param(dma_64bit, int, 0);
  5505. MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
  5506. module_param(phy_cross, int, 0);
  5507. MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
  5508. module_param(phy_power_down, int, 0);
  5509. MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
  5510. MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
  5511. MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
  5512. MODULE_LICENSE("GPL");
  5513. MODULE_DEVICE_TABLE(pci, pci_tbl);
  5514. module_init(init_nic);
  5515. module_exit(exit_nic);