fec.c 36 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428
  1. /*
  2. * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * Right now, I am very wasteful with the buffers. I allocate memory
  6. * pages and then divide them into 2K frame buffers. This way I know I
  7. * have buffers large enough to hold one frame within one buffer descriptor.
  8. * Once I get this working, I will use 64 or 128 byte CPM buffers, which
  9. * will be much more memory efficient and will easily handle lots of
  10. * small packets.
  11. *
  12. * Much better multiple PHY support by Magnus Damm.
  13. * Copyright (c) 2000 Ericsson Radio Systems AB.
  14. *
  15. * Support for FEC controller of ColdFire processors.
  16. * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
  17. *
  18. * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  19. * Copyright (c) 2004-2006 Macq Electronique SA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/string.h>
  24. #include <linux/ptrace.h>
  25. #include <linux/errno.h>
  26. #include <linux/ioport.h>
  27. #include <linux/slab.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/pci.h>
  30. #include <linux/init.h>
  31. #include <linux/delay.h>
  32. #include <linux/netdevice.h>
  33. #include <linux/etherdevice.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/spinlock.h>
  36. #include <linux/workqueue.h>
  37. #include <linux/bitops.h>
  38. #include <linux/io.h>
  39. #include <linux/irq.h>
  40. #include <linux/clk.h>
  41. #include <linux/platform_device.h>
  42. #include <linux/phy.h>
  43. #include <linux/fec.h>
  44. #include <asm/cacheflush.h>
  45. #ifndef CONFIG_ARCH_MXC
  46. #include <asm/coldfire.h>
  47. #include <asm/mcfsim.h>
  48. #endif
  49. #include "fec.h"
  50. #ifdef CONFIG_ARCH_MXC
  51. #include <mach/hardware.h>
  52. #define FEC_ALIGNMENT 0xf
  53. #else
  54. #define FEC_ALIGNMENT 0x3
  55. #endif
  56. /*
  57. * Define the fixed address of the FEC hardware.
  58. */
  59. #if defined(CONFIG_M5272)
  60. static unsigned char fec_mac_default[] = {
  61. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  62. };
  63. /*
  64. * Some hardware gets it MAC address out of local flash memory.
  65. * if this is non-zero then assume it is the address to get MAC from.
  66. */
  67. #if defined(CONFIG_NETtel)
  68. #define FEC_FLASHMAC 0xf0006006
  69. #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
  70. #define FEC_FLASHMAC 0xf0006000
  71. #elif defined(CONFIG_CANCam)
  72. #define FEC_FLASHMAC 0xf0020000
  73. #elif defined (CONFIG_M5272C3)
  74. #define FEC_FLASHMAC (0xffe04000 + 4)
  75. #elif defined(CONFIG_MOD5272)
  76. #define FEC_FLASHMAC 0xffc0406b
  77. #else
  78. #define FEC_FLASHMAC 0
  79. #endif
  80. #endif /* CONFIG_M5272 */
  81. /* The number of Tx and Rx buffers. These are allocated from the page
  82. * pool. The code may assume these are power of two, so it it best
  83. * to keep them that size.
  84. * We don't need to allocate pages for the transmitter. We just use
  85. * the skbuffer directly.
  86. */
  87. #define FEC_ENET_RX_PAGES 8
  88. #define FEC_ENET_RX_FRSIZE 2048
  89. #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
  90. #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
  91. #define FEC_ENET_TX_FRSIZE 2048
  92. #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
  93. #define TX_RING_SIZE 16 /* Must be power of two */
  94. #define TX_RING_MOD_MASK 15 /* for this to work */
  95. #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
  96. #error "FEC: descriptor ring size constants too large"
  97. #endif
  98. /* Interrupt events/masks. */
  99. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  100. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  101. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  102. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  103. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  104. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  105. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  106. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  107. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  108. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  109. #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
  110. /* The FEC stores dest/src/type, data, and checksum for receive packets.
  111. */
  112. #define PKT_MAXBUF_SIZE 1518
  113. #define PKT_MINBUF_SIZE 64
  114. #define PKT_MAXBLR_SIZE 1520
  115. /*
  116. * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
  117. * size bits. Other FEC hardware does not, so we need to take that into
  118. * account when setting it.
  119. */
  120. #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
  121. defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
  122. #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
  123. #else
  124. #define OPT_FRAME_SIZE 0
  125. #endif
  126. /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
  127. * tx_bd_base always point to the base of the buffer descriptors. The
  128. * cur_rx and cur_tx point to the currently available buffer.
  129. * The dirty_tx tracks the current buffer that is being sent by the
  130. * controller. The cur_tx and dirty_tx are equal under both completely
  131. * empty and completely full conditions. The empty/ready indicator in
  132. * the buffer descriptor determines the actual condition.
  133. */
  134. struct fec_enet_private {
  135. /* Hardware registers of the FEC device */
  136. void __iomem *hwp;
  137. struct net_device *netdev;
  138. struct clk *clk;
  139. /* The saved address of a sent-in-place packet/buffer, for skfree(). */
  140. unsigned char *tx_bounce[TX_RING_SIZE];
  141. struct sk_buff* tx_skbuff[TX_RING_SIZE];
  142. struct sk_buff* rx_skbuff[RX_RING_SIZE];
  143. ushort skb_cur;
  144. ushort skb_dirty;
  145. /* CPM dual port RAM relative addresses */
  146. dma_addr_t bd_dma;
  147. /* Address of Rx and Tx buffers */
  148. struct bufdesc *rx_bd_base;
  149. struct bufdesc *tx_bd_base;
  150. /* The next free ring entry */
  151. struct bufdesc *cur_rx, *cur_tx;
  152. /* The ring entries to be free()ed */
  153. struct bufdesc *dirty_tx;
  154. uint tx_full;
  155. /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
  156. spinlock_t hw_lock;
  157. struct platform_device *pdev;
  158. int opened;
  159. /* Phylib and MDIO interface */
  160. struct mii_bus *mii_bus;
  161. struct phy_device *phy_dev;
  162. int mii_timeout;
  163. uint phy_speed;
  164. phy_interface_t phy_interface;
  165. int index;
  166. int link;
  167. int full_duplex;
  168. struct completion mdio_done;
  169. };
  170. static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
  171. static void fec_enet_tx(struct net_device *dev);
  172. static void fec_enet_rx(struct net_device *dev);
  173. static int fec_enet_close(struct net_device *dev);
  174. static void fec_restart(struct net_device *dev, int duplex);
  175. static void fec_stop(struct net_device *dev);
  176. /* FEC MII MMFR bits definition */
  177. #define FEC_MMFR_ST (1 << 30)
  178. #define FEC_MMFR_OP_READ (2 << 28)
  179. #define FEC_MMFR_OP_WRITE (1 << 28)
  180. #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
  181. #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
  182. #define FEC_MMFR_TA (2 << 16)
  183. #define FEC_MMFR_DATA(v) (v & 0xffff)
  184. #define FEC_MII_TIMEOUT 1000 /* us */
  185. /* Transmitter timeout */
  186. #define TX_TIMEOUT (2 * HZ)
  187. static netdev_tx_t
  188. fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
  189. {
  190. struct fec_enet_private *fep = netdev_priv(dev);
  191. struct bufdesc *bdp;
  192. void *bufaddr;
  193. unsigned short status;
  194. unsigned long flags;
  195. if (!fep->link) {
  196. /* Link is down or autonegotiation is in progress. */
  197. return NETDEV_TX_BUSY;
  198. }
  199. spin_lock_irqsave(&fep->hw_lock, flags);
  200. /* Fill in a Tx ring entry */
  201. bdp = fep->cur_tx;
  202. status = bdp->cbd_sc;
  203. if (status & BD_ENET_TX_READY) {
  204. /* Ooops. All transmit buffers are full. Bail out.
  205. * This should not happen, since dev->tbusy should be set.
  206. */
  207. printk("%s: tx queue full!.\n", dev->name);
  208. spin_unlock_irqrestore(&fep->hw_lock, flags);
  209. return NETDEV_TX_BUSY;
  210. }
  211. /* Clear all of the status flags */
  212. status &= ~BD_ENET_TX_STATS;
  213. /* Set buffer length and buffer pointer */
  214. bufaddr = skb->data;
  215. bdp->cbd_datlen = skb->len;
  216. /*
  217. * On some FEC implementations data must be aligned on
  218. * 4-byte boundaries. Use bounce buffers to copy data
  219. * and get it aligned. Ugh.
  220. */
  221. if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
  222. unsigned int index;
  223. index = bdp - fep->tx_bd_base;
  224. memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
  225. bufaddr = fep->tx_bounce[index];
  226. }
  227. /* Save skb pointer */
  228. fep->tx_skbuff[fep->skb_cur] = skb;
  229. dev->stats.tx_bytes += skb->len;
  230. fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
  231. /* Push the data cache so the CPM does not get stale memory
  232. * data.
  233. */
  234. bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr,
  235. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  236. /* Send it on its way. Tell FEC it's ready, interrupt when done,
  237. * it's the last BD of the frame, and to put the CRC on the end.
  238. */
  239. status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
  240. | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  241. bdp->cbd_sc = status;
  242. /* Trigger transmission start */
  243. writel(0, fep->hwp + FEC_X_DES_ACTIVE);
  244. /* If this was the last BD in the ring, start at the beginning again. */
  245. if (status & BD_ENET_TX_WRAP)
  246. bdp = fep->tx_bd_base;
  247. else
  248. bdp++;
  249. if (bdp == fep->dirty_tx) {
  250. fep->tx_full = 1;
  251. netif_stop_queue(dev);
  252. }
  253. fep->cur_tx = bdp;
  254. spin_unlock_irqrestore(&fep->hw_lock, flags);
  255. return NETDEV_TX_OK;
  256. }
  257. static void
  258. fec_timeout(struct net_device *dev)
  259. {
  260. struct fec_enet_private *fep = netdev_priv(dev);
  261. dev->stats.tx_errors++;
  262. fec_restart(dev, fep->full_duplex);
  263. netif_wake_queue(dev);
  264. }
  265. static irqreturn_t
  266. fec_enet_interrupt(int irq, void * dev_id)
  267. {
  268. struct net_device *dev = dev_id;
  269. struct fec_enet_private *fep = netdev_priv(dev);
  270. uint int_events;
  271. irqreturn_t ret = IRQ_NONE;
  272. do {
  273. int_events = readl(fep->hwp + FEC_IEVENT);
  274. writel(int_events, fep->hwp + FEC_IEVENT);
  275. if (int_events & FEC_ENET_RXF) {
  276. ret = IRQ_HANDLED;
  277. fec_enet_rx(dev);
  278. }
  279. /* Transmit OK, or non-fatal error. Update the buffer
  280. * descriptors. FEC handles all errors, we just discover
  281. * them as part of the transmit process.
  282. */
  283. if (int_events & FEC_ENET_TXF) {
  284. ret = IRQ_HANDLED;
  285. fec_enet_tx(dev);
  286. }
  287. if (int_events & FEC_ENET_MII) {
  288. ret = IRQ_HANDLED;
  289. complete(&fep->mdio_done);
  290. }
  291. } while (int_events);
  292. return ret;
  293. }
  294. static void
  295. fec_enet_tx(struct net_device *dev)
  296. {
  297. struct fec_enet_private *fep;
  298. struct bufdesc *bdp;
  299. unsigned short status;
  300. struct sk_buff *skb;
  301. fep = netdev_priv(dev);
  302. spin_lock(&fep->hw_lock);
  303. bdp = fep->dirty_tx;
  304. while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
  305. if (bdp == fep->cur_tx && fep->tx_full == 0)
  306. break;
  307. dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  308. bdp->cbd_bufaddr = 0;
  309. skb = fep->tx_skbuff[fep->skb_dirty];
  310. /* Check for errors. */
  311. if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
  312. BD_ENET_TX_RL | BD_ENET_TX_UN |
  313. BD_ENET_TX_CSL)) {
  314. dev->stats.tx_errors++;
  315. if (status & BD_ENET_TX_HB) /* No heartbeat */
  316. dev->stats.tx_heartbeat_errors++;
  317. if (status & BD_ENET_TX_LC) /* Late collision */
  318. dev->stats.tx_window_errors++;
  319. if (status & BD_ENET_TX_RL) /* Retrans limit */
  320. dev->stats.tx_aborted_errors++;
  321. if (status & BD_ENET_TX_UN) /* Underrun */
  322. dev->stats.tx_fifo_errors++;
  323. if (status & BD_ENET_TX_CSL) /* Carrier lost */
  324. dev->stats.tx_carrier_errors++;
  325. } else {
  326. dev->stats.tx_packets++;
  327. }
  328. if (status & BD_ENET_TX_READY)
  329. printk("HEY! Enet xmit interrupt and TX_READY.\n");
  330. /* Deferred means some collisions occurred during transmit,
  331. * but we eventually sent the packet OK.
  332. */
  333. if (status & BD_ENET_TX_DEF)
  334. dev->stats.collisions++;
  335. /* Free the sk buffer associated with this last transmit */
  336. dev_kfree_skb_any(skb);
  337. fep->tx_skbuff[fep->skb_dirty] = NULL;
  338. fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
  339. /* Update pointer to next buffer descriptor to be transmitted */
  340. if (status & BD_ENET_TX_WRAP)
  341. bdp = fep->tx_bd_base;
  342. else
  343. bdp++;
  344. /* Since we have freed up a buffer, the ring is no longer full
  345. */
  346. if (fep->tx_full) {
  347. fep->tx_full = 0;
  348. if (netif_queue_stopped(dev))
  349. netif_wake_queue(dev);
  350. }
  351. }
  352. fep->dirty_tx = bdp;
  353. spin_unlock(&fep->hw_lock);
  354. }
  355. /* During a receive, the cur_rx points to the current incoming buffer.
  356. * When we update through the ring, if the next incoming buffer has
  357. * not been given to the system, we just set the empty indicator,
  358. * effectively tossing the packet.
  359. */
  360. static void
  361. fec_enet_rx(struct net_device *dev)
  362. {
  363. struct fec_enet_private *fep = netdev_priv(dev);
  364. struct bufdesc *bdp;
  365. unsigned short status;
  366. struct sk_buff *skb;
  367. ushort pkt_len;
  368. __u8 *data;
  369. #ifdef CONFIG_M532x
  370. flush_cache_all();
  371. #endif
  372. spin_lock(&fep->hw_lock);
  373. /* First, grab all of the stats for the incoming packet.
  374. * These get messed up if we get called due to a busy condition.
  375. */
  376. bdp = fep->cur_rx;
  377. while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
  378. /* Since we have allocated space to hold a complete frame,
  379. * the last indicator should be set.
  380. */
  381. if ((status & BD_ENET_RX_LAST) == 0)
  382. printk("FEC ENET: rcv is not +last\n");
  383. if (!fep->opened)
  384. goto rx_processing_done;
  385. /* Check for errors. */
  386. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
  387. BD_ENET_RX_CR | BD_ENET_RX_OV)) {
  388. dev->stats.rx_errors++;
  389. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
  390. /* Frame too long or too short. */
  391. dev->stats.rx_length_errors++;
  392. }
  393. if (status & BD_ENET_RX_NO) /* Frame alignment */
  394. dev->stats.rx_frame_errors++;
  395. if (status & BD_ENET_RX_CR) /* CRC Error */
  396. dev->stats.rx_crc_errors++;
  397. if (status & BD_ENET_RX_OV) /* FIFO overrun */
  398. dev->stats.rx_fifo_errors++;
  399. }
  400. /* Report late collisions as a frame error.
  401. * On this error, the BD is closed, but we don't know what we
  402. * have in the buffer. So, just drop this frame on the floor.
  403. */
  404. if (status & BD_ENET_RX_CL) {
  405. dev->stats.rx_errors++;
  406. dev->stats.rx_frame_errors++;
  407. goto rx_processing_done;
  408. }
  409. /* Process the incoming frame. */
  410. dev->stats.rx_packets++;
  411. pkt_len = bdp->cbd_datlen;
  412. dev->stats.rx_bytes += pkt_len;
  413. data = (__u8*)__va(bdp->cbd_bufaddr);
  414. dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
  415. DMA_FROM_DEVICE);
  416. /* This does 16 byte alignment, exactly what we need.
  417. * The packet length includes FCS, but we don't want to
  418. * include that when passing upstream as it messes up
  419. * bridging applications.
  420. */
  421. skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
  422. if (unlikely(!skb)) {
  423. printk("%s: Memory squeeze, dropping packet.\n",
  424. dev->name);
  425. dev->stats.rx_dropped++;
  426. } else {
  427. skb_reserve(skb, NET_IP_ALIGN);
  428. skb_put(skb, pkt_len - 4); /* Make room */
  429. skb_copy_to_linear_data(skb, data, pkt_len - 4);
  430. skb->protocol = eth_type_trans(skb, dev);
  431. netif_rx(skb);
  432. }
  433. bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
  434. DMA_FROM_DEVICE);
  435. rx_processing_done:
  436. /* Clear the status flags for this buffer */
  437. status &= ~BD_ENET_RX_STATS;
  438. /* Mark the buffer empty */
  439. status |= BD_ENET_RX_EMPTY;
  440. bdp->cbd_sc = status;
  441. /* Update BD pointer to next entry */
  442. if (status & BD_ENET_RX_WRAP)
  443. bdp = fep->rx_bd_base;
  444. else
  445. bdp++;
  446. /* Doing this here will keep the FEC running while we process
  447. * incoming frames. On a heavily loaded network, we should be
  448. * able to keep up at the expense of system resources.
  449. */
  450. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  451. }
  452. fep->cur_rx = bdp;
  453. spin_unlock(&fep->hw_lock);
  454. }
  455. /* ------------------------------------------------------------------------- */
  456. #ifdef CONFIG_M5272
  457. static void __inline__ fec_get_mac(struct net_device *dev)
  458. {
  459. struct fec_enet_private *fep = netdev_priv(dev);
  460. unsigned char *iap, tmpaddr[ETH_ALEN];
  461. if (FEC_FLASHMAC) {
  462. /*
  463. * Get MAC address from FLASH.
  464. * If it is all 1's or 0's, use the default.
  465. */
  466. iap = (unsigned char *)FEC_FLASHMAC;
  467. if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
  468. (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
  469. iap = fec_mac_default;
  470. if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
  471. (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
  472. iap = fec_mac_default;
  473. } else {
  474. *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW);
  475. *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
  476. iap = &tmpaddr[0];
  477. }
  478. memcpy(dev->dev_addr, iap, ETH_ALEN);
  479. /* Adjust MAC if using default MAC address */
  480. if (iap == fec_mac_default)
  481. dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
  482. }
  483. #endif
  484. /* ------------------------------------------------------------------------- */
  485. /*
  486. * Phy section
  487. */
  488. static void fec_enet_adjust_link(struct net_device *dev)
  489. {
  490. struct fec_enet_private *fep = netdev_priv(dev);
  491. struct phy_device *phy_dev = fep->phy_dev;
  492. unsigned long flags;
  493. int status_change = 0;
  494. spin_lock_irqsave(&fep->hw_lock, flags);
  495. /* Prevent a state halted on mii error */
  496. if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
  497. phy_dev->state = PHY_RESUMING;
  498. goto spin_unlock;
  499. }
  500. /* Duplex link change */
  501. if (phy_dev->link) {
  502. if (fep->full_duplex != phy_dev->duplex) {
  503. fec_restart(dev, phy_dev->duplex);
  504. status_change = 1;
  505. }
  506. }
  507. /* Link on or off change */
  508. if (phy_dev->link != fep->link) {
  509. fep->link = phy_dev->link;
  510. if (phy_dev->link)
  511. fec_restart(dev, phy_dev->duplex);
  512. else
  513. fec_stop(dev);
  514. status_change = 1;
  515. }
  516. spin_unlock:
  517. spin_unlock_irqrestore(&fep->hw_lock, flags);
  518. if (status_change)
  519. phy_print_status(phy_dev);
  520. }
  521. static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  522. {
  523. struct fec_enet_private *fep = bus->priv;
  524. unsigned long time_left;
  525. fep->mii_timeout = 0;
  526. init_completion(&fep->mdio_done);
  527. /* start a read op */
  528. writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
  529. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  530. FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
  531. /* wait for end of transfer */
  532. time_left = wait_for_completion_timeout(&fep->mdio_done,
  533. usecs_to_jiffies(FEC_MII_TIMEOUT));
  534. if (time_left == 0) {
  535. fep->mii_timeout = 1;
  536. printk(KERN_ERR "FEC: MDIO read timeout\n");
  537. return -ETIMEDOUT;
  538. }
  539. /* return value */
  540. return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
  541. }
  542. static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  543. u16 value)
  544. {
  545. struct fec_enet_private *fep = bus->priv;
  546. unsigned long time_left;
  547. fep->mii_timeout = 0;
  548. init_completion(&fep->mdio_done);
  549. /* start a read op */
  550. writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
  551. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  552. FEC_MMFR_TA | FEC_MMFR_DATA(value),
  553. fep->hwp + FEC_MII_DATA);
  554. /* wait for end of transfer */
  555. time_left = wait_for_completion_timeout(&fep->mdio_done,
  556. usecs_to_jiffies(FEC_MII_TIMEOUT));
  557. if (time_left == 0) {
  558. fep->mii_timeout = 1;
  559. printk(KERN_ERR "FEC: MDIO write timeout\n");
  560. return -ETIMEDOUT;
  561. }
  562. return 0;
  563. }
  564. static int fec_enet_mdio_reset(struct mii_bus *bus)
  565. {
  566. return 0;
  567. }
  568. static int fec_enet_mii_probe(struct net_device *dev)
  569. {
  570. struct fec_enet_private *fep = netdev_priv(dev);
  571. struct phy_device *phy_dev = NULL;
  572. int ret;
  573. fep->phy_dev = NULL;
  574. /* find the first phy */
  575. phy_dev = phy_find_first(fep->mii_bus);
  576. if (!phy_dev) {
  577. printk(KERN_ERR "%s: no PHY found\n", dev->name);
  578. return -ENODEV;
  579. }
  580. /* attach the mac to the phy */
  581. ret = phy_connect_direct(dev, phy_dev,
  582. &fec_enet_adjust_link, 0,
  583. PHY_INTERFACE_MODE_MII);
  584. if (ret) {
  585. printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
  586. return ret;
  587. }
  588. /* mask with MAC supported features */
  589. phy_dev->supported &= PHY_BASIC_FEATURES;
  590. phy_dev->advertising = phy_dev->supported;
  591. fep->phy_dev = phy_dev;
  592. fep->link = 0;
  593. fep->full_duplex = 0;
  594. printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
  595. "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
  596. fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
  597. fep->phy_dev->irq);
  598. return 0;
  599. }
  600. static int fec_enet_mii_init(struct platform_device *pdev)
  601. {
  602. struct net_device *dev = platform_get_drvdata(pdev);
  603. struct fec_enet_private *fep = netdev_priv(dev);
  604. int err = -ENXIO, i;
  605. fep->mii_timeout = 0;
  606. /*
  607. * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
  608. */
  609. fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
  610. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  611. fep->mii_bus = mdiobus_alloc();
  612. if (fep->mii_bus == NULL) {
  613. err = -ENOMEM;
  614. goto err_out;
  615. }
  616. fep->mii_bus->name = "fec_enet_mii_bus";
  617. fep->mii_bus->read = fec_enet_mdio_read;
  618. fep->mii_bus->write = fec_enet_mdio_write;
  619. fep->mii_bus->reset = fec_enet_mdio_reset;
  620. snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
  621. fep->mii_bus->priv = fep;
  622. fep->mii_bus->parent = &pdev->dev;
  623. fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
  624. if (!fep->mii_bus->irq) {
  625. err = -ENOMEM;
  626. goto err_out_free_mdiobus;
  627. }
  628. for (i = 0; i < PHY_MAX_ADDR; i++)
  629. fep->mii_bus->irq[i] = PHY_POLL;
  630. platform_set_drvdata(dev, fep->mii_bus);
  631. if (mdiobus_register(fep->mii_bus))
  632. goto err_out_free_mdio_irq;
  633. return 0;
  634. err_out_free_mdio_irq:
  635. kfree(fep->mii_bus->irq);
  636. err_out_free_mdiobus:
  637. mdiobus_free(fep->mii_bus);
  638. err_out:
  639. return err;
  640. }
  641. static void fec_enet_mii_remove(struct fec_enet_private *fep)
  642. {
  643. if (fep->phy_dev)
  644. phy_disconnect(fep->phy_dev);
  645. mdiobus_unregister(fep->mii_bus);
  646. kfree(fep->mii_bus->irq);
  647. mdiobus_free(fep->mii_bus);
  648. }
  649. static int fec_enet_get_settings(struct net_device *dev,
  650. struct ethtool_cmd *cmd)
  651. {
  652. struct fec_enet_private *fep = netdev_priv(dev);
  653. struct phy_device *phydev = fep->phy_dev;
  654. if (!phydev)
  655. return -ENODEV;
  656. return phy_ethtool_gset(phydev, cmd);
  657. }
  658. static int fec_enet_set_settings(struct net_device *dev,
  659. struct ethtool_cmd *cmd)
  660. {
  661. struct fec_enet_private *fep = netdev_priv(dev);
  662. struct phy_device *phydev = fep->phy_dev;
  663. if (!phydev)
  664. return -ENODEV;
  665. return phy_ethtool_sset(phydev, cmd);
  666. }
  667. static void fec_enet_get_drvinfo(struct net_device *dev,
  668. struct ethtool_drvinfo *info)
  669. {
  670. struct fec_enet_private *fep = netdev_priv(dev);
  671. strcpy(info->driver, fep->pdev->dev.driver->name);
  672. strcpy(info->version, "Revision: 1.0");
  673. strcpy(info->bus_info, dev_name(&dev->dev));
  674. }
  675. static struct ethtool_ops fec_enet_ethtool_ops = {
  676. .get_settings = fec_enet_get_settings,
  677. .set_settings = fec_enet_set_settings,
  678. .get_drvinfo = fec_enet_get_drvinfo,
  679. .get_link = ethtool_op_get_link,
  680. };
  681. static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  682. {
  683. struct fec_enet_private *fep = netdev_priv(dev);
  684. struct phy_device *phydev = fep->phy_dev;
  685. if (!netif_running(dev))
  686. return -EINVAL;
  687. if (!phydev)
  688. return -ENODEV;
  689. return phy_mii_ioctl(phydev, rq, cmd);
  690. }
  691. static void fec_enet_free_buffers(struct net_device *dev)
  692. {
  693. struct fec_enet_private *fep = netdev_priv(dev);
  694. int i;
  695. struct sk_buff *skb;
  696. struct bufdesc *bdp;
  697. bdp = fep->rx_bd_base;
  698. for (i = 0; i < RX_RING_SIZE; i++) {
  699. skb = fep->rx_skbuff[i];
  700. if (bdp->cbd_bufaddr)
  701. dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
  702. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  703. if (skb)
  704. dev_kfree_skb(skb);
  705. bdp++;
  706. }
  707. bdp = fep->tx_bd_base;
  708. for (i = 0; i < TX_RING_SIZE; i++)
  709. kfree(fep->tx_bounce[i]);
  710. }
  711. static int fec_enet_alloc_buffers(struct net_device *dev)
  712. {
  713. struct fec_enet_private *fep = netdev_priv(dev);
  714. int i;
  715. struct sk_buff *skb;
  716. struct bufdesc *bdp;
  717. bdp = fep->rx_bd_base;
  718. for (i = 0; i < RX_RING_SIZE; i++) {
  719. skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
  720. if (!skb) {
  721. fec_enet_free_buffers(dev);
  722. return -ENOMEM;
  723. }
  724. fep->rx_skbuff[i] = skb;
  725. bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data,
  726. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  727. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  728. bdp++;
  729. }
  730. /* Set the last buffer to wrap. */
  731. bdp--;
  732. bdp->cbd_sc |= BD_SC_WRAP;
  733. bdp = fep->tx_bd_base;
  734. for (i = 0; i < TX_RING_SIZE; i++) {
  735. fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
  736. bdp->cbd_sc = 0;
  737. bdp->cbd_bufaddr = 0;
  738. bdp++;
  739. }
  740. /* Set the last buffer to wrap. */
  741. bdp--;
  742. bdp->cbd_sc |= BD_SC_WRAP;
  743. return 0;
  744. }
  745. static int
  746. fec_enet_open(struct net_device *dev)
  747. {
  748. struct fec_enet_private *fep = netdev_priv(dev);
  749. int ret;
  750. /* I should reset the ring buffers here, but I don't yet know
  751. * a simple way to do that.
  752. */
  753. ret = fec_enet_alloc_buffers(dev);
  754. if (ret)
  755. return ret;
  756. /* Probe and connect to PHY when open the interface */
  757. ret = fec_enet_mii_probe(dev);
  758. if (ret) {
  759. fec_enet_free_buffers(dev);
  760. return ret;
  761. }
  762. phy_start(fep->phy_dev);
  763. netif_start_queue(dev);
  764. fep->opened = 1;
  765. return 0;
  766. }
  767. static int
  768. fec_enet_close(struct net_device *dev)
  769. {
  770. struct fec_enet_private *fep = netdev_priv(dev);
  771. /* Don't know what to do yet. */
  772. fep->opened = 0;
  773. netif_stop_queue(dev);
  774. fec_stop(dev);
  775. if (fep->phy_dev)
  776. phy_disconnect(fep->phy_dev);
  777. fec_enet_free_buffers(dev);
  778. return 0;
  779. }
  780. /* Set or clear the multicast filter for this adaptor.
  781. * Skeleton taken from sunlance driver.
  782. * The CPM Ethernet implementation allows Multicast as well as individual
  783. * MAC address filtering. Some of the drivers check to make sure it is
  784. * a group multicast address, and discard those that are not. I guess I
  785. * will do the same for now, but just remove the test if you want
  786. * individual filtering as well (do the upper net layers want or support
  787. * this kind of feature?).
  788. */
  789. #define HASH_BITS 6 /* #bits in hash */
  790. #define CRC32_POLY 0xEDB88320
  791. static void set_multicast_list(struct net_device *dev)
  792. {
  793. struct fec_enet_private *fep = netdev_priv(dev);
  794. struct netdev_hw_addr *ha;
  795. unsigned int i, bit, data, crc, tmp;
  796. unsigned char hash;
  797. if (dev->flags & IFF_PROMISC) {
  798. tmp = readl(fep->hwp + FEC_R_CNTRL);
  799. tmp |= 0x8;
  800. writel(tmp, fep->hwp + FEC_R_CNTRL);
  801. return;
  802. }
  803. tmp = readl(fep->hwp + FEC_R_CNTRL);
  804. tmp &= ~0x8;
  805. writel(tmp, fep->hwp + FEC_R_CNTRL);
  806. if (dev->flags & IFF_ALLMULTI) {
  807. /* Catch all multicast addresses, so set the
  808. * filter to all 1's
  809. */
  810. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  811. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  812. return;
  813. }
  814. /* Clear filter and add the addresses in hash register
  815. */
  816. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  817. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  818. netdev_for_each_mc_addr(ha, dev) {
  819. /* Only support group multicast for now */
  820. if (!(ha->addr[0] & 1))
  821. continue;
  822. /* calculate crc32 value of mac address */
  823. crc = 0xffffffff;
  824. for (i = 0; i < dev->addr_len; i++) {
  825. data = ha->addr[i];
  826. for (bit = 0; bit < 8; bit++, data >>= 1) {
  827. crc = (crc >> 1) ^
  828. (((crc ^ data) & 1) ? CRC32_POLY : 0);
  829. }
  830. }
  831. /* only upper 6 bits (HASH_BITS) are used
  832. * which point to specific bit in he hash registers
  833. */
  834. hash = (crc >> (32 - HASH_BITS)) & 0x3f;
  835. if (hash > 31) {
  836. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  837. tmp |= 1 << (hash - 32);
  838. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  839. } else {
  840. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  841. tmp |= 1 << hash;
  842. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  843. }
  844. }
  845. }
  846. /* Set a MAC change in hardware. */
  847. static int
  848. fec_set_mac_address(struct net_device *dev, void *p)
  849. {
  850. struct fec_enet_private *fep = netdev_priv(dev);
  851. struct sockaddr *addr = p;
  852. if (!is_valid_ether_addr(addr->sa_data))
  853. return -EADDRNOTAVAIL;
  854. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  855. writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
  856. (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
  857. fep->hwp + FEC_ADDR_LOW);
  858. writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
  859. fep->hwp + FEC_ADDR_HIGH);
  860. return 0;
  861. }
  862. static const struct net_device_ops fec_netdev_ops = {
  863. .ndo_open = fec_enet_open,
  864. .ndo_stop = fec_enet_close,
  865. .ndo_start_xmit = fec_enet_start_xmit,
  866. .ndo_set_multicast_list = set_multicast_list,
  867. .ndo_change_mtu = eth_change_mtu,
  868. .ndo_validate_addr = eth_validate_addr,
  869. .ndo_tx_timeout = fec_timeout,
  870. .ndo_set_mac_address = fec_set_mac_address,
  871. .ndo_do_ioctl = fec_enet_ioctl,
  872. };
  873. /*
  874. * XXX: We need to clean up on failure exits here.
  875. *
  876. * index is only used in legacy code
  877. */
  878. static int fec_enet_init(struct net_device *dev, int index)
  879. {
  880. struct fec_enet_private *fep = netdev_priv(dev);
  881. struct bufdesc *cbd_base;
  882. struct bufdesc *bdp;
  883. int i;
  884. /* Allocate memory for buffer descriptors. */
  885. cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
  886. GFP_KERNEL);
  887. if (!cbd_base) {
  888. printk("FEC: allocate descriptor memory failed?\n");
  889. return -ENOMEM;
  890. }
  891. spin_lock_init(&fep->hw_lock);
  892. fep->index = index;
  893. fep->hwp = (void __iomem *)dev->base_addr;
  894. fep->netdev = dev;
  895. /* Set the Ethernet address */
  896. #ifdef CONFIG_M5272
  897. fec_get_mac(dev);
  898. #else
  899. {
  900. unsigned long l;
  901. l = readl(fep->hwp + FEC_ADDR_LOW);
  902. dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24);
  903. dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16);
  904. dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8);
  905. dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0);
  906. l = readl(fep->hwp + FEC_ADDR_HIGH);
  907. dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24);
  908. dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16);
  909. }
  910. #endif
  911. /* Set receive and transmit descriptor base. */
  912. fep->rx_bd_base = cbd_base;
  913. fep->tx_bd_base = cbd_base + RX_RING_SIZE;
  914. /* The FEC Ethernet specific entries in the device structure */
  915. dev->watchdog_timeo = TX_TIMEOUT;
  916. dev->netdev_ops = &fec_netdev_ops;
  917. dev->ethtool_ops = &fec_enet_ethtool_ops;
  918. /* Initialize the receive buffer descriptors. */
  919. bdp = fep->rx_bd_base;
  920. for (i = 0; i < RX_RING_SIZE; i++) {
  921. /* Initialize the BD for every fragment in the page. */
  922. bdp->cbd_sc = 0;
  923. bdp++;
  924. }
  925. /* Set the last buffer to wrap */
  926. bdp--;
  927. bdp->cbd_sc |= BD_SC_WRAP;
  928. /* ...and the same for transmit */
  929. bdp = fep->tx_bd_base;
  930. for (i = 0; i < TX_RING_SIZE; i++) {
  931. /* Initialize the BD for every fragment in the page. */
  932. bdp->cbd_sc = 0;
  933. bdp->cbd_bufaddr = 0;
  934. bdp++;
  935. }
  936. /* Set the last buffer to wrap */
  937. bdp--;
  938. bdp->cbd_sc |= BD_SC_WRAP;
  939. fec_restart(dev, 0);
  940. return 0;
  941. }
  942. /* This function is called to start or restart the FEC during a link
  943. * change. This only happens when switching between half and full
  944. * duplex.
  945. */
  946. static void
  947. fec_restart(struct net_device *dev, int duplex)
  948. {
  949. struct fec_enet_private *fep = netdev_priv(dev);
  950. int i;
  951. /* Whack a reset. We should wait for this. */
  952. writel(1, fep->hwp + FEC_ECNTRL);
  953. udelay(10);
  954. /* Clear any outstanding interrupt. */
  955. writel(0xffc00000, fep->hwp + FEC_IEVENT);
  956. /* Reset all multicast. */
  957. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  958. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  959. #ifndef CONFIG_M5272
  960. writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
  961. writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
  962. #endif
  963. /* Set maximum receive buffer size. */
  964. writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
  965. /* Set receive and transmit descriptor base. */
  966. writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
  967. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
  968. fep->hwp + FEC_X_DES_START);
  969. fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
  970. fep->cur_rx = fep->rx_bd_base;
  971. /* Reset SKB transmit buffers. */
  972. fep->skb_cur = fep->skb_dirty = 0;
  973. for (i = 0; i <= TX_RING_MOD_MASK; i++) {
  974. if (fep->tx_skbuff[i]) {
  975. dev_kfree_skb_any(fep->tx_skbuff[i]);
  976. fep->tx_skbuff[i] = NULL;
  977. }
  978. }
  979. /* Enable MII mode */
  980. if (duplex) {
  981. /* MII enable / FD enable */
  982. writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
  983. writel(0x04, fep->hwp + FEC_X_CNTRL);
  984. } else {
  985. /* MII enable / No Rcv on Xmit */
  986. writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
  987. writel(0x0, fep->hwp + FEC_X_CNTRL);
  988. }
  989. fep->full_duplex = duplex;
  990. /* Set MII speed */
  991. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  992. #ifdef FEC_MIIGSK_ENR
  993. if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
  994. /* disable the gasket and wait */
  995. writel(0, fep->hwp + FEC_MIIGSK_ENR);
  996. while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
  997. udelay(1);
  998. /* configure the gasket: RMII, 50 MHz, no loopback, no echo */
  999. writel(1, fep->hwp + FEC_MIIGSK_CFGR);
  1000. /* re-enable the gasket */
  1001. writel(2, fep->hwp + FEC_MIIGSK_ENR);
  1002. }
  1003. #endif
  1004. /* And last, enable the transmit and receive processing */
  1005. writel(2, fep->hwp + FEC_ECNTRL);
  1006. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  1007. /* Enable interrupts we wish to service */
  1008. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  1009. }
  1010. static void
  1011. fec_stop(struct net_device *dev)
  1012. {
  1013. struct fec_enet_private *fep = netdev_priv(dev);
  1014. /* We cannot expect a graceful transmit stop without link !!! */
  1015. if (fep->link) {
  1016. writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
  1017. udelay(10);
  1018. if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
  1019. printk("fec_stop : Graceful transmit stop did not complete !\n");
  1020. }
  1021. /* Whack a reset. We should wait for this. */
  1022. writel(1, fep->hwp + FEC_ECNTRL);
  1023. udelay(10);
  1024. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  1025. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  1026. }
  1027. static int __devinit
  1028. fec_probe(struct platform_device *pdev)
  1029. {
  1030. struct fec_enet_private *fep;
  1031. struct fec_platform_data *pdata;
  1032. struct net_device *ndev;
  1033. int i, irq, ret = 0;
  1034. struct resource *r;
  1035. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1036. if (!r)
  1037. return -ENXIO;
  1038. r = request_mem_region(r->start, resource_size(r), pdev->name);
  1039. if (!r)
  1040. return -EBUSY;
  1041. /* Init network device */
  1042. ndev = alloc_etherdev(sizeof(struct fec_enet_private));
  1043. if (!ndev)
  1044. return -ENOMEM;
  1045. SET_NETDEV_DEV(ndev, &pdev->dev);
  1046. /* setup board info structure */
  1047. fep = netdev_priv(ndev);
  1048. memset(fep, 0, sizeof(*fep));
  1049. ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
  1050. fep->pdev = pdev;
  1051. if (!ndev->base_addr) {
  1052. ret = -ENOMEM;
  1053. goto failed_ioremap;
  1054. }
  1055. platform_set_drvdata(pdev, ndev);
  1056. pdata = pdev->dev.platform_data;
  1057. if (pdata)
  1058. fep->phy_interface = pdata->phy;
  1059. /* This device has up to three irqs on some platforms */
  1060. for (i = 0; i < 3; i++) {
  1061. irq = platform_get_irq(pdev, i);
  1062. if (i && irq < 0)
  1063. break;
  1064. ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
  1065. if (ret) {
  1066. while (i >= 0) {
  1067. irq = platform_get_irq(pdev, i);
  1068. free_irq(irq, ndev);
  1069. i--;
  1070. }
  1071. goto failed_irq;
  1072. }
  1073. }
  1074. fep->clk = clk_get(&pdev->dev, "fec_clk");
  1075. if (IS_ERR(fep->clk)) {
  1076. ret = PTR_ERR(fep->clk);
  1077. goto failed_clk;
  1078. }
  1079. clk_enable(fep->clk);
  1080. ret = fec_enet_init(ndev, 0);
  1081. if (ret)
  1082. goto failed_init;
  1083. ret = fec_enet_mii_init(pdev);
  1084. if (ret)
  1085. goto failed_mii_init;
  1086. ret = register_netdev(ndev);
  1087. if (ret)
  1088. goto failed_register;
  1089. return 0;
  1090. failed_register:
  1091. fec_enet_mii_remove(fep);
  1092. failed_mii_init:
  1093. failed_init:
  1094. clk_disable(fep->clk);
  1095. clk_put(fep->clk);
  1096. failed_clk:
  1097. for (i = 0; i < 3; i++) {
  1098. irq = platform_get_irq(pdev, i);
  1099. if (irq > 0)
  1100. free_irq(irq, ndev);
  1101. }
  1102. failed_irq:
  1103. iounmap((void __iomem *)ndev->base_addr);
  1104. failed_ioremap:
  1105. free_netdev(ndev);
  1106. return ret;
  1107. }
  1108. static int __devexit
  1109. fec_drv_remove(struct platform_device *pdev)
  1110. {
  1111. struct net_device *ndev = platform_get_drvdata(pdev);
  1112. struct fec_enet_private *fep = netdev_priv(ndev);
  1113. platform_set_drvdata(pdev, NULL);
  1114. fec_stop(ndev);
  1115. fec_enet_mii_remove(fep);
  1116. clk_disable(fep->clk);
  1117. clk_put(fep->clk);
  1118. iounmap((void __iomem *)ndev->base_addr);
  1119. unregister_netdev(ndev);
  1120. free_netdev(ndev);
  1121. return 0;
  1122. }
  1123. #ifdef CONFIG_PM
  1124. static int
  1125. fec_suspend(struct device *dev)
  1126. {
  1127. struct net_device *ndev = dev_get_drvdata(dev);
  1128. struct fec_enet_private *fep;
  1129. if (ndev) {
  1130. fep = netdev_priv(ndev);
  1131. if (netif_running(ndev))
  1132. fec_enet_close(ndev);
  1133. clk_disable(fep->clk);
  1134. }
  1135. return 0;
  1136. }
  1137. static int
  1138. fec_resume(struct device *dev)
  1139. {
  1140. struct net_device *ndev = dev_get_drvdata(dev);
  1141. struct fec_enet_private *fep;
  1142. if (ndev) {
  1143. fep = netdev_priv(ndev);
  1144. clk_enable(fep->clk);
  1145. if (netif_running(ndev))
  1146. fec_enet_open(ndev);
  1147. }
  1148. return 0;
  1149. }
  1150. static const struct dev_pm_ops fec_pm_ops = {
  1151. .suspend = fec_suspend,
  1152. .resume = fec_resume,
  1153. .freeze = fec_suspend,
  1154. .thaw = fec_resume,
  1155. .poweroff = fec_suspend,
  1156. .restore = fec_resume,
  1157. };
  1158. #endif
  1159. static struct platform_driver fec_driver = {
  1160. .driver = {
  1161. .name = "fec",
  1162. .owner = THIS_MODULE,
  1163. #ifdef CONFIG_PM
  1164. .pm = &fec_pm_ops,
  1165. #endif
  1166. },
  1167. .probe = fec_probe,
  1168. .remove = __devexit_p(fec_drv_remove),
  1169. };
  1170. static int __init
  1171. fec_enet_module_init(void)
  1172. {
  1173. printk(KERN_INFO "FEC Ethernet Driver\n");
  1174. return platform_driver_register(&fec_driver);
  1175. }
  1176. static void __exit
  1177. fec_enet_cleanup(void)
  1178. {
  1179. platform_driver_unregister(&fec_driver);
  1180. }
  1181. module_exit(fec_enet_cleanup);
  1182. module_init(fec_enet_module_init);
  1183. MODULE_LICENSE("GPL");