cpmac.c 35 KB

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  1. /*
  2. * Copyright (C) 2006, 2007 Eugene Konev
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. */
  18. #include <linux/module.h>
  19. #include <linux/init.h>
  20. #include <linux/moduleparam.h>
  21. #include <linux/sched.h>
  22. #include <linux/kernel.h>
  23. #include <linux/slab.h>
  24. #include <linux/errno.h>
  25. #include <linux/types.h>
  26. #include <linux/delay.h>
  27. #include <linux/netdevice.h>
  28. #include <linux/if_vlan.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/ethtool.h>
  31. #include <linux/skbuff.h>
  32. #include <linux/mii.h>
  33. #include <linux/phy.h>
  34. #include <linux/phy_fixed.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/clk.h>
  38. #include <asm/gpio.h>
  39. #include <asm/atomic.h>
  40. MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
  41. MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
  42. MODULE_LICENSE("GPL");
  43. MODULE_ALIAS("platform:cpmac");
  44. static int debug_level = 8;
  45. static int dumb_switch;
  46. /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
  47. module_param(debug_level, int, 0444);
  48. module_param(dumb_switch, int, 0444);
  49. MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
  50. MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
  51. #define CPMAC_VERSION "0.5.2"
  52. /* frame size + 802.1q tag + FCS size */
  53. #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  54. #define CPMAC_QUEUES 8
  55. /* Ethernet registers */
  56. #define CPMAC_TX_CONTROL 0x0004
  57. #define CPMAC_TX_TEARDOWN 0x0008
  58. #define CPMAC_RX_CONTROL 0x0014
  59. #define CPMAC_RX_TEARDOWN 0x0018
  60. #define CPMAC_MBP 0x0100
  61. # define MBP_RXPASSCRC 0x40000000
  62. # define MBP_RXQOS 0x20000000
  63. # define MBP_RXNOCHAIN 0x10000000
  64. # define MBP_RXCMF 0x01000000
  65. # define MBP_RXSHORT 0x00800000
  66. # define MBP_RXCEF 0x00400000
  67. # define MBP_RXPROMISC 0x00200000
  68. # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
  69. # define MBP_RXBCAST 0x00002000
  70. # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
  71. # define MBP_RXMCAST 0x00000020
  72. # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
  73. #define CPMAC_UNICAST_ENABLE 0x0104
  74. #define CPMAC_UNICAST_CLEAR 0x0108
  75. #define CPMAC_MAX_LENGTH 0x010c
  76. #define CPMAC_BUFFER_OFFSET 0x0110
  77. #define CPMAC_MAC_CONTROL 0x0160
  78. # define MAC_TXPTYPE 0x00000200
  79. # define MAC_TXPACE 0x00000040
  80. # define MAC_MII 0x00000020
  81. # define MAC_TXFLOW 0x00000010
  82. # define MAC_RXFLOW 0x00000008
  83. # define MAC_MTEST 0x00000004
  84. # define MAC_LOOPBACK 0x00000002
  85. # define MAC_FDX 0x00000001
  86. #define CPMAC_MAC_STATUS 0x0164
  87. # define MAC_STATUS_QOS 0x00000004
  88. # define MAC_STATUS_RXFLOW 0x00000002
  89. # define MAC_STATUS_TXFLOW 0x00000001
  90. #define CPMAC_TX_INT_ENABLE 0x0178
  91. #define CPMAC_TX_INT_CLEAR 0x017c
  92. #define CPMAC_MAC_INT_VECTOR 0x0180
  93. # define MAC_INT_STATUS 0x00080000
  94. # define MAC_INT_HOST 0x00040000
  95. # define MAC_INT_RX 0x00020000
  96. # define MAC_INT_TX 0x00010000
  97. #define CPMAC_MAC_EOI_VECTOR 0x0184
  98. #define CPMAC_RX_INT_ENABLE 0x0198
  99. #define CPMAC_RX_INT_CLEAR 0x019c
  100. #define CPMAC_MAC_INT_ENABLE 0x01a8
  101. #define CPMAC_MAC_INT_CLEAR 0x01ac
  102. #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
  103. #define CPMAC_MAC_ADDR_MID 0x01d0
  104. #define CPMAC_MAC_ADDR_HI 0x01d4
  105. #define CPMAC_MAC_HASH_LO 0x01d8
  106. #define CPMAC_MAC_HASH_HI 0x01dc
  107. #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
  108. #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
  109. #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
  110. #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
  111. #define CPMAC_REG_END 0x0680
  112. /*
  113. * Rx/Tx statistics
  114. * TODO: use some of them to fill stats in cpmac_stats()
  115. */
  116. #define CPMAC_STATS_RX_GOOD 0x0200
  117. #define CPMAC_STATS_RX_BCAST 0x0204
  118. #define CPMAC_STATS_RX_MCAST 0x0208
  119. #define CPMAC_STATS_RX_PAUSE 0x020c
  120. #define CPMAC_STATS_RX_CRC 0x0210
  121. #define CPMAC_STATS_RX_ALIGN 0x0214
  122. #define CPMAC_STATS_RX_OVER 0x0218
  123. #define CPMAC_STATS_RX_JABBER 0x021c
  124. #define CPMAC_STATS_RX_UNDER 0x0220
  125. #define CPMAC_STATS_RX_FRAG 0x0224
  126. #define CPMAC_STATS_RX_FILTER 0x0228
  127. #define CPMAC_STATS_RX_QOSFILTER 0x022c
  128. #define CPMAC_STATS_RX_OCTETS 0x0230
  129. #define CPMAC_STATS_TX_GOOD 0x0234
  130. #define CPMAC_STATS_TX_BCAST 0x0238
  131. #define CPMAC_STATS_TX_MCAST 0x023c
  132. #define CPMAC_STATS_TX_PAUSE 0x0240
  133. #define CPMAC_STATS_TX_DEFER 0x0244
  134. #define CPMAC_STATS_TX_COLLISION 0x0248
  135. #define CPMAC_STATS_TX_SINGLECOLL 0x024c
  136. #define CPMAC_STATS_TX_MULTICOLL 0x0250
  137. #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
  138. #define CPMAC_STATS_TX_LATECOLL 0x0258
  139. #define CPMAC_STATS_TX_UNDERRUN 0x025c
  140. #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
  141. #define CPMAC_STATS_TX_OCTETS 0x0264
  142. #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
  143. #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
  144. (reg)))
  145. /* MDIO bus */
  146. #define CPMAC_MDIO_VERSION 0x0000
  147. #define CPMAC_MDIO_CONTROL 0x0004
  148. # define MDIOC_IDLE 0x80000000
  149. # define MDIOC_ENABLE 0x40000000
  150. # define MDIOC_PREAMBLE 0x00100000
  151. # define MDIOC_FAULT 0x00080000
  152. # define MDIOC_FAULTDETECT 0x00040000
  153. # define MDIOC_INTTEST 0x00020000
  154. # define MDIOC_CLKDIV(div) ((div) & 0xff)
  155. #define CPMAC_MDIO_ALIVE 0x0008
  156. #define CPMAC_MDIO_LINK 0x000c
  157. #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
  158. # define MDIO_BUSY 0x80000000
  159. # define MDIO_WRITE 0x40000000
  160. # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
  161. # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
  162. # define MDIO_DATA(data) ((data) & 0xffff)
  163. #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
  164. # define PHYSEL_LINKSEL 0x00000040
  165. # define PHYSEL_LINKINT 0x00000020
  166. struct cpmac_desc {
  167. u32 hw_next;
  168. u32 hw_data;
  169. u16 buflen;
  170. u16 bufflags;
  171. u16 datalen;
  172. u16 dataflags;
  173. #define CPMAC_SOP 0x8000
  174. #define CPMAC_EOP 0x4000
  175. #define CPMAC_OWN 0x2000
  176. #define CPMAC_EOQ 0x1000
  177. struct sk_buff *skb;
  178. struct cpmac_desc *next;
  179. struct cpmac_desc *prev;
  180. dma_addr_t mapping;
  181. dma_addr_t data_mapping;
  182. };
  183. struct cpmac_priv {
  184. spinlock_t lock;
  185. spinlock_t rx_lock;
  186. struct cpmac_desc *rx_head;
  187. int ring_size;
  188. struct cpmac_desc *desc_ring;
  189. dma_addr_t dma_ring;
  190. void __iomem *regs;
  191. struct mii_bus *mii_bus;
  192. struct phy_device *phy;
  193. char phy_name[MII_BUS_ID_SIZE + 3];
  194. int oldlink, oldspeed, oldduplex;
  195. u32 msg_enable;
  196. struct net_device *dev;
  197. struct work_struct reset_work;
  198. struct platform_device *pdev;
  199. struct napi_struct napi;
  200. atomic_t reset_pending;
  201. };
  202. static irqreturn_t cpmac_irq(int, void *);
  203. static void cpmac_hw_start(struct net_device *dev);
  204. static void cpmac_hw_stop(struct net_device *dev);
  205. static int cpmac_stop(struct net_device *dev);
  206. static int cpmac_open(struct net_device *dev);
  207. static void cpmac_dump_regs(struct net_device *dev)
  208. {
  209. int i;
  210. struct cpmac_priv *priv = netdev_priv(dev);
  211. for (i = 0; i < CPMAC_REG_END; i += 4) {
  212. if (i % 16 == 0) {
  213. if (i)
  214. printk("\n");
  215. printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
  216. priv->regs + i);
  217. }
  218. printk(" %08x", cpmac_read(priv->regs, i));
  219. }
  220. printk("\n");
  221. }
  222. static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
  223. {
  224. int i;
  225. printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
  226. for (i = 0; i < sizeof(*desc) / 4; i++)
  227. printk(" %08x", ((u32 *)desc)[i]);
  228. printk("\n");
  229. }
  230. static void cpmac_dump_all_desc(struct net_device *dev)
  231. {
  232. struct cpmac_priv *priv = netdev_priv(dev);
  233. struct cpmac_desc *dump = priv->rx_head;
  234. do {
  235. cpmac_dump_desc(dev, dump);
  236. dump = dump->next;
  237. } while (dump != priv->rx_head);
  238. }
  239. static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
  240. {
  241. int i;
  242. printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
  243. for (i = 0; i < skb->len; i++) {
  244. if (i % 16 == 0) {
  245. if (i)
  246. printk("\n");
  247. printk(KERN_DEBUG "%s: data[%p]:", dev->name,
  248. skb->data + i);
  249. }
  250. printk(" %02x", ((u8 *)skb->data)[i]);
  251. }
  252. printk("\n");
  253. }
  254. static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
  255. {
  256. u32 val;
  257. while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
  258. cpu_relax();
  259. cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
  260. MDIO_PHY(phy_id));
  261. while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
  262. cpu_relax();
  263. return MDIO_DATA(val);
  264. }
  265. static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
  266. int reg, u16 val)
  267. {
  268. while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
  269. cpu_relax();
  270. cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
  271. MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
  272. return 0;
  273. }
  274. static int cpmac_mdio_reset(struct mii_bus *bus)
  275. {
  276. struct clk *cpmac_clk;
  277. cpmac_clk = clk_get(&bus->dev, "cpmac");
  278. if (IS_ERR(cpmac_clk)) {
  279. printk(KERN_ERR "unable to get cpmac clock\n");
  280. return -1;
  281. }
  282. ar7_device_reset(AR7_RESET_BIT_MDIO);
  283. cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
  284. MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
  285. return 0;
  286. }
  287. static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
  288. static struct mii_bus *cpmac_mii;
  289. static int cpmac_config(struct net_device *dev, struct ifmap *map)
  290. {
  291. if (dev->flags & IFF_UP)
  292. return -EBUSY;
  293. /* Don't allow changing the I/O address */
  294. if (map->base_addr != dev->base_addr)
  295. return -EOPNOTSUPP;
  296. /* ignore other fields */
  297. return 0;
  298. }
  299. static void cpmac_set_multicast_list(struct net_device *dev)
  300. {
  301. struct netdev_hw_addr *ha;
  302. u8 tmp;
  303. u32 mbp, bit, hash[2] = { 0, };
  304. struct cpmac_priv *priv = netdev_priv(dev);
  305. mbp = cpmac_read(priv->regs, CPMAC_MBP);
  306. if (dev->flags & IFF_PROMISC) {
  307. cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
  308. MBP_RXPROMISC);
  309. } else {
  310. cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
  311. if (dev->flags & IFF_ALLMULTI) {
  312. /* enable all multicast mode */
  313. cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
  314. cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
  315. } else {
  316. /*
  317. * cpmac uses some strange mac address hashing
  318. * (not crc32)
  319. */
  320. netdev_for_each_mc_addr(ha, dev) {
  321. bit = 0;
  322. tmp = ha->addr[0];
  323. bit ^= (tmp >> 2) ^ (tmp << 4);
  324. tmp = ha->addr[1];
  325. bit ^= (tmp >> 4) ^ (tmp << 2);
  326. tmp = ha->addr[2];
  327. bit ^= (tmp >> 6) ^ tmp;
  328. tmp = ha->addr[3];
  329. bit ^= (tmp >> 2) ^ (tmp << 4);
  330. tmp = ha->addr[4];
  331. bit ^= (tmp >> 4) ^ (tmp << 2);
  332. tmp = ha->addr[5];
  333. bit ^= (tmp >> 6) ^ tmp;
  334. bit &= 0x3f;
  335. hash[bit / 32] |= 1 << (bit % 32);
  336. }
  337. cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
  338. cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
  339. }
  340. }
  341. }
  342. static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
  343. struct cpmac_desc *desc)
  344. {
  345. struct sk_buff *skb, *result = NULL;
  346. if (unlikely(netif_msg_hw(priv)))
  347. cpmac_dump_desc(priv->dev, desc);
  348. cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
  349. if (unlikely(!desc->datalen)) {
  350. if (netif_msg_rx_err(priv) && net_ratelimit())
  351. printk(KERN_WARNING "%s: rx: spurious interrupt\n",
  352. priv->dev->name);
  353. return NULL;
  354. }
  355. skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
  356. if (likely(skb)) {
  357. skb_put(desc->skb, desc->datalen);
  358. desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
  359. desc->skb->ip_summed = CHECKSUM_NONE;
  360. priv->dev->stats.rx_packets++;
  361. priv->dev->stats.rx_bytes += desc->datalen;
  362. result = desc->skb;
  363. dma_unmap_single(&priv->dev->dev, desc->data_mapping,
  364. CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
  365. desc->skb = skb;
  366. desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
  367. CPMAC_SKB_SIZE,
  368. DMA_FROM_DEVICE);
  369. desc->hw_data = (u32)desc->data_mapping;
  370. if (unlikely(netif_msg_pktdata(priv))) {
  371. printk(KERN_DEBUG "%s: received packet:\n",
  372. priv->dev->name);
  373. cpmac_dump_skb(priv->dev, result);
  374. }
  375. } else {
  376. if (netif_msg_rx_err(priv) && net_ratelimit())
  377. printk(KERN_WARNING
  378. "%s: low on skbs, dropping packet\n",
  379. priv->dev->name);
  380. priv->dev->stats.rx_dropped++;
  381. }
  382. desc->buflen = CPMAC_SKB_SIZE;
  383. desc->dataflags = CPMAC_OWN;
  384. return result;
  385. }
  386. static int cpmac_poll(struct napi_struct *napi, int budget)
  387. {
  388. struct sk_buff *skb;
  389. struct cpmac_desc *desc, *restart;
  390. struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
  391. int received = 0, processed = 0;
  392. spin_lock(&priv->rx_lock);
  393. if (unlikely(!priv->rx_head)) {
  394. if (netif_msg_rx_err(priv) && net_ratelimit())
  395. printk(KERN_WARNING "%s: rx: polling, but no queue\n",
  396. priv->dev->name);
  397. spin_unlock(&priv->rx_lock);
  398. napi_complete(napi);
  399. return 0;
  400. }
  401. desc = priv->rx_head;
  402. restart = NULL;
  403. while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
  404. processed++;
  405. if ((desc->dataflags & CPMAC_EOQ) != 0) {
  406. /* The last update to eoq->hw_next didn't happen
  407. * soon enough, and the receiver stopped here.
  408. *Remember this descriptor so we can restart
  409. * the receiver after freeing some space.
  410. */
  411. if (unlikely(restart)) {
  412. if (netif_msg_rx_err(priv))
  413. printk(KERN_ERR "%s: poll found a"
  414. " duplicate EOQ: %p and %p\n",
  415. priv->dev->name, restart, desc);
  416. goto fatal_error;
  417. }
  418. restart = desc->next;
  419. }
  420. skb = cpmac_rx_one(priv, desc);
  421. if (likely(skb)) {
  422. netif_receive_skb(skb);
  423. received++;
  424. }
  425. desc = desc->next;
  426. }
  427. if (desc != priv->rx_head) {
  428. /* We freed some buffers, but not the whole ring,
  429. * add what we did free to the rx list */
  430. desc->prev->hw_next = (u32)0;
  431. priv->rx_head->prev->hw_next = priv->rx_head->mapping;
  432. }
  433. /* Optimization: If we did not actually process an EOQ (perhaps because
  434. * of quota limits), check to see if the tail of the queue has EOQ set.
  435. * We should immediately restart in that case so that the receiver can
  436. * restart and run in parallel with more packet processing.
  437. * This lets us handle slightly larger bursts before running
  438. * out of ring space (assuming dev->weight < ring_size) */
  439. if (!restart &&
  440. (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
  441. == CPMAC_EOQ &&
  442. (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
  443. /* reset EOQ so the poll loop (above) doesn't try to
  444. * restart this when it eventually gets to this descriptor.
  445. */
  446. priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
  447. restart = priv->rx_head;
  448. }
  449. if (restart) {
  450. priv->dev->stats.rx_errors++;
  451. priv->dev->stats.rx_fifo_errors++;
  452. if (netif_msg_rx_err(priv) && net_ratelimit())
  453. printk(KERN_WARNING "%s: rx dma ring overrun\n",
  454. priv->dev->name);
  455. if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
  456. if (netif_msg_drv(priv))
  457. printk(KERN_ERR "%s: cpmac_poll is trying to "
  458. "restart rx from a descriptor that's "
  459. "not free: %p\n",
  460. priv->dev->name, restart);
  461. goto fatal_error;
  462. }
  463. cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
  464. }
  465. priv->rx_head = desc;
  466. spin_unlock(&priv->rx_lock);
  467. if (unlikely(netif_msg_rx_status(priv)))
  468. printk(KERN_DEBUG "%s: poll processed %d packets\n",
  469. priv->dev->name, received);
  470. if (processed == 0) {
  471. /* we ran out of packets to read,
  472. * revert to interrupt-driven mode */
  473. napi_complete(napi);
  474. cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
  475. return 0;
  476. }
  477. return 1;
  478. fatal_error:
  479. /* Something went horribly wrong.
  480. * Reset hardware to try to recover rather than wedging. */
  481. if (netif_msg_drv(priv)) {
  482. printk(KERN_ERR "%s: cpmac_poll is confused. "
  483. "Resetting hardware\n", priv->dev->name);
  484. cpmac_dump_all_desc(priv->dev);
  485. printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
  486. priv->dev->name,
  487. cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
  488. cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
  489. }
  490. spin_unlock(&priv->rx_lock);
  491. napi_complete(napi);
  492. netif_tx_stop_all_queues(priv->dev);
  493. napi_disable(&priv->napi);
  494. atomic_inc(&priv->reset_pending);
  495. cpmac_hw_stop(priv->dev);
  496. if (!schedule_work(&priv->reset_work))
  497. atomic_dec(&priv->reset_pending);
  498. return 0;
  499. }
  500. static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
  501. {
  502. int queue, len;
  503. struct cpmac_desc *desc;
  504. struct cpmac_priv *priv = netdev_priv(dev);
  505. if (unlikely(atomic_read(&priv->reset_pending)))
  506. return NETDEV_TX_BUSY;
  507. if (unlikely(skb_padto(skb, ETH_ZLEN)))
  508. return NETDEV_TX_OK;
  509. len = max(skb->len, ETH_ZLEN);
  510. queue = skb_get_queue_mapping(skb);
  511. netif_stop_subqueue(dev, queue);
  512. desc = &priv->desc_ring[queue];
  513. if (unlikely(desc->dataflags & CPMAC_OWN)) {
  514. if (netif_msg_tx_err(priv) && net_ratelimit())
  515. printk(KERN_WARNING "%s: tx dma ring full\n",
  516. dev->name);
  517. return NETDEV_TX_BUSY;
  518. }
  519. spin_lock(&priv->lock);
  520. spin_unlock(&priv->lock);
  521. desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
  522. desc->skb = skb;
  523. desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
  524. DMA_TO_DEVICE);
  525. desc->hw_data = (u32)desc->data_mapping;
  526. desc->datalen = len;
  527. desc->buflen = len;
  528. if (unlikely(netif_msg_tx_queued(priv)))
  529. printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
  530. skb->len);
  531. if (unlikely(netif_msg_hw(priv)))
  532. cpmac_dump_desc(dev, desc);
  533. if (unlikely(netif_msg_pktdata(priv)))
  534. cpmac_dump_skb(dev, skb);
  535. cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
  536. return NETDEV_TX_OK;
  537. }
  538. static void cpmac_end_xmit(struct net_device *dev, int queue)
  539. {
  540. struct cpmac_desc *desc;
  541. struct cpmac_priv *priv = netdev_priv(dev);
  542. desc = &priv->desc_ring[queue];
  543. cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
  544. if (likely(desc->skb)) {
  545. spin_lock(&priv->lock);
  546. dev->stats.tx_packets++;
  547. dev->stats.tx_bytes += desc->skb->len;
  548. spin_unlock(&priv->lock);
  549. dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
  550. DMA_TO_DEVICE);
  551. if (unlikely(netif_msg_tx_done(priv)))
  552. printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
  553. desc->skb, desc->skb->len);
  554. dev_kfree_skb_irq(desc->skb);
  555. desc->skb = NULL;
  556. if (__netif_subqueue_stopped(dev, queue))
  557. netif_wake_subqueue(dev, queue);
  558. } else {
  559. if (netif_msg_tx_err(priv) && net_ratelimit())
  560. printk(KERN_WARNING
  561. "%s: end_xmit: spurious interrupt\n", dev->name);
  562. if (__netif_subqueue_stopped(dev, queue))
  563. netif_wake_subqueue(dev, queue);
  564. }
  565. }
  566. static void cpmac_hw_stop(struct net_device *dev)
  567. {
  568. int i;
  569. struct cpmac_priv *priv = netdev_priv(dev);
  570. struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
  571. ar7_device_reset(pdata->reset_bit);
  572. cpmac_write(priv->regs, CPMAC_RX_CONTROL,
  573. cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
  574. cpmac_write(priv->regs, CPMAC_TX_CONTROL,
  575. cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
  576. for (i = 0; i < 8; i++) {
  577. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  578. cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
  579. }
  580. cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
  581. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
  582. cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
  583. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  584. cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
  585. cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
  586. }
  587. static void cpmac_hw_start(struct net_device *dev)
  588. {
  589. int i;
  590. struct cpmac_priv *priv = netdev_priv(dev);
  591. struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
  592. ar7_device_reset(pdata->reset_bit);
  593. for (i = 0; i < 8; i++) {
  594. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  595. cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
  596. }
  597. cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
  598. cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
  599. MBP_RXMCAST);
  600. cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
  601. for (i = 0; i < 8; i++)
  602. cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
  603. cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
  604. cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
  605. (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
  606. (dev->dev_addr[3] << 24));
  607. cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
  608. cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
  609. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
  610. cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
  611. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  612. cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
  613. cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
  614. cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
  615. cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
  616. cpmac_write(priv->regs, CPMAC_RX_CONTROL,
  617. cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
  618. cpmac_write(priv->regs, CPMAC_TX_CONTROL,
  619. cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
  620. cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
  621. cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
  622. MAC_FDX);
  623. }
  624. static void cpmac_clear_rx(struct net_device *dev)
  625. {
  626. struct cpmac_priv *priv = netdev_priv(dev);
  627. struct cpmac_desc *desc;
  628. int i;
  629. if (unlikely(!priv->rx_head))
  630. return;
  631. desc = priv->rx_head;
  632. for (i = 0; i < priv->ring_size; i++) {
  633. if ((desc->dataflags & CPMAC_OWN) == 0) {
  634. if (netif_msg_rx_err(priv) && net_ratelimit())
  635. printk(KERN_WARNING "%s: packet dropped\n",
  636. dev->name);
  637. if (unlikely(netif_msg_hw(priv)))
  638. cpmac_dump_desc(dev, desc);
  639. desc->dataflags = CPMAC_OWN;
  640. dev->stats.rx_dropped++;
  641. }
  642. desc->hw_next = desc->next->mapping;
  643. desc = desc->next;
  644. }
  645. priv->rx_head->prev->hw_next = 0;
  646. }
  647. static void cpmac_clear_tx(struct net_device *dev)
  648. {
  649. struct cpmac_priv *priv = netdev_priv(dev);
  650. int i;
  651. if (unlikely(!priv->desc_ring))
  652. return;
  653. for (i = 0; i < CPMAC_QUEUES; i++) {
  654. priv->desc_ring[i].dataflags = 0;
  655. if (priv->desc_ring[i].skb) {
  656. dev_kfree_skb_any(priv->desc_ring[i].skb);
  657. priv->desc_ring[i].skb = NULL;
  658. }
  659. }
  660. }
  661. static void cpmac_hw_error(struct work_struct *work)
  662. {
  663. struct cpmac_priv *priv =
  664. container_of(work, struct cpmac_priv, reset_work);
  665. spin_lock(&priv->rx_lock);
  666. cpmac_clear_rx(priv->dev);
  667. spin_unlock(&priv->rx_lock);
  668. cpmac_clear_tx(priv->dev);
  669. cpmac_hw_start(priv->dev);
  670. barrier();
  671. atomic_dec(&priv->reset_pending);
  672. netif_tx_wake_all_queues(priv->dev);
  673. cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
  674. }
  675. static void cpmac_check_status(struct net_device *dev)
  676. {
  677. struct cpmac_priv *priv = netdev_priv(dev);
  678. u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
  679. int rx_channel = (macstatus >> 8) & 7;
  680. int rx_code = (macstatus >> 12) & 15;
  681. int tx_channel = (macstatus >> 16) & 7;
  682. int tx_code = (macstatus >> 20) & 15;
  683. if (rx_code || tx_code) {
  684. if (netif_msg_drv(priv) && net_ratelimit()) {
  685. /* Can't find any documentation on what these
  686. *error codes actually are. So just log them and hope..
  687. */
  688. if (rx_code)
  689. printk(KERN_WARNING "%s: host error %d on rx "
  690. "channel %d (macstatus %08x), resetting\n",
  691. dev->name, rx_code, rx_channel, macstatus);
  692. if (tx_code)
  693. printk(KERN_WARNING "%s: host error %d on tx "
  694. "channel %d (macstatus %08x), resetting\n",
  695. dev->name, tx_code, tx_channel, macstatus);
  696. }
  697. netif_tx_stop_all_queues(dev);
  698. cpmac_hw_stop(dev);
  699. if (schedule_work(&priv->reset_work))
  700. atomic_inc(&priv->reset_pending);
  701. if (unlikely(netif_msg_hw(priv)))
  702. cpmac_dump_regs(dev);
  703. }
  704. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  705. }
  706. static irqreturn_t cpmac_irq(int irq, void *dev_id)
  707. {
  708. struct net_device *dev = dev_id;
  709. struct cpmac_priv *priv;
  710. int queue;
  711. u32 status;
  712. priv = netdev_priv(dev);
  713. status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
  714. if (unlikely(netif_msg_intr(priv)))
  715. printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
  716. status);
  717. if (status & MAC_INT_TX)
  718. cpmac_end_xmit(dev, (status & 7));
  719. if (status & MAC_INT_RX) {
  720. queue = (status >> 8) & 7;
  721. if (napi_schedule_prep(&priv->napi)) {
  722. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
  723. __napi_schedule(&priv->napi);
  724. }
  725. }
  726. cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
  727. if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
  728. cpmac_check_status(dev);
  729. return IRQ_HANDLED;
  730. }
  731. static void cpmac_tx_timeout(struct net_device *dev)
  732. {
  733. struct cpmac_priv *priv = netdev_priv(dev);
  734. spin_lock(&priv->lock);
  735. dev->stats.tx_errors++;
  736. spin_unlock(&priv->lock);
  737. if (netif_msg_tx_err(priv) && net_ratelimit())
  738. printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
  739. atomic_inc(&priv->reset_pending);
  740. barrier();
  741. cpmac_clear_tx(dev);
  742. barrier();
  743. atomic_dec(&priv->reset_pending);
  744. netif_tx_wake_all_queues(priv->dev);
  745. }
  746. static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  747. {
  748. struct cpmac_priv *priv = netdev_priv(dev);
  749. if (!(netif_running(dev)))
  750. return -EINVAL;
  751. if (!priv->phy)
  752. return -EINVAL;
  753. return phy_mii_ioctl(priv->phy, ifr, cmd);
  754. }
  755. static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  756. {
  757. struct cpmac_priv *priv = netdev_priv(dev);
  758. if (priv->phy)
  759. return phy_ethtool_gset(priv->phy, cmd);
  760. return -EINVAL;
  761. }
  762. static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  763. {
  764. struct cpmac_priv *priv = netdev_priv(dev);
  765. if (!capable(CAP_NET_ADMIN))
  766. return -EPERM;
  767. if (priv->phy)
  768. return phy_ethtool_sset(priv->phy, cmd);
  769. return -EINVAL;
  770. }
  771. static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  772. {
  773. struct cpmac_priv *priv = netdev_priv(dev);
  774. ring->rx_max_pending = 1024;
  775. ring->rx_mini_max_pending = 1;
  776. ring->rx_jumbo_max_pending = 1;
  777. ring->tx_max_pending = 1;
  778. ring->rx_pending = priv->ring_size;
  779. ring->rx_mini_pending = 1;
  780. ring->rx_jumbo_pending = 1;
  781. ring->tx_pending = 1;
  782. }
  783. static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  784. {
  785. struct cpmac_priv *priv = netdev_priv(dev);
  786. if (netif_running(dev))
  787. return -EBUSY;
  788. priv->ring_size = ring->rx_pending;
  789. return 0;
  790. }
  791. static void cpmac_get_drvinfo(struct net_device *dev,
  792. struct ethtool_drvinfo *info)
  793. {
  794. strcpy(info->driver, "cpmac");
  795. strcpy(info->version, CPMAC_VERSION);
  796. info->fw_version[0] = '\0';
  797. sprintf(info->bus_info, "%s", "cpmac");
  798. info->regdump_len = 0;
  799. }
  800. static const struct ethtool_ops cpmac_ethtool_ops = {
  801. .get_settings = cpmac_get_settings,
  802. .set_settings = cpmac_set_settings,
  803. .get_drvinfo = cpmac_get_drvinfo,
  804. .get_link = ethtool_op_get_link,
  805. .get_ringparam = cpmac_get_ringparam,
  806. .set_ringparam = cpmac_set_ringparam,
  807. };
  808. static void cpmac_adjust_link(struct net_device *dev)
  809. {
  810. struct cpmac_priv *priv = netdev_priv(dev);
  811. int new_state = 0;
  812. spin_lock(&priv->lock);
  813. if (priv->phy->link) {
  814. netif_tx_start_all_queues(dev);
  815. if (priv->phy->duplex != priv->oldduplex) {
  816. new_state = 1;
  817. priv->oldduplex = priv->phy->duplex;
  818. }
  819. if (priv->phy->speed != priv->oldspeed) {
  820. new_state = 1;
  821. priv->oldspeed = priv->phy->speed;
  822. }
  823. if (!priv->oldlink) {
  824. new_state = 1;
  825. priv->oldlink = 1;
  826. }
  827. } else if (priv->oldlink) {
  828. new_state = 1;
  829. priv->oldlink = 0;
  830. priv->oldspeed = 0;
  831. priv->oldduplex = -1;
  832. }
  833. if (new_state && netif_msg_link(priv) && net_ratelimit())
  834. phy_print_status(priv->phy);
  835. spin_unlock(&priv->lock);
  836. }
  837. static int cpmac_open(struct net_device *dev)
  838. {
  839. int i, size, res;
  840. struct cpmac_priv *priv = netdev_priv(dev);
  841. struct resource *mem;
  842. struct cpmac_desc *desc;
  843. struct sk_buff *skb;
  844. mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
  845. if (!request_mem_region(mem->start, resource_size(mem), dev->name)) {
  846. if (netif_msg_drv(priv))
  847. printk(KERN_ERR "%s: failed to request registers\n",
  848. dev->name);
  849. res = -ENXIO;
  850. goto fail_reserve;
  851. }
  852. priv->regs = ioremap(mem->start, resource_size(mem));
  853. if (!priv->regs) {
  854. if (netif_msg_drv(priv))
  855. printk(KERN_ERR "%s: failed to remap registers\n",
  856. dev->name);
  857. res = -ENXIO;
  858. goto fail_remap;
  859. }
  860. size = priv->ring_size + CPMAC_QUEUES;
  861. priv->desc_ring = dma_alloc_coherent(&dev->dev,
  862. sizeof(struct cpmac_desc) * size,
  863. &priv->dma_ring,
  864. GFP_KERNEL);
  865. if (!priv->desc_ring) {
  866. res = -ENOMEM;
  867. goto fail_alloc;
  868. }
  869. for (i = 0; i < size; i++)
  870. priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
  871. priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
  872. for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
  873. skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
  874. if (unlikely(!skb)) {
  875. res = -ENOMEM;
  876. goto fail_desc;
  877. }
  878. desc->skb = skb;
  879. desc->data_mapping = dma_map_single(&dev->dev, skb->data,
  880. CPMAC_SKB_SIZE,
  881. DMA_FROM_DEVICE);
  882. desc->hw_data = (u32)desc->data_mapping;
  883. desc->buflen = CPMAC_SKB_SIZE;
  884. desc->dataflags = CPMAC_OWN;
  885. desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
  886. desc->next->prev = desc;
  887. desc->hw_next = (u32)desc->next->mapping;
  888. }
  889. priv->rx_head->prev->hw_next = (u32)0;
  890. if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
  891. dev->name, dev))) {
  892. if (netif_msg_drv(priv))
  893. printk(KERN_ERR "%s: failed to obtain irq\n",
  894. dev->name);
  895. goto fail_irq;
  896. }
  897. atomic_set(&priv->reset_pending, 0);
  898. INIT_WORK(&priv->reset_work, cpmac_hw_error);
  899. cpmac_hw_start(dev);
  900. napi_enable(&priv->napi);
  901. priv->phy->state = PHY_CHANGELINK;
  902. phy_start(priv->phy);
  903. return 0;
  904. fail_irq:
  905. fail_desc:
  906. for (i = 0; i < priv->ring_size; i++) {
  907. if (priv->rx_head[i].skb) {
  908. dma_unmap_single(&dev->dev,
  909. priv->rx_head[i].data_mapping,
  910. CPMAC_SKB_SIZE,
  911. DMA_FROM_DEVICE);
  912. kfree_skb(priv->rx_head[i].skb);
  913. }
  914. }
  915. fail_alloc:
  916. kfree(priv->desc_ring);
  917. iounmap(priv->regs);
  918. fail_remap:
  919. release_mem_region(mem->start, resource_size(mem));
  920. fail_reserve:
  921. return res;
  922. }
  923. static int cpmac_stop(struct net_device *dev)
  924. {
  925. int i;
  926. struct cpmac_priv *priv = netdev_priv(dev);
  927. struct resource *mem;
  928. netif_tx_stop_all_queues(dev);
  929. cancel_work_sync(&priv->reset_work);
  930. napi_disable(&priv->napi);
  931. phy_stop(priv->phy);
  932. cpmac_hw_stop(dev);
  933. for (i = 0; i < 8; i++)
  934. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  935. cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
  936. cpmac_write(priv->regs, CPMAC_MBP, 0);
  937. free_irq(dev->irq, dev);
  938. iounmap(priv->regs);
  939. mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
  940. release_mem_region(mem->start, resource_size(mem));
  941. priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
  942. for (i = 0; i < priv->ring_size; i++) {
  943. if (priv->rx_head[i].skb) {
  944. dma_unmap_single(&dev->dev,
  945. priv->rx_head[i].data_mapping,
  946. CPMAC_SKB_SIZE,
  947. DMA_FROM_DEVICE);
  948. kfree_skb(priv->rx_head[i].skb);
  949. }
  950. }
  951. dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
  952. (CPMAC_QUEUES + priv->ring_size),
  953. priv->desc_ring, priv->dma_ring);
  954. return 0;
  955. }
  956. static const struct net_device_ops cpmac_netdev_ops = {
  957. .ndo_open = cpmac_open,
  958. .ndo_stop = cpmac_stop,
  959. .ndo_start_xmit = cpmac_start_xmit,
  960. .ndo_tx_timeout = cpmac_tx_timeout,
  961. .ndo_set_multicast_list = cpmac_set_multicast_list,
  962. .ndo_do_ioctl = cpmac_ioctl,
  963. .ndo_set_config = cpmac_config,
  964. .ndo_change_mtu = eth_change_mtu,
  965. .ndo_validate_addr = eth_validate_addr,
  966. .ndo_set_mac_address = eth_mac_addr,
  967. };
  968. static int external_switch;
  969. static int __devinit cpmac_probe(struct platform_device *pdev)
  970. {
  971. int rc, phy_id;
  972. char mdio_bus_id[MII_BUS_ID_SIZE];
  973. struct resource *mem;
  974. struct cpmac_priv *priv;
  975. struct net_device *dev;
  976. struct plat_cpmac_data *pdata;
  977. pdata = pdev->dev.platform_data;
  978. if (external_switch || dumb_switch) {
  979. strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
  980. phy_id = pdev->id;
  981. } else {
  982. for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
  983. if (!(pdata->phy_mask & (1 << phy_id)))
  984. continue;
  985. if (!cpmac_mii->phy_map[phy_id])
  986. continue;
  987. strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
  988. break;
  989. }
  990. }
  991. if (phy_id == PHY_MAX_ADDR) {
  992. dev_err(&pdev->dev, "no PHY present, falling back to switch on MDIO bus 0\n");
  993. strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
  994. phy_id = pdev->id;
  995. }
  996. dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
  997. if (!dev) {
  998. printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
  999. return -ENOMEM;
  1000. }
  1001. platform_set_drvdata(pdev, dev);
  1002. priv = netdev_priv(dev);
  1003. priv->pdev = pdev;
  1004. mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  1005. if (!mem) {
  1006. rc = -ENODEV;
  1007. goto fail;
  1008. }
  1009. dev->irq = platform_get_irq_byname(pdev, "irq");
  1010. dev->netdev_ops = &cpmac_netdev_ops;
  1011. dev->ethtool_ops = &cpmac_ethtool_ops;
  1012. netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
  1013. spin_lock_init(&priv->lock);
  1014. spin_lock_init(&priv->rx_lock);
  1015. priv->dev = dev;
  1016. priv->ring_size = 64;
  1017. priv->msg_enable = netif_msg_init(debug_level, 0xff);
  1018. memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
  1019. snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
  1020. priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0,
  1021. PHY_INTERFACE_MODE_MII);
  1022. if (IS_ERR(priv->phy)) {
  1023. if (netif_msg_drv(priv))
  1024. printk(KERN_ERR "%s: Could not attach to PHY\n",
  1025. dev->name);
  1026. rc = PTR_ERR(priv->phy);
  1027. goto fail;
  1028. }
  1029. if ((rc = register_netdev(dev))) {
  1030. printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
  1031. dev->name);
  1032. goto fail;
  1033. }
  1034. if (netif_msg_probe(priv)) {
  1035. printk(KERN_INFO
  1036. "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
  1037. "mac: %pM)\n", dev->name, (void *)mem->start, dev->irq,
  1038. priv->phy_name, dev->dev_addr);
  1039. }
  1040. return 0;
  1041. fail:
  1042. free_netdev(dev);
  1043. return rc;
  1044. }
  1045. static int __devexit cpmac_remove(struct platform_device *pdev)
  1046. {
  1047. struct net_device *dev = platform_get_drvdata(pdev);
  1048. unregister_netdev(dev);
  1049. free_netdev(dev);
  1050. return 0;
  1051. }
  1052. static struct platform_driver cpmac_driver = {
  1053. .driver.name = "cpmac",
  1054. .driver.owner = THIS_MODULE,
  1055. .probe = cpmac_probe,
  1056. .remove = __devexit_p(cpmac_remove),
  1057. };
  1058. int __devinit cpmac_init(void)
  1059. {
  1060. u32 mask;
  1061. int i, res;
  1062. cpmac_mii = mdiobus_alloc();
  1063. if (cpmac_mii == NULL)
  1064. return -ENOMEM;
  1065. cpmac_mii->name = "cpmac-mii";
  1066. cpmac_mii->read = cpmac_mdio_read;
  1067. cpmac_mii->write = cpmac_mdio_write;
  1068. cpmac_mii->reset = cpmac_mdio_reset;
  1069. cpmac_mii->irq = mii_irqs;
  1070. cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
  1071. if (!cpmac_mii->priv) {
  1072. printk(KERN_ERR "Can't ioremap mdio registers\n");
  1073. res = -ENXIO;
  1074. goto fail_alloc;
  1075. }
  1076. #warning FIXME: unhardcode gpio&reset bits
  1077. ar7_gpio_disable(26);
  1078. ar7_gpio_disable(27);
  1079. ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
  1080. ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
  1081. ar7_device_reset(AR7_RESET_BIT_EPHY);
  1082. cpmac_mii->reset(cpmac_mii);
  1083. for (i = 0; i < 300; i++)
  1084. if ((mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE)))
  1085. break;
  1086. else
  1087. msleep(10);
  1088. mask &= 0x7fffffff;
  1089. if (mask & (mask - 1)) {
  1090. external_switch = 1;
  1091. mask = 0;
  1092. }
  1093. cpmac_mii->phy_mask = ~(mask | 0x80000000);
  1094. snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1");
  1095. res = mdiobus_register(cpmac_mii);
  1096. if (res)
  1097. goto fail_mii;
  1098. res = platform_driver_register(&cpmac_driver);
  1099. if (res)
  1100. goto fail_cpmac;
  1101. return 0;
  1102. fail_cpmac:
  1103. mdiobus_unregister(cpmac_mii);
  1104. fail_mii:
  1105. iounmap(cpmac_mii->priv);
  1106. fail_alloc:
  1107. mdiobus_free(cpmac_mii);
  1108. return res;
  1109. }
  1110. void __devexit cpmac_exit(void)
  1111. {
  1112. platform_driver_unregister(&cpmac_driver);
  1113. mdiobus_unregister(cpmac_mii);
  1114. iounmap(cpmac_mii->priv);
  1115. mdiobus_free(cpmac_mii);
  1116. }
  1117. module_init(cpmac_init);
  1118. module_exit(cpmac_exit);