bnx2.c 208 KB

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  1. /* bnx2.c: Broadcom NX2 network driver.
  2. *
  3. * Copyright (c) 2004-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Written by: Michael Chan (mchan@broadcom.com)
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/kernel.h>
  15. #include <linux/timer.h>
  16. #include <linux/errno.h>
  17. #include <linux/ioport.h>
  18. #include <linux/slab.h>
  19. #include <linux/vmalloc.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/pci.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/skbuff.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/bitops.h>
  28. #include <asm/io.h>
  29. #include <asm/irq.h>
  30. #include <linux/delay.h>
  31. #include <asm/byteorder.h>
  32. #include <asm/page.h>
  33. #include <linux/time.h>
  34. #include <linux/ethtool.h>
  35. #include <linux/mii.h>
  36. #include <linux/if_vlan.h>
  37. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  38. #define BCM_VLAN 1
  39. #endif
  40. #include <net/ip.h>
  41. #include <net/tcp.h>
  42. #include <net/checksum.h>
  43. #include <linux/workqueue.h>
  44. #include <linux/crc32.h>
  45. #include <linux/prefetch.h>
  46. #include <linux/cache.h>
  47. #include <linux/firmware.h>
  48. #include <linux/log2.h>
  49. #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
  50. #define BCM_CNIC 1
  51. #include "cnic_if.h"
  52. #endif
  53. #include "bnx2.h"
  54. #include "bnx2_fw.h"
  55. #define DRV_MODULE_NAME "bnx2"
  56. #define DRV_MODULE_VERSION "2.0.17"
  57. #define DRV_MODULE_RELDATE "July 18, 2010"
  58. #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
  59. #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
  60. #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j15.fw"
  61. #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
  62. #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
  63. #define RUN_AT(x) (jiffies + (x))
  64. /* Time in jiffies before concluding the transmitter is hung. */
  65. #define TX_TIMEOUT (5*HZ)
  66. static char version[] __devinitdata =
  67. "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  68. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  69. MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
  70. MODULE_LICENSE("GPL");
  71. MODULE_VERSION(DRV_MODULE_VERSION);
  72. MODULE_FIRMWARE(FW_MIPS_FILE_06);
  73. MODULE_FIRMWARE(FW_RV2P_FILE_06);
  74. MODULE_FIRMWARE(FW_MIPS_FILE_09);
  75. MODULE_FIRMWARE(FW_RV2P_FILE_09);
  76. MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
  77. static int disable_msi = 0;
  78. module_param(disable_msi, int, 0);
  79. MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  80. typedef enum {
  81. BCM5706 = 0,
  82. NC370T,
  83. NC370I,
  84. BCM5706S,
  85. NC370F,
  86. BCM5708,
  87. BCM5708S,
  88. BCM5709,
  89. BCM5709S,
  90. BCM5716,
  91. BCM5716S,
  92. } board_t;
  93. /* indexed by board_t, above */
  94. static struct {
  95. char *name;
  96. } board_info[] __devinitdata = {
  97. { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  98. { "HP NC370T Multifunction Gigabit Server Adapter" },
  99. { "HP NC370i Multifunction Gigabit Server Adapter" },
  100. { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  101. { "HP NC370F Multifunction Gigabit Server Adapter" },
  102. { "Broadcom NetXtreme II BCM5708 1000Base-T" },
  103. { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
  104. { "Broadcom NetXtreme II BCM5709 1000Base-T" },
  105. { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
  106. { "Broadcom NetXtreme II BCM5716 1000Base-T" },
  107. { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
  108. };
  109. static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
  110. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  111. PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  112. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  113. PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  114. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  115. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  116. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
  117. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
  118. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  119. PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  120. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  121. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  122. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
  123. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
  124. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
  125. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
  126. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
  127. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
  128. { PCI_VENDOR_ID_BROADCOM, 0x163b,
  129. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
  130. { PCI_VENDOR_ID_BROADCOM, 0x163c,
  131. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
  132. { 0, }
  133. };
  134. static const struct flash_spec flash_table[] =
  135. {
  136. #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
  137. #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
  138. /* Slow EEPROM */
  139. {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
  140. BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  141. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  142. "EEPROM - slow"},
  143. /* Expansion entry 0001 */
  144. {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
  145. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  146. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  147. "Entry 0001"},
  148. /* Saifun SA25F010 (non-buffered flash) */
  149. /* strap, cfg1, & write1 need updates */
  150. {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
  151. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  152. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  153. "Non-buffered flash (128kB)"},
  154. /* Saifun SA25F020 (non-buffered flash) */
  155. /* strap, cfg1, & write1 need updates */
  156. {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
  157. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  158. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
  159. "Non-buffered flash (256kB)"},
  160. /* Expansion entry 0100 */
  161. {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
  162. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  163. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  164. "Entry 0100"},
  165. /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
  166. {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
  167. NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  168. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
  169. "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
  170. /* Entry 0110: ST M45PE20 (non-buffered flash)*/
  171. {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
  172. NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  173. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
  174. "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
  175. /* Saifun SA25F005 (non-buffered flash) */
  176. /* strap, cfg1, & write1 need updates */
  177. {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
  178. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  179. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
  180. "Non-buffered flash (64kB)"},
  181. /* Fast EEPROM */
  182. {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
  183. BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  184. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  185. "EEPROM - fast"},
  186. /* Expansion entry 1001 */
  187. {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
  188. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  189. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  190. "Entry 1001"},
  191. /* Expansion entry 1010 */
  192. {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
  193. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  194. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  195. "Entry 1010"},
  196. /* ATMEL AT45DB011B (buffered flash) */
  197. {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
  198. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  199. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
  200. "Buffered flash (128kB)"},
  201. /* Expansion entry 1100 */
  202. {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
  203. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  204. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  205. "Entry 1100"},
  206. /* Expansion entry 1101 */
  207. {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
  208. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  209. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  210. "Entry 1101"},
  211. /* Ateml Expansion entry 1110 */
  212. {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
  213. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  214. BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
  215. "Entry 1110 (Atmel)"},
  216. /* ATMEL AT45DB021B (buffered flash) */
  217. {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
  218. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  219. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
  220. "Buffered flash (256kB)"},
  221. };
  222. static const struct flash_spec flash_5709 = {
  223. .flags = BNX2_NV_BUFFERED,
  224. .page_bits = BCM5709_FLASH_PAGE_BITS,
  225. .page_size = BCM5709_FLASH_PAGE_SIZE,
  226. .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
  227. .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
  228. .name = "5709 Buffered flash (256kB)",
  229. };
  230. MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
  231. static void bnx2_init_napi(struct bnx2 *bp);
  232. static void bnx2_del_napi(struct bnx2 *bp);
  233. static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
  234. {
  235. u32 diff;
  236. /* Tell compiler to fetch tx_prod and tx_cons from memory. */
  237. barrier();
  238. /* The ring uses 256 indices for 255 entries, one of them
  239. * needs to be skipped.
  240. */
  241. diff = txr->tx_prod - txr->tx_cons;
  242. if (unlikely(diff >= TX_DESC_CNT)) {
  243. diff &= 0xffff;
  244. if (diff == TX_DESC_CNT)
  245. diff = MAX_TX_DESC_CNT;
  246. }
  247. return (bp->tx_ring_size - diff);
  248. }
  249. static u32
  250. bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
  251. {
  252. u32 val;
  253. spin_lock_bh(&bp->indirect_lock);
  254. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  255. val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
  256. spin_unlock_bh(&bp->indirect_lock);
  257. return val;
  258. }
  259. static void
  260. bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
  261. {
  262. spin_lock_bh(&bp->indirect_lock);
  263. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  264. REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
  265. spin_unlock_bh(&bp->indirect_lock);
  266. }
  267. static void
  268. bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
  269. {
  270. bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
  271. }
  272. static u32
  273. bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
  274. {
  275. return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
  276. }
  277. static void
  278. bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
  279. {
  280. offset += cid_addr;
  281. spin_lock_bh(&bp->indirect_lock);
  282. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  283. int i;
  284. REG_WR(bp, BNX2_CTX_CTX_DATA, val);
  285. REG_WR(bp, BNX2_CTX_CTX_CTRL,
  286. offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
  287. for (i = 0; i < 5; i++) {
  288. val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
  289. if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
  290. break;
  291. udelay(5);
  292. }
  293. } else {
  294. REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
  295. REG_WR(bp, BNX2_CTX_DATA, val);
  296. }
  297. spin_unlock_bh(&bp->indirect_lock);
  298. }
  299. #ifdef BCM_CNIC
  300. static int
  301. bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
  302. {
  303. struct bnx2 *bp = netdev_priv(dev);
  304. struct drv_ctl_io *io = &info->data.io;
  305. switch (info->cmd) {
  306. case DRV_CTL_IO_WR_CMD:
  307. bnx2_reg_wr_ind(bp, io->offset, io->data);
  308. break;
  309. case DRV_CTL_IO_RD_CMD:
  310. io->data = bnx2_reg_rd_ind(bp, io->offset);
  311. break;
  312. case DRV_CTL_CTX_WR_CMD:
  313. bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
  314. break;
  315. default:
  316. return -EINVAL;
  317. }
  318. return 0;
  319. }
  320. static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
  321. {
  322. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  323. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  324. int sb_id;
  325. if (bp->flags & BNX2_FLAG_USING_MSIX) {
  326. cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
  327. bnapi->cnic_present = 0;
  328. sb_id = bp->irq_nvecs;
  329. cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
  330. } else {
  331. cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
  332. bnapi->cnic_tag = bnapi->last_status_idx;
  333. bnapi->cnic_present = 1;
  334. sb_id = 0;
  335. cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
  336. }
  337. cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
  338. cp->irq_arr[0].status_blk = (void *)
  339. ((unsigned long) bnapi->status_blk.msi +
  340. (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
  341. cp->irq_arr[0].status_blk_num = sb_id;
  342. cp->num_irq = 1;
  343. }
  344. static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
  345. void *data)
  346. {
  347. struct bnx2 *bp = netdev_priv(dev);
  348. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  349. if (ops == NULL)
  350. return -EINVAL;
  351. if (cp->drv_state & CNIC_DRV_STATE_REGD)
  352. return -EBUSY;
  353. bp->cnic_data = data;
  354. rcu_assign_pointer(bp->cnic_ops, ops);
  355. cp->num_irq = 0;
  356. cp->drv_state = CNIC_DRV_STATE_REGD;
  357. bnx2_setup_cnic_irq_info(bp);
  358. return 0;
  359. }
  360. static int bnx2_unregister_cnic(struct net_device *dev)
  361. {
  362. struct bnx2 *bp = netdev_priv(dev);
  363. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  364. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  365. mutex_lock(&bp->cnic_lock);
  366. cp->drv_state = 0;
  367. bnapi->cnic_present = 0;
  368. rcu_assign_pointer(bp->cnic_ops, NULL);
  369. mutex_unlock(&bp->cnic_lock);
  370. synchronize_rcu();
  371. return 0;
  372. }
  373. struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
  374. {
  375. struct bnx2 *bp = netdev_priv(dev);
  376. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  377. cp->drv_owner = THIS_MODULE;
  378. cp->chip_id = bp->chip_id;
  379. cp->pdev = bp->pdev;
  380. cp->io_base = bp->regview;
  381. cp->drv_ctl = bnx2_drv_ctl;
  382. cp->drv_register_cnic = bnx2_register_cnic;
  383. cp->drv_unregister_cnic = bnx2_unregister_cnic;
  384. return cp;
  385. }
  386. EXPORT_SYMBOL(bnx2_cnic_probe);
  387. static void
  388. bnx2_cnic_stop(struct bnx2 *bp)
  389. {
  390. struct cnic_ops *c_ops;
  391. struct cnic_ctl_info info;
  392. mutex_lock(&bp->cnic_lock);
  393. c_ops = bp->cnic_ops;
  394. if (c_ops) {
  395. info.cmd = CNIC_CTL_STOP_CMD;
  396. c_ops->cnic_ctl(bp->cnic_data, &info);
  397. }
  398. mutex_unlock(&bp->cnic_lock);
  399. }
  400. static void
  401. bnx2_cnic_start(struct bnx2 *bp)
  402. {
  403. struct cnic_ops *c_ops;
  404. struct cnic_ctl_info info;
  405. mutex_lock(&bp->cnic_lock);
  406. c_ops = bp->cnic_ops;
  407. if (c_ops) {
  408. if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
  409. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  410. bnapi->cnic_tag = bnapi->last_status_idx;
  411. }
  412. info.cmd = CNIC_CTL_START_CMD;
  413. c_ops->cnic_ctl(bp->cnic_data, &info);
  414. }
  415. mutex_unlock(&bp->cnic_lock);
  416. }
  417. #else
  418. static void
  419. bnx2_cnic_stop(struct bnx2 *bp)
  420. {
  421. }
  422. static void
  423. bnx2_cnic_start(struct bnx2 *bp)
  424. {
  425. }
  426. #endif
  427. static int
  428. bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
  429. {
  430. u32 val1;
  431. int i, ret;
  432. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  433. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  434. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  435. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  436. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  437. udelay(40);
  438. }
  439. val1 = (bp->phy_addr << 21) | (reg << 16) |
  440. BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
  441. BNX2_EMAC_MDIO_COMM_START_BUSY;
  442. REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  443. for (i = 0; i < 50; i++) {
  444. udelay(10);
  445. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  446. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  447. udelay(5);
  448. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  449. val1 &= BNX2_EMAC_MDIO_COMM_DATA;
  450. break;
  451. }
  452. }
  453. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
  454. *val = 0x0;
  455. ret = -EBUSY;
  456. }
  457. else {
  458. *val = val1;
  459. ret = 0;
  460. }
  461. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  462. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  463. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  464. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  465. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  466. udelay(40);
  467. }
  468. return ret;
  469. }
  470. static int
  471. bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
  472. {
  473. u32 val1;
  474. int i, ret;
  475. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  476. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  477. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  478. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  479. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  480. udelay(40);
  481. }
  482. val1 = (bp->phy_addr << 21) | (reg << 16) | val |
  483. BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
  484. BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
  485. REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  486. for (i = 0; i < 50; i++) {
  487. udelay(10);
  488. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  489. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  490. udelay(5);
  491. break;
  492. }
  493. }
  494. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
  495. ret = -EBUSY;
  496. else
  497. ret = 0;
  498. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  499. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  500. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  501. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  502. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  503. udelay(40);
  504. }
  505. return ret;
  506. }
  507. static void
  508. bnx2_disable_int(struct bnx2 *bp)
  509. {
  510. int i;
  511. struct bnx2_napi *bnapi;
  512. for (i = 0; i < bp->irq_nvecs; i++) {
  513. bnapi = &bp->bnx2_napi[i];
  514. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  515. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  516. }
  517. REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
  518. }
  519. static void
  520. bnx2_enable_int(struct bnx2 *bp)
  521. {
  522. int i;
  523. struct bnx2_napi *bnapi;
  524. for (i = 0; i < bp->irq_nvecs; i++) {
  525. bnapi = &bp->bnx2_napi[i];
  526. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  527. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  528. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  529. bnapi->last_status_idx);
  530. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  531. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  532. bnapi->last_status_idx);
  533. }
  534. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
  535. }
  536. static void
  537. bnx2_disable_int_sync(struct bnx2 *bp)
  538. {
  539. int i;
  540. atomic_inc(&bp->intr_sem);
  541. if (!netif_running(bp->dev))
  542. return;
  543. bnx2_disable_int(bp);
  544. for (i = 0; i < bp->irq_nvecs; i++)
  545. synchronize_irq(bp->irq_tbl[i].vector);
  546. }
  547. static void
  548. bnx2_napi_disable(struct bnx2 *bp)
  549. {
  550. int i;
  551. for (i = 0; i < bp->irq_nvecs; i++)
  552. napi_disable(&bp->bnx2_napi[i].napi);
  553. }
  554. static void
  555. bnx2_napi_enable(struct bnx2 *bp)
  556. {
  557. int i;
  558. for (i = 0; i < bp->irq_nvecs; i++)
  559. napi_enable(&bp->bnx2_napi[i].napi);
  560. }
  561. static void
  562. bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
  563. {
  564. if (stop_cnic)
  565. bnx2_cnic_stop(bp);
  566. if (netif_running(bp->dev)) {
  567. bnx2_napi_disable(bp);
  568. netif_tx_disable(bp->dev);
  569. }
  570. bnx2_disable_int_sync(bp);
  571. netif_carrier_off(bp->dev); /* prevent tx timeout */
  572. }
  573. static void
  574. bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
  575. {
  576. if (atomic_dec_and_test(&bp->intr_sem)) {
  577. if (netif_running(bp->dev)) {
  578. netif_tx_wake_all_queues(bp->dev);
  579. spin_lock_bh(&bp->phy_lock);
  580. if (bp->link_up)
  581. netif_carrier_on(bp->dev);
  582. spin_unlock_bh(&bp->phy_lock);
  583. bnx2_napi_enable(bp);
  584. bnx2_enable_int(bp);
  585. if (start_cnic)
  586. bnx2_cnic_start(bp);
  587. }
  588. }
  589. }
  590. static void
  591. bnx2_free_tx_mem(struct bnx2 *bp)
  592. {
  593. int i;
  594. for (i = 0; i < bp->num_tx_rings; i++) {
  595. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  596. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  597. if (txr->tx_desc_ring) {
  598. dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
  599. txr->tx_desc_ring,
  600. txr->tx_desc_mapping);
  601. txr->tx_desc_ring = NULL;
  602. }
  603. kfree(txr->tx_buf_ring);
  604. txr->tx_buf_ring = NULL;
  605. }
  606. }
  607. static void
  608. bnx2_free_rx_mem(struct bnx2 *bp)
  609. {
  610. int i;
  611. for (i = 0; i < bp->num_rx_rings; i++) {
  612. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  613. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  614. int j;
  615. for (j = 0; j < bp->rx_max_ring; j++) {
  616. if (rxr->rx_desc_ring[j])
  617. dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
  618. rxr->rx_desc_ring[j],
  619. rxr->rx_desc_mapping[j]);
  620. rxr->rx_desc_ring[j] = NULL;
  621. }
  622. vfree(rxr->rx_buf_ring);
  623. rxr->rx_buf_ring = NULL;
  624. for (j = 0; j < bp->rx_max_pg_ring; j++) {
  625. if (rxr->rx_pg_desc_ring[j])
  626. dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
  627. rxr->rx_pg_desc_ring[j],
  628. rxr->rx_pg_desc_mapping[j]);
  629. rxr->rx_pg_desc_ring[j] = NULL;
  630. }
  631. vfree(rxr->rx_pg_ring);
  632. rxr->rx_pg_ring = NULL;
  633. }
  634. }
  635. static int
  636. bnx2_alloc_tx_mem(struct bnx2 *bp)
  637. {
  638. int i;
  639. for (i = 0; i < bp->num_tx_rings; i++) {
  640. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  641. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  642. txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
  643. if (txr->tx_buf_ring == NULL)
  644. return -ENOMEM;
  645. txr->tx_desc_ring =
  646. dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
  647. &txr->tx_desc_mapping, GFP_KERNEL);
  648. if (txr->tx_desc_ring == NULL)
  649. return -ENOMEM;
  650. }
  651. return 0;
  652. }
  653. static int
  654. bnx2_alloc_rx_mem(struct bnx2 *bp)
  655. {
  656. int i;
  657. for (i = 0; i < bp->num_rx_rings; i++) {
  658. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  659. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  660. int j;
  661. rxr->rx_buf_ring =
  662. vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
  663. if (rxr->rx_buf_ring == NULL)
  664. return -ENOMEM;
  665. memset(rxr->rx_buf_ring, 0,
  666. SW_RXBD_RING_SIZE * bp->rx_max_ring);
  667. for (j = 0; j < bp->rx_max_ring; j++) {
  668. rxr->rx_desc_ring[j] =
  669. dma_alloc_coherent(&bp->pdev->dev,
  670. RXBD_RING_SIZE,
  671. &rxr->rx_desc_mapping[j],
  672. GFP_KERNEL);
  673. if (rxr->rx_desc_ring[j] == NULL)
  674. return -ENOMEM;
  675. }
  676. if (bp->rx_pg_ring_size) {
  677. rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
  678. bp->rx_max_pg_ring);
  679. if (rxr->rx_pg_ring == NULL)
  680. return -ENOMEM;
  681. memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
  682. bp->rx_max_pg_ring);
  683. }
  684. for (j = 0; j < bp->rx_max_pg_ring; j++) {
  685. rxr->rx_pg_desc_ring[j] =
  686. dma_alloc_coherent(&bp->pdev->dev,
  687. RXBD_RING_SIZE,
  688. &rxr->rx_pg_desc_mapping[j],
  689. GFP_KERNEL);
  690. if (rxr->rx_pg_desc_ring[j] == NULL)
  691. return -ENOMEM;
  692. }
  693. }
  694. return 0;
  695. }
  696. static void
  697. bnx2_free_mem(struct bnx2 *bp)
  698. {
  699. int i;
  700. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  701. bnx2_free_tx_mem(bp);
  702. bnx2_free_rx_mem(bp);
  703. for (i = 0; i < bp->ctx_pages; i++) {
  704. if (bp->ctx_blk[i]) {
  705. dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
  706. bp->ctx_blk[i],
  707. bp->ctx_blk_mapping[i]);
  708. bp->ctx_blk[i] = NULL;
  709. }
  710. }
  711. if (bnapi->status_blk.msi) {
  712. dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
  713. bnapi->status_blk.msi,
  714. bp->status_blk_mapping);
  715. bnapi->status_blk.msi = NULL;
  716. bp->stats_blk = NULL;
  717. }
  718. }
  719. static int
  720. bnx2_alloc_mem(struct bnx2 *bp)
  721. {
  722. int i, status_blk_size, err;
  723. struct bnx2_napi *bnapi;
  724. void *status_blk;
  725. /* Combine status and statistics blocks into one allocation. */
  726. status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
  727. if (bp->flags & BNX2_FLAG_MSIX_CAP)
  728. status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
  729. BNX2_SBLK_MSIX_ALIGN_SIZE);
  730. bp->status_stats_size = status_blk_size +
  731. sizeof(struct statistics_block);
  732. status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
  733. &bp->status_blk_mapping, GFP_KERNEL);
  734. if (status_blk == NULL)
  735. goto alloc_mem_err;
  736. memset(status_blk, 0, bp->status_stats_size);
  737. bnapi = &bp->bnx2_napi[0];
  738. bnapi->status_blk.msi = status_blk;
  739. bnapi->hw_tx_cons_ptr =
  740. &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
  741. bnapi->hw_rx_cons_ptr =
  742. &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
  743. if (bp->flags & BNX2_FLAG_MSIX_CAP) {
  744. for (i = 1; i < bp->irq_nvecs; i++) {
  745. struct status_block_msix *sblk;
  746. bnapi = &bp->bnx2_napi[i];
  747. sblk = (void *) (status_blk +
  748. BNX2_SBLK_MSIX_ALIGN_SIZE * i);
  749. bnapi->status_blk.msix = sblk;
  750. bnapi->hw_tx_cons_ptr =
  751. &sblk->status_tx_quick_consumer_index;
  752. bnapi->hw_rx_cons_ptr =
  753. &sblk->status_rx_quick_consumer_index;
  754. bnapi->int_num = i << 24;
  755. }
  756. }
  757. bp->stats_blk = status_blk + status_blk_size;
  758. bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
  759. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  760. bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
  761. if (bp->ctx_pages == 0)
  762. bp->ctx_pages = 1;
  763. for (i = 0; i < bp->ctx_pages; i++) {
  764. bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
  765. BCM_PAGE_SIZE,
  766. &bp->ctx_blk_mapping[i],
  767. GFP_KERNEL);
  768. if (bp->ctx_blk[i] == NULL)
  769. goto alloc_mem_err;
  770. }
  771. }
  772. err = bnx2_alloc_rx_mem(bp);
  773. if (err)
  774. goto alloc_mem_err;
  775. err = bnx2_alloc_tx_mem(bp);
  776. if (err)
  777. goto alloc_mem_err;
  778. return 0;
  779. alloc_mem_err:
  780. bnx2_free_mem(bp);
  781. return -ENOMEM;
  782. }
  783. static void
  784. bnx2_report_fw_link(struct bnx2 *bp)
  785. {
  786. u32 fw_link_status = 0;
  787. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  788. return;
  789. if (bp->link_up) {
  790. u32 bmsr;
  791. switch (bp->line_speed) {
  792. case SPEED_10:
  793. if (bp->duplex == DUPLEX_HALF)
  794. fw_link_status = BNX2_LINK_STATUS_10HALF;
  795. else
  796. fw_link_status = BNX2_LINK_STATUS_10FULL;
  797. break;
  798. case SPEED_100:
  799. if (bp->duplex == DUPLEX_HALF)
  800. fw_link_status = BNX2_LINK_STATUS_100HALF;
  801. else
  802. fw_link_status = BNX2_LINK_STATUS_100FULL;
  803. break;
  804. case SPEED_1000:
  805. if (bp->duplex == DUPLEX_HALF)
  806. fw_link_status = BNX2_LINK_STATUS_1000HALF;
  807. else
  808. fw_link_status = BNX2_LINK_STATUS_1000FULL;
  809. break;
  810. case SPEED_2500:
  811. if (bp->duplex == DUPLEX_HALF)
  812. fw_link_status = BNX2_LINK_STATUS_2500HALF;
  813. else
  814. fw_link_status = BNX2_LINK_STATUS_2500FULL;
  815. break;
  816. }
  817. fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
  818. if (bp->autoneg) {
  819. fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
  820. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  821. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  822. if (!(bmsr & BMSR_ANEGCOMPLETE) ||
  823. bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
  824. fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
  825. else
  826. fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
  827. }
  828. }
  829. else
  830. fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
  831. bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
  832. }
  833. static char *
  834. bnx2_xceiver_str(struct bnx2 *bp)
  835. {
  836. return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
  837. ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
  838. "Copper"));
  839. }
  840. static void
  841. bnx2_report_link(struct bnx2 *bp)
  842. {
  843. if (bp->link_up) {
  844. netif_carrier_on(bp->dev);
  845. netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
  846. bnx2_xceiver_str(bp),
  847. bp->line_speed,
  848. bp->duplex == DUPLEX_FULL ? "full" : "half");
  849. if (bp->flow_ctrl) {
  850. if (bp->flow_ctrl & FLOW_CTRL_RX) {
  851. pr_cont(", receive ");
  852. if (bp->flow_ctrl & FLOW_CTRL_TX)
  853. pr_cont("& transmit ");
  854. }
  855. else {
  856. pr_cont(", transmit ");
  857. }
  858. pr_cont("flow control ON");
  859. }
  860. pr_cont("\n");
  861. } else {
  862. netif_carrier_off(bp->dev);
  863. netdev_err(bp->dev, "NIC %s Link is Down\n",
  864. bnx2_xceiver_str(bp));
  865. }
  866. bnx2_report_fw_link(bp);
  867. }
  868. static void
  869. bnx2_resolve_flow_ctrl(struct bnx2 *bp)
  870. {
  871. u32 local_adv, remote_adv;
  872. bp->flow_ctrl = 0;
  873. if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
  874. (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
  875. if (bp->duplex == DUPLEX_FULL) {
  876. bp->flow_ctrl = bp->req_flow_ctrl;
  877. }
  878. return;
  879. }
  880. if (bp->duplex != DUPLEX_FULL) {
  881. return;
  882. }
  883. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  884. (CHIP_NUM(bp) == CHIP_NUM_5708)) {
  885. u32 val;
  886. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  887. if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
  888. bp->flow_ctrl |= FLOW_CTRL_TX;
  889. if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
  890. bp->flow_ctrl |= FLOW_CTRL_RX;
  891. return;
  892. }
  893. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  894. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  895. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  896. u32 new_local_adv = 0;
  897. u32 new_remote_adv = 0;
  898. if (local_adv & ADVERTISE_1000XPAUSE)
  899. new_local_adv |= ADVERTISE_PAUSE_CAP;
  900. if (local_adv & ADVERTISE_1000XPSE_ASYM)
  901. new_local_adv |= ADVERTISE_PAUSE_ASYM;
  902. if (remote_adv & ADVERTISE_1000XPAUSE)
  903. new_remote_adv |= ADVERTISE_PAUSE_CAP;
  904. if (remote_adv & ADVERTISE_1000XPSE_ASYM)
  905. new_remote_adv |= ADVERTISE_PAUSE_ASYM;
  906. local_adv = new_local_adv;
  907. remote_adv = new_remote_adv;
  908. }
  909. /* See Table 28B-3 of 802.3ab-1999 spec. */
  910. if (local_adv & ADVERTISE_PAUSE_CAP) {
  911. if(local_adv & ADVERTISE_PAUSE_ASYM) {
  912. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  913. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  914. }
  915. else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
  916. bp->flow_ctrl = FLOW_CTRL_RX;
  917. }
  918. }
  919. else {
  920. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  921. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  922. }
  923. }
  924. }
  925. else if (local_adv & ADVERTISE_PAUSE_ASYM) {
  926. if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
  927. (remote_adv & ADVERTISE_PAUSE_ASYM)) {
  928. bp->flow_ctrl = FLOW_CTRL_TX;
  929. }
  930. }
  931. }
  932. static int
  933. bnx2_5709s_linkup(struct bnx2 *bp)
  934. {
  935. u32 val, speed;
  936. bp->link_up = 1;
  937. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
  938. bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
  939. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  940. if ((bp->autoneg & AUTONEG_SPEED) == 0) {
  941. bp->line_speed = bp->req_line_speed;
  942. bp->duplex = bp->req_duplex;
  943. return 0;
  944. }
  945. speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
  946. switch (speed) {
  947. case MII_BNX2_GP_TOP_AN_SPEED_10:
  948. bp->line_speed = SPEED_10;
  949. break;
  950. case MII_BNX2_GP_TOP_AN_SPEED_100:
  951. bp->line_speed = SPEED_100;
  952. break;
  953. case MII_BNX2_GP_TOP_AN_SPEED_1G:
  954. case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
  955. bp->line_speed = SPEED_1000;
  956. break;
  957. case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
  958. bp->line_speed = SPEED_2500;
  959. break;
  960. }
  961. if (val & MII_BNX2_GP_TOP_AN_FD)
  962. bp->duplex = DUPLEX_FULL;
  963. else
  964. bp->duplex = DUPLEX_HALF;
  965. return 0;
  966. }
  967. static int
  968. bnx2_5708s_linkup(struct bnx2 *bp)
  969. {
  970. u32 val;
  971. bp->link_up = 1;
  972. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  973. switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
  974. case BCM5708S_1000X_STAT1_SPEED_10:
  975. bp->line_speed = SPEED_10;
  976. break;
  977. case BCM5708S_1000X_STAT1_SPEED_100:
  978. bp->line_speed = SPEED_100;
  979. break;
  980. case BCM5708S_1000X_STAT1_SPEED_1G:
  981. bp->line_speed = SPEED_1000;
  982. break;
  983. case BCM5708S_1000X_STAT1_SPEED_2G5:
  984. bp->line_speed = SPEED_2500;
  985. break;
  986. }
  987. if (val & BCM5708S_1000X_STAT1_FD)
  988. bp->duplex = DUPLEX_FULL;
  989. else
  990. bp->duplex = DUPLEX_HALF;
  991. return 0;
  992. }
  993. static int
  994. bnx2_5706s_linkup(struct bnx2 *bp)
  995. {
  996. u32 bmcr, local_adv, remote_adv, common;
  997. bp->link_up = 1;
  998. bp->line_speed = SPEED_1000;
  999. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1000. if (bmcr & BMCR_FULLDPLX) {
  1001. bp->duplex = DUPLEX_FULL;
  1002. }
  1003. else {
  1004. bp->duplex = DUPLEX_HALF;
  1005. }
  1006. if (!(bmcr & BMCR_ANENABLE)) {
  1007. return 0;
  1008. }
  1009. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  1010. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  1011. common = local_adv & remote_adv;
  1012. if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
  1013. if (common & ADVERTISE_1000XFULL) {
  1014. bp->duplex = DUPLEX_FULL;
  1015. }
  1016. else {
  1017. bp->duplex = DUPLEX_HALF;
  1018. }
  1019. }
  1020. return 0;
  1021. }
  1022. static int
  1023. bnx2_copper_linkup(struct bnx2 *bp)
  1024. {
  1025. u32 bmcr;
  1026. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1027. if (bmcr & BMCR_ANENABLE) {
  1028. u32 local_adv, remote_adv, common;
  1029. bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
  1030. bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
  1031. common = local_adv & (remote_adv >> 2);
  1032. if (common & ADVERTISE_1000FULL) {
  1033. bp->line_speed = SPEED_1000;
  1034. bp->duplex = DUPLEX_FULL;
  1035. }
  1036. else if (common & ADVERTISE_1000HALF) {
  1037. bp->line_speed = SPEED_1000;
  1038. bp->duplex = DUPLEX_HALF;
  1039. }
  1040. else {
  1041. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  1042. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  1043. common = local_adv & remote_adv;
  1044. if (common & ADVERTISE_100FULL) {
  1045. bp->line_speed = SPEED_100;
  1046. bp->duplex = DUPLEX_FULL;
  1047. }
  1048. else if (common & ADVERTISE_100HALF) {
  1049. bp->line_speed = SPEED_100;
  1050. bp->duplex = DUPLEX_HALF;
  1051. }
  1052. else if (common & ADVERTISE_10FULL) {
  1053. bp->line_speed = SPEED_10;
  1054. bp->duplex = DUPLEX_FULL;
  1055. }
  1056. else if (common & ADVERTISE_10HALF) {
  1057. bp->line_speed = SPEED_10;
  1058. bp->duplex = DUPLEX_HALF;
  1059. }
  1060. else {
  1061. bp->line_speed = 0;
  1062. bp->link_up = 0;
  1063. }
  1064. }
  1065. }
  1066. else {
  1067. if (bmcr & BMCR_SPEED100) {
  1068. bp->line_speed = SPEED_100;
  1069. }
  1070. else {
  1071. bp->line_speed = SPEED_10;
  1072. }
  1073. if (bmcr & BMCR_FULLDPLX) {
  1074. bp->duplex = DUPLEX_FULL;
  1075. }
  1076. else {
  1077. bp->duplex = DUPLEX_HALF;
  1078. }
  1079. }
  1080. return 0;
  1081. }
  1082. static void
  1083. bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
  1084. {
  1085. u32 val, rx_cid_addr = GET_CID_ADDR(cid);
  1086. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
  1087. val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
  1088. val |= 0x02 << 8;
  1089. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  1090. u32 lo_water, hi_water;
  1091. if (bp->flow_ctrl & FLOW_CTRL_TX)
  1092. lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
  1093. else
  1094. lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
  1095. if (lo_water >= bp->rx_ring_size)
  1096. lo_water = 0;
  1097. hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
  1098. if (hi_water <= lo_water)
  1099. lo_water = 0;
  1100. hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
  1101. lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
  1102. if (hi_water > 0xf)
  1103. hi_water = 0xf;
  1104. else if (hi_water == 0)
  1105. lo_water = 0;
  1106. val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
  1107. }
  1108. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  1109. }
  1110. static void
  1111. bnx2_init_all_rx_contexts(struct bnx2 *bp)
  1112. {
  1113. int i;
  1114. u32 cid;
  1115. for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
  1116. if (i == 1)
  1117. cid = RX_RSS_CID;
  1118. bnx2_init_rx_context(bp, cid);
  1119. }
  1120. }
  1121. static void
  1122. bnx2_set_mac_link(struct bnx2 *bp)
  1123. {
  1124. u32 val;
  1125. REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
  1126. if (bp->link_up && (bp->line_speed == SPEED_1000) &&
  1127. (bp->duplex == DUPLEX_HALF)) {
  1128. REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
  1129. }
  1130. /* Configure the EMAC mode register. */
  1131. val = REG_RD(bp, BNX2_EMAC_MODE);
  1132. val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  1133. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  1134. BNX2_EMAC_MODE_25G_MODE);
  1135. if (bp->link_up) {
  1136. switch (bp->line_speed) {
  1137. case SPEED_10:
  1138. if (CHIP_NUM(bp) != CHIP_NUM_5706) {
  1139. val |= BNX2_EMAC_MODE_PORT_MII_10M;
  1140. break;
  1141. }
  1142. /* fall through */
  1143. case SPEED_100:
  1144. val |= BNX2_EMAC_MODE_PORT_MII;
  1145. break;
  1146. case SPEED_2500:
  1147. val |= BNX2_EMAC_MODE_25G_MODE;
  1148. /* fall through */
  1149. case SPEED_1000:
  1150. val |= BNX2_EMAC_MODE_PORT_GMII;
  1151. break;
  1152. }
  1153. }
  1154. else {
  1155. val |= BNX2_EMAC_MODE_PORT_GMII;
  1156. }
  1157. /* Set the MAC to operate in the appropriate duplex mode. */
  1158. if (bp->duplex == DUPLEX_HALF)
  1159. val |= BNX2_EMAC_MODE_HALF_DUPLEX;
  1160. REG_WR(bp, BNX2_EMAC_MODE, val);
  1161. /* Enable/disable rx PAUSE. */
  1162. bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
  1163. if (bp->flow_ctrl & FLOW_CTRL_RX)
  1164. bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
  1165. REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
  1166. /* Enable/disable tx PAUSE. */
  1167. val = REG_RD(bp, BNX2_EMAC_TX_MODE);
  1168. val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
  1169. if (bp->flow_ctrl & FLOW_CTRL_TX)
  1170. val |= BNX2_EMAC_TX_MODE_FLOW_EN;
  1171. REG_WR(bp, BNX2_EMAC_TX_MODE, val);
  1172. /* Acknowledge the interrupt. */
  1173. REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
  1174. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1175. bnx2_init_all_rx_contexts(bp);
  1176. }
  1177. static void
  1178. bnx2_enable_bmsr1(struct bnx2 *bp)
  1179. {
  1180. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1181. (CHIP_NUM(bp) == CHIP_NUM_5709))
  1182. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1183. MII_BNX2_BLK_ADDR_GP_STATUS);
  1184. }
  1185. static void
  1186. bnx2_disable_bmsr1(struct bnx2 *bp)
  1187. {
  1188. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1189. (CHIP_NUM(bp) == CHIP_NUM_5709))
  1190. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1191. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1192. }
  1193. static int
  1194. bnx2_test_and_enable_2g5(struct bnx2 *bp)
  1195. {
  1196. u32 up1;
  1197. int ret = 1;
  1198. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1199. return 0;
  1200. if (bp->autoneg & AUTONEG_SPEED)
  1201. bp->advertising |= ADVERTISED_2500baseX_Full;
  1202. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1203. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1204. bnx2_read_phy(bp, bp->mii_up1, &up1);
  1205. if (!(up1 & BCM5708S_UP1_2G5)) {
  1206. up1 |= BCM5708S_UP1_2G5;
  1207. bnx2_write_phy(bp, bp->mii_up1, up1);
  1208. ret = 0;
  1209. }
  1210. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1211. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1212. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1213. return ret;
  1214. }
  1215. static int
  1216. bnx2_test_and_disable_2g5(struct bnx2 *bp)
  1217. {
  1218. u32 up1;
  1219. int ret = 0;
  1220. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1221. return 0;
  1222. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1223. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1224. bnx2_read_phy(bp, bp->mii_up1, &up1);
  1225. if (up1 & BCM5708S_UP1_2G5) {
  1226. up1 &= ~BCM5708S_UP1_2G5;
  1227. bnx2_write_phy(bp, bp->mii_up1, up1);
  1228. ret = 1;
  1229. }
  1230. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1231. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1232. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1233. return ret;
  1234. }
  1235. static void
  1236. bnx2_enable_forced_2g5(struct bnx2 *bp)
  1237. {
  1238. u32 uninitialized_var(bmcr);
  1239. int err;
  1240. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1241. return;
  1242. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  1243. u32 val;
  1244. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1245. MII_BNX2_BLK_ADDR_SERDES_DIG);
  1246. if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
  1247. val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
  1248. val |= MII_BNX2_SD_MISC1_FORCE |
  1249. MII_BNX2_SD_MISC1_FORCE_2_5G;
  1250. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
  1251. }
  1252. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1253. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1254. err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1255. } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  1256. err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1257. if (!err)
  1258. bmcr |= BCM5708S_BMCR_FORCE_2500;
  1259. } else {
  1260. return;
  1261. }
  1262. if (err)
  1263. return;
  1264. if (bp->autoneg & AUTONEG_SPEED) {
  1265. bmcr &= ~BMCR_ANENABLE;
  1266. if (bp->req_duplex == DUPLEX_FULL)
  1267. bmcr |= BMCR_FULLDPLX;
  1268. }
  1269. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1270. }
  1271. static void
  1272. bnx2_disable_forced_2g5(struct bnx2 *bp)
  1273. {
  1274. u32 uninitialized_var(bmcr);
  1275. int err;
  1276. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1277. return;
  1278. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  1279. u32 val;
  1280. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1281. MII_BNX2_BLK_ADDR_SERDES_DIG);
  1282. if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
  1283. val &= ~MII_BNX2_SD_MISC1_FORCE;
  1284. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
  1285. }
  1286. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1287. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1288. err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1289. } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  1290. err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1291. if (!err)
  1292. bmcr &= ~BCM5708S_BMCR_FORCE_2500;
  1293. } else {
  1294. return;
  1295. }
  1296. if (err)
  1297. return;
  1298. if (bp->autoneg & AUTONEG_SPEED)
  1299. bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
  1300. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1301. }
  1302. static void
  1303. bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
  1304. {
  1305. u32 val;
  1306. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
  1307. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
  1308. if (start)
  1309. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
  1310. else
  1311. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
  1312. }
  1313. static int
  1314. bnx2_set_link(struct bnx2 *bp)
  1315. {
  1316. u32 bmsr;
  1317. u8 link_up;
  1318. if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
  1319. bp->link_up = 1;
  1320. return 0;
  1321. }
  1322. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  1323. return 0;
  1324. link_up = bp->link_up;
  1325. bnx2_enable_bmsr1(bp);
  1326. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  1327. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  1328. bnx2_disable_bmsr1(bp);
  1329. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1330. (CHIP_NUM(bp) == CHIP_NUM_5706)) {
  1331. u32 val, an_dbg;
  1332. if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
  1333. bnx2_5706s_force_link_dn(bp, 0);
  1334. bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
  1335. }
  1336. val = REG_RD(bp, BNX2_EMAC_STATUS);
  1337. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  1338. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  1339. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  1340. if ((val & BNX2_EMAC_STATUS_LINK) &&
  1341. !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
  1342. bmsr |= BMSR_LSTATUS;
  1343. else
  1344. bmsr &= ~BMSR_LSTATUS;
  1345. }
  1346. if (bmsr & BMSR_LSTATUS) {
  1347. bp->link_up = 1;
  1348. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1349. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  1350. bnx2_5706s_linkup(bp);
  1351. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  1352. bnx2_5708s_linkup(bp);
  1353. else if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1354. bnx2_5709s_linkup(bp);
  1355. }
  1356. else {
  1357. bnx2_copper_linkup(bp);
  1358. }
  1359. bnx2_resolve_flow_ctrl(bp);
  1360. }
  1361. else {
  1362. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1363. (bp->autoneg & AUTONEG_SPEED))
  1364. bnx2_disable_forced_2g5(bp);
  1365. if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
  1366. u32 bmcr;
  1367. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1368. bmcr |= BMCR_ANENABLE;
  1369. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1370. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  1371. }
  1372. bp->link_up = 0;
  1373. }
  1374. if (bp->link_up != link_up) {
  1375. bnx2_report_link(bp);
  1376. }
  1377. bnx2_set_mac_link(bp);
  1378. return 0;
  1379. }
  1380. static int
  1381. bnx2_reset_phy(struct bnx2 *bp)
  1382. {
  1383. int i;
  1384. u32 reg;
  1385. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
  1386. #define PHY_RESET_MAX_WAIT 100
  1387. for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
  1388. udelay(10);
  1389. bnx2_read_phy(bp, bp->mii_bmcr, &reg);
  1390. if (!(reg & BMCR_RESET)) {
  1391. udelay(20);
  1392. break;
  1393. }
  1394. }
  1395. if (i == PHY_RESET_MAX_WAIT) {
  1396. return -EBUSY;
  1397. }
  1398. return 0;
  1399. }
  1400. static u32
  1401. bnx2_phy_get_pause_adv(struct bnx2 *bp)
  1402. {
  1403. u32 adv = 0;
  1404. if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
  1405. (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
  1406. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1407. adv = ADVERTISE_1000XPAUSE;
  1408. }
  1409. else {
  1410. adv = ADVERTISE_PAUSE_CAP;
  1411. }
  1412. }
  1413. else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
  1414. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1415. adv = ADVERTISE_1000XPSE_ASYM;
  1416. }
  1417. else {
  1418. adv = ADVERTISE_PAUSE_ASYM;
  1419. }
  1420. }
  1421. else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
  1422. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1423. adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1424. }
  1425. else {
  1426. adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1427. }
  1428. }
  1429. return adv;
  1430. }
  1431. static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
  1432. static int
  1433. bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
  1434. __releases(&bp->phy_lock)
  1435. __acquires(&bp->phy_lock)
  1436. {
  1437. u32 speed_arg = 0, pause_adv;
  1438. pause_adv = bnx2_phy_get_pause_adv(bp);
  1439. if (bp->autoneg & AUTONEG_SPEED) {
  1440. speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
  1441. if (bp->advertising & ADVERTISED_10baseT_Half)
  1442. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
  1443. if (bp->advertising & ADVERTISED_10baseT_Full)
  1444. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
  1445. if (bp->advertising & ADVERTISED_100baseT_Half)
  1446. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
  1447. if (bp->advertising & ADVERTISED_100baseT_Full)
  1448. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
  1449. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1450. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
  1451. if (bp->advertising & ADVERTISED_2500baseX_Full)
  1452. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
  1453. } else {
  1454. if (bp->req_line_speed == SPEED_2500)
  1455. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
  1456. else if (bp->req_line_speed == SPEED_1000)
  1457. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
  1458. else if (bp->req_line_speed == SPEED_100) {
  1459. if (bp->req_duplex == DUPLEX_FULL)
  1460. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
  1461. else
  1462. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
  1463. } else if (bp->req_line_speed == SPEED_10) {
  1464. if (bp->req_duplex == DUPLEX_FULL)
  1465. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
  1466. else
  1467. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
  1468. }
  1469. }
  1470. if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
  1471. speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
  1472. if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
  1473. speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
  1474. if (port == PORT_TP)
  1475. speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
  1476. BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
  1477. bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
  1478. spin_unlock_bh(&bp->phy_lock);
  1479. bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
  1480. spin_lock_bh(&bp->phy_lock);
  1481. return 0;
  1482. }
  1483. static int
  1484. bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
  1485. __releases(&bp->phy_lock)
  1486. __acquires(&bp->phy_lock)
  1487. {
  1488. u32 adv, bmcr;
  1489. u32 new_adv = 0;
  1490. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  1491. return (bnx2_setup_remote_phy(bp, port));
  1492. if (!(bp->autoneg & AUTONEG_SPEED)) {
  1493. u32 new_bmcr;
  1494. int force_link_down = 0;
  1495. if (bp->req_line_speed == SPEED_2500) {
  1496. if (!bnx2_test_and_enable_2g5(bp))
  1497. force_link_down = 1;
  1498. } else if (bp->req_line_speed == SPEED_1000) {
  1499. if (bnx2_test_and_disable_2g5(bp))
  1500. force_link_down = 1;
  1501. }
  1502. bnx2_read_phy(bp, bp->mii_adv, &adv);
  1503. adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
  1504. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1505. new_bmcr = bmcr & ~BMCR_ANENABLE;
  1506. new_bmcr |= BMCR_SPEED1000;
  1507. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  1508. if (bp->req_line_speed == SPEED_2500)
  1509. bnx2_enable_forced_2g5(bp);
  1510. else if (bp->req_line_speed == SPEED_1000) {
  1511. bnx2_disable_forced_2g5(bp);
  1512. new_bmcr &= ~0x2000;
  1513. }
  1514. } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  1515. if (bp->req_line_speed == SPEED_2500)
  1516. new_bmcr |= BCM5708S_BMCR_FORCE_2500;
  1517. else
  1518. new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
  1519. }
  1520. if (bp->req_duplex == DUPLEX_FULL) {
  1521. adv |= ADVERTISE_1000XFULL;
  1522. new_bmcr |= BMCR_FULLDPLX;
  1523. }
  1524. else {
  1525. adv |= ADVERTISE_1000XHALF;
  1526. new_bmcr &= ~BMCR_FULLDPLX;
  1527. }
  1528. if ((new_bmcr != bmcr) || (force_link_down)) {
  1529. /* Force a link down visible on the other side */
  1530. if (bp->link_up) {
  1531. bnx2_write_phy(bp, bp->mii_adv, adv &
  1532. ~(ADVERTISE_1000XFULL |
  1533. ADVERTISE_1000XHALF));
  1534. bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
  1535. BMCR_ANRESTART | BMCR_ANENABLE);
  1536. bp->link_up = 0;
  1537. netif_carrier_off(bp->dev);
  1538. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1539. bnx2_report_link(bp);
  1540. }
  1541. bnx2_write_phy(bp, bp->mii_adv, adv);
  1542. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1543. } else {
  1544. bnx2_resolve_flow_ctrl(bp);
  1545. bnx2_set_mac_link(bp);
  1546. }
  1547. return 0;
  1548. }
  1549. bnx2_test_and_enable_2g5(bp);
  1550. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1551. new_adv |= ADVERTISE_1000XFULL;
  1552. new_adv |= bnx2_phy_get_pause_adv(bp);
  1553. bnx2_read_phy(bp, bp->mii_adv, &adv);
  1554. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1555. bp->serdes_an_pending = 0;
  1556. if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
  1557. /* Force a link down visible on the other side */
  1558. if (bp->link_up) {
  1559. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  1560. spin_unlock_bh(&bp->phy_lock);
  1561. msleep(20);
  1562. spin_lock_bh(&bp->phy_lock);
  1563. }
  1564. bnx2_write_phy(bp, bp->mii_adv, new_adv);
  1565. bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
  1566. BMCR_ANENABLE);
  1567. /* Speed up link-up time when the link partner
  1568. * does not autonegotiate which is very common
  1569. * in blade servers. Some blade servers use
  1570. * IPMI for kerboard input and it's important
  1571. * to minimize link disruptions. Autoneg. involves
  1572. * exchanging base pages plus 3 next pages and
  1573. * normally completes in about 120 msec.
  1574. */
  1575. bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
  1576. bp->serdes_an_pending = 1;
  1577. mod_timer(&bp->timer, jiffies + bp->current_interval);
  1578. } else {
  1579. bnx2_resolve_flow_ctrl(bp);
  1580. bnx2_set_mac_link(bp);
  1581. }
  1582. return 0;
  1583. }
  1584. #define ETHTOOL_ALL_FIBRE_SPEED \
  1585. (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
  1586. (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
  1587. (ADVERTISED_1000baseT_Full)
  1588. #define ETHTOOL_ALL_COPPER_SPEED \
  1589. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
  1590. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
  1591. ADVERTISED_1000baseT_Full)
  1592. #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
  1593. ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
  1594. #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
  1595. static void
  1596. bnx2_set_default_remote_link(struct bnx2 *bp)
  1597. {
  1598. u32 link;
  1599. if (bp->phy_port == PORT_TP)
  1600. link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
  1601. else
  1602. link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
  1603. if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
  1604. bp->req_line_speed = 0;
  1605. bp->autoneg |= AUTONEG_SPEED;
  1606. bp->advertising = ADVERTISED_Autoneg;
  1607. if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
  1608. bp->advertising |= ADVERTISED_10baseT_Half;
  1609. if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
  1610. bp->advertising |= ADVERTISED_10baseT_Full;
  1611. if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
  1612. bp->advertising |= ADVERTISED_100baseT_Half;
  1613. if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
  1614. bp->advertising |= ADVERTISED_100baseT_Full;
  1615. if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
  1616. bp->advertising |= ADVERTISED_1000baseT_Full;
  1617. if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
  1618. bp->advertising |= ADVERTISED_2500baseX_Full;
  1619. } else {
  1620. bp->autoneg = 0;
  1621. bp->advertising = 0;
  1622. bp->req_duplex = DUPLEX_FULL;
  1623. if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
  1624. bp->req_line_speed = SPEED_10;
  1625. if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
  1626. bp->req_duplex = DUPLEX_HALF;
  1627. }
  1628. if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
  1629. bp->req_line_speed = SPEED_100;
  1630. if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
  1631. bp->req_duplex = DUPLEX_HALF;
  1632. }
  1633. if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
  1634. bp->req_line_speed = SPEED_1000;
  1635. if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
  1636. bp->req_line_speed = SPEED_2500;
  1637. }
  1638. }
  1639. static void
  1640. bnx2_set_default_link(struct bnx2 *bp)
  1641. {
  1642. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  1643. bnx2_set_default_remote_link(bp);
  1644. return;
  1645. }
  1646. bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
  1647. bp->req_line_speed = 0;
  1648. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1649. u32 reg;
  1650. bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
  1651. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
  1652. reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
  1653. if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
  1654. bp->autoneg = 0;
  1655. bp->req_line_speed = bp->line_speed = SPEED_1000;
  1656. bp->req_duplex = DUPLEX_FULL;
  1657. }
  1658. } else
  1659. bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
  1660. }
  1661. static void
  1662. bnx2_send_heart_beat(struct bnx2 *bp)
  1663. {
  1664. u32 msg;
  1665. u32 addr;
  1666. spin_lock(&bp->indirect_lock);
  1667. msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
  1668. addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
  1669. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
  1670. REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
  1671. spin_unlock(&bp->indirect_lock);
  1672. }
  1673. static void
  1674. bnx2_remote_phy_event(struct bnx2 *bp)
  1675. {
  1676. u32 msg;
  1677. u8 link_up = bp->link_up;
  1678. u8 old_port;
  1679. msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
  1680. if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
  1681. bnx2_send_heart_beat(bp);
  1682. msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
  1683. if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
  1684. bp->link_up = 0;
  1685. else {
  1686. u32 speed;
  1687. bp->link_up = 1;
  1688. speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
  1689. bp->duplex = DUPLEX_FULL;
  1690. switch (speed) {
  1691. case BNX2_LINK_STATUS_10HALF:
  1692. bp->duplex = DUPLEX_HALF;
  1693. case BNX2_LINK_STATUS_10FULL:
  1694. bp->line_speed = SPEED_10;
  1695. break;
  1696. case BNX2_LINK_STATUS_100HALF:
  1697. bp->duplex = DUPLEX_HALF;
  1698. case BNX2_LINK_STATUS_100BASE_T4:
  1699. case BNX2_LINK_STATUS_100FULL:
  1700. bp->line_speed = SPEED_100;
  1701. break;
  1702. case BNX2_LINK_STATUS_1000HALF:
  1703. bp->duplex = DUPLEX_HALF;
  1704. case BNX2_LINK_STATUS_1000FULL:
  1705. bp->line_speed = SPEED_1000;
  1706. break;
  1707. case BNX2_LINK_STATUS_2500HALF:
  1708. bp->duplex = DUPLEX_HALF;
  1709. case BNX2_LINK_STATUS_2500FULL:
  1710. bp->line_speed = SPEED_2500;
  1711. break;
  1712. default:
  1713. bp->line_speed = 0;
  1714. break;
  1715. }
  1716. bp->flow_ctrl = 0;
  1717. if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
  1718. (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
  1719. if (bp->duplex == DUPLEX_FULL)
  1720. bp->flow_ctrl = bp->req_flow_ctrl;
  1721. } else {
  1722. if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
  1723. bp->flow_ctrl |= FLOW_CTRL_TX;
  1724. if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
  1725. bp->flow_ctrl |= FLOW_CTRL_RX;
  1726. }
  1727. old_port = bp->phy_port;
  1728. if (msg & BNX2_LINK_STATUS_SERDES_LINK)
  1729. bp->phy_port = PORT_FIBRE;
  1730. else
  1731. bp->phy_port = PORT_TP;
  1732. if (old_port != bp->phy_port)
  1733. bnx2_set_default_link(bp);
  1734. }
  1735. if (bp->link_up != link_up)
  1736. bnx2_report_link(bp);
  1737. bnx2_set_mac_link(bp);
  1738. }
  1739. static int
  1740. bnx2_set_remote_link(struct bnx2 *bp)
  1741. {
  1742. u32 evt_code;
  1743. evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
  1744. switch (evt_code) {
  1745. case BNX2_FW_EVT_CODE_LINK_EVENT:
  1746. bnx2_remote_phy_event(bp);
  1747. break;
  1748. case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
  1749. default:
  1750. bnx2_send_heart_beat(bp);
  1751. break;
  1752. }
  1753. return 0;
  1754. }
  1755. static int
  1756. bnx2_setup_copper_phy(struct bnx2 *bp)
  1757. __releases(&bp->phy_lock)
  1758. __acquires(&bp->phy_lock)
  1759. {
  1760. u32 bmcr;
  1761. u32 new_bmcr;
  1762. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1763. if (bp->autoneg & AUTONEG_SPEED) {
  1764. u32 adv_reg, adv1000_reg;
  1765. u32 new_adv_reg = 0;
  1766. u32 new_adv1000_reg = 0;
  1767. bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
  1768. adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
  1769. ADVERTISE_PAUSE_ASYM);
  1770. bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
  1771. adv1000_reg &= PHY_ALL_1000_SPEED;
  1772. if (bp->advertising & ADVERTISED_10baseT_Half)
  1773. new_adv_reg |= ADVERTISE_10HALF;
  1774. if (bp->advertising & ADVERTISED_10baseT_Full)
  1775. new_adv_reg |= ADVERTISE_10FULL;
  1776. if (bp->advertising & ADVERTISED_100baseT_Half)
  1777. new_adv_reg |= ADVERTISE_100HALF;
  1778. if (bp->advertising & ADVERTISED_100baseT_Full)
  1779. new_adv_reg |= ADVERTISE_100FULL;
  1780. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1781. new_adv1000_reg |= ADVERTISE_1000FULL;
  1782. new_adv_reg |= ADVERTISE_CSMA;
  1783. new_adv_reg |= bnx2_phy_get_pause_adv(bp);
  1784. if ((adv1000_reg != new_adv1000_reg) ||
  1785. (adv_reg != new_adv_reg) ||
  1786. ((bmcr & BMCR_ANENABLE) == 0)) {
  1787. bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
  1788. bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
  1789. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
  1790. BMCR_ANENABLE);
  1791. }
  1792. else if (bp->link_up) {
  1793. /* Flow ctrl may have changed from auto to forced */
  1794. /* or vice-versa. */
  1795. bnx2_resolve_flow_ctrl(bp);
  1796. bnx2_set_mac_link(bp);
  1797. }
  1798. return 0;
  1799. }
  1800. new_bmcr = 0;
  1801. if (bp->req_line_speed == SPEED_100) {
  1802. new_bmcr |= BMCR_SPEED100;
  1803. }
  1804. if (bp->req_duplex == DUPLEX_FULL) {
  1805. new_bmcr |= BMCR_FULLDPLX;
  1806. }
  1807. if (new_bmcr != bmcr) {
  1808. u32 bmsr;
  1809. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1810. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1811. if (bmsr & BMSR_LSTATUS) {
  1812. /* Force link down */
  1813. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  1814. spin_unlock_bh(&bp->phy_lock);
  1815. msleep(50);
  1816. spin_lock_bh(&bp->phy_lock);
  1817. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1818. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1819. }
  1820. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1821. /* Normally, the new speed is setup after the link has
  1822. * gone down and up again. In some cases, link will not go
  1823. * down so we need to set up the new speed here.
  1824. */
  1825. if (bmsr & BMSR_LSTATUS) {
  1826. bp->line_speed = bp->req_line_speed;
  1827. bp->duplex = bp->req_duplex;
  1828. bnx2_resolve_flow_ctrl(bp);
  1829. bnx2_set_mac_link(bp);
  1830. }
  1831. } else {
  1832. bnx2_resolve_flow_ctrl(bp);
  1833. bnx2_set_mac_link(bp);
  1834. }
  1835. return 0;
  1836. }
  1837. static int
  1838. bnx2_setup_phy(struct bnx2 *bp, u8 port)
  1839. __releases(&bp->phy_lock)
  1840. __acquires(&bp->phy_lock)
  1841. {
  1842. if (bp->loopback == MAC_LOOPBACK)
  1843. return 0;
  1844. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1845. return (bnx2_setup_serdes_phy(bp, port));
  1846. }
  1847. else {
  1848. return (bnx2_setup_copper_phy(bp));
  1849. }
  1850. }
  1851. static int
  1852. bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
  1853. {
  1854. u32 val;
  1855. bp->mii_bmcr = MII_BMCR + 0x10;
  1856. bp->mii_bmsr = MII_BMSR + 0x10;
  1857. bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
  1858. bp->mii_adv = MII_ADVERTISE + 0x10;
  1859. bp->mii_lpa = MII_LPA + 0x10;
  1860. bp->mii_up1 = MII_BNX2_OVER1G_UP1;
  1861. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
  1862. bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
  1863. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1864. if (reset_phy)
  1865. bnx2_reset_phy(bp);
  1866. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
  1867. bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
  1868. val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
  1869. val |= MII_BNX2_SD_1000XCTL1_FIBER;
  1870. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
  1871. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1872. bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
  1873. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
  1874. val |= BCM5708S_UP1_2G5;
  1875. else
  1876. val &= ~BCM5708S_UP1_2G5;
  1877. bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
  1878. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
  1879. bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
  1880. val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
  1881. bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
  1882. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
  1883. val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
  1884. MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
  1885. bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
  1886. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1887. return 0;
  1888. }
  1889. static int
  1890. bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
  1891. {
  1892. u32 val;
  1893. if (reset_phy)
  1894. bnx2_reset_phy(bp);
  1895. bp->mii_up1 = BCM5708S_UP1;
  1896. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
  1897. bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
  1898. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  1899. bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
  1900. val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
  1901. bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
  1902. bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
  1903. val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
  1904. bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
  1905. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
  1906. bnx2_read_phy(bp, BCM5708S_UP1, &val);
  1907. val |= BCM5708S_UP1_2G5;
  1908. bnx2_write_phy(bp, BCM5708S_UP1, val);
  1909. }
  1910. if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
  1911. (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
  1912. (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
  1913. /* increase tx signal amplitude */
  1914. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1915. BCM5708S_BLK_ADDR_TX_MISC);
  1916. bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
  1917. val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
  1918. bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
  1919. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  1920. }
  1921. val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
  1922. BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
  1923. if (val) {
  1924. u32 is_backplane;
  1925. is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
  1926. if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
  1927. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1928. BCM5708S_BLK_ADDR_TX_MISC);
  1929. bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
  1930. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1931. BCM5708S_BLK_ADDR_DIG);
  1932. }
  1933. }
  1934. return 0;
  1935. }
  1936. static int
  1937. bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
  1938. {
  1939. if (reset_phy)
  1940. bnx2_reset_phy(bp);
  1941. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  1942. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  1943. REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
  1944. if (bp->dev->mtu > 1500) {
  1945. u32 val;
  1946. /* Set extended packet length bit */
  1947. bnx2_write_phy(bp, 0x18, 0x7);
  1948. bnx2_read_phy(bp, 0x18, &val);
  1949. bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
  1950. bnx2_write_phy(bp, 0x1c, 0x6c00);
  1951. bnx2_read_phy(bp, 0x1c, &val);
  1952. bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
  1953. }
  1954. else {
  1955. u32 val;
  1956. bnx2_write_phy(bp, 0x18, 0x7);
  1957. bnx2_read_phy(bp, 0x18, &val);
  1958. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  1959. bnx2_write_phy(bp, 0x1c, 0x6c00);
  1960. bnx2_read_phy(bp, 0x1c, &val);
  1961. bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
  1962. }
  1963. return 0;
  1964. }
  1965. static int
  1966. bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
  1967. {
  1968. u32 val;
  1969. if (reset_phy)
  1970. bnx2_reset_phy(bp);
  1971. if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
  1972. bnx2_write_phy(bp, 0x18, 0x0c00);
  1973. bnx2_write_phy(bp, 0x17, 0x000a);
  1974. bnx2_write_phy(bp, 0x15, 0x310b);
  1975. bnx2_write_phy(bp, 0x17, 0x201f);
  1976. bnx2_write_phy(bp, 0x15, 0x9506);
  1977. bnx2_write_phy(bp, 0x17, 0x401f);
  1978. bnx2_write_phy(bp, 0x15, 0x14e2);
  1979. bnx2_write_phy(bp, 0x18, 0x0400);
  1980. }
  1981. if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
  1982. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
  1983. MII_BNX2_DSP_EXPAND_REG | 0x8);
  1984. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
  1985. val &= ~(1 << 8);
  1986. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
  1987. }
  1988. if (bp->dev->mtu > 1500) {
  1989. /* Set extended packet length bit */
  1990. bnx2_write_phy(bp, 0x18, 0x7);
  1991. bnx2_read_phy(bp, 0x18, &val);
  1992. bnx2_write_phy(bp, 0x18, val | 0x4000);
  1993. bnx2_read_phy(bp, 0x10, &val);
  1994. bnx2_write_phy(bp, 0x10, val | 0x1);
  1995. }
  1996. else {
  1997. bnx2_write_phy(bp, 0x18, 0x7);
  1998. bnx2_read_phy(bp, 0x18, &val);
  1999. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  2000. bnx2_read_phy(bp, 0x10, &val);
  2001. bnx2_write_phy(bp, 0x10, val & ~0x1);
  2002. }
  2003. /* ethernet@wirespeed */
  2004. bnx2_write_phy(bp, 0x18, 0x7007);
  2005. bnx2_read_phy(bp, 0x18, &val);
  2006. bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
  2007. return 0;
  2008. }
  2009. static int
  2010. bnx2_init_phy(struct bnx2 *bp, int reset_phy)
  2011. __releases(&bp->phy_lock)
  2012. __acquires(&bp->phy_lock)
  2013. {
  2014. u32 val;
  2015. int rc = 0;
  2016. bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
  2017. bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
  2018. bp->mii_bmcr = MII_BMCR;
  2019. bp->mii_bmsr = MII_BMSR;
  2020. bp->mii_bmsr1 = MII_BMSR;
  2021. bp->mii_adv = MII_ADVERTISE;
  2022. bp->mii_lpa = MII_LPA;
  2023. REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  2024. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  2025. goto setup_phy;
  2026. bnx2_read_phy(bp, MII_PHYSID1, &val);
  2027. bp->phy_id = val << 16;
  2028. bnx2_read_phy(bp, MII_PHYSID2, &val);
  2029. bp->phy_id |= val & 0xffff;
  2030. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  2031. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  2032. rc = bnx2_init_5706s_phy(bp, reset_phy);
  2033. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  2034. rc = bnx2_init_5708s_phy(bp, reset_phy);
  2035. else if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2036. rc = bnx2_init_5709s_phy(bp, reset_phy);
  2037. }
  2038. else {
  2039. rc = bnx2_init_copper_phy(bp, reset_phy);
  2040. }
  2041. setup_phy:
  2042. if (!rc)
  2043. rc = bnx2_setup_phy(bp, bp->phy_port);
  2044. return rc;
  2045. }
  2046. static int
  2047. bnx2_set_mac_loopback(struct bnx2 *bp)
  2048. {
  2049. u32 mac_mode;
  2050. mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
  2051. mac_mode &= ~BNX2_EMAC_MODE_PORT;
  2052. mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
  2053. REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
  2054. bp->link_up = 1;
  2055. return 0;
  2056. }
  2057. static int bnx2_test_link(struct bnx2 *);
  2058. static int
  2059. bnx2_set_phy_loopback(struct bnx2 *bp)
  2060. {
  2061. u32 mac_mode;
  2062. int rc, i;
  2063. spin_lock_bh(&bp->phy_lock);
  2064. rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
  2065. BMCR_SPEED1000);
  2066. spin_unlock_bh(&bp->phy_lock);
  2067. if (rc)
  2068. return rc;
  2069. for (i = 0; i < 10; i++) {
  2070. if (bnx2_test_link(bp) == 0)
  2071. break;
  2072. msleep(100);
  2073. }
  2074. mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
  2075. mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  2076. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  2077. BNX2_EMAC_MODE_25G_MODE);
  2078. mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
  2079. REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
  2080. bp->link_up = 1;
  2081. return 0;
  2082. }
  2083. static int
  2084. bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
  2085. {
  2086. int i;
  2087. u32 val;
  2088. bp->fw_wr_seq++;
  2089. msg_data |= bp->fw_wr_seq;
  2090. bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
  2091. if (!ack)
  2092. return 0;
  2093. /* wait for an acknowledgement. */
  2094. for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
  2095. msleep(10);
  2096. val = bnx2_shmem_rd(bp, BNX2_FW_MB);
  2097. if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
  2098. break;
  2099. }
  2100. if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
  2101. return 0;
  2102. /* If we timed out, inform the firmware that this is the case. */
  2103. if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
  2104. if (!silent)
  2105. pr_err("fw sync timeout, reset code = %x\n", msg_data);
  2106. msg_data &= ~BNX2_DRV_MSG_CODE;
  2107. msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
  2108. bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
  2109. return -EBUSY;
  2110. }
  2111. if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
  2112. return -EIO;
  2113. return 0;
  2114. }
  2115. static int
  2116. bnx2_init_5709_context(struct bnx2 *bp)
  2117. {
  2118. int i, ret = 0;
  2119. u32 val;
  2120. val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
  2121. val |= (BCM_PAGE_BITS - 8) << 16;
  2122. REG_WR(bp, BNX2_CTX_COMMAND, val);
  2123. for (i = 0; i < 10; i++) {
  2124. val = REG_RD(bp, BNX2_CTX_COMMAND);
  2125. if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
  2126. break;
  2127. udelay(2);
  2128. }
  2129. if (val & BNX2_CTX_COMMAND_MEM_INIT)
  2130. return -EBUSY;
  2131. for (i = 0; i < bp->ctx_pages; i++) {
  2132. int j;
  2133. if (bp->ctx_blk[i])
  2134. memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
  2135. else
  2136. return -ENOMEM;
  2137. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2138. (bp->ctx_blk_mapping[i] & 0xffffffff) |
  2139. BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
  2140. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2141. (u64) bp->ctx_blk_mapping[i] >> 32);
  2142. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
  2143. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2144. for (j = 0; j < 10; j++) {
  2145. val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2146. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2147. break;
  2148. udelay(5);
  2149. }
  2150. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2151. ret = -EBUSY;
  2152. break;
  2153. }
  2154. }
  2155. return ret;
  2156. }
  2157. static void
  2158. bnx2_init_context(struct bnx2 *bp)
  2159. {
  2160. u32 vcid;
  2161. vcid = 96;
  2162. while (vcid) {
  2163. u32 vcid_addr, pcid_addr, offset;
  2164. int i;
  2165. vcid--;
  2166. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  2167. u32 new_vcid;
  2168. vcid_addr = GET_PCID_ADDR(vcid);
  2169. if (vcid & 0x8) {
  2170. new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
  2171. }
  2172. else {
  2173. new_vcid = vcid;
  2174. }
  2175. pcid_addr = GET_PCID_ADDR(new_vcid);
  2176. }
  2177. else {
  2178. vcid_addr = GET_CID_ADDR(vcid);
  2179. pcid_addr = vcid_addr;
  2180. }
  2181. for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
  2182. vcid_addr += (i << PHY_CTX_SHIFT);
  2183. pcid_addr += (i << PHY_CTX_SHIFT);
  2184. REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
  2185. REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
  2186. /* Zero out the context. */
  2187. for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
  2188. bnx2_ctx_wr(bp, vcid_addr, offset, 0);
  2189. }
  2190. }
  2191. }
  2192. static int
  2193. bnx2_alloc_bad_rbuf(struct bnx2 *bp)
  2194. {
  2195. u16 *good_mbuf;
  2196. u32 good_mbuf_cnt;
  2197. u32 val;
  2198. good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
  2199. if (good_mbuf == NULL) {
  2200. pr_err("Failed to allocate memory in %s\n", __func__);
  2201. return -ENOMEM;
  2202. }
  2203. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  2204. BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
  2205. good_mbuf_cnt = 0;
  2206. /* Allocate a bunch of mbufs and save the good ones in an array. */
  2207. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
  2208. while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
  2209. bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
  2210. BNX2_RBUF_COMMAND_ALLOC_REQ);
  2211. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
  2212. val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
  2213. /* The addresses with Bit 9 set are bad memory blocks. */
  2214. if (!(val & (1 << 9))) {
  2215. good_mbuf[good_mbuf_cnt] = (u16) val;
  2216. good_mbuf_cnt++;
  2217. }
  2218. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
  2219. }
  2220. /* Free the good ones back to the mbuf pool thus discarding
  2221. * all the bad ones. */
  2222. while (good_mbuf_cnt) {
  2223. good_mbuf_cnt--;
  2224. val = good_mbuf[good_mbuf_cnt];
  2225. val = (val << 9) | val | 1;
  2226. bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
  2227. }
  2228. kfree(good_mbuf);
  2229. return 0;
  2230. }
  2231. static void
  2232. bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
  2233. {
  2234. u32 val;
  2235. val = (mac_addr[0] << 8) | mac_addr[1];
  2236. REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
  2237. val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
  2238. (mac_addr[4] << 8) | mac_addr[5];
  2239. REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
  2240. }
  2241. static inline int
  2242. bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
  2243. {
  2244. dma_addr_t mapping;
  2245. struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
  2246. struct rx_bd *rxbd =
  2247. &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
  2248. struct page *page = alloc_page(gfp);
  2249. if (!page)
  2250. return -ENOMEM;
  2251. mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
  2252. PCI_DMA_FROMDEVICE);
  2253. if (dma_mapping_error(&bp->pdev->dev, mapping)) {
  2254. __free_page(page);
  2255. return -EIO;
  2256. }
  2257. rx_pg->page = page;
  2258. dma_unmap_addr_set(rx_pg, mapping, mapping);
  2259. rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
  2260. rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  2261. return 0;
  2262. }
  2263. static void
  2264. bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
  2265. {
  2266. struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
  2267. struct page *page = rx_pg->page;
  2268. if (!page)
  2269. return;
  2270. dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
  2271. PAGE_SIZE, PCI_DMA_FROMDEVICE);
  2272. __free_page(page);
  2273. rx_pg->page = NULL;
  2274. }
  2275. static inline int
  2276. bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
  2277. {
  2278. struct sk_buff *skb;
  2279. struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
  2280. dma_addr_t mapping;
  2281. struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
  2282. unsigned long align;
  2283. skb = __netdev_alloc_skb(bp->dev, bp->rx_buf_size, gfp);
  2284. if (skb == NULL) {
  2285. return -ENOMEM;
  2286. }
  2287. if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
  2288. skb_reserve(skb, BNX2_RX_ALIGN - align);
  2289. mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_use_size,
  2290. PCI_DMA_FROMDEVICE);
  2291. if (dma_mapping_error(&bp->pdev->dev, mapping)) {
  2292. dev_kfree_skb(skb);
  2293. return -EIO;
  2294. }
  2295. rx_buf->skb = skb;
  2296. rx_buf->desc = (struct l2_fhdr *) skb->data;
  2297. dma_unmap_addr_set(rx_buf, mapping, mapping);
  2298. rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
  2299. rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  2300. rxr->rx_prod_bseq += bp->rx_buf_use_size;
  2301. return 0;
  2302. }
  2303. static int
  2304. bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
  2305. {
  2306. struct status_block *sblk = bnapi->status_blk.msi;
  2307. u32 new_link_state, old_link_state;
  2308. int is_set = 1;
  2309. new_link_state = sblk->status_attn_bits & event;
  2310. old_link_state = sblk->status_attn_bits_ack & event;
  2311. if (new_link_state != old_link_state) {
  2312. if (new_link_state)
  2313. REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
  2314. else
  2315. REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
  2316. } else
  2317. is_set = 0;
  2318. return is_set;
  2319. }
  2320. static void
  2321. bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
  2322. {
  2323. spin_lock(&bp->phy_lock);
  2324. if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
  2325. bnx2_set_link(bp);
  2326. if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
  2327. bnx2_set_remote_link(bp);
  2328. spin_unlock(&bp->phy_lock);
  2329. }
  2330. static inline u16
  2331. bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
  2332. {
  2333. u16 cons;
  2334. /* Tell compiler that status block fields can change. */
  2335. barrier();
  2336. cons = *bnapi->hw_tx_cons_ptr;
  2337. barrier();
  2338. if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
  2339. cons++;
  2340. return cons;
  2341. }
  2342. static int
  2343. bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
  2344. {
  2345. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2346. u16 hw_cons, sw_cons, sw_ring_cons;
  2347. int tx_pkt = 0, index;
  2348. struct netdev_queue *txq;
  2349. index = (bnapi - bp->bnx2_napi);
  2350. txq = netdev_get_tx_queue(bp->dev, index);
  2351. hw_cons = bnx2_get_hw_tx_cons(bnapi);
  2352. sw_cons = txr->tx_cons;
  2353. while (sw_cons != hw_cons) {
  2354. struct sw_tx_bd *tx_buf;
  2355. struct sk_buff *skb;
  2356. int i, last;
  2357. sw_ring_cons = TX_RING_IDX(sw_cons);
  2358. tx_buf = &txr->tx_buf_ring[sw_ring_cons];
  2359. skb = tx_buf->skb;
  2360. /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
  2361. prefetch(&skb->end);
  2362. /* partial BD completions possible with TSO packets */
  2363. if (tx_buf->is_gso) {
  2364. u16 last_idx, last_ring_idx;
  2365. last_idx = sw_cons + tx_buf->nr_frags + 1;
  2366. last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
  2367. if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
  2368. last_idx++;
  2369. }
  2370. if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
  2371. break;
  2372. }
  2373. }
  2374. dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
  2375. skb_headlen(skb), PCI_DMA_TODEVICE);
  2376. tx_buf->skb = NULL;
  2377. last = tx_buf->nr_frags;
  2378. for (i = 0; i < last; i++) {
  2379. sw_cons = NEXT_TX_BD(sw_cons);
  2380. dma_unmap_page(&bp->pdev->dev,
  2381. dma_unmap_addr(
  2382. &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
  2383. mapping),
  2384. skb_shinfo(skb)->frags[i].size,
  2385. PCI_DMA_TODEVICE);
  2386. }
  2387. sw_cons = NEXT_TX_BD(sw_cons);
  2388. dev_kfree_skb(skb);
  2389. tx_pkt++;
  2390. if (tx_pkt == budget)
  2391. break;
  2392. if (hw_cons == sw_cons)
  2393. hw_cons = bnx2_get_hw_tx_cons(bnapi);
  2394. }
  2395. txr->hw_tx_cons = hw_cons;
  2396. txr->tx_cons = sw_cons;
  2397. /* Need to make the tx_cons update visible to bnx2_start_xmit()
  2398. * before checking for netif_tx_queue_stopped(). Without the
  2399. * memory barrier, there is a small possibility that bnx2_start_xmit()
  2400. * will miss it and cause the queue to be stopped forever.
  2401. */
  2402. smp_mb();
  2403. if (unlikely(netif_tx_queue_stopped(txq)) &&
  2404. (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
  2405. __netif_tx_lock(txq, smp_processor_id());
  2406. if ((netif_tx_queue_stopped(txq)) &&
  2407. (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
  2408. netif_tx_wake_queue(txq);
  2409. __netif_tx_unlock(txq);
  2410. }
  2411. return tx_pkt;
  2412. }
  2413. static void
  2414. bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
  2415. struct sk_buff *skb, int count)
  2416. {
  2417. struct sw_pg *cons_rx_pg, *prod_rx_pg;
  2418. struct rx_bd *cons_bd, *prod_bd;
  2419. int i;
  2420. u16 hw_prod, prod;
  2421. u16 cons = rxr->rx_pg_cons;
  2422. cons_rx_pg = &rxr->rx_pg_ring[cons];
  2423. /* The caller was unable to allocate a new page to replace the
  2424. * last one in the frags array, so we need to recycle that page
  2425. * and then free the skb.
  2426. */
  2427. if (skb) {
  2428. struct page *page;
  2429. struct skb_shared_info *shinfo;
  2430. shinfo = skb_shinfo(skb);
  2431. shinfo->nr_frags--;
  2432. page = shinfo->frags[shinfo->nr_frags].page;
  2433. shinfo->frags[shinfo->nr_frags].page = NULL;
  2434. cons_rx_pg->page = page;
  2435. dev_kfree_skb(skb);
  2436. }
  2437. hw_prod = rxr->rx_pg_prod;
  2438. for (i = 0; i < count; i++) {
  2439. prod = RX_PG_RING_IDX(hw_prod);
  2440. prod_rx_pg = &rxr->rx_pg_ring[prod];
  2441. cons_rx_pg = &rxr->rx_pg_ring[cons];
  2442. cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
  2443. prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
  2444. if (prod != cons) {
  2445. prod_rx_pg->page = cons_rx_pg->page;
  2446. cons_rx_pg->page = NULL;
  2447. dma_unmap_addr_set(prod_rx_pg, mapping,
  2448. dma_unmap_addr(cons_rx_pg, mapping));
  2449. prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
  2450. prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
  2451. }
  2452. cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
  2453. hw_prod = NEXT_RX_BD(hw_prod);
  2454. }
  2455. rxr->rx_pg_prod = hw_prod;
  2456. rxr->rx_pg_cons = cons;
  2457. }
  2458. static inline void
  2459. bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
  2460. struct sk_buff *skb, u16 cons, u16 prod)
  2461. {
  2462. struct sw_bd *cons_rx_buf, *prod_rx_buf;
  2463. struct rx_bd *cons_bd, *prod_bd;
  2464. cons_rx_buf = &rxr->rx_buf_ring[cons];
  2465. prod_rx_buf = &rxr->rx_buf_ring[prod];
  2466. dma_sync_single_for_device(&bp->pdev->dev,
  2467. dma_unmap_addr(cons_rx_buf, mapping),
  2468. BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
  2469. rxr->rx_prod_bseq += bp->rx_buf_use_size;
  2470. prod_rx_buf->skb = skb;
  2471. prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
  2472. if (cons == prod)
  2473. return;
  2474. dma_unmap_addr_set(prod_rx_buf, mapping,
  2475. dma_unmap_addr(cons_rx_buf, mapping));
  2476. cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
  2477. prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
  2478. prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
  2479. prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
  2480. }
  2481. static int
  2482. bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
  2483. unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
  2484. u32 ring_idx)
  2485. {
  2486. int err;
  2487. u16 prod = ring_idx & 0xffff;
  2488. err = bnx2_alloc_rx_skb(bp, rxr, prod, GFP_ATOMIC);
  2489. if (unlikely(err)) {
  2490. bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
  2491. if (hdr_len) {
  2492. unsigned int raw_len = len + 4;
  2493. int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
  2494. bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
  2495. }
  2496. return err;
  2497. }
  2498. skb_reserve(skb, BNX2_RX_OFFSET);
  2499. dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
  2500. PCI_DMA_FROMDEVICE);
  2501. if (hdr_len == 0) {
  2502. skb_put(skb, len);
  2503. return 0;
  2504. } else {
  2505. unsigned int i, frag_len, frag_size, pages;
  2506. struct sw_pg *rx_pg;
  2507. u16 pg_cons = rxr->rx_pg_cons;
  2508. u16 pg_prod = rxr->rx_pg_prod;
  2509. frag_size = len + 4 - hdr_len;
  2510. pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
  2511. skb_put(skb, hdr_len);
  2512. for (i = 0; i < pages; i++) {
  2513. dma_addr_t mapping_old;
  2514. frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
  2515. if (unlikely(frag_len <= 4)) {
  2516. unsigned int tail = 4 - frag_len;
  2517. rxr->rx_pg_cons = pg_cons;
  2518. rxr->rx_pg_prod = pg_prod;
  2519. bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
  2520. pages - i);
  2521. skb->len -= tail;
  2522. if (i == 0) {
  2523. skb->tail -= tail;
  2524. } else {
  2525. skb_frag_t *frag =
  2526. &skb_shinfo(skb)->frags[i - 1];
  2527. frag->size -= tail;
  2528. skb->data_len -= tail;
  2529. skb->truesize -= tail;
  2530. }
  2531. return 0;
  2532. }
  2533. rx_pg = &rxr->rx_pg_ring[pg_cons];
  2534. /* Don't unmap yet. If we're unable to allocate a new
  2535. * page, we need to recycle the page and the DMA addr.
  2536. */
  2537. mapping_old = dma_unmap_addr(rx_pg, mapping);
  2538. if (i == pages - 1)
  2539. frag_len -= 4;
  2540. skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
  2541. rx_pg->page = NULL;
  2542. err = bnx2_alloc_rx_page(bp, rxr,
  2543. RX_PG_RING_IDX(pg_prod),
  2544. GFP_ATOMIC);
  2545. if (unlikely(err)) {
  2546. rxr->rx_pg_cons = pg_cons;
  2547. rxr->rx_pg_prod = pg_prod;
  2548. bnx2_reuse_rx_skb_pages(bp, rxr, skb,
  2549. pages - i);
  2550. return err;
  2551. }
  2552. dma_unmap_page(&bp->pdev->dev, mapping_old,
  2553. PAGE_SIZE, PCI_DMA_FROMDEVICE);
  2554. frag_size -= frag_len;
  2555. skb->data_len += frag_len;
  2556. skb->truesize += frag_len;
  2557. skb->len += frag_len;
  2558. pg_prod = NEXT_RX_BD(pg_prod);
  2559. pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
  2560. }
  2561. rxr->rx_pg_prod = pg_prod;
  2562. rxr->rx_pg_cons = pg_cons;
  2563. }
  2564. return 0;
  2565. }
  2566. static inline u16
  2567. bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
  2568. {
  2569. u16 cons;
  2570. /* Tell compiler that status block fields can change. */
  2571. barrier();
  2572. cons = *bnapi->hw_rx_cons_ptr;
  2573. barrier();
  2574. if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
  2575. cons++;
  2576. return cons;
  2577. }
  2578. static int
  2579. bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
  2580. {
  2581. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2582. u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
  2583. struct l2_fhdr *rx_hdr;
  2584. int rx_pkt = 0, pg_ring_used = 0;
  2585. hw_cons = bnx2_get_hw_rx_cons(bnapi);
  2586. sw_cons = rxr->rx_cons;
  2587. sw_prod = rxr->rx_prod;
  2588. /* Memory barrier necessary as speculative reads of the rx
  2589. * buffer can be ahead of the index in the status block
  2590. */
  2591. rmb();
  2592. while (sw_cons != hw_cons) {
  2593. unsigned int len, hdr_len;
  2594. u32 status;
  2595. struct sw_bd *rx_buf, *next_rx_buf;
  2596. struct sk_buff *skb;
  2597. dma_addr_t dma_addr;
  2598. u16 vtag = 0;
  2599. int hw_vlan __maybe_unused = 0;
  2600. sw_ring_cons = RX_RING_IDX(sw_cons);
  2601. sw_ring_prod = RX_RING_IDX(sw_prod);
  2602. rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
  2603. skb = rx_buf->skb;
  2604. prefetchw(skb);
  2605. next_rx_buf =
  2606. &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
  2607. prefetch(next_rx_buf->desc);
  2608. rx_buf->skb = NULL;
  2609. dma_addr = dma_unmap_addr(rx_buf, mapping);
  2610. dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
  2611. BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
  2612. PCI_DMA_FROMDEVICE);
  2613. rx_hdr = rx_buf->desc;
  2614. len = rx_hdr->l2_fhdr_pkt_len;
  2615. status = rx_hdr->l2_fhdr_status;
  2616. hdr_len = 0;
  2617. if (status & L2_FHDR_STATUS_SPLIT) {
  2618. hdr_len = rx_hdr->l2_fhdr_ip_xsum;
  2619. pg_ring_used = 1;
  2620. } else if (len > bp->rx_jumbo_thresh) {
  2621. hdr_len = bp->rx_jumbo_thresh;
  2622. pg_ring_used = 1;
  2623. }
  2624. if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
  2625. L2_FHDR_ERRORS_PHY_DECODE |
  2626. L2_FHDR_ERRORS_ALIGNMENT |
  2627. L2_FHDR_ERRORS_TOO_SHORT |
  2628. L2_FHDR_ERRORS_GIANT_FRAME))) {
  2629. bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
  2630. sw_ring_prod);
  2631. if (pg_ring_used) {
  2632. int pages;
  2633. pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
  2634. bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
  2635. }
  2636. goto next_rx;
  2637. }
  2638. len -= 4;
  2639. if (len <= bp->rx_copy_thresh) {
  2640. struct sk_buff *new_skb;
  2641. new_skb = netdev_alloc_skb(bp->dev, len + 6);
  2642. if (new_skb == NULL) {
  2643. bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
  2644. sw_ring_prod);
  2645. goto next_rx;
  2646. }
  2647. /* aligned copy */
  2648. skb_copy_from_linear_data_offset(skb,
  2649. BNX2_RX_OFFSET - 6,
  2650. new_skb->data, len + 6);
  2651. skb_reserve(new_skb, 6);
  2652. skb_put(new_skb, len);
  2653. bnx2_reuse_rx_skb(bp, rxr, skb,
  2654. sw_ring_cons, sw_ring_prod);
  2655. skb = new_skb;
  2656. } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
  2657. dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
  2658. goto next_rx;
  2659. if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
  2660. !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
  2661. vtag = rx_hdr->l2_fhdr_vlan_tag;
  2662. #ifdef BCM_VLAN
  2663. if (bp->vlgrp)
  2664. hw_vlan = 1;
  2665. else
  2666. #endif
  2667. {
  2668. struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
  2669. __skb_push(skb, 4);
  2670. memmove(ve, skb->data + 4, ETH_ALEN * 2);
  2671. ve->h_vlan_proto = htons(ETH_P_8021Q);
  2672. ve->h_vlan_TCI = htons(vtag);
  2673. len += 4;
  2674. }
  2675. }
  2676. skb->protocol = eth_type_trans(skb, bp->dev);
  2677. if ((len > (bp->dev->mtu + ETH_HLEN)) &&
  2678. (ntohs(skb->protocol) != 0x8100)) {
  2679. dev_kfree_skb(skb);
  2680. goto next_rx;
  2681. }
  2682. skb->ip_summed = CHECKSUM_NONE;
  2683. if (bp->rx_csum &&
  2684. (status & (L2_FHDR_STATUS_TCP_SEGMENT |
  2685. L2_FHDR_STATUS_UDP_DATAGRAM))) {
  2686. if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
  2687. L2_FHDR_ERRORS_UDP_XSUM)) == 0))
  2688. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2689. }
  2690. if ((bp->dev->features & NETIF_F_RXHASH) &&
  2691. ((status & L2_FHDR_STATUS_USE_RXHASH) ==
  2692. L2_FHDR_STATUS_USE_RXHASH))
  2693. skb->rxhash = rx_hdr->l2_fhdr_hash;
  2694. skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
  2695. #ifdef BCM_VLAN
  2696. if (hw_vlan)
  2697. vlan_gro_receive(&bnapi->napi, bp->vlgrp, vtag, skb);
  2698. else
  2699. #endif
  2700. napi_gro_receive(&bnapi->napi, skb);
  2701. rx_pkt++;
  2702. next_rx:
  2703. sw_cons = NEXT_RX_BD(sw_cons);
  2704. sw_prod = NEXT_RX_BD(sw_prod);
  2705. if ((rx_pkt == budget))
  2706. break;
  2707. /* Refresh hw_cons to see if there is new work */
  2708. if (sw_cons == hw_cons) {
  2709. hw_cons = bnx2_get_hw_rx_cons(bnapi);
  2710. rmb();
  2711. }
  2712. }
  2713. rxr->rx_cons = sw_cons;
  2714. rxr->rx_prod = sw_prod;
  2715. if (pg_ring_used)
  2716. REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
  2717. REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
  2718. REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
  2719. mmiowb();
  2720. return rx_pkt;
  2721. }
  2722. /* MSI ISR - The only difference between this and the INTx ISR
  2723. * is that the MSI interrupt is always serviced.
  2724. */
  2725. static irqreturn_t
  2726. bnx2_msi(int irq, void *dev_instance)
  2727. {
  2728. struct bnx2_napi *bnapi = dev_instance;
  2729. struct bnx2 *bp = bnapi->bp;
  2730. prefetch(bnapi->status_blk.msi);
  2731. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2732. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
  2733. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2734. /* Return here if interrupt is disabled. */
  2735. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2736. return IRQ_HANDLED;
  2737. napi_schedule(&bnapi->napi);
  2738. return IRQ_HANDLED;
  2739. }
  2740. static irqreturn_t
  2741. bnx2_msi_1shot(int irq, void *dev_instance)
  2742. {
  2743. struct bnx2_napi *bnapi = dev_instance;
  2744. struct bnx2 *bp = bnapi->bp;
  2745. prefetch(bnapi->status_blk.msi);
  2746. /* Return here if interrupt is disabled. */
  2747. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2748. return IRQ_HANDLED;
  2749. napi_schedule(&bnapi->napi);
  2750. return IRQ_HANDLED;
  2751. }
  2752. static irqreturn_t
  2753. bnx2_interrupt(int irq, void *dev_instance)
  2754. {
  2755. struct bnx2_napi *bnapi = dev_instance;
  2756. struct bnx2 *bp = bnapi->bp;
  2757. struct status_block *sblk = bnapi->status_blk.msi;
  2758. /* When using INTx, it is possible for the interrupt to arrive
  2759. * at the CPU before the status block posted prior to the
  2760. * interrupt. Reading a register will flush the status block.
  2761. * When using MSI, the MSI message will always complete after
  2762. * the status block write.
  2763. */
  2764. if ((sblk->status_idx == bnapi->last_status_idx) &&
  2765. (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
  2766. BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
  2767. return IRQ_NONE;
  2768. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2769. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
  2770. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2771. /* Read back to deassert IRQ immediately to avoid too many
  2772. * spurious interrupts.
  2773. */
  2774. REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
  2775. /* Return here if interrupt is shared and is disabled. */
  2776. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2777. return IRQ_HANDLED;
  2778. if (napi_schedule_prep(&bnapi->napi)) {
  2779. bnapi->last_status_idx = sblk->status_idx;
  2780. __napi_schedule(&bnapi->napi);
  2781. }
  2782. return IRQ_HANDLED;
  2783. }
  2784. static inline int
  2785. bnx2_has_fast_work(struct bnx2_napi *bnapi)
  2786. {
  2787. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2788. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2789. if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
  2790. (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
  2791. return 1;
  2792. return 0;
  2793. }
  2794. #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
  2795. STATUS_ATTN_BITS_TIMER_ABORT)
  2796. static inline int
  2797. bnx2_has_work(struct bnx2_napi *bnapi)
  2798. {
  2799. struct status_block *sblk = bnapi->status_blk.msi;
  2800. if (bnx2_has_fast_work(bnapi))
  2801. return 1;
  2802. #ifdef BCM_CNIC
  2803. if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
  2804. return 1;
  2805. #endif
  2806. if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
  2807. (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
  2808. return 1;
  2809. return 0;
  2810. }
  2811. static void
  2812. bnx2_chk_missed_msi(struct bnx2 *bp)
  2813. {
  2814. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  2815. u32 msi_ctrl;
  2816. if (bnx2_has_work(bnapi)) {
  2817. msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
  2818. if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
  2819. return;
  2820. if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
  2821. REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
  2822. ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
  2823. REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
  2824. bnx2_msi(bp->irq_tbl[0].vector, bnapi);
  2825. }
  2826. }
  2827. bp->idle_chk_status_idx = bnapi->last_status_idx;
  2828. }
  2829. #ifdef BCM_CNIC
  2830. static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
  2831. {
  2832. struct cnic_ops *c_ops;
  2833. if (!bnapi->cnic_present)
  2834. return;
  2835. rcu_read_lock();
  2836. c_ops = rcu_dereference(bp->cnic_ops);
  2837. if (c_ops)
  2838. bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
  2839. bnapi->status_blk.msi);
  2840. rcu_read_unlock();
  2841. }
  2842. #endif
  2843. static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
  2844. {
  2845. struct status_block *sblk = bnapi->status_blk.msi;
  2846. u32 status_attn_bits = sblk->status_attn_bits;
  2847. u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
  2848. if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
  2849. (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
  2850. bnx2_phy_int(bp, bnapi);
  2851. /* This is needed to take care of transient status
  2852. * during link changes.
  2853. */
  2854. REG_WR(bp, BNX2_HC_COMMAND,
  2855. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2856. REG_RD(bp, BNX2_HC_COMMAND);
  2857. }
  2858. }
  2859. static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
  2860. int work_done, int budget)
  2861. {
  2862. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2863. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2864. if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
  2865. bnx2_tx_int(bp, bnapi, 0);
  2866. if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
  2867. work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
  2868. return work_done;
  2869. }
  2870. static int bnx2_poll_msix(struct napi_struct *napi, int budget)
  2871. {
  2872. struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
  2873. struct bnx2 *bp = bnapi->bp;
  2874. int work_done = 0;
  2875. struct status_block_msix *sblk = bnapi->status_blk.msix;
  2876. while (1) {
  2877. work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
  2878. if (unlikely(work_done >= budget))
  2879. break;
  2880. bnapi->last_status_idx = sblk->status_idx;
  2881. /* status idx must be read before checking for more work. */
  2882. rmb();
  2883. if (likely(!bnx2_has_fast_work(bnapi))) {
  2884. napi_complete(napi);
  2885. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  2886. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2887. bnapi->last_status_idx);
  2888. break;
  2889. }
  2890. }
  2891. return work_done;
  2892. }
  2893. static int bnx2_poll(struct napi_struct *napi, int budget)
  2894. {
  2895. struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
  2896. struct bnx2 *bp = bnapi->bp;
  2897. int work_done = 0;
  2898. struct status_block *sblk = bnapi->status_blk.msi;
  2899. while (1) {
  2900. bnx2_poll_link(bp, bnapi);
  2901. work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
  2902. #ifdef BCM_CNIC
  2903. bnx2_poll_cnic(bp, bnapi);
  2904. #endif
  2905. /* bnapi->last_status_idx is used below to tell the hw how
  2906. * much work has been processed, so we must read it before
  2907. * checking for more work.
  2908. */
  2909. bnapi->last_status_idx = sblk->status_idx;
  2910. if (unlikely(work_done >= budget))
  2911. break;
  2912. rmb();
  2913. if (likely(!bnx2_has_work(bnapi))) {
  2914. napi_complete(napi);
  2915. if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
  2916. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2917. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2918. bnapi->last_status_idx);
  2919. break;
  2920. }
  2921. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2922. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2923. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  2924. bnapi->last_status_idx);
  2925. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2926. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2927. bnapi->last_status_idx);
  2928. break;
  2929. }
  2930. }
  2931. return work_done;
  2932. }
  2933. /* Called with rtnl_lock from vlan functions and also netif_tx_lock
  2934. * from set_multicast.
  2935. */
  2936. static void
  2937. bnx2_set_rx_mode(struct net_device *dev)
  2938. {
  2939. struct bnx2 *bp = netdev_priv(dev);
  2940. u32 rx_mode, sort_mode;
  2941. struct netdev_hw_addr *ha;
  2942. int i;
  2943. if (!netif_running(dev))
  2944. return;
  2945. spin_lock_bh(&bp->phy_lock);
  2946. rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
  2947. BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
  2948. sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
  2949. #ifdef BCM_VLAN
  2950. if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
  2951. rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
  2952. #else
  2953. if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
  2954. rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
  2955. #endif
  2956. if (dev->flags & IFF_PROMISC) {
  2957. /* Promiscuous mode. */
  2958. rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
  2959. sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
  2960. BNX2_RPM_SORT_USER0_PROM_VLAN;
  2961. }
  2962. else if (dev->flags & IFF_ALLMULTI) {
  2963. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  2964. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  2965. 0xffffffff);
  2966. }
  2967. sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
  2968. }
  2969. else {
  2970. /* Accept one or more multicast(s). */
  2971. u32 mc_filter[NUM_MC_HASH_REGISTERS];
  2972. u32 regidx;
  2973. u32 bit;
  2974. u32 crc;
  2975. memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
  2976. netdev_for_each_mc_addr(ha, dev) {
  2977. crc = ether_crc_le(ETH_ALEN, ha->addr);
  2978. bit = crc & 0xff;
  2979. regidx = (bit & 0xe0) >> 5;
  2980. bit &= 0x1f;
  2981. mc_filter[regidx] |= (1 << bit);
  2982. }
  2983. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  2984. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  2985. mc_filter[i]);
  2986. }
  2987. sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
  2988. }
  2989. if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
  2990. rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
  2991. sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
  2992. BNX2_RPM_SORT_USER0_PROM_VLAN;
  2993. } else if (!(dev->flags & IFF_PROMISC)) {
  2994. /* Add all entries into to the match filter list */
  2995. i = 0;
  2996. netdev_for_each_uc_addr(ha, dev) {
  2997. bnx2_set_mac_addr(bp, ha->addr,
  2998. i + BNX2_START_UNICAST_ADDRESS_INDEX);
  2999. sort_mode |= (1 <<
  3000. (i + BNX2_START_UNICAST_ADDRESS_INDEX));
  3001. i++;
  3002. }
  3003. }
  3004. if (rx_mode != bp->rx_mode) {
  3005. bp->rx_mode = rx_mode;
  3006. REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
  3007. }
  3008. REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  3009. REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
  3010. REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
  3011. spin_unlock_bh(&bp->phy_lock);
  3012. }
  3013. static int __devinit
  3014. check_fw_section(const struct firmware *fw,
  3015. const struct bnx2_fw_file_section *section,
  3016. u32 alignment, bool non_empty)
  3017. {
  3018. u32 offset = be32_to_cpu(section->offset);
  3019. u32 len = be32_to_cpu(section->len);
  3020. if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
  3021. return -EINVAL;
  3022. if ((non_empty && len == 0) || len > fw->size - offset ||
  3023. len & (alignment - 1))
  3024. return -EINVAL;
  3025. return 0;
  3026. }
  3027. static int __devinit
  3028. check_mips_fw_entry(const struct firmware *fw,
  3029. const struct bnx2_mips_fw_file_entry *entry)
  3030. {
  3031. if (check_fw_section(fw, &entry->text, 4, true) ||
  3032. check_fw_section(fw, &entry->data, 4, false) ||
  3033. check_fw_section(fw, &entry->rodata, 4, false))
  3034. return -EINVAL;
  3035. return 0;
  3036. }
  3037. static int __devinit
  3038. bnx2_request_firmware(struct bnx2 *bp)
  3039. {
  3040. const char *mips_fw_file, *rv2p_fw_file;
  3041. const struct bnx2_mips_fw_file *mips_fw;
  3042. const struct bnx2_rv2p_fw_file *rv2p_fw;
  3043. int rc;
  3044. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3045. mips_fw_file = FW_MIPS_FILE_09;
  3046. if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
  3047. (CHIP_ID(bp) == CHIP_ID_5709_A1))
  3048. rv2p_fw_file = FW_RV2P_FILE_09_Ax;
  3049. else
  3050. rv2p_fw_file = FW_RV2P_FILE_09;
  3051. } else {
  3052. mips_fw_file = FW_MIPS_FILE_06;
  3053. rv2p_fw_file = FW_RV2P_FILE_06;
  3054. }
  3055. rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
  3056. if (rc) {
  3057. pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
  3058. return rc;
  3059. }
  3060. rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
  3061. if (rc) {
  3062. pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
  3063. return rc;
  3064. }
  3065. mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
  3066. rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
  3067. if (bp->mips_firmware->size < sizeof(*mips_fw) ||
  3068. check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
  3069. check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
  3070. check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
  3071. check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
  3072. check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
  3073. pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
  3074. return -EINVAL;
  3075. }
  3076. if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
  3077. check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
  3078. check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
  3079. pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
  3080. return -EINVAL;
  3081. }
  3082. return 0;
  3083. }
  3084. static u32
  3085. rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
  3086. {
  3087. switch (idx) {
  3088. case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
  3089. rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
  3090. rv2p_code |= RV2P_BD_PAGE_SIZE;
  3091. break;
  3092. }
  3093. return rv2p_code;
  3094. }
  3095. static int
  3096. load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
  3097. const struct bnx2_rv2p_fw_file_entry *fw_entry)
  3098. {
  3099. u32 rv2p_code_len, file_offset;
  3100. __be32 *rv2p_code;
  3101. int i;
  3102. u32 val, cmd, addr;
  3103. rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
  3104. file_offset = be32_to_cpu(fw_entry->rv2p.offset);
  3105. rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
  3106. if (rv2p_proc == RV2P_PROC1) {
  3107. cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
  3108. addr = BNX2_RV2P_PROC1_ADDR_CMD;
  3109. } else {
  3110. cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
  3111. addr = BNX2_RV2P_PROC2_ADDR_CMD;
  3112. }
  3113. for (i = 0; i < rv2p_code_len; i += 8) {
  3114. REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
  3115. rv2p_code++;
  3116. REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
  3117. rv2p_code++;
  3118. val = (i / 8) | cmd;
  3119. REG_WR(bp, addr, val);
  3120. }
  3121. rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
  3122. for (i = 0; i < 8; i++) {
  3123. u32 loc, code;
  3124. loc = be32_to_cpu(fw_entry->fixup[i]);
  3125. if (loc && ((loc * 4) < rv2p_code_len)) {
  3126. code = be32_to_cpu(*(rv2p_code + loc - 1));
  3127. REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
  3128. code = be32_to_cpu(*(rv2p_code + loc));
  3129. code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
  3130. REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
  3131. val = (loc / 2) | cmd;
  3132. REG_WR(bp, addr, val);
  3133. }
  3134. }
  3135. /* Reset the processor, un-stall is done later. */
  3136. if (rv2p_proc == RV2P_PROC1) {
  3137. REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
  3138. }
  3139. else {
  3140. REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
  3141. }
  3142. return 0;
  3143. }
  3144. static int
  3145. load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
  3146. const struct bnx2_mips_fw_file_entry *fw_entry)
  3147. {
  3148. u32 addr, len, file_offset;
  3149. __be32 *data;
  3150. u32 offset;
  3151. u32 val;
  3152. /* Halt the CPU. */
  3153. val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
  3154. val |= cpu_reg->mode_value_halt;
  3155. bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
  3156. bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
  3157. /* Load the Text area. */
  3158. addr = be32_to_cpu(fw_entry->text.addr);
  3159. len = be32_to_cpu(fw_entry->text.len);
  3160. file_offset = be32_to_cpu(fw_entry->text.offset);
  3161. data = (__be32 *)(bp->mips_firmware->data + file_offset);
  3162. offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
  3163. if (len) {
  3164. int j;
  3165. for (j = 0; j < (len / 4); j++, offset += 4)
  3166. bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
  3167. }
  3168. /* Load the Data area. */
  3169. addr = be32_to_cpu(fw_entry->data.addr);
  3170. len = be32_to_cpu(fw_entry->data.len);
  3171. file_offset = be32_to_cpu(fw_entry->data.offset);
  3172. data = (__be32 *)(bp->mips_firmware->data + file_offset);
  3173. offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
  3174. if (len) {
  3175. int j;
  3176. for (j = 0; j < (len / 4); j++, offset += 4)
  3177. bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
  3178. }
  3179. /* Load the Read-Only area. */
  3180. addr = be32_to_cpu(fw_entry->rodata.addr);
  3181. len = be32_to_cpu(fw_entry->rodata.len);
  3182. file_offset = be32_to_cpu(fw_entry->rodata.offset);
  3183. data = (__be32 *)(bp->mips_firmware->data + file_offset);
  3184. offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
  3185. if (len) {
  3186. int j;
  3187. for (j = 0; j < (len / 4); j++, offset += 4)
  3188. bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
  3189. }
  3190. /* Clear the pre-fetch instruction. */
  3191. bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
  3192. val = be32_to_cpu(fw_entry->start_addr);
  3193. bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
  3194. /* Start the CPU. */
  3195. val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
  3196. val &= ~cpu_reg->mode_value_halt;
  3197. bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
  3198. bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
  3199. return 0;
  3200. }
  3201. static int
  3202. bnx2_init_cpus(struct bnx2 *bp)
  3203. {
  3204. const struct bnx2_mips_fw_file *mips_fw =
  3205. (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
  3206. const struct bnx2_rv2p_fw_file *rv2p_fw =
  3207. (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
  3208. int rc;
  3209. /* Initialize the RV2P processor. */
  3210. load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
  3211. load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
  3212. /* Initialize the RX Processor. */
  3213. rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
  3214. if (rc)
  3215. goto init_cpu_err;
  3216. /* Initialize the TX Processor. */
  3217. rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
  3218. if (rc)
  3219. goto init_cpu_err;
  3220. /* Initialize the TX Patch-up Processor. */
  3221. rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
  3222. if (rc)
  3223. goto init_cpu_err;
  3224. /* Initialize the Completion Processor. */
  3225. rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
  3226. if (rc)
  3227. goto init_cpu_err;
  3228. /* Initialize the Command Processor. */
  3229. rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
  3230. init_cpu_err:
  3231. return rc;
  3232. }
  3233. static int
  3234. bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
  3235. {
  3236. u16 pmcsr;
  3237. pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
  3238. switch (state) {
  3239. case PCI_D0: {
  3240. u32 val;
  3241. pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
  3242. (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
  3243. PCI_PM_CTRL_PME_STATUS);
  3244. if (pmcsr & PCI_PM_CTRL_STATE_MASK)
  3245. /* delay required during transition out of D3hot */
  3246. msleep(20);
  3247. val = REG_RD(bp, BNX2_EMAC_MODE);
  3248. val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
  3249. val &= ~BNX2_EMAC_MODE_MPKT;
  3250. REG_WR(bp, BNX2_EMAC_MODE, val);
  3251. val = REG_RD(bp, BNX2_RPM_CONFIG);
  3252. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  3253. REG_WR(bp, BNX2_RPM_CONFIG, val);
  3254. break;
  3255. }
  3256. case PCI_D3hot: {
  3257. int i;
  3258. u32 val, wol_msg;
  3259. if (bp->wol) {
  3260. u32 advertising;
  3261. u8 autoneg;
  3262. autoneg = bp->autoneg;
  3263. advertising = bp->advertising;
  3264. if (bp->phy_port == PORT_TP) {
  3265. bp->autoneg = AUTONEG_SPEED;
  3266. bp->advertising = ADVERTISED_10baseT_Half |
  3267. ADVERTISED_10baseT_Full |
  3268. ADVERTISED_100baseT_Half |
  3269. ADVERTISED_100baseT_Full |
  3270. ADVERTISED_Autoneg;
  3271. }
  3272. spin_lock_bh(&bp->phy_lock);
  3273. bnx2_setup_phy(bp, bp->phy_port);
  3274. spin_unlock_bh(&bp->phy_lock);
  3275. bp->autoneg = autoneg;
  3276. bp->advertising = advertising;
  3277. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  3278. val = REG_RD(bp, BNX2_EMAC_MODE);
  3279. /* Enable port mode. */
  3280. val &= ~BNX2_EMAC_MODE_PORT;
  3281. val |= BNX2_EMAC_MODE_MPKT_RCVD |
  3282. BNX2_EMAC_MODE_ACPI_RCVD |
  3283. BNX2_EMAC_MODE_MPKT;
  3284. if (bp->phy_port == PORT_TP)
  3285. val |= BNX2_EMAC_MODE_PORT_MII;
  3286. else {
  3287. val |= BNX2_EMAC_MODE_PORT_GMII;
  3288. if (bp->line_speed == SPEED_2500)
  3289. val |= BNX2_EMAC_MODE_25G_MODE;
  3290. }
  3291. REG_WR(bp, BNX2_EMAC_MODE, val);
  3292. /* receive all multicast */
  3293. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  3294. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  3295. 0xffffffff);
  3296. }
  3297. REG_WR(bp, BNX2_EMAC_RX_MODE,
  3298. BNX2_EMAC_RX_MODE_SORT_MODE);
  3299. val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
  3300. BNX2_RPM_SORT_USER0_MC_EN;
  3301. REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  3302. REG_WR(bp, BNX2_RPM_SORT_USER0, val);
  3303. REG_WR(bp, BNX2_RPM_SORT_USER0, val |
  3304. BNX2_RPM_SORT_USER0_ENA);
  3305. /* Need to enable EMAC and RPM for WOL. */
  3306. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  3307. BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
  3308. BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
  3309. BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
  3310. val = REG_RD(bp, BNX2_RPM_CONFIG);
  3311. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  3312. REG_WR(bp, BNX2_RPM_CONFIG, val);
  3313. wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  3314. }
  3315. else {
  3316. wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  3317. }
  3318. if (!(bp->flags & BNX2_FLAG_NO_WOL))
  3319. bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
  3320. 1, 0);
  3321. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  3322. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  3323. (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
  3324. if (bp->wol)
  3325. pmcsr |= 3;
  3326. }
  3327. else {
  3328. pmcsr |= 3;
  3329. }
  3330. if (bp->wol) {
  3331. pmcsr |= PCI_PM_CTRL_PME_ENABLE;
  3332. }
  3333. pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
  3334. pmcsr);
  3335. /* No more memory access after this point until
  3336. * device is brought back to D0.
  3337. */
  3338. udelay(50);
  3339. break;
  3340. }
  3341. default:
  3342. return -EINVAL;
  3343. }
  3344. return 0;
  3345. }
  3346. static int
  3347. bnx2_acquire_nvram_lock(struct bnx2 *bp)
  3348. {
  3349. u32 val;
  3350. int j;
  3351. /* Request access to the flash interface. */
  3352. REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
  3353. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3354. val = REG_RD(bp, BNX2_NVM_SW_ARB);
  3355. if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
  3356. break;
  3357. udelay(5);
  3358. }
  3359. if (j >= NVRAM_TIMEOUT_COUNT)
  3360. return -EBUSY;
  3361. return 0;
  3362. }
  3363. static int
  3364. bnx2_release_nvram_lock(struct bnx2 *bp)
  3365. {
  3366. int j;
  3367. u32 val;
  3368. /* Relinquish nvram interface. */
  3369. REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
  3370. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3371. val = REG_RD(bp, BNX2_NVM_SW_ARB);
  3372. if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
  3373. break;
  3374. udelay(5);
  3375. }
  3376. if (j >= NVRAM_TIMEOUT_COUNT)
  3377. return -EBUSY;
  3378. return 0;
  3379. }
  3380. static int
  3381. bnx2_enable_nvram_write(struct bnx2 *bp)
  3382. {
  3383. u32 val;
  3384. val = REG_RD(bp, BNX2_MISC_CFG);
  3385. REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
  3386. if (bp->flash_info->flags & BNX2_NV_WREN) {
  3387. int j;
  3388. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3389. REG_WR(bp, BNX2_NVM_COMMAND,
  3390. BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
  3391. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3392. udelay(5);
  3393. val = REG_RD(bp, BNX2_NVM_COMMAND);
  3394. if (val & BNX2_NVM_COMMAND_DONE)
  3395. break;
  3396. }
  3397. if (j >= NVRAM_TIMEOUT_COUNT)
  3398. return -EBUSY;
  3399. }
  3400. return 0;
  3401. }
  3402. static void
  3403. bnx2_disable_nvram_write(struct bnx2 *bp)
  3404. {
  3405. u32 val;
  3406. val = REG_RD(bp, BNX2_MISC_CFG);
  3407. REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
  3408. }
  3409. static void
  3410. bnx2_enable_nvram_access(struct bnx2 *bp)
  3411. {
  3412. u32 val;
  3413. val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  3414. /* Enable both bits, even on read. */
  3415. REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  3416. val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
  3417. }
  3418. static void
  3419. bnx2_disable_nvram_access(struct bnx2 *bp)
  3420. {
  3421. u32 val;
  3422. val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  3423. /* Disable both bits, even after read. */
  3424. REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  3425. val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
  3426. BNX2_NVM_ACCESS_ENABLE_WR_EN));
  3427. }
  3428. static int
  3429. bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
  3430. {
  3431. u32 cmd;
  3432. int j;
  3433. if (bp->flash_info->flags & BNX2_NV_BUFFERED)
  3434. /* Buffered flash, no erase needed */
  3435. return 0;
  3436. /* Build an erase command */
  3437. cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
  3438. BNX2_NVM_COMMAND_DOIT;
  3439. /* Need to clear DONE bit separately. */
  3440. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3441. /* Address of the NVRAM to read from. */
  3442. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3443. /* Issue an erase command. */
  3444. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  3445. /* Wait for completion. */
  3446. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3447. u32 val;
  3448. udelay(5);
  3449. val = REG_RD(bp, BNX2_NVM_COMMAND);
  3450. if (val & BNX2_NVM_COMMAND_DONE)
  3451. break;
  3452. }
  3453. if (j >= NVRAM_TIMEOUT_COUNT)
  3454. return -EBUSY;
  3455. return 0;
  3456. }
  3457. static int
  3458. bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
  3459. {
  3460. u32 cmd;
  3461. int j;
  3462. /* Build the command word. */
  3463. cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
  3464. /* Calculate an offset of a buffered flash, not needed for 5709. */
  3465. if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
  3466. offset = ((offset / bp->flash_info->page_size) <<
  3467. bp->flash_info->page_bits) +
  3468. (offset % bp->flash_info->page_size);
  3469. }
  3470. /* Need to clear DONE bit separately. */
  3471. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3472. /* Address of the NVRAM to read from. */
  3473. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3474. /* Issue a read command. */
  3475. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  3476. /* Wait for completion. */
  3477. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3478. u32 val;
  3479. udelay(5);
  3480. val = REG_RD(bp, BNX2_NVM_COMMAND);
  3481. if (val & BNX2_NVM_COMMAND_DONE) {
  3482. __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
  3483. memcpy(ret_val, &v, 4);
  3484. break;
  3485. }
  3486. }
  3487. if (j >= NVRAM_TIMEOUT_COUNT)
  3488. return -EBUSY;
  3489. return 0;
  3490. }
  3491. static int
  3492. bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
  3493. {
  3494. u32 cmd;
  3495. __be32 val32;
  3496. int j;
  3497. /* Build the command word. */
  3498. cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
  3499. /* Calculate an offset of a buffered flash, not needed for 5709. */
  3500. if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
  3501. offset = ((offset / bp->flash_info->page_size) <<
  3502. bp->flash_info->page_bits) +
  3503. (offset % bp->flash_info->page_size);
  3504. }
  3505. /* Need to clear DONE bit separately. */
  3506. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3507. memcpy(&val32, val, 4);
  3508. /* Write the data. */
  3509. REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
  3510. /* Address of the NVRAM to write to. */
  3511. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3512. /* Issue the write command. */
  3513. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  3514. /* Wait for completion. */
  3515. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3516. udelay(5);
  3517. if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
  3518. break;
  3519. }
  3520. if (j >= NVRAM_TIMEOUT_COUNT)
  3521. return -EBUSY;
  3522. return 0;
  3523. }
  3524. static int
  3525. bnx2_init_nvram(struct bnx2 *bp)
  3526. {
  3527. u32 val;
  3528. int j, entry_count, rc = 0;
  3529. const struct flash_spec *flash;
  3530. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3531. bp->flash_info = &flash_5709;
  3532. goto get_flash_size;
  3533. }
  3534. /* Determine the selected interface. */
  3535. val = REG_RD(bp, BNX2_NVM_CFG1);
  3536. entry_count = ARRAY_SIZE(flash_table);
  3537. if (val & 0x40000000) {
  3538. /* Flash interface has been reconfigured */
  3539. for (j = 0, flash = &flash_table[0]; j < entry_count;
  3540. j++, flash++) {
  3541. if ((val & FLASH_BACKUP_STRAP_MASK) ==
  3542. (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
  3543. bp->flash_info = flash;
  3544. break;
  3545. }
  3546. }
  3547. }
  3548. else {
  3549. u32 mask;
  3550. /* Not yet been reconfigured */
  3551. if (val & (1 << 23))
  3552. mask = FLASH_BACKUP_STRAP_MASK;
  3553. else
  3554. mask = FLASH_STRAP_MASK;
  3555. for (j = 0, flash = &flash_table[0]; j < entry_count;
  3556. j++, flash++) {
  3557. if ((val & mask) == (flash->strapping & mask)) {
  3558. bp->flash_info = flash;
  3559. /* Request access to the flash interface. */
  3560. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3561. return rc;
  3562. /* Enable access to flash interface */
  3563. bnx2_enable_nvram_access(bp);
  3564. /* Reconfigure the flash interface */
  3565. REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
  3566. REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
  3567. REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
  3568. REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
  3569. /* Disable access to flash interface */
  3570. bnx2_disable_nvram_access(bp);
  3571. bnx2_release_nvram_lock(bp);
  3572. break;
  3573. }
  3574. }
  3575. } /* if (val & 0x40000000) */
  3576. if (j == entry_count) {
  3577. bp->flash_info = NULL;
  3578. pr_alert("Unknown flash/EEPROM type\n");
  3579. return -ENODEV;
  3580. }
  3581. get_flash_size:
  3582. val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
  3583. val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
  3584. if (val)
  3585. bp->flash_size = val;
  3586. else
  3587. bp->flash_size = bp->flash_info->total_size;
  3588. return rc;
  3589. }
  3590. static int
  3591. bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
  3592. int buf_size)
  3593. {
  3594. int rc = 0;
  3595. u32 cmd_flags, offset32, len32, extra;
  3596. if (buf_size == 0)
  3597. return 0;
  3598. /* Request access to the flash interface. */
  3599. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3600. return rc;
  3601. /* Enable access to flash interface */
  3602. bnx2_enable_nvram_access(bp);
  3603. len32 = buf_size;
  3604. offset32 = offset;
  3605. extra = 0;
  3606. cmd_flags = 0;
  3607. if (offset32 & 3) {
  3608. u8 buf[4];
  3609. u32 pre_len;
  3610. offset32 &= ~3;
  3611. pre_len = 4 - (offset & 3);
  3612. if (pre_len >= len32) {
  3613. pre_len = len32;
  3614. cmd_flags = BNX2_NVM_COMMAND_FIRST |
  3615. BNX2_NVM_COMMAND_LAST;
  3616. }
  3617. else {
  3618. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3619. }
  3620. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3621. if (rc)
  3622. return rc;
  3623. memcpy(ret_buf, buf + (offset & 3), pre_len);
  3624. offset32 += 4;
  3625. ret_buf += pre_len;
  3626. len32 -= pre_len;
  3627. }
  3628. if (len32 & 3) {
  3629. extra = 4 - (len32 & 3);
  3630. len32 = (len32 + 4) & ~3;
  3631. }
  3632. if (len32 == 4) {
  3633. u8 buf[4];
  3634. if (cmd_flags)
  3635. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3636. else
  3637. cmd_flags = BNX2_NVM_COMMAND_FIRST |
  3638. BNX2_NVM_COMMAND_LAST;
  3639. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3640. memcpy(ret_buf, buf, 4 - extra);
  3641. }
  3642. else if (len32 > 0) {
  3643. u8 buf[4];
  3644. /* Read the first word. */
  3645. if (cmd_flags)
  3646. cmd_flags = 0;
  3647. else
  3648. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3649. rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
  3650. /* Advance to the next dword. */
  3651. offset32 += 4;
  3652. ret_buf += 4;
  3653. len32 -= 4;
  3654. while (len32 > 4 && rc == 0) {
  3655. rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
  3656. /* Advance to the next dword. */
  3657. offset32 += 4;
  3658. ret_buf += 4;
  3659. len32 -= 4;
  3660. }
  3661. if (rc)
  3662. return rc;
  3663. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3664. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3665. memcpy(ret_buf, buf, 4 - extra);
  3666. }
  3667. /* Disable access to flash interface */
  3668. bnx2_disable_nvram_access(bp);
  3669. bnx2_release_nvram_lock(bp);
  3670. return rc;
  3671. }
  3672. static int
  3673. bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
  3674. int buf_size)
  3675. {
  3676. u32 written, offset32, len32;
  3677. u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
  3678. int rc = 0;
  3679. int align_start, align_end;
  3680. buf = data_buf;
  3681. offset32 = offset;
  3682. len32 = buf_size;
  3683. align_start = align_end = 0;
  3684. if ((align_start = (offset32 & 3))) {
  3685. offset32 &= ~3;
  3686. len32 += align_start;
  3687. if (len32 < 4)
  3688. len32 = 4;
  3689. if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
  3690. return rc;
  3691. }
  3692. if (len32 & 3) {
  3693. align_end = 4 - (len32 & 3);
  3694. len32 += align_end;
  3695. if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
  3696. return rc;
  3697. }
  3698. if (align_start || align_end) {
  3699. align_buf = kmalloc(len32, GFP_KERNEL);
  3700. if (align_buf == NULL)
  3701. return -ENOMEM;
  3702. if (align_start) {
  3703. memcpy(align_buf, start, 4);
  3704. }
  3705. if (align_end) {
  3706. memcpy(align_buf + len32 - 4, end, 4);
  3707. }
  3708. memcpy(align_buf + align_start, data_buf, buf_size);
  3709. buf = align_buf;
  3710. }
  3711. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3712. flash_buffer = kmalloc(264, GFP_KERNEL);
  3713. if (flash_buffer == NULL) {
  3714. rc = -ENOMEM;
  3715. goto nvram_write_end;
  3716. }
  3717. }
  3718. written = 0;
  3719. while ((written < len32) && (rc == 0)) {
  3720. u32 page_start, page_end, data_start, data_end;
  3721. u32 addr, cmd_flags;
  3722. int i;
  3723. /* Find the page_start addr */
  3724. page_start = offset32 + written;
  3725. page_start -= (page_start % bp->flash_info->page_size);
  3726. /* Find the page_end addr */
  3727. page_end = page_start + bp->flash_info->page_size;
  3728. /* Find the data_start addr */
  3729. data_start = (written == 0) ? offset32 : page_start;
  3730. /* Find the data_end addr */
  3731. data_end = (page_end > offset32 + len32) ?
  3732. (offset32 + len32) : page_end;
  3733. /* Request access to the flash interface. */
  3734. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3735. goto nvram_write_end;
  3736. /* Enable access to flash interface */
  3737. bnx2_enable_nvram_access(bp);
  3738. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3739. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3740. int j;
  3741. /* Read the whole page into the buffer
  3742. * (non-buffer flash only) */
  3743. for (j = 0; j < bp->flash_info->page_size; j += 4) {
  3744. if (j == (bp->flash_info->page_size - 4)) {
  3745. cmd_flags |= BNX2_NVM_COMMAND_LAST;
  3746. }
  3747. rc = bnx2_nvram_read_dword(bp,
  3748. page_start + j,
  3749. &flash_buffer[j],
  3750. cmd_flags);
  3751. if (rc)
  3752. goto nvram_write_end;
  3753. cmd_flags = 0;
  3754. }
  3755. }
  3756. /* Enable writes to flash interface (unlock write-protect) */
  3757. if ((rc = bnx2_enable_nvram_write(bp)) != 0)
  3758. goto nvram_write_end;
  3759. /* Loop to write back the buffer data from page_start to
  3760. * data_start */
  3761. i = 0;
  3762. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3763. /* Erase the page */
  3764. if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
  3765. goto nvram_write_end;
  3766. /* Re-enable the write again for the actual write */
  3767. bnx2_enable_nvram_write(bp);
  3768. for (addr = page_start; addr < data_start;
  3769. addr += 4, i += 4) {
  3770. rc = bnx2_nvram_write_dword(bp, addr,
  3771. &flash_buffer[i], cmd_flags);
  3772. if (rc != 0)
  3773. goto nvram_write_end;
  3774. cmd_flags = 0;
  3775. }
  3776. }
  3777. /* Loop to write the new data from data_start to data_end */
  3778. for (addr = data_start; addr < data_end; addr += 4, i += 4) {
  3779. if ((addr == page_end - 4) ||
  3780. ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
  3781. (addr == data_end - 4))) {
  3782. cmd_flags |= BNX2_NVM_COMMAND_LAST;
  3783. }
  3784. rc = bnx2_nvram_write_dword(bp, addr, buf,
  3785. cmd_flags);
  3786. if (rc != 0)
  3787. goto nvram_write_end;
  3788. cmd_flags = 0;
  3789. buf += 4;
  3790. }
  3791. /* Loop to write back the buffer data from data_end
  3792. * to page_end */
  3793. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3794. for (addr = data_end; addr < page_end;
  3795. addr += 4, i += 4) {
  3796. if (addr == page_end-4) {
  3797. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3798. }
  3799. rc = bnx2_nvram_write_dword(bp, addr,
  3800. &flash_buffer[i], cmd_flags);
  3801. if (rc != 0)
  3802. goto nvram_write_end;
  3803. cmd_flags = 0;
  3804. }
  3805. }
  3806. /* Disable writes to flash interface (lock write-protect) */
  3807. bnx2_disable_nvram_write(bp);
  3808. /* Disable access to flash interface */
  3809. bnx2_disable_nvram_access(bp);
  3810. bnx2_release_nvram_lock(bp);
  3811. /* Increment written */
  3812. written += data_end - data_start;
  3813. }
  3814. nvram_write_end:
  3815. kfree(flash_buffer);
  3816. kfree(align_buf);
  3817. return rc;
  3818. }
  3819. static void
  3820. bnx2_init_fw_cap(struct bnx2 *bp)
  3821. {
  3822. u32 val, sig = 0;
  3823. bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
  3824. bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
  3825. if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
  3826. bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
  3827. val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
  3828. if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
  3829. return;
  3830. if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
  3831. bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
  3832. sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
  3833. }
  3834. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  3835. (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
  3836. u32 link;
  3837. bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
  3838. link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
  3839. if (link & BNX2_LINK_STATUS_SERDES_LINK)
  3840. bp->phy_port = PORT_FIBRE;
  3841. else
  3842. bp->phy_port = PORT_TP;
  3843. sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
  3844. BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
  3845. }
  3846. if (netif_running(bp->dev) && sig)
  3847. bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
  3848. }
  3849. static void
  3850. bnx2_setup_msix_tbl(struct bnx2 *bp)
  3851. {
  3852. REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
  3853. REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
  3854. REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
  3855. }
  3856. static int
  3857. bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
  3858. {
  3859. u32 val;
  3860. int i, rc = 0;
  3861. u8 old_port;
  3862. /* Wait for the current PCI transaction to complete before
  3863. * issuing a reset. */
  3864. REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
  3865. BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
  3866. BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
  3867. BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
  3868. BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
  3869. val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
  3870. udelay(5);
  3871. /* Wait for the firmware to tell us it is ok to issue a reset. */
  3872. bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
  3873. /* Deposit a driver reset signature so the firmware knows that
  3874. * this is a soft reset. */
  3875. bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
  3876. BNX2_DRV_RESET_SIGNATURE_MAGIC);
  3877. /* Do a dummy read to force the chip to complete all current transaction
  3878. * before we issue a reset. */
  3879. val = REG_RD(bp, BNX2_MISC_ID);
  3880. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3881. REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
  3882. REG_RD(bp, BNX2_MISC_COMMAND);
  3883. udelay(5);
  3884. val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  3885. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  3886. pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
  3887. } else {
  3888. val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3889. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  3890. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  3891. /* Chip reset. */
  3892. REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
  3893. /* Reading back any register after chip reset will hang the
  3894. * bus on 5706 A0 and A1. The msleep below provides plenty
  3895. * of margin for write posting.
  3896. */
  3897. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  3898. (CHIP_ID(bp) == CHIP_ID_5706_A1))
  3899. msleep(20);
  3900. /* Reset takes approximate 30 usec */
  3901. for (i = 0; i < 10; i++) {
  3902. val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
  3903. if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3904. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
  3905. break;
  3906. udelay(10);
  3907. }
  3908. if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3909. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
  3910. pr_err("Chip reset did not complete\n");
  3911. return -EBUSY;
  3912. }
  3913. }
  3914. /* Make sure byte swapping is properly configured. */
  3915. val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
  3916. if (val != 0x01020304) {
  3917. pr_err("Chip not in correct endian mode\n");
  3918. return -ENODEV;
  3919. }
  3920. /* Wait for the firmware to finish its initialization. */
  3921. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
  3922. if (rc)
  3923. return rc;
  3924. spin_lock_bh(&bp->phy_lock);
  3925. old_port = bp->phy_port;
  3926. bnx2_init_fw_cap(bp);
  3927. if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
  3928. old_port != bp->phy_port)
  3929. bnx2_set_default_remote_link(bp);
  3930. spin_unlock_bh(&bp->phy_lock);
  3931. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  3932. /* Adjust the voltage regular to two steps lower. The default
  3933. * of this register is 0x0000000e. */
  3934. REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
  3935. /* Remove bad rbuf memory from the free pool. */
  3936. rc = bnx2_alloc_bad_rbuf(bp);
  3937. }
  3938. if (bp->flags & BNX2_FLAG_USING_MSIX) {
  3939. bnx2_setup_msix_tbl(bp);
  3940. /* Prevent MSIX table reads and write from timing out */
  3941. REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
  3942. BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
  3943. }
  3944. return rc;
  3945. }
  3946. static int
  3947. bnx2_init_chip(struct bnx2 *bp)
  3948. {
  3949. u32 val, mtu;
  3950. int rc, i;
  3951. /* Make sure the interrupt is not active. */
  3952. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3953. val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
  3954. BNX2_DMA_CONFIG_DATA_WORD_SWAP |
  3955. #ifdef __BIG_ENDIAN
  3956. BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
  3957. #endif
  3958. BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
  3959. DMA_READ_CHANS << 12 |
  3960. DMA_WRITE_CHANS << 16;
  3961. val |= (0x2 << 20) | (1 << 11);
  3962. if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
  3963. val |= (1 << 23);
  3964. if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
  3965. (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
  3966. val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
  3967. REG_WR(bp, BNX2_DMA_CONFIG, val);
  3968. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  3969. val = REG_RD(bp, BNX2_TDMA_CONFIG);
  3970. val |= BNX2_TDMA_CONFIG_ONE_DMA;
  3971. REG_WR(bp, BNX2_TDMA_CONFIG, val);
  3972. }
  3973. if (bp->flags & BNX2_FLAG_PCIX) {
  3974. u16 val16;
  3975. pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  3976. &val16);
  3977. pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  3978. val16 & ~PCI_X_CMD_ERO);
  3979. }
  3980. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  3981. BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
  3982. BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
  3983. BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
  3984. /* Initialize context mapping and zero out the quick contexts. The
  3985. * context block must have already been enabled. */
  3986. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3987. rc = bnx2_init_5709_context(bp);
  3988. if (rc)
  3989. return rc;
  3990. } else
  3991. bnx2_init_context(bp);
  3992. if ((rc = bnx2_init_cpus(bp)) != 0)
  3993. return rc;
  3994. bnx2_init_nvram(bp);
  3995. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  3996. val = REG_RD(bp, BNX2_MQ_CONFIG);
  3997. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3998. val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
  3999. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  4000. val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
  4001. if (CHIP_REV(bp) == CHIP_REV_Ax)
  4002. val |= BNX2_MQ_CONFIG_HALT_DIS;
  4003. }
  4004. REG_WR(bp, BNX2_MQ_CONFIG, val);
  4005. val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
  4006. REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
  4007. REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
  4008. val = (BCM_PAGE_BITS - 8) << 24;
  4009. REG_WR(bp, BNX2_RV2P_CONFIG, val);
  4010. /* Configure page size. */
  4011. val = REG_RD(bp, BNX2_TBDR_CONFIG);
  4012. val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
  4013. val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
  4014. REG_WR(bp, BNX2_TBDR_CONFIG, val);
  4015. val = bp->mac_addr[0] +
  4016. (bp->mac_addr[1] << 8) +
  4017. (bp->mac_addr[2] << 16) +
  4018. bp->mac_addr[3] +
  4019. (bp->mac_addr[4] << 8) +
  4020. (bp->mac_addr[5] << 16);
  4021. REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
  4022. /* Program the MTU. Also include 4 bytes for CRC32. */
  4023. mtu = bp->dev->mtu;
  4024. val = mtu + ETH_HLEN + ETH_FCS_LEN;
  4025. if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
  4026. val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
  4027. REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
  4028. if (mtu < 1500)
  4029. mtu = 1500;
  4030. bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
  4031. bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
  4032. bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
  4033. memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
  4034. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
  4035. bp->bnx2_napi[i].last_status_idx = 0;
  4036. bp->idle_chk_status_idx = 0xffff;
  4037. bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
  4038. /* Set up how to generate a link change interrupt. */
  4039. REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  4040. REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
  4041. (u64) bp->status_blk_mapping & 0xffffffff);
  4042. REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
  4043. REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
  4044. (u64) bp->stats_blk_mapping & 0xffffffff);
  4045. REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
  4046. (u64) bp->stats_blk_mapping >> 32);
  4047. REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
  4048. (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
  4049. REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
  4050. (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
  4051. REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
  4052. (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
  4053. REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
  4054. REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
  4055. REG_WR(bp, BNX2_HC_COM_TICKS,
  4056. (bp->com_ticks_int << 16) | bp->com_ticks);
  4057. REG_WR(bp, BNX2_HC_CMD_TICKS,
  4058. (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
  4059. if (bp->flags & BNX2_FLAG_BROKEN_STATS)
  4060. REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
  4061. else
  4062. REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
  4063. REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
  4064. if (CHIP_ID(bp) == CHIP_ID_5706_A1)
  4065. val = BNX2_HC_CONFIG_COLLECT_STATS;
  4066. else {
  4067. val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
  4068. BNX2_HC_CONFIG_COLLECT_STATS;
  4069. }
  4070. if (bp->flags & BNX2_FLAG_USING_MSIX) {
  4071. REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
  4072. BNX2_HC_MSIX_BIT_VECTOR_VAL);
  4073. val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
  4074. }
  4075. if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
  4076. val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
  4077. REG_WR(bp, BNX2_HC_CONFIG, val);
  4078. for (i = 1; i < bp->irq_nvecs; i++) {
  4079. u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  4080. BNX2_HC_SB_CONFIG_1;
  4081. REG_WR(bp, base,
  4082. BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
  4083. BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
  4084. BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  4085. REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
  4086. (bp->tx_quick_cons_trip_int << 16) |
  4087. bp->tx_quick_cons_trip);
  4088. REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
  4089. (bp->tx_ticks_int << 16) | bp->tx_ticks);
  4090. REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
  4091. (bp->rx_quick_cons_trip_int << 16) |
  4092. bp->rx_quick_cons_trip);
  4093. REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
  4094. (bp->rx_ticks_int << 16) | bp->rx_ticks);
  4095. }
  4096. /* Clear internal stats counters. */
  4097. REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
  4098. REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
  4099. /* Initialize the receive filter. */
  4100. bnx2_set_rx_mode(bp->dev);
  4101. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  4102. val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
  4103. val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
  4104. REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
  4105. }
  4106. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
  4107. 1, 0);
  4108. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
  4109. REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
  4110. udelay(20);
  4111. bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
  4112. return rc;
  4113. }
  4114. static void
  4115. bnx2_clear_ring_states(struct bnx2 *bp)
  4116. {
  4117. struct bnx2_napi *bnapi;
  4118. struct bnx2_tx_ring_info *txr;
  4119. struct bnx2_rx_ring_info *rxr;
  4120. int i;
  4121. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
  4122. bnapi = &bp->bnx2_napi[i];
  4123. txr = &bnapi->tx_ring;
  4124. rxr = &bnapi->rx_ring;
  4125. txr->tx_cons = 0;
  4126. txr->hw_tx_cons = 0;
  4127. rxr->rx_prod_bseq = 0;
  4128. rxr->rx_prod = 0;
  4129. rxr->rx_cons = 0;
  4130. rxr->rx_pg_prod = 0;
  4131. rxr->rx_pg_cons = 0;
  4132. }
  4133. }
  4134. static void
  4135. bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
  4136. {
  4137. u32 val, offset0, offset1, offset2, offset3;
  4138. u32 cid_addr = GET_CID_ADDR(cid);
  4139. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  4140. offset0 = BNX2_L2CTX_TYPE_XI;
  4141. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  4142. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  4143. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  4144. } else {
  4145. offset0 = BNX2_L2CTX_TYPE;
  4146. offset1 = BNX2_L2CTX_CMD_TYPE;
  4147. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  4148. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  4149. }
  4150. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  4151. bnx2_ctx_wr(bp, cid_addr, offset0, val);
  4152. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  4153. bnx2_ctx_wr(bp, cid_addr, offset1, val);
  4154. val = (u64) txr->tx_desc_mapping >> 32;
  4155. bnx2_ctx_wr(bp, cid_addr, offset2, val);
  4156. val = (u64) txr->tx_desc_mapping & 0xffffffff;
  4157. bnx2_ctx_wr(bp, cid_addr, offset3, val);
  4158. }
  4159. static void
  4160. bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
  4161. {
  4162. struct tx_bd *txbd;
  4163. u32 cid = TX_CID;
  4164. struct bnx2_napi *bnapi;
  4165. struct bnx2_tx_ring_info *txr;
  4166. bnapi = &bp->bnx2_napi[ring_num];
  4167. txr = &bnapi->tx_ring;
  4168. if (ring_num == 0)
  4169. cid = TX_CID;
  4170. else
  4171. cid = TX_TSS_CID + ring_num - 1;
  4172. bp->tx_wake_thresh = bp->tx_ring_size / 2;
  4173. txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
  4174. txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
  4175. txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
  4176. txr->tx_prod = 0;
  4177. txr->tx_prod_bseq = 0;
  4178. txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
  4179. txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
  4180. bnx2_init_tx_context(bp, cid, txr);
  4181. }
  4182. static void
  4183. bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
  4184. int num_rings)
  4185. {
  4186. int i;
  4187. struct rx_bd *rxbd;
  4188. for (i = 0; i < num_rings; i++) {
  4189. int j;
  4190. rxbd = &rx_ring[i][0];
  4191. for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
  4192. rxbd->rx_bd_len = buf_size;
  4193. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  4194. }
  4195. if (i == (num_rings - 1))
  4196. j = 0;
  4197. else
  4198. j = i + 1;
  4199. rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
  4200. rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
  4201. }
  4202. }
  4203. static void
  4204. bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
  4205. {
  4206. int i;
  4207. u16 prod, ring_prod;
  4208. u32 cid, rx_cid_addr, val;
  4209. struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
  4210. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  4211. if (ring_num == 0)
  4212. cid = RX_CID;
  4213. else
  4214. cid = RX_RSS_CID + ring_num - 1;
  4215. rx_cid_addr = GET_CID_ADDR(cid);
  4216. bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
  4217. bp->rx_buf_use_size, bp->rx_max_ring);
  4218. bnx2_init_rx_context(bp, cid);
  4219. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  4220. val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
  4221. REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
  4222. }
  4223. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
  4224. if (bp->rx_pg_ring_size) {
  4225. bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
  4226. rxr->rx_pg_desc_mapping,
  4227. PAGE_SIZE, bp->rx_max_pg_ring);
  4228. val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
  4229. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
  4230. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
  4231. BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
  4232. val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
  4233. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
  4234. val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
  4235. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
  4236. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  4237. REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
  4238. }
  4239. val = (u64) rxr->rx_desc_mapping[0] >> 32;
  4240. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  4241. val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
  4242. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  4243. ring_prod = prod = rxr->rx_pg_prod;
  4244. for (i = 0; i < bp->rx_pg_ring_size; i++) {
  4245. if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
  4246. netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
  4247. ring_num, i, bp->rx_pg_ring_size);
  4248. break;
  4249. }
  4250. prod = NEXT_RX_BD(prod);
  4251. ring_prod = RX_PG_RING_IDX(prod);
  4252. }
  4253. rxr->rx_pg_prod = prod;
  4254. ring_prod = prod = rxr->rx_prod;
  4255. for (i = 0; i < bp->rx_ring_size; i++) {
  4256. if (bnx2_alloc_rx_skb(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
  4257. netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
  4258. ring_num, i, bp->rx_ring_size);
  4259. break;
  4260. }
  4261. prod = NEXT_RX_BD(prod);
  4262. ring_prod = RX_RING_IDX(prod);
  4263. }
  4264. rxr->rx_prod = prod;
  4265. rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
  4266. rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
  4267. rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
  4268. REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
  4269. REG_WR16(bp, rxr->rx_bidx_addr, prod);
  4270. REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
  4271. }
  4272. static void
  4273. bnx2_init_all_rings(struct bnx2 *bp)
  4274. {
  4275. int i;
  4276. u32 val;
  4277. bnx2_clear_ring_states(bp);
  4278. REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
  4279. for (i = 0; i < bp->num_tx_rings; i++)
  4280. bnx2_init_tx_ring(bp, i);
  4281. if (bp->num_tx_rings > 1)
  4282. REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
  4283. (TX_TSS_CID << 7));
  4284. REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
  4285. bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
  4286. for (i = 0; i < bp->num_rx_rings; i++)
  4287. bnx2_init_rx_ring(bp, i);
  4288. if (bp->num_rx_rings > 1) {
  4289. u32 tbl_32;
  4290. u8 *tbl = (u8 *) &tbl_32;
  4291. bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
  4292. BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
  4293. for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
  4294. tbl[i % 4] = i % (bp->num_rx_rings - 1);
  4295. if ((i % 4) == 3)
  4296. bnx2_reg_wr_ind(bp,
  4297. BNX2_RXP_SCRATCH_RSS_TBL + i,
  4298. cpu_to_be32(tbl_32));
  4299. }
  4300. val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
  4301. BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
  4302. REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
  4303. }
  4304. }
  4305. static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
  4306. {
  4307. u32 max, num_rings = 1;
  4308. while (ring_size > MAX_RX_DESC_CNT) {
  4309. ring_size -= MAX_RX_DESC_CNT;
  4310. num_rings++;
  4311. }
  4312. /* round to next power of 2 */
  4313. max = max_size;
  4314. while ((max & num_rings) == 0)
  4315. max >>= 1;
  4316. if (num_rings != max)
  4317. max <<= 1;
  4318. return max;
  4319. }
  4320. static void
  4321. bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
  4322. {
  4323. u32 rx_size, rx_space, jumbo_size;
  4324. /* 8 for CRC and VLAN */
  4325. rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
  4326. rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
  4327. sizeof(struct skb_shared_info);
  4328. bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
  4329. bp->rx_pg_ring_size = 0;
  4330. bp->rx_max_pg_ring = 0;
  4331. bp->rx_max_pg_ring_idx = 0;
  4332. if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
  4333. int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
  4334. jumbo_size = size * pages;
  4335. if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
  4336. jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
  4337. bp->rx_pg_ring_size = jumbo_size;
  4338. bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
  4339. MAX_RX_PG_RINGS);
  4340. bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
  4341. rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
  4342. bp->rx_copy_thresh = 0;
  4343. }
  4344. bp->rx_buf_use_size = rx_size;
  4345. /* hw alignment */
  4346. bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
  4347. bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
  4348. bp->rx_ring_size = size;
  4349. bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
  4350. bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
  4351. }
  4352. static void
  4353. bnx2_free_tx_skbs(struct bnx2 *bp)
  4354. {
  4355. int i;
  4356. for (i = 0; i < bp->num_tx_rings; i++) {
  4357. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  4358. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  4359. int j;
  4360. if (txr->tx_buf_ring == NULL)
  4361. continue;
  4362. for (j = 0; j < TX_DESC_CNT; ) {
  4363. struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
  4364. struct sk_buff *skb = tx_buf->skb;
  4365. int k, last;
  4366. if (skb == NULL) {
  4367. j++;
  4368. continue;
  4369. }
  4370. dma_unmap_single(&bp->pdev->dev,
  4371. dma_unmap_addr(tx_buf, mapping),
  4372. skb_headlen(skb),
  4373. PCI_DMA_TODEVICE);
  4374. tx_buf->skb = NULL;
  4375. last = tx_buf->nr_frags;
  4376. j++;
  4377. for (k = 0; k < last; k++, j++) {
  4378. tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
  4379. dma_unmap_page(&bp->pdev->dev,
  4380. dma_unmap_addr(tx_buf, mapping),
  4381. skb_shinfo(skb)->frags[k].size,
  4382. PCI_DMA_TODEVICE);
  4383. }
  4384. dev_kfree_skb(skb);
  4385. }
  4386. }
  4387. }
  4388. static void
  4389. bnx2_free_rx_skbs(struct bnx2 *bp)
  4390. {
  4391. int i;
  4392. for (i = 0; i < bp->num_rx_rings; i++) {
  4393. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  4394. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  4395. int j;
  4396. if (rxr->rx_buf_ring == NULL)
  4397. return;
  4398. for (j = 0; j < bp->rx_max_ring_idx; j++) {
  4399. struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
  4400. struct sk_buff *skb = rx_buf->skb;
  4401. if (skb == NULL)
  4402. continue;
  4403. dma_unmap_single(&bp->pdev->dev,
  4404. dma_unmap_addr(rx_buf, mapping),
  4405. bp->rx_buf_use_size,
  4406. PCI_DMA_FROMDEVICE);
  4407. rx_buf->skb = NULL;
  4408. dev_kfree_skb(skb);
  4409. }
  4410. for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
  4411. bnx2_free_rx_page(bp, rxr, j);
  4412. }
  4413. }
  4414. static void
  4415. bnx2_free_skbs(struct bnx2 *bp)
  4416. {
  4417. bnx2_free_tx_skbs(bp);
  4418. bnx2_free_rx_skbs(bp);
  4419. }
  4420. static int
  4421. bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
  4422. {
  4423. int rc;
  4424. rc = bnx2_reset_chip(bp, reset_code);
  4425. bnx2_free_skbs(bp);
  4426. if (rc)
  4427. return rc;
  4428. if ((rc = bnx2_init_chip(bp)) != 0)
  4429. return rc;
  4430. bnx2_init_all_rings(bp);
  4431. return 0;
  4432. }
  4433. static int
  4434. bnx2_init_nic(struct bnx2 *bp, int reset_phy)
  4435. {
  4436. int rc;
  4437. if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
  4438. return rc;
  4439. spin_lock_bh(&bp->phy_lock);
  4440. bnx2_init_phy(bp, reset_phy);
  4441. bnx2_set_link(bp);
  4442. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  4443. bnx2_remote_phy_event(bp);
  4444. spin_unlock_bh(&bp->phy_lock);
  4445. return 0;
  4446. }
  4447. static int
  4448. bnx2_shutdown_chip(struct bnx2 *bp)
  4449. {
  4450. u32 reset_code;
  4451. if (bp->flags & BNX2_FLAG_NO_WOL)
  4452. reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
  4453. else if (bp->wol)
  4454. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  4455. else
  4456. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  4457. return bnx2_reset_chip(bp, reset_code);
  4458. }
  4459. static int
  4460. bnx2_test_registers(struct bnx2 *bp)
  4461. {
  4462. int ret;
  4463. int i, is_5709;
  4464. static const struct {
  4465. u16 offset;
  4466. u16 flags;
  4467. #define BNX2_FL_NOT_5709 1
  4468. u32 rw_mask;
  4469. u32 ro_mask;
  4470. } reg_tbl[] = {
  4471. { 0x006c, 0, 0x00000000, 0x0000003f },
  4472. { 0x0090, 0, 0xffffffff, 0x00000000 },
  4473. { 0x0094, 0, 0x00000000, 0x00000000 },
  4474. { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
  4475. { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4476. { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4477. { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
  4478. { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
  4479. { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
  4480. { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
  4481. { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4482. { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4483. { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4484. { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4485. { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4486. { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4487. { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4488. { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4489. { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
  4490. { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
  4491. { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
  4492. { 0x1000, 0, 0x00000000, 0x00000001 },
  4493. { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
  4494. { 0x1408, 0, 0x01c00800, 0x00000000 },
  4495. { 0x149c, 0, 0x8000ffff, 0x00000000 },
  4496. { 0x14a8, 0, 0x00000000, 0x000001ff },
  4497. { 0x14ac, 0, 0x0fffffff, 0x10000000 },
  4498. { 0x14b0, 0, 0x00000002, 0x00000001 },
  4499. { 0x14b8, 0, 0x00000000, 0x00000000 },
  4500. { 0x14c0, 0, 0x00000000, 0x00000009 },
  4501. { 0x14c4, 0, 0x00003fff, 0x00000000 },
  4502. { 0x14cc, 0, 0x00000000, 0x00000001 },
  4503. { 0x14d0, 0, 0xffffffff, 0x00000000 },
  4504. { 0x1800, 0, 0x00000000, 0x00000001 },
  4505. { 0x1804, 0, 0x00000000, 0x00000003 },
  4506. { 0x2800, 0, 0x00000000, 0x00000001 },
  4507. { 0x2804, 0, 0x00000000, 0x00003f01 },
  4508. { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
  4509. { 0x2810, 0, 0xffff0000, 0x00000000 },
  4510. { 0x2814, 0, 0xffff0000, 0x00000000 },
  4511. { 0x2818, 0, 0xffff0000, 0x00000000 },
  4512. { 0x281c, 0, 0xffff0000, 0x00000000 },
  4513. { 0x2834, 0, 0xffffffff, 0x00000000 },
  4514. { 0x2840, 0, 0x00000000, 0xffffffff },
  4515. { 0x2844, 0, 0x00000000, 0xffffffff },
  4516. { 0x2848, 0, 0xffffffff, 0x00000000 },
  4517. { 0x284c, 0, 0xf800f800, 0x07ff07ff },
  4518. { 0x2c00, 0, 0x00000000, 0x00000011 },
  4519. { 0x2c04, 0, 0x00000000, 0x00030007 },
  4520. { 0x3c00, 0, 0x00000000, 0x00000001 },
  4521. { 0x3c04, 0, 0x00000000, 0x00070000 },
  4522. { 0x3c08, 0, 0x00007f71, 0x07f00000 },
  4523. { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
  4524. { 0x3c10, 0, 0xffffffff, 0x00000000 },
  4525. { 0x3c14, 0, 0x00000000, 0xffffffff },
  4526. { 0x3c18, 0, 0x00000000, 0xffffffff },
  4527. { 0x3c1c, 0, 0xfffff000, 0x00000000 },
  4528. { 0x3c20, 0, 0xffffff00, 0x00000000 },
  4529. { 0x5004, 0, 0x00000000, 0x0000007f },
  4530. { 0x5008, 0, 0x0f0007ff, 0x00000000 },
  4531. { 0x5c00, 0, 0x00000000, 0x00000001 },
  4532. { 0x5c04, 0, 0x00000000, 0x0003000f },
  4533. { 0x5c08, 0, 0x00000003, 0x00000000 },
  4534. { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
  4535. { 0x5c10, 0, 0x00000000, 0xffffffff },
  4536. { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
  4537. { 0x5c84, 0, 0x00000000, 0x0000f333 },
  4538. { 0x5c88, 0, 0x00000000, 0x00077373 },
  4539. { 0x5c8c, 0, 0x00000000, 0x0007f737 },
  4540. { 0x6808, 0, 0x0000ff7f, 0x00000000 },
  4541. { 0x680c, 0, 0xffffffff, 0x00000000 },
  4542. { 0x6810, 0, 0xffffffff, 0x00000000 },
  4543. { 0x6814, 0, 0xffffffff, 0x00000000 },
  4544. { 0x6818, 0, 0xffffffff, 0x00000000 },
  4545. { 0x681c, 0, 0xffffffff, 0x00000000 },
  4546. { 0x6820, 0, 0x00ff00ff, 0x00000000 },
  4547. { 0x6824, 0, 0x00ff00ff, 0x00000000 },
  4548. { 0x6828, 0, 0x00ff00ff, 0x00000000 },
  4549. { 0x682c, 0, 0x03ff03ff, 0x00000000 },
  4550. { 0x6830, 0, 0x03ff03ff, 0x00000000 },
  4551. { 0x6834, 0, 0x03ff03ff, 0x00000000 },
  4552. { 0x6838, 0, 0x03ff03ff, 0x00000000 },
  4553. { 0x683c, 0, 0x0000ffff, 0x00000000 },
  4554. { 0x6840, 0, 0x00000ff0, 0x00000000 },
  4555. { 0x6844, 0, 0x00ffff00, 0x00000000 },
  4556. { 0x684c, 0, 0xffffffff, 0x00000000 },
  4557. { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
  4558. { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
  4559. { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
  4560. { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
  4561. { 0x6908, 0, 0x00000000, 0x0001ff0f },
  4562. { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
  4563. { 0xffff, 0, 0x00000000, 0x00000000 },
  4564. };
  4565. ret = 0;
  4566. is_5709 = 0;
  4567. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  4568. is_5709 = 1;
  4569. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  4570. u32 offset, rw_mask, ro_mask, save_val, val;
  4571. u16 flags = reg_tbl[i].flags;
  4572. if (is_5709 && (flags & BNX2_FL_NOT_5709))
  4573. continue;
  4574. offset = (u32) reg_tbl[i].offset;
  4575. rw_mask = reg_tbl[i].rw_mask;
  4576. ro_mask = reg_tbl[i].ro_mask;
  4577. save_val = readl(bp->regview + offset);
  4578. writel(0, bp->regview + offset);
  4579. val = readl(bp->regview + offset);
  4580. if ((val & rw_mask) != 0) {
  4581. goto reg_test_err;
  4582. }
  4583. if ((val & ro_mask) != (save_val & ro_mask)) {
  4584. goto reg_test_err;
  4585. }
  4586. writel(0xffffffff, bp->regview + offset);
  4587. val = readl(bp->regview + offset);
  4588. if ((val & rw_mask) != rw_mask) {
  4589. goto reg_test_err;
  4590. }
  4591. if ((val & ro_mask) != (save_val & ro_mask)) {
  4592. goto reg_test_err;
  4593. }
  4594. writel(save_val, bp->regview + offset);
  4595. continue;
  4596. reg_test_err:
  4597. writel(save_val, bp->regview + offset);
  4598. ret = -ENODEV;
  4599. break;
  4600. }
  4601. return ret;
  4602. }
  4603. static int
  4604. bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
  4605. {
  4606. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
  4607. 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
  4608. int i;
  4609. for (i = 0; i < sizeof(test_pattern) / 4; i++) {
  4610. u32 offset;
  4611. for (offset = 0; offset < size; offset += 4) {
  4612. bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
  4613. if (bnx2_reg_rd_ind(bp, start + offset) !=
  4614. test_pattern[i]) {
  4615. return -ENODEV;
  4616. }
  4617. }
  4618. }
  4619. return 0;
  4620. }
  4621. static int
  4622. bnx2_test_memory(struct bnx2 *bp)
  4623. {
  4624. int ret = 0;
  4625. int i;
  4626. static struct mem_entry {
  4627. u32 offset;
  4628. u32 len;
  4629. } mem_tbl_5706[] = {
  4630. { 0x60000, 0x4000 },
  4631. { 0xa0000, 0x3000 },
  4632. { 0xe0000, 0x4000 },
  4633. { 0x120000, 0x4000 },
  4634. { 0x1a0000, 0x4000 },
  4635. { 0x160000, 0x4000 },
  4636. { 0xffffffff, 0 },
  4637. },
  4638. mem_tbl_5709[] = {
  4639. { 0x60000, 0x4000 },
  4640. { 0xa0000, 0x3000 },
  4641. { 0xe0000, 0x4000 },
  4642. { 0x120000, 0x4000 },
  4643. { 0x1a0000, 0x4000 },
  4644. { 0xffffffff, 0 },
  4645. };
  4646. struct mem_entry *mem_tbl;
  4647. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  4648. mem_tbl = mem_tbl_5709;
  4649. else
  4650. mem_tbl = mem_tbl_5706;
  4651. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  4652. if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
  4653. mem_tbl[i].len)) != 0) {
  4654. return ret;
  4655. }
  4656. }
  4657. return ret;
  4658. }
  4659. #define BNX2_MAC_LOOPBACK 0
  4660. #define BNX2_PHY_LOOPBACK 1
  4661. static int
  4662. bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
  4663. {
  4664. unsigned int pkt_size, num_pkts, i;
  4665. struct sk_buff *skb, *rx_skb;
  4666. unsigned char *packet;
  4667. u16 rx_start_idx, rx_idx;
  4668. dma_addr_t map;
  4669. struct tx_bd *txbd;
  4670. struct sw_bd *rx_buf;
  4671. struct l2_fhdr *rx_hdr;
  4672. int ret = -ENODEV;
  4673. struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
  4674. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  4675. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  4676. tx_napi = bnapi;
  4677. txr = &tx_napi->tx_ring;
  4678. rxr = &bnapi->rx_ring;
  4679. if (loopback_mode == BNX2_MAC_LOOPBACK) {
  4680. bp->loopback = MAC_LOOPBACK;
  4681. bnx2_set_mac_loopback(bp);
  4682. }
  4683. else if (loopback_mode == BNX2_PHY_LOOPBACK) {
  4684. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  4685. return 0;
  4686. bp->loopback = PHY_LOOPBACK;
  4687. bnx2_set_phy_loopback(bp);
  4688. }
  4689. else
  4690. return -EINVAL;
  4691. pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
  4692. skb = netdev_alloc_skb(bp->dev, pkt_size);
  4693. if (!skb)
  4694. return -ENOMEM;
  4695. packet = skb_put(skb, pkt_size);
  4696. memcpy(packet, bp->dev->dev_addr, 6);
  4697. memset(packet + 6, 0x0, 8);
  4698. for (i = 14; i < pkt_size; i++)
  4699. packet[i] = (unsigned char) (i & 0xff);
  4700. map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
  4701. PCI_DMA_TODEVICE);
  4702. if (dma_mapping_error(&bp->pdev->dev, map)) {
  4703. dev_kfree_skb(skb);
  4704. return -EIO;
  4705. }
  4706. REG_WR(bp, BNX2_HC_COMMAND,
  4707. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  4708. REG_RD(bp, BNX2_HC_COMMAND);
  4709. udelay(5);
  4710. rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
  4711. num_pkts = 0;
  4712. txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
  4713. txbd->tx_bd_haddr_hi = (u64) map >> 32;
  4714. txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
  4715. txbd->tx_bd_mss_nbytes = pkt_size;
  4716. txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
  4717. num_pkts++;
  4718. txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
  4719. txr->tx_prod_bseq += pkt_size;
  4720. REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
  4721. REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
  4722. udelay(100);
  4723. REG_WR(bp, BNX2_HC_COMMAND,
  4724. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  4725. REG_RD(bp, BNX2_HC_COMMAND);
  4726. udelay(5);
  4727. dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
  4728. dev_kfree_skb(skb);
  4729. if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
  4730. goto loopback_test_done;
  4731. rx_idx = bnx2_get_hw_rx_cons(bnapi);
  4732. if (rx_idx != rx_start_idx + num_pkts) {
  4733. goto loopback_test_done;
  4734. }
  4735. rx_buf = &rxr->rx_buf_ring[rx_start_idx];
  4736. rx_skb = rx_buf->skb;
  4737. rx_hdr = rx_buf->desc;
  4738. skb_reserve(rx_skb, BNX2_RX_OFFSET);
  4739. dma_sync_single_for_cpu(&bp->pdev->dev,
  4740. dma_unmap_addr(rx_buf, mapping),
  4741. bp->rx_buf_size, PCI_DMA_FROMDEVICE);
  4742. if (rx_hdr->l2_fhdr_status &
  4743. (L2_FHDR_ERRORS_BAD_CRC |
  4744. L2_FHDR_ERRORS_PHY_DECODE |
  4745. L2_FHDR_ERRORS_ALIGNMENT |
  4746. L2_FHDR_ERRORS_TOO_SHORT |
  4747. L2_FHDR_ERRORS_GIANT_FRAME)) {
  4748. goto loopback_test_done;
  4749. }
  4750. if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
  4751. goto loopback_test_done;
  4752. }
  4753. for (i = 14; i < pkt_size; i++) {
  4754. if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
  4755. goto loopback_test_done;
  4756. }
  4757. }
  4758. ret = 0;
  4759. loopback_test_done:
  4760. bp->loopback = 0;
  4761. return ret;
  4762. }
  4763. #define BNX2_MAC_LOOPBACK_FAILED 1
  4764. #define BNX2_PHY_LOOPBACK_FAILED 2
  4765. #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
  4766. BNX2_PHY_LOOPBACK_FAILED)
  4767. static int
  4768. bnx2_test_loopback(struct bnx2 *bp)
  4769. {
  4770. int rc = 0;
  4771. if (!netif_running(bp->dev))
  4772. return BNX2_LOOPBACK_FAILED;
  4773. bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
  4774. spin_lock_bh(&bp->phy_lock);
  4775. bnx2_init_phy(bp, 1);
  4776. spin_unlock_bh(&bp->phy_lock);
  4777. if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
  4778. rc |= BNX2_MAC_LOOPBACK_FAILED;
  4779. if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
  4780. rc |= BNX2_PHY_LOOPBACK_FAILED;
  4781. return rc;
  4782. }
  4783. #define NVRAM_SIZE 0x200
  4784. #define CRC32_RESIDUAL 0xdebb20e3
  4785. static int
  4786. bnx2_test_nvram(struct bnx2 *bp)
  4787. {
  4788. __be32 buf[NVRAM_SIZE / 4];
  4789. u8 *data = (u8 *) buf;
  4790. int rc = 0;
  4791. u32 magic, csum;
  4792. if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
  4793. goto test_nvram_done;
  4794. magic = be32_to_cpu(buf[0]);
  4795. if (magic != 0x669955aa) {
  4796. rc = -ENODEV;
  4797. goto test_nvram_done;
  4798. }
  4799. if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
  4800. goto test_nvram_done;
  4801. csum = ether_crc_le(0x100, data);
  4802. if (csum != CRC32_RESIDUAL) {
  4803. rc = -ENODEV;
  4804. goto test_nvram_done;
  4805. }
  4806. csum = ether_crc_le(0x100, data + 0x100);
  4807. if (csum != CRC32_RESIDUAL) {
  4808. rc = -ENODEV;
  4809. }
  4810. test_nvram_done:
  4811. return rc;
  4812. }
  4813. static int
  4814. bnx2_test_link(struct bnx2 *bp)
  4815. {
  4816. u32 bmsr;
  4817. if (!netif_running(bp->dev))
  4818. return -ENODEV;
  4819. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  4820. if (bp->link_up)
  4821. return 0;
  4822. return -ENODEV;
  4823. }
  4824. spin_lock_bh(&bp->phy_lock);
  4825. bnx2_enable_bmsr1(bp);
  4826. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  4827. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  4828. bnx2_disable_bmsr1(bp);
  4829. spin_unlock_bh(&bp->phy_lock);
  4830. if (bmsr & BMSR_LSTATUS) {
  4831. return 0;
  4832. }
  4833. return -ENODEV;
  4834. }
  4835. static int
  4836. bnx2_test_intr(struct bnx2 *bp)
  4837. {
  4838. int i;
  4839. u16 status_idx;
  4840. if (!netif_running(bp->dev))
  4841. return -ENODEV;
  4842. status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
  4843. /* This register is not touched during run-time. */
  4844. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
  4845. REG_RD(bp, BNX2_HC_COMMAND);
  4846. for (i = 0; i < 10; i++) {
  4847. if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
  4848. status_idx) {
  4849. break;
  4850. }
  4851. msleep_interruptible(10);
  4852. }
  4853. if (i < 10)
  4854. return 0;
  4855. return -ENODEV;
  4856. }
  4857. /* Determining link for parallel detection. */
  4858. static int
  4859. bnx2_5706_serdes_has_link(struct bnx2 *bp)
  4860. {
  4861. u32 mode_ctl, an_dbg, exp;
  4862. if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
  4863. return 0;
  4864. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
  4865. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
  4866. if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
  4867. return 0;
  4868. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  4869. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  4870. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  4871. if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
  4872. return 0;
  4873. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
  4874. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
  4875. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
  4876. if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
  4877. return 0;
  4878. return 1;
  4879. }
  4880. static void
  4881. bnx2_5706_serdes_timer(struct bnx2 *bp)
  4882. {
  4883. int check_link = 1;
  4884. spin_lock(&bp->phy_lock);
  4885. if (bp->serdes_an_pending) {
  4886. bp->serdes_an_pending--;
  4887. check_link = 0;
  4888. } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
  4889. u32 bmcr;
  4890. bp->current_interval = BNX2_TIMER_INTERVAL;
  4891. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  4892. if (bmcr & BMCR_ANENABLE) {
  4893. if (bnx2_5706_serdes_has_link(bp)) {
  4894. bmcr &= ~BMCR_ANENABLE;
  4895. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  4896. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  4897. bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
  4898. }
  4899. }
  4900. }
  4901. else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
  4902. (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
  4903. u32 phy2;
  4904. bnx2_write_phy(bp, 0x17, 0x0f01);
  4905. bnx2_read_phy(bp, 0x15, &phy2);
  4906. if (phy2 & 0x20) {
  4907. u32 bmcr;
  4908. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  4909. bmcr |= BMCR_ANENABLE;
  4910. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  4911. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  4912. }
  4913. } else
  4914. bp->current_interval = BNX2_TIMER_INTERVAL;
  4915. if (check_link) {
  4916. u32 val;
  4917. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  4918. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
  4919. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
  4920. if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
  4921. if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
  4922. bnx2_5706s_force_link_dn(bp, 1);
  4923. bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
  4924. } else
  4925. bnx2_set_link(bp);
  4926. } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
  4927. bnx2_set_link(bp);
  4928. }
  4929. spin_unlock(&bp->phy_lock);
  4930. }
  4931. static void
  4932. bnx2_5708_serdes_timer(struct bnx2 *bp)
  4933. {
  4934. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  4935. return;
  4936. if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
  4937. bp->serdes_an_pending = 0;
  4938. return;
  4939. }
  4940. spin_lock(&bp->phy_lock);
  4941. if (bp->serdes_an_pending)
  4942. bp->serdes_an_pending--;
  4943. else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
  4944. u32 bmcr;
  4945. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  4946. if (bmcr & BMCR_ANENABLE) {
  4947. bnx2_enable_forced_2g5(bp);
  4948. bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
  4949. } else {
  4950. bnx2_disable_forced_2g5(bp);
  4951. bp->serdes_an_pending = 2;
  4952. bp->current_interval = BNX2_TIMER_INTERVAL;
  4953. }
  4954. } else
  4955. bp->current_interval = BNX2_TIMER_INTERVAL;
  4956. spin_unlock(&bp->phy_lock);
  4957. }
  4958. static void
  4959. bnx2_timer(unsigned long data)
  4960. {
  4961. struct bnx2 *bp = (struct bnx2 *) data;
  4962. if (!netif_running(bp->dev))
  4963. return;
  4964. if (atomic_read(&bp->intr_sem) != 0)
  4965. goto bnx2_restart_timer;
  4966. if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
  4967. BNX2_FLAG_USING_MSI)
  4968. bnx2_chk_missed_msi(bp);
  4969. bnx2_send_heart_beat(bp);
  4970. bp->stats_blk->stat_FwRxDrop =
  4971. bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
  4972. /* workaround occasional corrupted counters */
  4973. if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
  4974. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
  4975. BNX2_HC_COMMAND_STATS_NOW);
  4976. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  4977. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  4978. bnx2_5706_serdes_timer(bp);
  4979. else
  4980. bnx2_5708_serdes_timer(bp);
  4981. }
  4982. bnx2_restart_timer:
  4983. mod_timer(&bp->timer, jiffies + bp->current_interval);
  4984. }
  4985. static int
  4986. bnx2_request_irq(struct bnx2 *bp)
  4987. {
  4988. unsigned long flags;
  4989. struct bnx2_irq *irq;
  4990. int rc = 0, i;
  4991. if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
  4992. flags = 0;
  4993. else
  4994. flags = IRQF_SHARED;
  4995. for (i = 0; i < bp->irq_nvecs; i++) {
  4996. irq = &bp->irq_tbl[i];
  4997. rc = request_irq(irq->vector, irq->handler, flags, irq->name,
  4998. &bp->bnx2_napi[i]);
  4999. if (rc)
  5000. break;
  5001. irq->requested = 1;
  5002. }
  5003. return rc;
  5004. }
  5005. static void
  5006. bnx2_free_irq(struct bnx2 *bp)
  5007. {
  5008. struct bnx2_irq *irq;
  5009. int i;
  5010. for (i = 0; i < bp->irq_nvecs; i++) {
  5011. irq = &bp->irq_tbl[i];
  5012. if (irq->requested)
  5013. free_irq(irq->vector, &bp->bnx2_napi[i]);
  5014. irq->requested = 0;
  5015. }
  5016. if (bp->flags & BNX2_FLAG_USING_MSI)
  5017. pci_disable_msi(bp->pdev);
  5018. else if (bp->flags & BNX2_FLAG_USING_MSIX)
  5019. pci_disable_msix(bp->pdev);
  5020. bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
  5021. }
  5022. static void
  5023. bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
  5024. {
  5025. int i, total_vecs, rc;
  5026. struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
  5027. struct net_device *dev = bp->dev;
  5028. const int len = sizeof(bp->irq_tbl[0].name);
  5029. bnx2_setup_msix_tbl(bp);
  5030. REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
  5031. REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
  5032. REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
  5033. /* Need to flush the previous three writes to ensure MSI-X
  5034. * is setup properly */
  5035. REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
  5036. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
  5037. msix_ent[i].entry = i;
  5038. msix_ent[i].vector = 0;
  5039. }
  5040. total_vecs = msix_vecs;
  5041. #ifdef BCM_CNIC
  5042. total_vecs++;
  5043. #endif
  5044. rc = -ENOSPC;
  5045. while (total_vecs >= BNX2_MIN_MSIX_VEC) {
  5046. rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
  5047. if (rc <= 0)
  5048. break;
  5049. if (rc > 0)
  5050. total_vecs = rc;
  5051. }
  5052. if (rc != 0)
  5053. return;
  5054. msix_vecs = total_vecs;
  5055. #ifdef BCM_CNIC
  5056. msix_vecs--;
  5057. #endif
  5058. bp->irq_nvecs = msix_vecs;
  5059. bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
  5060. for (i = 0; i < total_vecs; i++) {
  5061. bp->irq_tbl[i].vector = msix_ent[i].vector;
  5062. snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
  5063. bp->irq_tbl[i].handler = bnx2_msi_1shot;
  5064. }
  5065. }
  5066. static void
  5067. bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
  5068. {
  5069. int cpus = num_online_cpus();
  5070. int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
  5071. bp->irq_tbl[0].handler = bnx2_interrupt;
  5072. strcpy(bp->irq_tbl[0].name, bp->dev->name);
  5073. bp->irq_nvecs = 1;
  5074. bp->irq_tbl[0].vector = bp->pdev->irq;
  5075. if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
  5076. bnx2_enable_msix(bp, msix_vecs);
  5077. if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
  5078. !(bp->flags & BNX2_FLAG_USING_MSIX)) {
  5079. if (pci_enable_msi(bp->pdev) == 0) {
  5080. bp->flags |= BNX2_FLAG_USING_MSI;
  5081. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  5082. bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
  5083. bp->irq_tbl[0].handler = bnx2_msi_1shot;
  5084. } else
  5085. bp->irq_tbl[0].handler = bnx2_msi;
  5086. bp->irq_tbl[0].vector = bp->pdev->irq;
  5087. }
  5088. }
  5089. bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
  5090. bp->dev->real_num_tx_queues = bp->num_tx_rings;
  5091. bp->num_rx_rings = bp->irq_nvecs;
  5092. }
  5093. /* Called with rtnl_lock */
  5094. static int
  5095. bnx2_open(struct net_device *dev)
  5096. {
  5097. struct bnx2 *bp = netdev_priv(dev);
  5098. int rc;
  5099. netif_carrier_off(dev);
  5100. bnx2_set_power_state(bp, PCI_D0);
  5101. bnx2_disable_int(bp);
  5102. bnx2_setup_int_mode(bp, disable_msi);
  5103. bnx2_init_napi(bp);
  5104. bnx2_napi_enable(bp);
  5105. rc = bnx2_alloc_mem(bp);
  5106. if (rc)
  5107. goto open_err;
  5108. rc = bnx2_request_irq(bp);
  5109. if (rc)
  5110. goto open_err;
  5111. rc = bnx2_init_nic(bp, 1);
  5112. if (rc)
  5113. goto open_err;
  5114. mod_timer(&bp->timer, jiffies + bp->current_interval);
  5115. atomic_set(&bp->intr_sem, 0);
  5116. memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
  5117. bnx2_enable_int(bp);
  5118. if (bp->flags & BNX2_FLAG_USING_MSI) {
  5119. /* Test MSI to make sure it is working
  5120. * If MSI test fails, go back to INTx mode
  5121. */
  5122. if (bnx2_test_intr(bp) != 0) {
  5123. netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
  5124. bnx2_disable_int(bp);
  5125. bnx2_free_irq(bp);
  5126. bnx2_setup_int_mode(bp, 1);
  5127. rc = bnx2_init_nic(bp, 0);
  5128. if (!rc)
  5129. rc = bnx2_request_irq(bp);
  5130. if (rc) {
  5131. del_timer_sync(&bp->timer);
  5132. goto open_err;
  5133. }
  5134. bnx2_enable_int(bp);
  5135. }
  5136. }
  5137. if (bp->flags & BNX2_FLAG_USING_MSI)
  5138. netdev_info(dev, "using MSI\n");
  5139. else if (bp->flags & BNX2_FLAG_USING_MSIX)
  5140. netdev_info(dev, "using MSIX\n");
  5141. netif_tx_start_all_queues(dev);
  5142. return 0;
  5143. open_err:
  5144. bnx2_napi_disable(bp);
  5145. bnx2_free_skbs(bp);
  5146. bnx2_free_irq(bp);
  5147. bnx2_free_mem(bp);
  5148. bnx2_del_napi(bp);
  5149. return rc;
  5150. }
  5151. static void
  5152. bnx2_reset_task(struct work_struct *work)
  5153. {
  5154. struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
  5155. rtnl_lock();
  5156. if (!netif_running(bp->dev)) {
  5157. rtnl_unlock();
  5158. return;
  5159. }
  5160. bnx2_netif_stop(bp, true);
  5161. bnx2_init_nic(bp, 1);
  5162. atomic_set(&bp->intr_sem, 1);
  5163. bnx2_netif_start(bp, true);
  5164. rtnl_unlock();
  5165. }
  5166. static void
  5167. bnx2_dump_state(struct bnx2 *bp)
  5168. {
  5169. struct net_device *dev = bp->dev;
  5170. u32 mcp_p0, mcp_p1, val1, val2;
  5171. pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
  5172. netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
  5173. atomic_read(&bp->intr_sem), val1);
  5174. pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
  5175. pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
  5176. netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
  5177. netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
  5178. REG_RD(bp, BNX2_EMAC_TX_STATUS),
  5179. REG_RD(bp, BNX2_EMAC_RX_STATUS));
  5180. netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
  5181. REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
  5182. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  5183. mcp_p0 = BNX2_MCP_STATE_P0;
  5184. mcp_p1 = BNX2_MCP_STATE_P1;
  5185. } else {
  5186. mcp_p0 = BNX2_MCP_STATE_P0_5708;
  5187. mcp_p1 = BNX2_MCP_STATE_P1_5708;
  5188. }
  5189. netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
  5190. bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
  5191. netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
  5192. REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
  5193. if (bp->flags & BNX2_FLAG_USING_MSIX)
  5194. netdev_err(dev, "DEBUG: PBA[%08x]\n",
  5195. REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
  5196. }
  5197. static void
  5198. bnx2_tx_timeout(struct net_device *dev)
  5199. {
  5200. struct bnx2 *bp = netdev_priv(dev);
  5201. bnx2_dump_state(bp);
  5202. /* This allows the netif to be shutdown gracefully before resetting */
  5203. schedule_work(&bp->reset_task);
  5204. }
  5205. #ifdef BCM_VLAN
  5206. /* Called with rtnl_lock */
  5207. static void
  5208. bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
  5209. {
  5210. struct bnx2 *bp = netdev_priv(dev);
  5211. if (netif_running(dev))
  5212. bnx2_netif_stop(bp, false);
  5213. bp->vlgrp = vlgrp;
  5214. if (!netif_running(dev))
  5215. return;
  5216. bnx2_set_rx_mode(dev);
  5217. if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
  5218. bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
  5219. bnx2_netif_start(bp, false);
  5220. }
  5221. #endif
  5222. /* Called with netif_tx_lock.
  5223. * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
  5224. * netif_wake_queue().
  5225. */
  5226. static netdev_tx_t
  5227. bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
  5228. {
  5229. struct bnx2 *bp = netdev_priv(dev);
  5230. dma_addr_t mapping;
  5231. struct tx_bd *txbd;
  5232. struct sw_tx_bd *tx_buf;
  5233. u32 len, vlan_tag_flags, last_frag, mss;
  5234. u16 prod, ring_prod;
  5235. int i;
  5236. struct bnx2_napi *bnapi;
  5237. struct bnx2_tx_ring_info *txr;
  5238. struct netdev_queue *txq;
  5239. /* Determine which tx ring we will be placed on */
  5240. i = skb_get_queue_mapping(skb);
  5241. bnapi = &bp->bnx2_napi[i];
  5242. txr = &bnapi->tx_ring;
  5243. txq = netdev_get_tx_queue(dev, i);
  5244. if (unlikely(bnx2_tx_avail(bp, txr) <
  5245. (skb_shinfo(skb)->nr_frags + 1))) {
  5246. netif_tx_stop_queue(txq);
  5247. netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
  5248. return NETDEV_TX_BUSY;
  5249. }
  5250. len = skb_headlen(skb);
  5251. prod = txr->tx_prod;
  5252. ring_prod = TX_RING_IDX(prod);
  5253. vlan_tag_flags = 0;
  5254. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  5255. vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
  5256. }
  5257. #ifdef BCM_VLAN
  5258. if (bp->vlgrp && vlan_tx_tag_present(skb)) {
  5259. vlan_tag_flags |=
  5260. (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
  5261. }
  5262. #endif
  5263. if ((mss = skb_shinfo(skb)->gso_size)) {
  5264. u32 tcp_opt_len;
  5265. struct iphdr *iph;
  5266. vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
  5267. tcp_opt_len = tcp_optlen(skb);
  5268. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
  5269. u32 tcp_off = skb_transport_offset(skb) -
  5270. sizeof(struct ipv6hdr) - ETH_HLEN;
  5271. vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
  5272. TX_BD_FLAGS_SW_FLAGS;
  5273. if (likely(tcp_off == 0))
  5274. vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
  5275. else {
  5276. tcp_off >>= 3;
  5277. vlan_tag_flags |= ((tcp_off & 0x3) <<
  5278. TX_BD_FLAGS_TCP6_OFF0_SHL) |
  5279. ((tcp_off & 0x10) <<
  5280. TX_BD_FLAGS_TCP6_OFF4_SHL);
  5281. mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
  5282. }
  5283. } else {
  5284. iph = ip_hdr(skb);
  5285. if (tcp_opt_len || (iph->ihl > 5)) {
  5286. vlan_tag_flags |= ((iph->ihl - 5) +
  5287. (tcp_opt_len >> 2)) << 8;
  5288. }
  5289. }
  5290. } else
  5291. mss = 0;
  5292. mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
  5293. if (dma_mapping_error(&bp->pdev->dev, mapping)) {
  5294. dev_kfree_skb(skb);
  5295. return NETDEV_TX_OK;
  5296. }
  5297. tx_buf = &txr->tx_buf_ring[ring_prod];
  5298. tx_buf->skb = skb;
  5299. dma_unmap_addr_set(tx_buf, mapping, mapping);
  5300. txbd = &txr->tx_desc_ring[ring_prod];
  5301. txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
  5302. txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  5303. txbd->tx_bd_mss_nbytes = len | (mss << 16);
  5304. txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
  5305. last_frag = skb_shinfo(skb)->nr_frags;
  5306. tx_buf->nr_frags = last_frag;
  5307. tx_buf->is_gso = skb_is_gso(skb);
  5308. for (i = 0; i < last_frag; i++) {
  5309. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  5310. prod = NEXT_TX_BD(prod);
  5311. ring_prod = TX_RING_IDX(prod);
  5312. txbd = &txr->tx_desc_ring[ring_prod];
  5313. len = frag->size;
  5314. mapping = dma_map_page(&bp->pdev->dev, frag->page, frag->page_offset,
  5315. len, PCI_DMA_TODEVICE);
  5316. if (dma_mapping_error(&bp->pdev->dev, mapping))
  5317. goto dma_error;
  5318. dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
  5319. mapping);
  5320. txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
  5321. txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  5322. txbd->tx_bd_mss_nbytes = len | (mss << 16);
  5323. txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
  5324. }
  5325. txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
  5326. prod = NEXT_TX_BD(prod);
  5327. txr->tx_prod_bseq += skb->len;
  5328. REG_WR16(bp, txr->tx_bidx_addr, prod);
  5329. REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
  5330. mmiowb();
  5331. txr->tx_prod = prod;
  5332. if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
  5333. netif_tx_stop_queue(txq);
  5334. /* netif_tx_stop_queue() must be done before checking
  5335. * tx index in bnx2_tx_avail() below, because in
  5336. * bnx2_tx_int(), we update tx index before checking for
  5337. * netif_tx_queue_stopped().
  5338. */
  5339. smp_mb();
  5340. if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
  5341. netif_tx_wake_queue(txq);
  5342. }
  5343. return NETDEV_TX_OK;
  5344. dma_error:
  5345. /* save value of frag that failed */
  5346. last_frag = i;
  5347. /* start back at beginning and unmap skb */
  5348. prod = txr->tx_prod;
  5349. ring_prod = TX_RING_IDX(prod);
  5350. tx_buf = &txr->tx_buf_ring[ring_prod];
  5351. tx_buf->skb = NULL;
  5352. dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
  5353. skb_headlen(skb), PCI_DMA_TODEVICE);
  5354. /* unmap remaining mapped pages */
  5355. for (i = 0; i < last_frag; i++) {
  5356. prod = NEXT_TX_BD(prod);
  5357. ring_prod = TX_RING_IDX(prod);
  5358. tx_buf = &txr->tx_buf_ring[ring_prod];
  5359. dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
  5360. skb_shinfo(skb)->frags[i].size,
  5361. PCI_DMA_TODEVICE);
  5362. }
  5363. dev_kfree_skb(skb);
  5364. return NETDEV_TX_OK;
  5365. }
  5366. /* Called with rtnl_lock */
  5367. static int
  5368. bnx2_close(struct net_device *dev)
  5369. {
  5370. struct bnx2 *bp = netdev_priv(dev);
  5371. cancel_work_sync(&bp->reset_task);
  5372. bnx2_disable_int_sync(bp);
  5373. bnx2_napi_disable(bp);
  5374. del_timer_sync(&bp->timer);
  5375. bnx2_shutdown_chip(bp);
  5376. bnx2_free_irq(bp);
  5377. bnx2_free_skbs(bp);
  5378. bnx2_free_mem(bp);
  5379. bnx2_del_napi(bp);
  5380. bp->link_up = 0;
  5381. netif_carrier_off(bp->dev);
  5382. bnx2_set_power_state(bp, PCI_D3hot);
  5383. return 0;
  5384. }
  5385. static void
  5386. bnx2_save_stats(struct bnx2 *bp)
  5387. {
  5388. u32 *hw_stats = (u32 *) bp->stats_blk;
  5389. u32 *temp_stats = (u32 *) bp->temp_stats_blk;
  5390. int i;
  5391. /* The 1st 10 counters are 64-bit counters */
  5392. for (i = 0; i < 20; i += 2) {
  5393. u32 hi;
  5394. u64 lo;
  5395. hi = temp_stats[i] + hw_stats[i];
  5396. lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
  5397. if (lo > 0xffffffff)
  5398. hi++;
  5399. temp_stats[i] = hi;
  5400. temp_stats[i + 1] = lo & 0xffffffff;
  5401. }
  5402. for ( ; i < sizeof(struct statistics_block) / 4; i++)
  5403. temp_stats[i] += hw_stats[i];
  5404. }
  5405. #define GET_64BIT_NET_STATS64(ctr) \
  5406. (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
  5407. #define GET_64BIT_NET_STATS(ctr) \
  5408. GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
  5409. GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
  5410. #define GET_32BIT_NET_STATS(ctr) \
  5411. (unsigned long) (bp->stats_blk->ctr + \
  5412. bp->temp_stats_blk->ctr)
  5413. static struct rtnl_link_stats64 *
  5414. bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
  5415. {
  5416. struct bnx2 *bp = netdev_priv(dev);
  5417. if (bp->stats_blk == NULL)
  5418. return net_stats;
  5419. net_stats->rx_packets =
  5420. GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
  5421. GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
  5422. GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
  5423. net_stats->tx_packets =
  5424. GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
  5425. GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
  5426. GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
  5427. net_stats->rx_bytes =
  5428. GET_64BIT_NET_STATS(stat_IfHCInOctets);
  5429. net_stats->tx_bytes =
  5430. GET_64BIT_NET_STATS(stat_IfHCOutOctets);
  5431. net_stats->multicast =
  5432. GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
  5433. net_stats->collisions =
  5434. GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
  5435. net_stats->rx_length_errors =
  5436. GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
  5437. GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
  5438. net_stats->rx_over_errors =
  5439. GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
  5440. GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
  5441. net_stats->rx_frame_errors =
  5442. GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
  5443. net_stats->rx_crc_errors =
  5444. GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
  5445. net_stats->rx_errors = net_stats->rx_length_errors +
  5446. net_stats->rx_over_errors + net_stats->rx_frame_errors +
  5447. net_stats->rx_crc_errors;
  5448. net_stats->tx_aborted_errors =
  5449. GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
  5450. GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
  5451. if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
  5452. (CHIP_ID(bp) == CHIP_ID_5708_A0))
  5453. net_stats->tx_carrier_errors = 0;
  5454. else {
  5455. net_stats->tx_carrier_errors =
  5456. GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
  5457. }
  5458. net_stats->tx_errors =
  5459. GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
  5460. net_stats->tx_aborted_errors +
  5461. net_stats->tx_carrier_errors;
  5462. net_stats->rx_missed_errors =
  5463. GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
  5464. GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
  5465. GET_32BIT_NET_STATS(stat_FwRxDrop);
  5466. return net_stats;
  5467. }
  5468. /* All ethtool functions called with rtnl_lock */
  5469. static int
  5470. bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  5471. {
  5472. struct bnx2 *bp = netdev_priv(dev);
  5473. int support_serdes = 0, support_copper = 0;
  5474. cmd->supported = SUPPORTED_Autoneg;
  5475. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  5476. support_serdes = 1;
  5477. support_copper = 1;
  5478. } else if (bp->phy_port == PORT_FIBRE)
  5479. support_serdes = 1;
  5480. else
  5481. support_copper = 1;
  5482. if (support_serdes) {
  5483. cmd->supported |= SUPPORTED_1000baseT_Full |
  5484. SUPPORTED_FIBRE;
  5485. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
  5486. cmd->supported |= SUPPORTED_2500baseX_Full;
  5487. }
  5488. if (support_copper) {
  5489. cmd->supported |= SUPPORTED_10baseT_Half |
  5490. SUPPORTED_10baseT_Full |
  5491. SUPPORTED_100baseT_Half |
  5492. SUPPORTED_100baseT_Full |
  5493. SUPPORTED_1000baseT_Full |
  5494. SUPPORTED_TP;
  5495. }
  5496. spin_lock_bh(&bp->phy_lock);
  5497. cmd->port = bp->phy_port;
  5498. cmd->advertising = bp->advertising;
  5499. if (bp->autoneg & AUTONEG_SPEED) {
  5500. cmd->autoneg = AUTONEG_ENABLE;
  5501. }
  5502. else {
  5503. cmd->autoneg = AUTONEG_DISABLE;
  5504. }
  5505. if (netif_carrier_ok(dev)) {
  5506. cmd->speed = bp->line_speed;
  5507. cmd->duplex = bp->duplex;
  5508. }
  5509. else {
  5510. cmd->speed = -1;
  5511. cmd->duplex = -1;
  5512. }
  5513. spin_unlock_bh(&bp->phy_lock);
  5514. cmd->transceiver = XCVR_INTERNAL;
  5515. cmd->phy_address = bp->phy_addr;
  5516. return 0;
  5517. }
  5518. static int
  5519. bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  5520. {
  5521. struct bnx2 *bp = netdev_priv(dev);
  5522. u8 autoneg = bp->autoneg;
  5523. u8 req_duplex = bp->req_duplex;
  5524. u16 req_line_speed = bp->req_line_speed;
  5525. u32 advertising = bp->advertising;
  5526. int err = -EINVAL;
  5527. spin_lock_bh(&bp->phy_lock);
  5528. if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
  5529. goto err_out_unlock;
  5530. if (cmd->port != bp->phy_port &&
  5531. !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
  5532. goto err_out_unlock;
  5533. /* If device is down, we can store the settings only if the user
  5534. * is setting the currently active port.
  5535. */
  5536. if (!netif_running(dev) && cmd->port != bp->phy_port)
  5537. goto err_out_unlock;
  5538. if (cmd->autoneg == AUTONEG_ENABLE) {
  5539. autoneg |= AUTONEG_SPEED;
  5540. advertising = cmd->advertising;
  5541. if (cmd->port == PORT_TP) {
  5542. advertising &= ETHTOOL_ALL_COPPER_SPEED;
  5543. if (!advertising)
  5544. advertising = ETHTOOL_ALL_COPPER_SPEED;
  5545. } else {
  5546. advertising &= ETHTOOL_ALL_FIBRE_SPEED;
  5547. if (!advertising)
  5548. advertising = ETHTOOL_ALL_FIBRE_SPEED;
  5549. }
  5550. advertising |= ADVERTISED_Autoneg;
  5551. }
  5552. else {
  5553. if (cmd->port == PORT_FIBRE) {
  5554. if ((cmd->speed != SPEED_1000 &&
  5555. cmd->speed != SPEED_2500) ||
  5556. (cmd->duplex != DUPLEX_FULL))
  5557. goto err_out_unlock;
  5558. if (cmd->speed == SPEED_2500 &&
  5559. !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  5560. goto err_out_unlock;
  5561. }
  5562. else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
  5563. goto err_out_unlock;
  5564. autoneg &= ~AUTONEG_SPEED;
  5565. req_line_speed = cmd->speed;
  5566. req_duplex = cmd->duplex;
  5567. advertising = 0;
  5568. }
  5569. bp->autoneg = autoneg;
  5570. bp->advertising = advertising;
  5571. bp->req_line_speed = req_line_speed;
  5572. bp->req_duplex = req_duplex;
  5573. err = 0;
  5574. /* If device is down, the new settings will be picked up when it is
  5575. * brought up.
  5576. */
  5577. if (netif_running(dev))
  5578. err = bnx2_setup_phy(bp, cmd->port);
  5579. err_out_unlock:
  5580. spin_unlock_bh(&bp->phy_lock);
  5581. return err;
  5582. }
  5583. static void
  5584. bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  5585. {
  5586. struct bnx2 *bp = netdev_priv(dev);
  5587. strcpy(info->driver, DRV_MODULE_NAME);
  5588. strcpy(info->version, DRV_MODULE_VERSION);
  5589. strcpy(info->bus_info, pci_name(bp->pdev));
  5590. strcpy(info->fw_version, bp->fw_version);
  5591. }
  5592. #define BNX2_REGDUMP_LEN (32 * 1024)
  5593. static int
  5594. bnx2_get_regs_len(struct net_device *dev)
  5595. {
  5596. return BNX2_REGDUMP_LEN;
  5597. }
  5598. static void
  5599. bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
  5600. {
  5601. u32 *p = _p, i, offset;
  5602. u8 *orig_p = _p;
  5603. struct bnx2 *bp = netdev_priv(dev);
  5604. u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
  5605. 0x0800, 0x0880, 0x0c00, 0x0c10,
  5606. 0x0c30, 0x0d08, 0x1000, 0x101c,
  5607. 0x1040, 0x1048, 0x1080, 0x10a4,
  5608. 0x1400, 0x1490, 0x1498, 0x14f0,
  5609. 0x1500, 0x155c, 0x1580, 0x15dc,
  5610. 0x1600, 0x1658, 0x1680, 0x16d8,
  5611. 0x1800, 0x1820, 0x1840, 0x1854,
  5612. 0x1880, 0x1894, 0x1900, 0x1984,
  5613. 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
  5614. 0x1c80, 0x1c94, 0x1d00, 0x1d84,
  5615. 0x2000, 0x2030, 0x23c0, 0x2400,
  5616. 0x2800, 0x2820, 0x2830, 0x2850,
  5617. 0x2b40, 0x2c10, 0x2fc0, 0x3058,
  5618. 0x3c00, 0x3c94, 0x4000, 0x4010,
  5619. 0x4080, 0x4090, 0x43c0, 0x4458,
  5620. 0x4c00, 0x4c18, 0x4c40, 0x4c54,
  5621. 0x4fc0, 0x5010, 0x53c0, 0x5444,
  5622. 0x5c00, 0x5c18, 0x5c80, 0x5c90,
  5623. 0x5fc0, 0x6000, 0x6400, 0x6428,
  5624. 0x6800, 0x6848, 0x684c, 0x6860,
  5625. 0x6888, 0x6910, 0x8000 };
  5626. regs->version = 0;
  5627. memset(p, 0, BNX2_REGDUMP_LEN);
  5628. if (!netif_running(bp->dev))
  5629. return;
  5630. i = 0;
  5631. offset = reg_boundaries[0];
  5632. p += offset;
  5633. while (offset < BNX2_REGDUMP_LEN) {
  5634. *p++ = REG_RD(bp, offset);
  5635. offset += 4;
  5636. if (offset == reg_boundaries[i + 1]) {
  5637. offset = reg_boundaries[i + 2];
  5638. p = (u32 *) (orig_p + offset);
  5639. i += 2;
  5640. }
  5641. }
  5642. }
  5643. static void
  5644. bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  5645. {
  5646. struct bnx2 *bp = netdev_priv(dev);
  5647. if (bp->flags & BNX2_FLAG_NO_WOL) {
  5648. wol->supported = 0;
  5649. wol->wolopts = 0;
  5650. }
  5651. else {
  5652. wol->supported = WAKE_MAGIC;
  5653. if (bp->wol)
  5654. wol->wolopts = WAKE_MAGIC;
  5655. else
  5656. wol->wolopts = 0;
  5657. }
  5658. memset(&wol->sopass, 0, sizeof(wol->sopass));
  5659. }
  5660. static int
  5661. bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  5662. {
  5663. struct bnx2 *bp = netdev_priv(dev);
  5664. if (wol->wolopts & ~WAKE_MAGIC)
  5665. return -EINVAL;
  5666. if (wol->wolopts & WAKE_MAGIC) {
  5667. if (bp->flags & BNX2_FLAG_NO_WOL)
  5668. return -EINVAL;
  5669. bp->wol = 1;
  5670. }
  5671. else {
  5672. bp->wol = 0;
  5673. }
  5674. return 0;
  5675. }
  5676. static int
  5677. bnx2_nway_reset(struct net_device *dev)
  5678. {
  5679. struct bnx2 *bp = netdev_priv(dev);
  5680. u32 bmcr;
  5681. if (!netif_running(dev))
  5682. return -EAGAIN;
  5683. if (!(bp->autoneg & AUTONEG_SPEED)) {
  5684. return -EINVAL;
  5685. }
  5686. spin_lock_bh(&bp->phy_lock);
  5687. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  5688. int rc;
  5689. rc = bnx2_setup_remote_phy(bp, bp->phy_port);
  5690. spin_unlock_bh(&bp->phy_lock);
  5691. return rc;
  5692. }
  5693. /* Force a link down visible on the other side */
  5694. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  5695. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  5696. spin_unlock_bh(&bp->phy_lock);
  5697. msleep(20);
  5698. spin_lock_bh(&bp->phy_lock);
  5699. bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
  5700. bp->serdes_an_pending = 1;
  5701. mod_timer(&bp->timer, jiffies + bp->current_interval);
  5702. }
  5703. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  5704. bmcr &= ~BMCR_LOOPBACK;
  5705. bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
  5706. spin_unlock_bh(&bp->phy_lock);
  5707. return 0;
  5708. }
  5709. static u32
  5710. bnx2_get_link(struct net_device *dev)
  5711. {
  5712. struct bnx2 *bp = netdev_priv(dev);
  5713. return bp->link_up;
  5714. }
  5715. static int
  5716. bnx2_get_eeprom_len(struct net_device *dev)
  5717. {
  5718. struct bnx2 *bp = netdev_priv(dev);
  5719. if (bp->flash_info == NULL)
  5720. return 0;
  5721. return (int) bp->flash_size;
  5722. }
  5723. static int
  5724. bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  5725. u8 *eebuf)
  5726. {
  5727. struct bnx2 *bp = netdev_priv(dev);
  5728. int rc;
  5729. if (!netif_running(dev))
  5730. return -EAGAIN;
  5731. /* parameters already validated in ethtool_get_eeprom */
  5732. rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
  5733. return rc;
  5734. }
  5735. static int
  5736. bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  5737. u8 *eebuf)
  5738. {
  5739. struct bnx2 *bp = netdev_priv(dev);
  5740. int rc;
  5741. if (!netif_running(dev))
  5742. return -EAGAIN;
  5743. /* parameters already validated in ethtool_set_eeprom */
  5744. rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
  5745. return rc;
  5746. }
  5747. static int
  5748. bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
  5749. {
  5750. struct bnx2 *bp = netdev_priv(dev);
  5751. memset(coal, 0, sizeof(struct ethtool_coalesce));
  5752. coal->rx_coalesce_usecs = bp->rx_ticks;
  5753. coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
  5754. coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
  5755. coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
  5756. coal->tx_coalesce_usecs = bp->tx_ticks;
  5757. coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
  5758. coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
  5759. coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
  5760. coal->stats_block_coalesce_usecs = bp->stats_ticks;
  5761. return 0;
  5762. }
  5763. static int
  5764. bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
  5765. {
  5766. struct bnx2 *bp = netdev_priv(dev);
  5767. bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
  5768. if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
  5769. bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
  5770. if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
  5771. bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
  5772. if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
  5773. bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
  5774. if (bp->rx_quick_cons_trip_int > 0xff)
  5775. bp->rx_quick_cons_trip_int = 0xff;
  5776. bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
  5777. if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
  5778. bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
  5779. if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
  5780. bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
  5781. if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
  5782. bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
  5783. if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
  5784. 0xff;
  5785. bp->stats_ticks = coal->stats_block_coalesce_usecs;
  5786. if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
  5787. if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
  5788. bp->stats_ticks = USEC_PER_SEC;
  5789. }
  5790. if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
  5791. bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  5792. bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  5793. if (netif_running(bp->dev)) {
  5794. bnx2_netif_stop(bp, true);
  5795. bnx2_init_nic(bp, 0);
  5796. bnx2_netif_start(bp, true);
  5797. }
  5798. return 0;
  5799. }
  5800. static void
  5801. bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  5802. {
  5803. struct bnx2 *bp = netdev_priv(dev);
  5804. ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
  5805. ering->rx_mini_max_pending = 0;
  5806. ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
  5807. ering->rx_pending = bp->rx_ring_size;
  5808. ering->rx_mini_pending = 0;
  5809. ering->rx_jumbo_pending = bp->rx_pg_ring_size;
  5810. ering->tx_max_pending = MAX_TX_DESC_CNT;
  5811. ering->tx_pending = bp->tx_ring_size;
  5812. }
  5813. static int
  5814. bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
  5815. {
  5816. if (netif_running(bp->dev)) {
  5817. /* Reset will erase chipset stats; save them */
  5818. bnx2_save_stats(bp);
  5819. bnx2_netif_stop(bp, true);
  5820. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
  5821. bnx2_free_skbs(bp);
  5822. bnx2_free_mem(bp);
  5823. }
  5824. bnx2_set_rx_ring_size(bp, rx);
  5825. bp->tx_ring_size = tx;
  5826. if (netif_running(bp->dev)) {
  5827. int rc;
  5828. rc = bnx2_alloc_mem(bp);
  5829. if (!rc)
  5830. rc = bnx2_init_nic(bp, 0);
  5831. if (rc) {
  5832. bnx2_napi_enable(bp);
  5833. dev_close(bp->dev);
  5834. return rc;
  5835. }
  5836. #ifdef BCM_CNIC
  5837. mutex_lock(&bp->cnic_lock);
  5838. /* Let cnic know about the new status block. */
  5839. if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
  5840. bnx2_setup_cnic_irq_info(bp);
  5841. mutex_unlock(&bp->cnic_lock);
  5842. #endif
  5843. bnx2_netif_start(bp, true);
  5844. }
  5845. return 0;
  5846. }
  5847. static int
  5848. bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  5849. {
  5850. struct bnx2 *bp = netdev_priv(dev);
  5851. int rc;
  5852. if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
  5853. (ering->tx_pending > MAX_TX_DESC_CNT) ||
  5854. (ering->tx_pending <= MAX_SKB_FRAGS)) {
  5855. return -EINVAL;
  5856. }
  5857. rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
  5858. return rc;
  5859. }
  5860. static void
  5861. bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  5862. {
  5863. struct bnx2 *bp = netdev_priv(dev);
  5864. epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
  5865. epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
  5866. epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
  5867. }
  5868. static int
  5869. bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  5870. {
  5871. struct bnx2 *bp = netdev_priv(dev);
  5872. bp->req_flow_ctrl = 0;
  5873. if (epause->rx_pause)
  5874. bp->req_flow_ctrl |= FLOW_CTRL_RX;
  5875. if (epause->tx_pause)
  5876. bp->req_flow_ctrl |= FLOW_CTRL_TX;
  5877. if (epause->autoneg) {
  5878. bp->autoneg |= AUTONEG_FLOW_CTRL;
  5879. }
  5880. else {
  5881. bp->autoneg &= ~AUTONEG_FLOW_CTRL;
  5882. }
  5883. if (netif_running(dev)) {
  5884. spin_lock_bh(&bp->phy_lock);
  5885. bnx2_setup_phy(bp, bp->phy_port);
  5886. spin_unlock_bh(&bp->phy_lock);
  5887. }
  5888. return 0;
  5889. }
  5890. static u32
  5891. bnx2_get_rx_csum(struct net_device *dev)
  5892. {
  5893. struct bnx2 *bp = netdev_priv(dev);
  5894. return bp->rx_csum;
  5895. }
  5896. static int
  5897. bnx2_set_rx_csum(struct net_device *dev, u32 data)
  5898. {
  5899. struct bnx2 *bp = netdev_priv(dev);
  5900. bp->rx_csum = data;
  5901. return 0;
  5902. }
  5903. static int
  5904. bnx2_set_tso(struct net_device *dev, u32 data)
  5905. {
  5906. struct bnx2 *bp = netdev_priv(dev);
  5907. if (data) {
  5908. dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
  5909. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  5910. dev->features |= NETIF_F_TSO6;
  5911. } else
  5912. dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
  5913. NETIF_F_TSO_ECN);
  5914. return 0;
  5915. }
  5916. static struct {
  5917. char string[ETH_GSTRING_LEN];
  5918. } bnx2_stats_str_arr[] = {
  5919. { "rx_bytes" },
  5920. { "rx_error_bytes" },
  5921. { "tx_bytes" },
  5922. { "tx_error_bytes" },
  5923. { "rx_ucast_packets" },
  5924. { "rx_mcast_packets" },
  5925. { "rx_bcast_packets" },
  5926. { "tx_ucast_packets" },
  5927. { "tx_mcast_packets" },
  5928. { "tx_bcast_packets" },
  5929. { "tx_mac_errors" },
  5930. { "tx_carrier_errors" },
  5931. { "rx_crc_errors" },
  5932. { "rx_align_errors" },
  5933. { "tx_single_collisions" },
  5934. { "tx_multi_collisions" },
  5935. { "tx_deferred" },
  5936. { "tx_excess_collisions" },
  5937. { "tx_late_collisions" },
  5938. { "tx_total_collisions" },
  5939. { "rx_fragments" },
  5940. { "rx_jabbers" },
  5941. { "rx_undersize_packets" },
  5942. { "rx_oversize_packets" },
  5943. { "rx_64_byte_packets" },
  5944. { "rx_65_to_127_byte_packets" },
  5945. { "rx_128_to_255_byte_packets" },
  5946. { "rx_256_to_511_byte_packets" },
  5947. { "rx_512_to_1023_byte_packets" },
  5948. { "rx_1024_to_1522_byte_packets" },
  5949. { "rx_1523_to_9022_byte_packets" },
  5950. { "tx_64_byte_packets" },
  5951. { "tx_65_to_127_byte_packets" },
  5952. { "tx_128_to_255_byte_packets" },
  5953. { "tx_256_to_511_byte_packets" },
  5954. { "tx_512_to_1023_byte_packets" },
  5955. { "tx_1024_to_1522_byte_packets" },
  5956. { "tx_1523_to_9022_byte_packets" },
  5957. { "rx_xon_frames" },
  5958. { "rx_xoff_frames" },
  5959. { "tx_xon_frames" },
  5960. { "tx_xoff_frames" },
  5961. { "rx_mac_ctrl_frames" },
  5962. { "rx_filtered_packets" },
  5963. { "rx_ftq_discards" },
  5964. { "rx_discards" },
  5965. { "rx_fw_discards" },
  5966. };
  5967. #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
  5968. sizeof(bnx2_stats_str_arr[0]))
  5969. #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
  5970. static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
  5971. STATS_OFFSET32(stat_IfHCInOctets_hi),
  5972. STATS_OFFSET32(stat_IfHCInBadOctets_hi),
  5973. STATS_OFFSET32(stat_IfHCOutOctets_hi),
  5974. STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
  5975. STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
  5976. STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
  5977. STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
  5978. STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
  5979. STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
  5980. STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
  5981. STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
  5982. STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
  5983. STATS_OFFSET32(stat_Dot3StatsFCSErrors),
  5984. STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
  5985. STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
  5986. STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
  5987. STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
  5988. STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
  5989. STATS_OFFSET32(stat_Dot3StatsLateCollisions),
  5990. STATS_OFFSET32(stat_EtherStatsCollisions),
  5991. STATS_OFFSET32(stat_EtherStatsFragments),
  5992. STATS_OFFSET32(stat_EtherStatsJabbers),
  5993. STATS_OFFSET32(stat_EtherStatsUndersizePkts),
  5994. STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
  5995. STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
  5996. STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
  5997. STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
  5998. STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
  5999. STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
  6000. STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
  6001. STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
  6002. STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
  6003. STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
  6004. STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
  6005. STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
  6006. STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
  6007. STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
  6008. STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
  6009. STATS_OFFSET32(stat_XonPauseFramesReceived),
  6010. STATS_OFFSET32(stat_XoffPauseFramesReceived),
  6011. STATS_OFFSET32(stat_OutXonSent),
  6012. STATS_OFFSET32(stat_OutXoffSent),
  6013. STATS_OFFSET32(stat_MacControlFramesReceived),
  6014. STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
  6015. STATS_OFFSET32(stat_IfInFTQDiscards),
  6016. STATS_OFFSET32(stat_IfInMBUFDiscards),
  6017. STATS_OFFSET32(stat_FwRxDrop),
  6018. };
  6019. /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
  6020. * skipped because of errata.
  6021. */
  6022. static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
  6023. 8,0,8,8,8,8,8,8,8,8,
  6024. 4,0,4,4,4,4,4,4,4,4,
  6025. 4,4,4,4,4,4,4,4,4,4,
  6026. 4,4,4,4,4,4,4,4,4,4,
  6027. 4,4,4,4,4,4,4,
  6028. };
  6029. static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
  6030. 8,0,8,8,8,8,8,8,8,8,
  6031. 4,4,4,4,4,4,4,4,4,4,
  6032. 4,4,4,4,4,4,4,4,4,4,
  6033. 4,4,4,4,4,4,4,4,4,4,
  6034. 4,4,4,4,4,4,4,
  6035. };
  6036. #define BNX2_NUM_TESTS 6
  6037. static struct {
  6038. char string[ETH_GSTRING_LEN];
  6039. } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
  6040. { "register_test (offline)" },
  6041. { "memory_test (offline)" },
  6042. { "loopback_test (offline)" },
  6043. { "nvram_test (online)" },
  6044. { "interrupt_test (online)" },
  6045. { "link_test (online)" },
  6046. };
  6047. static int
  6048. bnx2_get_sset_count(struct net_device *dev, int sset)
  6049. {
  6050. switch (sset) {
  6051. case ETH_SS_TEST:
  6052. return BNX2_NUM_TESTS;
  6053. case ETH_SS_STATS:
  6054. return BNX2_NUM_STATS;
  6055. default:
  6056. return -EOPNOTSUPP;
  6057. }
  6058. }
  6059. static void
  6060. bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
  6061. {
  6062. struct bnx2 *bp = netdev_priv(dev);
  6063. bnx2_set_power_state(bp, PCI_D0);
  6064. memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
  6065. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  6066. int i;
  6067. bnx2_netif_stop(bp, true);
  6068. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
  6069. bnx2_free_skbs(bp);
  6070. if (bnx2_test_registers(bp) != 0) {
  6071. buf[0] = 1;
  6072. etest->flags |= ETH_TEST_FL_FAILED;
  6073. }
  6074. if (bnx2_test_memory(bp) != 0) {
  6075. buf[1] = 1;
  6076. etest->flags |= ETH_TEST_FL_FAILED;
  6077. }
  6078. if ((buf[2] = bnx2_test_loopback(bp)) != 0)
  6079. etest->flags |= ETH_TEST_FL_FAILED;
  6080. if (!netif_running(bp->dev))
  6081. bnx2_shutdown_chip(bp);
  6082. else {
  6083. bnx2_init_nic(bp, 1);
  6084. bnx2_netif_start(bp, true);
  6085. }
  6086. /* wait for link up */
  6087. for (i = 0; i < 7; i++) {
  6088. if (bp->link_up)
  6089. break;
  6090. msleep_interruptible(1000);
  6091. }
  6092. }
  6093. if (bnx2_test_nvram(bp) != 0) {
  6094. buf[3] = 1;
  6095. etest->flags |= ETH_TEST_FL_FAILED;
  6096. }
  6097. if (bnx2_test_intr(bp) != 0) {
  6098. buf[4] = 1;
  6099. etest->flags |= ETH_TEST_FL_FAILED;
  6100. }
  6101. if (bnx2_test_link(bp) != 0) {
  6102. buf[5] = 1;
  6103. etest->flags |= ETH_TEST_FL_FAILED;
  6104. }
  6105. if (!netif_running(bp->dev))
  6106. bnx2_set_power_state(bp, PCI_D3hot);
  6107. }
  6108. static void
  6109. bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  6110. {
  6111. switch (stringset) {
  6112. case ETH_SS_STATS:
  6113. memcpy(buf, bnx2_stats_str_arr,
  6114. sizeof(bnx2_stats_str_arr));
  6115. break;
  6116. case ETH_SS_TEST:
  6117. memcpy(buf, bnx2_tests_str_arr,
  6118. sizeof(bnx2_tests_str_arr));
  6119. break;
  6120. }
  6121. }
  6122. static void
  6123. bnx2_get_ethtool_stats(struct net_device *dev,
  6124. struct ethtool_stats *stats, u64 *buf)
  6125. {
  6126. struct bnx2 *bp = netdev_priv(dev);
  6127. int i;
  6128. u32 *hw_stats = (u32 *) bp->stats_blk;
  6129. u32 *temp_stats = (u32 *) bp->temp_stats_blk;
  6130. u8 *stats_len_arr = NULL;
  6131. if (hw_stats == NULL) {
  6132. memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
  6133. return;
  6134. }
  6135. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  6136. (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
  6137. (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
  6138. (CHIP_ID(bp) == CHIP_ID_5708_A0))
  6139. stats_len_arr = bnx2_5706_stats_len_arr;
  6140. else
  6141. stats_len_arr = bnx2_5708_stats_len_arr;
  6142. for (i = 0; i < BNX2_NUM_STATS; i++) {
  6143. unsigned long offset;
  6144. if (stats_len_arr[i] == 0) {
  6145. /* skip this counter */
  6146. buf[i] = 0;
  6147. continue;
  6148. }
  6149. offset = bnx2_stats_offset_arr[i];
  6150. if (stats_len_arr[i] == 4) {
  6151. /* 4-byte counter */
  6152. buf[i] = (u64) *(hw_stats + offset) +
  6153. *(temp_stats + offset);
  6154. continue;
  6155. }
  6156. /* 8-byte counter */
  6157. buf[i] = (((u64) *(hw_stats + offset)) << 32) +
  6158. *(hw_stats + offset + 1) +
  6159. (((u64) *(temp_stats + offset)) << 32) +
  6160. *(temp_stats + offset + 1);
  6161. }
  6162. }
  6163. static int
  6164. bnx2_phys_id(struct net_device *dev, u32 data)
  6165. {
  6166. struct bnx2 *bp = netdev_priv(dev);
  6167. int i;
  6168. u32 save;
  6169. bnx2_set_power_state(bp, PCI_D0);
  6170. if (data == 0)
  6171. data = 2;
  6172. save = REG_RD(bp, BNX2_MISC_CFG);
  6173. REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
  6174. for (i = 0; i < (data * 2); i++) {
  6175. if ((i % 2) == 0) {
  6176. REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
  6177. }
  6178. else {
  6179. REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
  6180. BNX2_EMAC_LED_1000MB_OVERRIDE |
  6181. BNX2_EMAC_LED_100MB_OVERRIDE |
  6182. BNX2_EMAC_LED_10MB_OVERRIDE |
  6183. BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
  6184. BNX2_EMAC_LED_TRAFFIC);
  6185. }
  6186. msleep_interruptible(500);
  6187. if (signal_pending(current))
  6188. break;
  6189. }
  6190. REG_WR(bp, BNX2_EMAC_LED, 0);
  6191. REG_WR(bp, BNX2_MISC_CFG, save);
  6192. if (!netif_running(dev))
  6193. bnx2_set_power_state(bp, PCI_D3hot);
  6194. return 0;
  6195. }
  6196. static int
  6197. bnx2_set_tx_csum(struct net_device *dev, u32 data)
  6198. {
  6199. struct bnx2 *bp = netdev_priv(dev);
  6200. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  6201. return (ethtool_op_set_tx_ipv6_csum(dev, data));
  6202. else
  6203. return (ethtool_op_set_tx_csum(dev, data));
  6204. }
  6205. static int
  6206. bnx2_set_flags(struct net_device *dev, u32 data)
  6207. {
  6208. return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
  6209. }
  6210. static const struct ethtool_ops bnx2_ethtool_ops = {
  6211. .get_settings = bnx2_get_settings,
  6212. .set_settings = bnx2_set_settings,
  6213. .get_drvinfo = bnx2_get_drvinfo,
  6214. .get_regs_len = bnx2_get_regs_len,
  6215. .get_regs = bnx2_get_regs,
  6216. .get_wol = bnx2_get_wol,
  6217. .set_wol = bnx2_set_wol,
  6218. .nway_reset = bnx2_nway_reset,
  6219. .get_link = bnx2_get_link,
  6220. .get_eeprom_len = bnx2_get_eeprom_len,
  6221. .get_eeprom = bnx2_get_eeprom,
  6222. .set_eeprom = bnx2_set_eeprom,
  6223. .get_coalesce = bnx2_get_coalesce,
  6224. .set_coalesce = bnx2_set_coalesce,
  6225. .get_ringparam = bnx2_get_ringparam,
  6226. .set_ringparam = bnx2_set_ringparam,
  6227. .get_pauseparam = bnx2_get_pauseparam,
  6228. .set_pauseparam = bnx2_set_pauseparam,
  6229. .get_rx_csum = bnx2_get_rx_csum,
  6230. .set_rx_csum = bnx2_set_rx_csum,
  6231. .set_tx_csum = bnx2_set_tx_csum,
  6232. .set_sg = ethtool_op_set_sg,
  6233. .set_tso = bnx2_set_tso,
  6234. .self_test = bnx2_self_test,
  6235. .get_strings = bnx2_get_strings,
  6236. .phys_id = bnx2_phys_id,
  6237. .get_ethtool_stats = bnx2_get_ethtool_stats,
  6238. .get_sset_count = bnx2_get_sset_count,
  6239. .set_flags = bnx2_set_flags,
  6240. .get_flags = ethtool_op_get_flags,
  6241. };
  6242. /* Called with rtnl_lock */
  6243. static int
  6244. bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  6245. {
  6246. struct mii_ioctl_data *data = if_mii(ifr);
  6247. struct bnx2 *bp = netdev_priv(dev);
  6248. int err;
  6249. switch(cmd) {
  6250. case SIOCGMIIPHY:
  6251. data->phy_id = bp->phy_addr;
  6252. /* fallthru */
  6253. case SIOCGMIIREG: {
  6254. u32 mii_regval;
  6255. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  6256. return -EOPNOTSUPP;
  6257. if (!netif_running(dev))
  6258. return -EAGAIN;
  6259. spin_lock_bh(&bp->phy_lock);
  6260. err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
  6261. spin_unlock_bh(&bp->phy_lock);
  6262. data->val_out = mii_regval;
  6263. return err;
  6264. }
  6265. case SIOCSMIIREG:
  6266. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  6267. return -EOPNOTSUPP;
  6268. if (!netif_running(dev))
  6269. return -EAGAIN;
  6270. spin_lock_bh(&bp->phy_lock);
  6271. err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
  6272. spin_unlock_bh(&bp->phy_lock);
  6273. return err;
  6274. default:
  6275. /* do nothing */
  6276. break;
  6277. }
  6278. return -EOPNOTSUPP;
  6279. }
  6280. /* Called with rtnl_lock */
  6281. static int
  6282. bnx2_change_mac_addr(struct net_device *dev, void *p)
  6283. {
  6284. struct sockaddr *addr = p;
  6285. struct bnx2 *bp = netdev_priv(dev);
  6286. if (!is_valid_ether_addr(addr->sa_data))
  6287. return -EINVAL;
  6288. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  6289. if (netif_running(dev))
  6290. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  6291. return 0;
  6292. }
  6293. /* Called with rtnl_lock */
  6294. static int
  6295. bnx2_change_mtu(struct net_device *dev, int new_mtu)
  6296. {
  6297. struct bnx2 *bp = netdev_priv(dev);
  6298. if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
  6299. ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
  6300. return -EINVAL;
  6301. dev->mtu = new_mtu;
  6302. return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
  6303. }
  6304. #ifdef CONFIG_NET_POLL_CONTROLLER
  6305. static void
  6306. poll_bnx2(struct net_device *dev)
  6307. {
  6308. struct bnx2 *bp = netdev_priv(dev);
  6309. int i;
  6310. for (i = 0; i < bp->irq_nvecs; i++) {
  6311. struct bnx2_irq *irq = &bp->irq_tbl[i];
  6312. disable_irq(irq->vector);
  6313. irq->handler(irq->vector, &bp->bnx2_napi[i]);
  6314. enable_irq(irq->vector);
  6315. }
  6316. }
  6317. #endif
  6318. static void __devinit
  6319. bnx2_get_5709_media(struct bnx2 *bp)
  6320. {
  6321. u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
  6322. u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
  6323. u32 strap;
  6324. if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
  6325. return;
  6326. else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
  6327. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6328. return;
  6329. }
  6330. if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
  6331. strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
  6332. else
  6333. strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
  6334. if (PCI_FUNC(bp->pdev->devfn) == 0) {
  6335. switch (strap) {
  6336. case 0x4:
  6337. case 0x5:
  6338. case 0x6:
  6339. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6340. return;
  6341. }
  6342. } else {
  6343. switch (strap) {
  6344. case 0x1:
  6345. case 0x2:
  6346. case 0x4:
  6347. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6348. return;
  6349. }
  6350. }
  6351. }
  6352. static void __devinit
  6353. bnx2_get_pci_speed(struct bnx2 *bp)
  6354. {
  6355. u32 reg;
  6356. reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
  6357. if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
  6358. u32 clkreg;
  6359. bp->flags |= BNX2_FLAG_PCIX;
  6360. clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
  6361. clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
  6362. switch (clkreg) {
  6363. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
  6364. bp->bus_speed_mhz = 133;
  6365. break;
  6366. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
  6367. bp->bus_speed_mhz = 100;
  6368. break;
  6369. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
  6370. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
  6371. bp->bus_speed_mhz = 66;
  6372. break;
  6373. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
  6374. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
  6375. bp->bus_speed_mhz = 50;
  6376. break;
  6377. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
  6378. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
  6379. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
  6380. bp->bus_speed_mhz = 33;
  6381. break;
  6382. }
  6383. }
  6384. else {
  6385. if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
  6386. bp->bus_speed_mhz = 66;
  6387. else
  6388. bp->bus_speed_mhz = 33;
  6389. }
  6390. if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
  6391. bp->flags |= BNX2_FLAG_PCI_32BIT;
  6392. }
  6393. static void __devinit
  6394. bnx2_read_vpd_fw_ver(struct bnx2 *bp)
  6395. {
  6396. int rc, i, j;
  6397. u8 *data;
  6398. unsigned int block_end, rosize, len;
  6399. #define BNX2_VPD_NVRAM_OFFSET 0x300
  6400. #define BNX2_VPD_LEN 128
  6401. #define BNX2_MAX_VER_SLEN 30
  6402. data = kmalloc(256, GFP_KERNEL);
  6403. if (!data)
  6404. return;
  6405. rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
  6406. BNX2_VPD_LEN);
  6407. if (rc)
  6408. goto vpd_done;
  6409. for (i = 0; i < BNX2_VPD_LEN; i += 4) {
  6410. data[i] = data[i + BNX2_VPD_LEN + 3];
  6411. data[i + 1] = data[i + BNX2_VPD_LEN + 2];
  6412. data[i + 2] = data[i + BNX2_VPD_LEN + 1];
  6413. data[i + 3] = data[i + BNX2_VPD_LEN];
  6414. }
  6415. i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
  6416. if (i < 0)
  6417. goto vpd_done;
  6418. rosize = pci_vpd_lrdt_size(&data[i]);
  6419. i += PCI_VPD_LRDT_TAG_SIZE;
  6420. block_end = i + rosize;
  6421. if (block_end > BNX2_VPD_LEN)
  6422. goto vpd_done;
  6423. j = pci_vpd_find_info_keyword(data, i, rosize,
  6424. PCI_VPD_RO_KEYWORD_MFR_ID);
  6425. if (j < 0)
  6426. goto vpd_done;
  6427. len = pci_vpd_info_field_size(&data[j]);
  6428. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  6429. if (j + len > block_end || len != 4 ||
  6430. memcmp(&data[j], "1028", 4))
  6431. goto vpd_done;
  6432. j = pci_vpd_find_info_keyword(data, i, rosize,
  6433. PCI_VPD_RO_KEYWORD_VENDOR0);
  6434. if (j < 0)
  6435. goto vpd_done;
  6436. len = pci_vpd_info_field_size(&data[j]);
  6437. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  6438. if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
  6439. goto vpd_done;
  6440. memcpy(bp->fw_version, &data[j], len);
  6441. bp->fw_version[len] = ' ';
  6442. vpd_done:
  6443. kfree(data);
  6444. }
  6445. static int __devinit
  6446. bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
  6447. {
  6448. struct bnx2 *bp;
  6449. unsigned long mem_len;
  6450. int rc, i, j;
  6451. u32 reg;
  6452. u64 dma_mask, persist_dma_mask;
  6453. SET_NETDEV_DEV(dev, &pdev->dev);
  6454. bp = netdev_priv(dev);
  6455. bp->flags = 0;
  6456. bp->phy_flags = 0;
  6457. bp->temp_stats_blk =
  6458. kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
  6459. if (bp->temp_stats_blk == NULL) {
  6460. rc = -ENOMEM;
  6461. goto err_out;
  6462. }
  6463. /* enable device (incl. PCI PM wakeup), and bus-mastering */
  6464. rc = pci_enable_device(pdev);
  6465. if (rc) {
  6466. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  6467. goto err_out;
  6468. }
  6469. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  6470. dev_err(&pdev->dev,
  6471. "Cannot find PCI device base address, aborting\n");
  6472. rc = -ENODEV;
  6473. goto err_out_disable;
  6474. }
  6475. rc = pci_request_regions(pdev, DRV_MODULE_NAME);
  6476. if (rc) {
  6477. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  6478. goto err_out_disable;
  6479. }
  6480. pci_set_master(pdev);
  6481. pci_save_state(pdev);
  6482. bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  6483. if (bp->pm_cap == 0) {
  6484. dev_err(&pdev->dev,
  6485. "Cannot find power management capability, aborting\n");
  6486. rc = -EIO;
  6487. goto err_out_release;
  6488. }
  6489. bp->dev = dev;
  6490. bp->pdev = pdev;
  6491. spin_lock_init(&bp->phy_lock);
  6492. spin_lock_init(&bp->indirect_lock);
  6493. #ifdef BCM_CNIC
  6494. mutex_init(&bp->cnic_lock);
  6495. #endif
  6496. INIT_WORK(&bp->reset_task, bnx2_reset_task);
  6497. dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
  6498. mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
  6499. dev->mem_end = dev->mem_start + mem_len;
  6500. dev->irq = pdev->irq;
  6501. bp->regview = ioremap_nocache(dev->base_addr, mem_len);
  6502. if (!bp->regview) {
  6503. dev_err(&pdev->dev, "Cannot map register space, aborting\n");
  6504. rc = -ENOMEM;
  6505. goto err_out_release;
  6506. }
  6507. /* Configure byte swap and enable write to the reg_window registers.
  6508. * Rely on CPU to do target byte swapping on big endian systems
  6509. * The chip's target access swapping will not swap all accesses
  6510. */
  6511. pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
  6512. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  6513. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
  6514. bnx2_set_power_state(bp, PCI_D0);
  6515. bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
  6516. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  6517. if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
  6518. dev_err(&pdev->dev,
  6519. "Cannot find PCIE capability, aborting\n");
  6520. rc = -EIO;
  6521. goto err_out_unmap;
  6522. }
  6523. bp->flags |= BNX2_FLAG_PCIE;
  6524. if (CHIP_REV(bp) == CHIP_REV_Ax)
  6525. bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
  6526. } else {
  6527. bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
  6528. if (bp->pcix_cap == 0) {
  6529. dev_err(&pdev->dev,
  6530. "Cannot find PCIX capability, aborting\n");
  6531. rc = -EIO;
  6532. goto err_out_unmap;
  6533. }
  6534. bp->flags |= BNX2_FLAG_BROKEN_STATS;
  6535. }
  6536. if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
  6537. if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
  6538. bp->flags |= BNX2_FLAG_MSIX_CAP;
  6539. }
  6540. if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
  6541. if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
  6542. bp->flags |= BNX2_FLAG_MSI_CAP;
  6543. }
  6544. /* 5708 cannot support DMA addresses > 40-bit. */
  6545. if (CHIP_NUM(bp) == CHIP_NUM_5708)
  6546. persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
  6547. else
  6548. persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
  6549. /* Configure DMA attributes. */
  6550. if (pci_set_dma_mask(pdev, dma_mask) == 0) {
  6551. dev->features |= NETIF_F_HIGHDMA;
  6552. rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
  6553. if (rc) {
  6554. dev_err(&pdev->dev,
  6555. "pci_set_consistent_dma_mask failed, aborting\n");
  6556. goto err_out_unmap;
  6557. }
  6558. } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
  6559. dev_err(&pdev->dev, "System does not support DMA, aborting\n");
  6560. goto err_out_unmap;
  6561. }
  6562. if (!(bp->flags & BNX2_FLAG_PCIE))
  6563. bnx2_get_pci_speed(bp);
  6564. /* 5706A0 may falsely detect SERR and PERR. */
  6565. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  6566. reg = REG_RD(bp, PCI_COMMAND);
  6567. reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  6568. REG_WR(bp, PCI_COMMAND, reg);
  6569. }
  6570. else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
  6571. !(bp->flags & BNX2_FLAG_PCIX)) {
  6572. dev_err(&pdev->dev,
  6573. "5706 A1 can only be used in a PCIX bus, aborting\n");
  6574. goto err_out_unmap;
  6575. }
  6576. bnx2_init_nvram(bp);
  6577. reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
  6578. if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
  6579. BNX2_SHM_HDR_SIGNATURE_SIG) {
  6580. u32 off = PCI_FUNC(pdev->devfn) << 2;
  6581. bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
  6582. } else
  6583. bp->shmem_base = HOST_VIEW_SHMEM_BASE;
  6584. /* Get the permanent MAC address. First we need to make sure the
  6585. * firmware is actually running.
  6586. */
  6587. reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
  6588. if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
  6589. BNX2_DEV_INFO_SIGNATURE_MAGIC) {
  6590. dev_err(&pdev->dev, "Firmware not running, aborting\n");
  6591. rc = -ENODEV;
  6592. goto err_out_unmap;
  6593. }
  6594. bnx2_read_vpd_fw_ver(bp);
  6595. j = strlen(bp->fw_version);
  6596. reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
  6597. for (i = 0; i < 3 && j < 24; i++) {
  6598. u8 num, k, skip0;
  6599. if (i == 0) {
  6600. bp->fw_version[j++] = 'b';
  6601. bp->fw_version[j++] = 'c';
  6602. bp->fw_version[j++] = ' ';
  6603. }
  6604. num = (u8) (reg >> (24 - (i * 8)));
  6605. for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
  6606. if (num >= k || !skip0 || k == 1) {
  6607. bp->fw_version[j++] = (num / k) + '0';
  6608. skip0 = 0;
  6609. }
  6610. }
  6611. if (i != 2)
  6612. bp->fw_version[j++] = '.';
  6613. }
  6614. reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
  6615. if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
  6616. bp->wol = 1;
  6617. if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
  6618. bp->flags |= BNX2_FLAG_ASF_ENABLE;
  6619. for (i = 0; i < 30; i++) {
  6620. reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
  6621. if (reg & BNX2_CONDITION_MFW_RUN_MASK)
  6622. break;
  6623. msleep(10);
  6624. }
  6625. }
  6626. reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
  6627. reg &= BNX2_CONDITION_MFW_RUN_MASK;
  6628. if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
  6629. reg != BNX2_CONDITION_MFW_RUN_NONE) {
  6630. u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
  6631. if (j < 32)
  6632. bp->fw_version[j++] = ' ';
  6633. for (i = 0; i < 3 && j < 28; i++) {
  6634. reg = bnx2_reg_rd_ind(bp, addr + i * 4);
  6635. reg = swab32(reg);
  6636. memcpy(&bp->fw_version[j], &reg, 4);
  6637. j += 4;
  6638. }
  6639. }
  6640. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
  6641. bp->mac_addr[0] = (u8) (reg >> 8);
  6642. bp->mac_addr[1] = (u8) reg;
  6643. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
  6644. bp->mac_addr[2] = (u8) (reg >> 24);
  6645. bp->mac_addr[3] = (u8) (reg >> 16);
  6646. bp->mac_addr[4] = (u8) (reg >> 8);
  6647. bp->mac_addr[5] = (u8) reg;
  6648. bp->tx_ring_size = MAX_TX_DESC_CNT;
  6649. bnx2_set_rx_ring_size(bp, 255);
  6650. bp->rx_csum = 1;
  6651. bp->tx_quick_cons_trip_int = 2;
  6652. bp->tx_quick_cons_trip = 20;
  6653. bp->tx_ticks_int = 18;
  6654. bp->tx_ticks = 80;
  6655. bp->rx_quick_cons_trip_int = 2;
  6656. bp->rx_quick_cons_trip = 12;
  6657. bp->rx_ticks_int = 18;
  6658. bp->rx_ticks = 18;
  6659. bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  6660. bp->current_interval = BNX2_TIMER_INTERVAL;
  6661. bp->phy_addr = 1;
  6662. /* Disable WOL support if we are running on a SERDES chip. */
  6663. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  6664. bnx2_get_5709_media(bp);
  6665. else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
  6666. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6667. bp->phy_port = PORT_TP;
  6668. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  6669. bp->phy_port = PORT_FIBRE;
  6670. reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
  6671. if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
  6672. bp->flags |= BNX2_FLAG_NO_WOL;
  6673. bp->wol = 0;
  6674. }
  6675. if (CHIP_NUM(bp) == CHIP_NUM_5706) {
  6676. /* Don't do parallel detect on this board because of
  6677. * some board problems. The link will not go down
  6678. * if we do parallel detect.
  6679. */
  6680. if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  6681. pdev->subsystem_device == 0x310c)
  6682. bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
  6683. } else {
  6684. bp->phy_addr = 2;
  6685. if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
  6686. bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
  6687. }
  6688. } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
  6689. CHIP_NUM(bp) == CHIP_NUM_5708)
  6690. bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
  6691. else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
  6692. (CHIP_REV(bp) == CHIP_REV_Ax ||
  6693. CHIP_REV(bp) == CHIP_REV_Bx))
  6694. bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
  6695. bnx2_init_fw_cap(bp);
  6696. if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
  6697. (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
  6698. (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
  6699. !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
  6700. bp->flags |= BNX2_FLAG_NO_WOL;
  6701. bp->wol = 0;
  6702. }
  6703. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  6704. bp->tx_quick_cons_trip_int =
  6705. bp->tx_quick_cons_trip;
  6706. bp->tx_ticks_int = bp->tx_ticks;
  6707. bp->rx_quick_cons_trip_int =
  6708. bp->rx_quick_cons_trip;
  6709. bp->rx_ticks_int = bp->rx_ticks;
  6710. bp->comp_prod_trip_int = bp->comp_prod_trip;
  6711. bp->com_ticks_int = bp->com_ticks;
  6712. bp->cmd_ticks_int = bp->cmd_ticks;
  6713. }
  6714. /* Disable MSI on 5706 if AMD 8132 bridge is found.
  6715. *
  6716. * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
  6717. * with byte enables disabled on the unused 32-bit word. This is legal
  6718. * but causes problems on the AMD 8132 which will eventually stop
  6719. * responding after a while.
  6720. *
  6721. * AMD believes this incompatibility is unique to the 5706, and
  6722. * prefers to locally disable MSI rather than globally disabling it.
  6723. */
  6724. if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
  6725. struct pci_dev *amd_8132 = NULL;
  6726. while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
  6727. PCI_DEVICE_ID_AMD_8132_BRIDGE,
  6728. amd_8132))) {
  6729. if (amd_8132->revision >= 0x10 &&
  6730. amd_8132->revision <= 0x13) {
  6731. disable_msi = 1;
  6732. pci_dev_put(amd_8132);
  6733. break;
  6734. }
  6735. }
  6736. }
  6737. bnx2_set_default_link(bp);
  6738. bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
  6739. init_timer(&bp->timer);
  6740. bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
  6741. bp->timer.data = (unsigned long) bp;
  6742. bp->timer.function = bnx2_timer;
  6743. return 0;
  6744. err_out_unmap:
  6745. if (bp->regview) {
  6746. iounmap(bp->regview);
  6747. bp->regview = NULL;
  6748. }
  6749. err_out_release:
  6750. pci_release_regions(pdev);
  6751. err_out_disable:
  6752. pci_disable_device(pdev);
  6753. pci_set_drvdata(pdev, NULL);
  6754. err_out:
  6755. return rc;
  6756. }
  6757. static char * __devinit
  6758. bnx2_bus_string(struct bnx2 *bp, char *str)
  6759. {
  6760. char *s = str;
  6761. if (bp->flags & BNX2_FLAG_PCIE) {
  6762. s += sprintf(s, "PCI Express");
  6763. } else {
  6764. s += sprintf(s, "PCI");
  6765. if (bp->flags & BNX2_FLAG_PCIX)
  6766. s += sprintf(s, "-X");
  6767. if (bp->flags & BNX2_FLAG_PCI_32BIT)
  6768. s += sprintf(s, " 32-bit");
  6769. else
  6770. s += sprintf(s, " 64-bit");
  6771. s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
  6772. }
  6773. return str;
  6774. }
  6775. static void
  6776. bnx2_del_napi(struct bnx2 *bp)
  6777. {
  6778. int i;
  6779. for (i = 0; i < bp->irq_nvecs; i++)
  6780. netif_napi_del(&bp->bnx2_napi[i].napi);
  6781. }
  6782. static void
  6783. bnx2_init_napi(struct bnx2 *bp)
  6784. {
  6785. int i;
  6786. for (i = 0; i < bp->irq_nvecs; i++) {
  6787. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  6788. int (*poll)(struct napi_struct *, int);
  6789. if (i == 0)
  6790. poll = bnx2_poll;
  6791. else
  6792. poll = bnx2_poll_msix;
  6793. netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
  6794. bnapi->bp = bp;
  6795. }
  6796. }
  6797. static const struct net_device_ops bnx2_netdev_ops = {
  6798. .ndo_open = bnx2_open,
  6799. .ndo_start_xmit = bnx2_start_xmit,
  6800. .ndo_stop = bnx2_close,
  6801. .ndo_get_stats64 = bnx2_get_stats64,
  6802. .ndo_set_rx_mode = bnx2_set_rx_mode,
  6803. .ndo_do_ioctl = bnx2_ioctl,
  6804. .ndo_validate_addr = eth_validate_addr,
  6805. .ndo_set_mac_address = bnx2_change_mac_addr,
  6806. .ndo_change_mtu = bnx2_change_mtu,
  6807. .ndo_tx_timeout = bnx2_tx_timeout,
  6808. #ifdef BCM_VLAN
  6809. .ndo_vlan_rx_register = bnx2_vlan_rx_register,
  6810. #endif
  6811. #ifdef CONFIG_NET_POLL_CONTROLLER
  6812. .ndo_poll_controller = poll_bnx2,
  6813. #endif
  6814. };
  6815. static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
  6816. {
  6817. #ifdef BCM_VLAN
  6818. dev->vlan_features |= flags;
  6819. #endif
  6820. }
  6821. static int __devinit
  6822. bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  6823. {
  6824. static int version_printed = 0;
  6825. struct net_device *dev = NULL;
  6826. struct bnx2 *bp;
  6827. int rc;
  6828. char str[40];
  6829. if (version_printed++ == 0)
  6830. pr_info("%s", version);
  6831. /* dev zeroed in init_etherdev */
  6832. dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
  6833. if (!dev)
  6834. return -ENOMEM;
  6835. rc = bnx2_init_board(pdev, dev);
  6836. if (rc < 0) {
  6837. free_netdev(dev);
  6838. return rc;
  6839. }
  6840. dev->netdev_ops = &bnx2_netdev_ops;
  6841. dev->watchdog_timeo = TX_TIMEOUT;
  6842. dev->ethtool_ops = &bnx2_ethtool_ops;
  6843. bp = netdev_priv(dev);
  6844. pci_set_drvdata(pdev, dev);
  6845. rc = bnx2_request_firmware(bp);
  6846. if (rc)
  6847. goto error;
  6848. memcpy(dev->dev_addr, bp->mac_addr, 6);
  6849. memcpy(dev->perm_addr, bp->mac_addr, 6);
  6850. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO |
  6851. NETIF_F_RXHASH;
  6852. vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
  6853. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  6854. dev->features |= NETIF_F_IPV6_CSUM;
  6855. vlan_features_add(dev, NETIF_F_IPV6_CSUM);
  6856. }
  6857. #ifdef BCM_VLAN
  6858. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  6859. #endif
  6860. dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
  6861. vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
  6862. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  6863. dev->features |= NETIF_F_TSO6;
  6864. vlan_features_add(dev, NETIF_F_TSO6);
  6865. }
  6866. if ((rc = register_netdev(dev))) {
  6867. dev_err(&pdev->dev, "Cannot register net device\n");
  6868. goto error;
  6869. }
  6870. netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
  6871. board_info[ent->driver_data].name,
  6872. ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
  6873. ((CHIP_ID(bp) & 0x0ff0) >> 4),
  6874. bnx2_bus_string(bp, str),
  6875. dev->base_addr,
  6876. bp->pdev->irq, dev->dev_addr);
  6877. return 0;
  6878. error:
  6879. if (bp->mips_firmware)
  6880. release_firmware(bp->mips_firmware);
  6881. if (bp->rv2p_firmware)
  6882. release_firmware(bp->rv2p_firmware);
  6883. if (bp->regview)
  6884. iounmap(bp->regview);
  6885. pci_release_regions(pdev);
  6886. pci_disable_device(pdev);
  6887. pci_set_drvdata(pdev, NULL);
  6888. free_netdev(dev);
  6889. return rc;
  6890. }
  6891. static void __devexit
  6892. bnx2_remove_one(struct pci_dev *pdev)
  6893. {
  6894. struct net_device *dev = pci_get_drvdata(pdev);
  6895. struct bnx2 *bp = netdev_priv(dev);
  6896. flush_scheduled_work();
  6897. unregister_netdev(dev);
  6898. if (bp->mips_firmware)
  6899. release_firmware(bp->mips_firmware);
  6900. if (bp->rv2p_firmware)
  6901. release_firmware(bp->rv2p_firmware);
  6902. if (bp->regview)
  6903. iounmap(bp->regview);
  6904. kfree(bp->temp_stats_blk);
  6905. free_netdev(dev);
  6906. pci_release_regions(pdev);
  6907. pci_disable_device(pdev);
  6908. pci_set_drvdata(pdev, NULL);
  6909. }
  6910. static int
  6911. bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
  6912. {
  6913. struct net_device *dev = pci_get_drvdata(pdev);
  6914. struct bnx2 *bp = netdev_priv(dev);
  6915. /* PCI register 4 needs to be saved whether netif_running() or not.
  6916. * MSI address and data need to be saved if using MSI and
  6917. * netif_running().
  6918. */
  6919. pci_save_state(pdev);
  6920. if (!netif_running(dev))
  6921. return 0;
  6922. flush_scheduled_work();
  6923. bnx2_netif_stop(bp, true);
  6924. netif_device_detach(dev);
  6925. del_timer_sync(&bp->timer);
  6926. bnx2_shutdown_chip(bp);
  6927. bnx2_free_skbs(bp);
  6928. bnx2_set_power_state(bp, pci_choose_state(pdev, state));
  6929. return 0;
  6930. }
  6931. static int
  6932. bnx2_resume(struct pci_dev *pdev)
  6933. {
  6934. struct net_device *dev = pci_get_drvdata(pdev);
  6935. struct bnx2 *bp = netdev_priv(dev);
  6936. pci_restore_state(pdev);
  6937. if (!netif_running(dev))
  6938. return 0;
  6939. bnx2_set_power_state(bp, PCI_D0);
  6940. netif_device_attach(dev);
  6941. bnx2_init_nic(bp, 1);
  6942. bnx2_netif_start(bp, true);
  6943. return 0;
  6944. }
  6945. /**
  6946. * bnx2_io_error_detected - called when PCI error is detected
  6947. * @pdev: Pointer to PCI device
  6948. * @state: The current pci connection state
  6949. *
  6950. * This function is called after a PCI bus error affecting
  6951. * this device has been detected.
  6952. */
  6953. static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
  6954. pci_channel_state_t state)
  6955. {
  6956. struct net_device *dev = pci_get_drvdata(pdev);
  6957. struct bnx2 *bp = netdev_priv(dev);
  6958. rtnl_lock();
  6959. netif_device_detach(dev);
  6960. if (state == pci_channel_io_perm_failure) {
  6961. rtnl_unlock();
  6962. return PCI_ERS_RESULT_DISCONNECT;
  6963. }
  6964. if (netif_running(dev)) {
  6965. bnx2_netif_stop(bp, true);
  6966. del_timer_sync(&bp->timer);
  6967. bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
  6968. }
  6969. pci_disable_device(pdev);
  6970. rtnl_unlock();
  6971. /* Request a slot slot reset. */
  6972. return PCI_ERS_RESULT_NEED_RESET;
  6973. }
  6974. /**
  6975. * bnx2_io_slot_reset - called after the pci bus has been reset.
  6976. * @pdev: Pointer to PCI device
  6977. *
  6978. * Restart the card from scratch, as if from a cold-boot.
  6979. */
  6980. static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
  6981. {
  6982. struct net_device *dev = pci_get_drvdata(pdev);
  6983. struct bnx2 *bp = netdev_priv(dev);
  6984. rtnl_lock();
  6985. if (pci_enable_device(pdev)) {
  6986. dev_err(&pdev->dev,
  6987. "Cannot re-enable PCI device after reset\n");
  6988. rtnl_unlock();
  6989. return PCI_ERS_RESULT_DISCONNECT;
  6990. }
  6991. pci_set_master(pdev);
  6992. pci_restore_state(pdev);
  6993. pci_save_state(pdev);
  6994. if (netif_running(dev)) {
  6995. bnx2_set_power_state(bp, PCI_D0);
  6996. bnx2_init_nic(bp, 1);
  6997. }
  6998. rtnl_unlock();
  6999. return PCI_ERS_RESULT_RECOVERED;
  7000. }
  7001. /**
  7002. * bnx2_io_resume - called when traffic can start flowing again.
  7003. * @pdev: Pointer to PCI device
  7004. *
  7005. * This callback is called when the error recovery driver tells us that
  7006. * its OK to resume normal operation.
  7007. */
  7008. static void bnx2_io_resume(struct pci_dev *pdev)
  7009. {
  7010. struct net_device *dev = pci_get_drvdata(pdev);
  7011. struct bnx2 *bp = netdev_priv(dev);
  7012. rtnl_lock();
  7013. if (netif_running(dev))
  7014. bnx2_netif_start(bp, true);
  7015. netif_device_attach(dev);
  7016. rtnl_unlock();
  7017. }
  7018. static struct pci_error_handlers bnx2_err_handler = {
  7019. .error_detected = bnx2_io_error_detected,
  7020. .slot_reset = bnx2_io_slot_reset,
  7021. .resume = bnx2_io_resume,
  7022. };
  7023. static struct pci_driver bnx2_pci_driver = {
  7024. .name = DRV_MODULE_NAME,
  7025. .id_table = bnx2_pci_tbl,
  7026. .probe = bnx2_init_one,
  7027. .remove = __devexit_p(bnx2_remove_one),
  7028. .suspend = bnx2_suspend,
  7029. .resume = bnx2_resume,
  7030. .err_handler = &bnx2_err_handler,
  7031. };
  7032. static int __init bnx2_init(void)
  7033. {
  7034. return pci_register_driver(&bnx2_pci_driver);
  7035. }
  7036. static void __exit bnx2_cleanup(void)
  7037. {
  7038. pci_unregister_driver(&bnx2_pci_driver);
  7039. }
  7040. module_init(bnx2_init);
  7041. module_exit(bnx2_cleanup);