au1000_eth.c 32 KB

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  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver
  4. *
  5. * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6. * Copyright 2002 TimeSys Corp.
  7. * Added ethtool/mii-tool support,
  8. * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9. * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
  10. * or riemer@riemer-nt.de: fixed the link beat detection with
  11. * ioctls (SIOCGMIIPHY)
  12. * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
  13. * converted to use linux-2.6.x's PHY framework
  14. *
  15. * Author: MontaVista Software, Inc.
  16. * ppopov@mvista.com or source@mvista.com
  17. *
  18. * ########################################################################
  19. *
  20. * This program is free software; you can distribute it and/or modify it
  21. * under the terms of the GNU General Public License (Version 2) as
  22. * published by the Free Software Foundation.
  23. *
  24. * This program is distributed in the hope it will be useful, but WITHOUT
  25. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  27. * for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, write to the Free Software Foundation, Inc.,
  31. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  32. *
  33. * ########################################################################
  34. *
  35. *
  36. */
  37. #include <linux/capability.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/module.h>
  40. #include <linux/kernel.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/errno.h>
  44. #include <linux/in.h>
  45. #include <linux/ioport.h>
  46. #include <linux/bitops.h>
  47. #include <linux/slab.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/init.h>
  50. #include <linux/netdevice.h>
  51. #include <linux/etherdevice.h>
  52. #include <linux/ethtool.h>
  53. #include <linux/mii.h>
  54. #include <linux/skbuff.h>
  55. #include <linux/delay.h>
  56. #include <linux/crc32.h>
  57. #include <linux/phy.h>
  58. #include <linux/platform_device.h>
  59. #include <asm/cpu.h>
  60. #include <asm/mipsregs.h>
  61. #include <asm/irq.h>
  62. #include <asm/io.h>
  63. #include <asm/processor.h>
  64. #include <au1000.h>
  65. #include <au1xxx_eth.h>
  66. #include <prom.h>
  67. #include "au1000_eth.h"
  68. #ifdef AU1000_ETH_DEBUG
  69. static int au1000_debug = 5;
  70. #else
  71. static int au1000_debug = 3;
  72. #endif
  73. #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
  74. NETIF_MSG_PROBE | \
  75. NETIF_MSG_LINK)
  76. #define DRV_NAME "au1000_eth"
  77. #define DRV_VERSION "1.7"
  78. #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
  79. #define DRV_DESC "Au1xxx on-chip Ethernet driver"
  80. MODULE_AUTHOR(DRV_AUTHOR);
  81. MODULE_DESCRIPTION(DRV_DESC);
  82. MODULE_LICENSE("GPL");
  83. MODULE_VERSION(DRV_VERSION);
  84. /*
  85. * Theory of operation
  86. *
  87. * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
  88. * There are four receive and four transmit descriptors. These
  89. * descriptors are not in memory; rather, they are just a set of
  90. * hardware registers.
  91. *
  92. * Since the Au1000 has a coherent data cache, the receive and
  93. * transmit buffers are allocated from the KSEG0 segment. The
  94. * hardware registers, however, are still mapped at KSEG1 to
  95. * make sure there's no out-of-order writes, and that all writes
  96. * complete immediately.
  97. */
  98. struct au1000_private *au_macs[NUM_ETH_INTERFACES];
  99. /*
  100. * board-specific configurations
  101. *
  102. * PHY detection algorithm
  103. *
  104. * If phy_static_config is undefined, the PHY setup is
  105. * autodetected:
  106. *
  107. * mii_probe() first searches the current MAC's MII bus for a PHY,
  108. * selecting the first (or last, if phy_search_highest_addr is
  109. * defined) PHY address not already claimed by another netdev.
  110. *
  111. * If nothing was found that way when searching for the 2nd ethernet
  112. * controller's PHY and phy1_search_mac0 is defined, then
  113. * the first MII bus is searched as well for an unclaimed PHY; this is
  114. * needed in case of a dual-PHY accessible only through the MAC0's MII
  115. * bus.
  116. *
  117. * Finally, if no PHY is found, then the corresponding ethernet
  118. * controller is not registered to the network subsystem.
  119. */
  120. /* autodetection defaults: phy1_search_mac0 */
  121. /* static PHY setup
  122. *
  123. * most boards PHY setup should be detectable properly with the
  124. * autodetection algorithm in mii_probe(), but in some cases (e.g. if
  125. * you have a switch attached, or want to use the PHY's interrupt
  126. * notification capabilities) you can provide a static PHY
  127. * configuration here
  128. *
  129. * IRQs may only be set, if a PHY address was configured
  130. * If a PHY address is given, also a bus id is required to be set
  131. *
  132. * ps: make sure the used irqs are configured properly in the board
  133. * specific irq-map
  134. */
  135. static void au1000_enable_mac(struct net_device *dev, int force_reset)
  136. {
  137. unsigned long flags;
  138. struct au1000_private *aup = netdev_priv(dev);
  139. spin_lock_irqsave(&aup->lock, flags);
  140. if(force_reset || (!aup->mac_enabled)) {
  141. *aup->enable = MAC_EN_CLOCK_ENABLE;
  142. au_sync_delay(2);
  143. *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
  144. | MAC_EN_CLOCK_ENABLE);
  145. au_sync_delay(2);
  146. aup->mac_enabled = 1;
  147. }
  148. spin_unlock_irqrestore(&aup->lock, flags);
  149. }
  150. /*
  151. * MII operations
  152. */
  153. static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
  154. {
  155. struct au1000_private *aup = netdev_priv(dev);
  156. volatile u32 *const mii_control_reg = &aup->mac->mii_control;
  157. volatile u32 *const mii_data_reg = &aup->mac->mii_data;
  158. u32 timedout = 20;
  159. u32 mii_control;
  160. while (*mii_control_reg & MAC_MII_BUSY) {
  161. mdelay(1);
  162. if (--timedout == 0) {
  163. netdev_err(dev, "read_MII busy timeout!!\n");
  164. return -1;
  165. }
  166. }
  167. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  168. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
  169. *mii_control_reg = mii_control;
  170. timedout = 20;
  171. while (*mii_control_reg & MAC_MII_BUSY) {
  172. mdelay(1);
  173. if (--timedout == 0) {
  174. netdev_err(dev, "mdio_read busy timeout!!\n");
  175. return -1;
  176. }
  177. }
  178. return (int)*mii_data_reg;
  179. }
  180. static void au1000_mdio_write(struct net_device *dev, int phy_addr,
  181. int reg, u16 value)
  182. {
  183. struct au1000_private *aup = netdev_priv(dev);
  184. volatile u32 *const mii_control_reg = &aup->mac->mii_control;
  185. volatile u32 *const mii_data_reg = &aup->mac->mii_data;
  186. u32 timedout = 20;
  187. u32 mii_control;
  188. while (*mii_control_reg & MAC_MII_BUSY) {
  189. mdelay(1);
  190. if (--timedout == 0) {
  191. netdev_err(dev, "mdio_write busy timeout!!\n");
  192. return;
  193. }
  194. }
  195. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  196. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
  197. *mii_data_reg = value;
  198. *mii_control_reg = mii_control;
  199. }
  200. static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  201. {
  202. /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
  203. * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
  204. struct net_device *const dev = bus->priv;
  205. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  206. * mii_bus is enabled */
  207. return au1000_mdio_read(dev, phy_addr, regnum);
  208. }
  209. static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  210. u16 value)
  211. {
  212. struct net_device *const dev = bus->priv;
  213. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  214. * mii_bus is enabled */
  215. au1000_mdio_write(dev, phy_addr, regnum, value);
  216. return 0;
  217. }
  218. static int au1000_mdiobus_reset(struct mii_bus *bus)
  219. {
  220. struct net_device *const dev = bus->priv;
  221. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  222. * mii_bus is enabled */
  223. return 0;
  224. }
  225. static void au1000_hard_stop(struct net_device *dev)
  226. {
  227. struct au1000_private *aup = netdev_priv(dev);
  228. netif_dbg(aup, drv, dev, "hard stop\n");
  229. aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
  230. au_sync_delay(10);
  231. }
  232. static void au1000_enable_rx_tx(struct net_device *dev)
  233. {
  234. struct au1000_private *aup = netdev_priv(dev);
  235. netif_dbg(aup, hw, dev, "enable_rx_tx\n");
  236. aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
  237. au_sync_delay(10);
  238. }
  239. static void
  240. au1000_adjust_link(struct net_device *dev)
  241. {
  242. struct au1000_private *aup = netdev_priv(dev);
  243. struct phy_device *phydev = aup->phy_dev;
  244. unsigned long flags;
  245. int status_change = 0;
  246. BUG_ON(!aup->phy_dev);
  247. spin_lock_irqsave(&aup->lock, flags);
  248. if (phydev->link && (aup->old_speed != phydev->speed)) {
  249. /* speed changed */
  250. switch (phydev->speed) {
  251. case SPEED_10:
  252. case SPEED_100:
  253. break;
  254. default:
  255. netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
  256. phydev->speed);
  257. break;
  258. }
  259. aup->old_speed = phydev->speed;
  260. status_change = 1;
  261. }
  262. if (phydev->link && (aup->old_duplex != phydev->duplex)) {
  263. /* duplex mode changed */
  264. /* switching duplex mode requires to disable rx and tx! */
  265. au1000_hard_stop(dev);
  266. if (DUPLEX_FULL == phydev->duplex)
  267. aup->mac->control = ((aup->mac->control
  268. | MAC_FULL_DUPLEX)
  269. & ~MAC_DISABLE_RX_OWN);
  270. else
  271. aup->mac->control = ((aup->mac->control
  272. & ~MAC_FULL_DUPLEX)
  273. | MAC_DISABLE_RX_OWN);
  274. au_sync_delay(1);
  275. au1000_enable_rx_tx(dev);
  276. aup->old_duplex = phydev->duplex;
  277. status_change = 1;
  278. }
  279. if (phydev->link != aup->old_link) {
  280. /* link state changed */
  281. if (!phydev->link) {
  282. /* link went down */
  283. aup->old_speed = 0;
  284. aup->old_duplex = -1;
  285. }
  286. aup->old_link = phydev->link;
  287. status_change = 1;
  288. }
  289. spin_unlock_irqrestore(&aup->lock, flags);
  290. if (status_change) {
  291. if (phydev->link)
  292. netdev_info(dev, "link up (%d/%s)\n",
  293. phydev->speed,
  294. DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
  295. else
  296. netdev_info(dev, "link down\n");
  297. }
  298. }
  299. static int au1000_mii_probe (struct net_device *dev)
  300. {
  301. struct au1000_private *const aup = netdev_priv(dev);
  302. struct phy_device *phydev = NULL;
  303. if (aup->phy_static_config) {
  304. BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
  305. if (aup->phy_addr)
  306. phydev = aup->mii_bus->phy_map[aup->phy_addr];
  307. else
  308. netdev_info(dev, "using PHY-less setup\n");
  309. return 0;
  310. } else {
  311. int phy_addr;
  312. /* find the first (lowest address) PHY on the current MAC's MII bus */
  313. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
  314. if (aup->mii_bus->phy_map[phy_addr]) {
  315. phydev = aup->mii_bus->phy_map[phy_addr];
  316. if (!aup->phy_search_highest_addr)
  317. break; /* break out with first one found */
  318. }
  319. if (aup->phy1_search_mac0) {
  320. /* try harder to find a PHY */
  321. if (!phydev && (aup->mac_id == 1)) {
  322. /* no PHY found, maybe we have a dual PHY? */
  323. dev_info(&dev->dev, ": no PHY found on MAC1, "
  324. "let's see if it's attached to MAC0...\n");
  325. /* find the first (lowest address) non-attached PHY on
  326. * the MAC0 MII bus */
  327. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  328. struct phy_device *const tmp_phydev =
  329. aup->mii_bus->phy_map[phy_addr];
  330. if (aup->mac_id == 1)
  331. break;
  332. if (!tmp_phydev)
  333. continue; /* no PHY here... */
  334. if (tmp_phydev->attached_dev)
  335. continue; /* already claimed by MAC0 */
  336. phydev = tmp_phydev;
  337. break; /* found it */
  338. }
  339. }
  340. }
  341. }
  342. if (!phydev) {
  343. netdev_err(dev, "no PHY found\n");
  344. return -1;
  345. }
  346. /* now we are supposed to have a proper phydev, to attach to... */
  347. BUG_ON(phydev->attached_dev);
  348. phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
  349. 0, PHY_INTERFACE_MODE_MII);
  350. if (IS_ERR(phydev)) {
  351. netdev_err(dev, "Could not attach to PHY\n");
  352. return PTR_ERR(phydev);
  353. }
  354. /* mask with MAC supported features */
  355. phydev->supported &= (SUPPORTED_10baseT_Half
  356. | SUPPORTED_10baseT_Full
  357. | SUPPORTED_100baseT_Half
  358. | SUPPORTED_100baseT_Full
  359. | SUPPORTED_Autoneg
  360. /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
  361. | SUPPORTED_MII
  362. | SUPPORTED_TP);
  363. phydev->advertising = phydev->supported;
  364. aup->old_link = 0;
  365. aup->old_speed = 0;
  366. aup->old_duplex = -1;
  367. aup->phy_dev = phydev;
  368. netdev_info(dev, "attached PHY driver [%s] "
  369. "(mii_bus:phy_addr=%s, irq=%d)\n",
  370. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  371. return 0;
  372. }
  373. /*
  374. * Buffer allocation/deallocation routines. The buffer descriptor returned
  375. * has the virtual and dma address of a buffer suitable for
  376. * both, receive and transmit operations.
  377. */
  378. static db_dest_t *au1000_GetFreeDB(struct au1000_private *aup)
  379. {
  380. db_dest_t *pDB;
  381. pDB = aup->pDBfree;
  382. if (pDB) {
  383. aup->pDBfree = pDB->pnext;
  384. }
  385. return pDB;
  386. }
  387. void au1000_ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
  388. {
  389. db_dest_t *pDBfree = aup->pDBfree;
  390. if (pDBfree)
  391. pDBfree->pnext = pDB;
  392. aup->pDBfree = pDB;
  393. }
  394. static void au1000_reset_mac_unlocked(struct net_device *dev)
  395. {
  396. struct au1000_private *const aup = netdev_priv(dev);
  397. int i;
  398. au1000_hard_stop(dev);
  399. *aup->enable = MAC_EN_CLOCK_ENABLE;
  400. au_sync_delay(2);
  401. *aup->enable = 0;
  402. au_sync_delay(2);
  403. aup->tx_full = 0;
  404. for (i = 0; i < NUM_RX_DMA; i++) {
  405. /* reset control bits */
  406. aup->rx_dma_ring[i]->buff_stat &= ~0xf;
  407. }
  408. for (i = 0; i < NUM_TX_DMA; i++) {
  409. /* reset control bits */
  410. aup->tx_dma_ring[i]->buff_stat &= ~0xf;
  411. }
  412. aup->mac_enabled = 0;
  413. }
  414. static void au1000_reset_mac(struct net_device *dev)
  415. {
  416. struct au1000_private *const aup = netdev_priv(dev);
  417. unsigned long flags;
  418. netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
  419. (unsigned)aup);
  420. spin_lock_irqsave(&aup->lock, flags);
  421. au1000_reset_mac_unlocked (dev);
  422. spin_unlock_irqrestore(&aup->lock, flags);
  423. }
  424. /*
  425. * Setup the receive and transmit "rings". These pointers are the addresses
  426. * of the rx and tx MAC DMA registers so they are fixed by the hardware --
  427. * these are not descriptors sitting in memory.
  428. */
  429. static void
  430. au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
  431. {
  432. int i;
  433. for (i = 0; i < NUM_RX_DMA; i++) {
  434. aup->rx_dma_ring[i] =
  435. (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
  436. }
  437. for (i = 0; i < NUM_TX_DMA; i++) {
  438. aup->tx_dma_ring[i] =
  439. (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
  440. }
  441. }
  442. /*
  443. * ethtool operations
  444. */
  445. static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  446. {
  447. struct au1000_private *aup = netdev_priv(dev);
  448. if (aup->phy_dev)
  449. return phy_ethtool_gset(aup->phy_dev, cmd);
  450. return -EINVAL;
  451. }
  452. static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  453. {
  454. struct au1000_private *aup = netdev_priv(dev);
  455. if (!capable(CAP_NET_ADMIN))
  456. return -EPERM;
  457. if (aup->phy_dev)
  458. return phy_ethtool_sset(aup->phy_dev, cmd);
  459. return -EINVAL;
  460. }
  461. static void
  462. au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  463. {
  464. struct au1000_private *aup = netdev_priv(dev);
  465. strcpy(info->driver, DRV_NAME);
  466. strcpy(info->version, DRV_VERSION);
  467. info->fw_version[0] = '\0';
  468. sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
  469. info->regdump_len = 0;
  470. }
  471. static void au1000_set_msglevel(struct net_device *dev, u32 value)
  472. {
  473. struct au1000_private *aup = netdev_priv(dev);
  474. aup->msg_enable = value;
  475. }
  476. static u32 au1000_get_msglevel(struct net_device *dev)
  477. {
  478. struct au1000_private *aup = netdev_priv(dev);
  479. return aup->msg_enable;
  480. }
  481. static const struct ethtool_ops au1000_ethtool_ops = {
  482. .get_settings = au1000_get_settings,
  483. .set_settings = au1000_set_settings,
  484. .get_drvinfo = au1000_get_drvinfo,
  485. .get_link = ethtool_op_get_link,
  486. .get_msglevel = au1000_get_msglevel,
  487. .set_msglevel = au1000_set_msglevel,
  488. };
  489. /*
  490. * Initialize the interface.
  491. *
  492. * When the device powers up, the clocks are disabled and the
  493. * mac is in reset state. When the interface is closed, we
  494. * do the same -- reset the device and disable the clocks to
  495. * conserve power. Thus, whenever au1000_init() is called,
  496. * the device should already be in reset state.
  497. */
  498. static int au1000_init(struct net_device *dev)
  499. {
  500. struct au1000_private *aup = netdev_priv(dev);
  501. unsigned long flags;
  502. int i;
  503. u32 control;
  504. netif_dbg(aup, hw, dev, "au1000_init\n");
  505. /* bring the device out of reset */
  506. au1000_enable_mac(dev, 1);
  507. spin_lock_irqsave(&aup->lock, flags);
  508. aup->mac->control = 0;
  509. aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
  510. aup->tx_tail = aup->tx_head;
  511. aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
  512. aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
  513. aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
  514. dev->dev_addr[1]<<8 | dev->dev_addr[0];
  515. for (i = 0; i < NUM_RX_DMA; i++) {
  516. aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
  517. }
  518. au_sync();
  519. control = MAC_RX_ENABLE | MAC_TX_ENABLE;
  520. #ifndef CONFIG_CPU_LITTLE_ENDIAN
  521. control |= MAC_BIG_ENDIAN;
  522. #endif
  523. if (aup->phy_dev) {
  524. if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
  525. control |= MAC_FULL_DUPLEX;
  526. else
  527. control |= MAC_DISABLE_RX_OWN;
  528. } else { /* PHY-less op, assume full-duplex */
  529. control |= MAC_FULL_DUPLEX;
  530. }
  531. aup->mac->control = control;
  532. aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
  533. au_sync();
  534. spin_unlock_irqrestore(&aup->lock, flags);
  535. return 0;
  536. }
  537. static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
  538. {
  539. struct net_device_stats *ps = &dev->stats;
  540. ps->rx_packets++;
  541. if (status & RX_MCAST_FRAME)
  542. ps->multicast++;
  543. if (status & RX_ERROR) {
  544. ps->rx_errors++;
  545. if (status & RX_MISSED_FRAME)
  546. ps->rx_missed_errors++;
  547. if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
  548. ps->rx_length_errors++;
  549. if (status & RX_CRC_ERROR)
  550. ps->rx_crc_errors++;
  551. if (status & RX_COLL)
  552. ps->collisions++;
  553. } else
  554. ps->rx_bytes += status & RX_FRAME_LEN_MASK;
  555. }
  556. /*
  557. * Au1000 receive routine.
  558. */
  559. static int au1000_rx(struct net_device *dev)
  560. {
  561. struct au1000_private *aup = netdev_priv(dev);
  562. struct sk_buff *skb;
  563. volatile rx_dma_t *prxd;
  564. u32 buff_stat, status;
  565. db_dest_t *pDB;
  566. u32 frmlen;
  567. netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
  568. prxd = aup->rx_dma_ring[aup->rx_head];
  569. buff_stat = prxd->buff_stat;
  570. while (buff_stat & RX_T_DONE) {
  571. status = prxd->status;
  572. pDB = aup->rx_db_inuse[aup->rx_head];
  573. au1000_update_rx_stats(dev, status);
  574. if (!(status & RX_ERROR)) {
  575. /* good frame */
  576. frmlen = (status & RX_FRAME_LEN_MASK);
  577. frmlen -= 4; /* Remove FCS */
  578. skb = dev_alloc_skb(frmlen + 2);
  579. if (skb == NULL) {
  580. netdev_err(dev, "Memory squeeze, dropping packet.\n");
  581. dev->stats.rx_dropped++;
  582. continue;
  583. }
  584. skb_reserve(skb, 2); /* 16 byte IP header align */
  585. skb_copy_to_linear_data(skb,
  586. (unsigned char *)pDB->vaddr, frmlen);
  587. skb_put(skb, frmlen);
  588. skb->protocol = eth_type_trans(skb, dev);
  589. netif_rx(skb); /* pass the packet to upper layers */
  590. } else {
  591. if (au1000_debug > 4) {
  592. if (status & RX_MISSED_FRAME)
  593. printk("rx miss\n");
  594. if (status & RX_WDOG_TIMER)
  595. printk("rx wdog\n");
  596. if (status & RX_RUNT)
  597. printk("rx runt\n");
  598. if (status & RX_OVERLEN)
  599. printk("rx overlen\n");
  600. if (status & RX_COLL)
  601. printk("rx coll\n");
  602. if (status & RX_MII_ERROR)
  603. printk("rx mii error\n");
  604. if (status & RX_CRC_ERROR)
  605. printk("rx crc error\n");
  606. if (status & RX_LEN_ERROR)
  607. printk("rx len error\n");
  608. if (status & RX_U_CNTRL_FRAME)
  609. printk("rx u control frame\n");
  610. }
  611. }
  612. prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
  613. aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
  614. au_sync();
  615. /* next descriptor */
  616. prxd = aup->rx_dma_ring[aup->rx_head];
  617. buff_stat = prxd->buff_stat;
  618. }
  619. return 0;
  620. }
  621. static void au1000_update_tx_stats(struct net_device *dev, u32 status)
  622. {
  623. struct au1000_private *aup = netdev_priv(dev);
  624. struct net_device_stats *ps = &dev->stats;
  625. if (status & TX_FRAME_ABORTED) {
  626. if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
  627. if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
  628. /* any other tx errors are only valid
  629. * in half duplex mode */
  630. ps->tx_errors++;
  631. ps->tx_aborted_errors++;
  632. }
  633. } else {
  634. ps->tx_errors++;
  635. ps->tx_aborted_errors++;
  636. if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
  637. ps->tx_carrier_errors++;
  638. }
  639. }
  640. }
  641. /*
  642. * Called from the interrupt service routine to acknowledge
  643. * the TX DONE bits. This is a must if the irq is setup as
  644. * edge triggered.
  645. */
  646. static void au1000_tx_ack(struct net_device *dev)
  647. {
  648. struct au1000_private *aup = netdev_priv(dev);
  649. volatile tx_dma_t *ptxd;
  650. ptxd = aup->tx_dma_ring[aup->tx_tail];
  651. while (ptxd->buff_stat & TX_T_DONE) {
  652. au1000_update_tx_stats(dev, ptxd->status);
  653. ptxd->buff_stat &= ~TX_T_DONE;
  654. ptxd->len = 0;
  655. au_sync();
  656. aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
  657. ptxd = aup->tx_dma_ring[aup->tx_tail];
  658. if (aup->tx_full) {
  659. aup->tx_full = 0;
  660. netif_wake_queue(dev);
  661. }
  662. }
  663. }
  664. /*
  665. * Au1000 interrupt service routine.
  666. */
  667. static irqreturn_t au1000_interrupt(int irq, void *dev_id)
  668. {
  669. struct net_device *dev = dev_id;
  670. /* Handle RX interrupts first to minimize chance of overrun */
  671. au1000_rx(dev);
  672. au1000_tx_ack(dev);
  673. return IRQ_RETVAL(1);
  674. }
  675. static int au1000_open(struct net_device *dev)
  676. {
  677. int retval;
  678. struct au1000_private *aup = netdev_priv(dev);
  679. netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
  680. retval = request_irq(dev->irq, au1000_interrupt, 0,
  681. dev->name, dev);
  682. if (retval) {
  683. netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
  684. return retval;
  685. }
  686. retval = au1000_init(dev);
  687. if (retval) {
  688. netdev_err(dev, "error in au1000_init\n");
  689. free_irq(dev->irq, dev);
  690. return retval;
  691. }
  692. if (aup->phy_dev) {
  693. /* cause the PHY state machine to schedule a link state check */
  694. aup->phy_dev->state = PHY_CHANGELINK;
  695. phy_start(aup->phy_dev);
  696. }
  697. netif_start_queue(dev);
  698. netif_dbg(aup, drv, dev, "open: Initialization done.\n");
  699. return 0;
  700. }
  701. static int au1000_close(struct net_device *dev)
  702. {
  703. unsigned long flags;
  704. struct au1000_private *const aup = netdev_priv(dev);
  705. netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
  706. if (aup->phy_dev)
  707. phy_stop(aup->phy_dev);
  708. spin_lock_irqsave(&aup->lock, flags);
  709. au1000_reset_mac_unlocked (dev);
  710. /* stop the device */
  711. netif_stop_queue(dev);
  712. /* disable the interrupt */
  713. free_irq(dev->irq, dev);
  714. spin_unlock_irqrestore(&aup->lock, flags);
  715. return 0;
  716. }
  717. /*
  718. * Au1000 transmit routine.
  719. */
  720. static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
  721. {
  722. struct au1000_private *aup = netdev_priv(dev);
  723. struct net_device_stats *ps = &dev->stats;
  724. volatile tx_dma_t *ptxd;
  725. u32 buff_stat;
  726. db_dest_t *pDB;
  727. int i;
  728. netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
  729. (unsigned)aup, skb->len,
  730. skb->data, aup->tx_head);
  731. ptxd = aup->tx_dma_ring[aup->tx_head];
  732. buff_stat = ptxd->buff_stat;
  733. if (buff_stat & TX_DMA_ENABLE) {
  734. /* We've wrapped around and the transmitter is still busy */
  735. netif_stop_queue(dev);
  736. aup->tx_full = 1;
  737. return NETDEV_TX_BUSY;
  738. } else if (buff_stat & TX_T_DONE) {
  739. au1000_update_tx_stats(dev, ptxd->status);
  740. ptxd->len = 0;
  741. }
  742. if (aup->tx_full) {
  743. aup->tx_full = 0;
  744. netif_wake_queue(dev);
  745. }
  746. pDB = aup->tx_db_inuse[aup->tx_head];
  747. skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
  748. if (skb->len < ETH_ZLEN) {
  749. for (i = skb->len; i < ETH_ZLEN; i++) {
  750. ((char *)pDB->vaddr)[i] = 0;
  751. }
  752. ptxd->len = ETH_ZLEN;
  753. } else
  754. ptxd->len = skb->len;
  755. ps->tx_packets++;
  756. ps->tx_bytes += ptxd->len;
  757. ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
  758. au_sync();
  759. dev_kfree_skb(skb);
  760. aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
  761. return NETDEV_TX_OK;
  762. }
  763. /*
  764. * The Tx ring has been full longer than the watchdog timeout
  765. * value. The transmitter must be hung?
  766. */
  767. static void au1000_tx_timeout(struct net_device *dev)
  768. {
  769. netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
  770. au1000_reset_mac(dev);
  771. au1000_init(dev);
  772. dev->trans_start = jiffies; /* prevent tx timeout */
  773. netif_wake_queue(dev);
  774. }
  775. static void au1000_multicast_list(struct net_device *dev)
  776. {
  777. struct au1000_private *aup = netdev_priv(dev);
  778. netif_dbg(aup, drv, dev, "au1000_multicast_list: flags=%x\n", dev->flags);
  779. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  780. aup->mac->control |= MAC_PROMISCUOUS;
  781. } else if ((dev->flags & IFF_ALLMULTI) ||
  782. netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
  783. aup->mac->control |= MAC_PASS_ALL_MULTI;
  784. aup->mac->control &= ~MAC_PROMISCUOUS;
  785. netdev_info(dev, "Pass all multicast\n");
  786. } else {
  787. struct netdev_hw_addr *ha;
  788. u32 mc_filter[2]; /* Multicast hash filter */
  789. mc_filter[1] = mc_filter[0] = 0;
  790. netdev_for_each_mc_addr(ha, dev)
  791. set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
  792. (long *)mc_filter);
  793. aup->mac->multi_hash_high = mc_filter[1];
  794. aup->mac->multi_hash_low = mc_filter[0];
  795. aup->mac->control &= ~MAC_PROMISCUOUS;
  796. aup->mac->control |= MAC_HASH_MODE;
  797. }
  798. }
  799. static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  800. {
  801. struct au1000_private *aup = netdev_priv(dev);
  802. if (!netif_running(dev))
  803. return -EINVAL;
  804. if (!aup->phy_dev)
  805. return -EINVAL; /* PHY not controllable */
  806. return phy_mii_ioctl(aup->phy_dev, rq, cmd);
  807. }
  808. static const struct net_device_ops au1000_netdev_ops = {
  809. .ndo_open = au1000_open,
  810. .ndo_stop = au1000_close,
  811. .ndo_start_xmit = au1000_tx,
  812. .ndo_set_multicast_list = au1000_multicast_list,
  813. .ndo_do_ioctl = au1000_ioctl,
  814. .ndo_tx_timeout = au1000_tx_timeout,
  815. .ndo_set_mac_address = eth_mac_addr,
  816. .ndo_validate_addr = eth_validate_addr,
  817. .ndo_change_mtu = eth_change_mtu,
  818. };
  819. static int __devinit au1000_probe(struct platform_device *pdev)
  820. {
  821. static unsigned version_printed;
  822. struct au1000_private *aup = NULL;
  823. struct au1000_eth_platform_data *pd;
  824. struct net_device *dev = NULL;
  825. db_dest_t *pDB, *pDBfree;
  826. int irq, i, err = 0;
  827. struct resource *base, *macen;
  828. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  829. if (!base) {
  830. dev_err(&pdev->dev, "failed to retrieve base register\n");
  831. err = -ENODEV;
  832. goto out;
  833. }
  834. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  835. if (!macen) {
  836. dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
  837. err = -ENODEV;
  838. goto out;
  839. }
  840. irq = platform_get_irq(pdev, 0);
  841. if (irq < 0) {
  842. dev_err(&pdev->dev, "failed to retrieve IRQ\n");
  843. err = -ENODEV;
  844. goto out;
  845. }
  846. if (!request_mem_region(base->start, resource_size(base), pdev->name)) {
  847. dev_err(&pdev->dev, "failed to request memory region for base registers\n");
  848. err = -ENXIO;
  849. goto out;
  850. }
  851. if (!request_mem_region(macen->start, resource_size(macen), pdev->name)) {
  852. dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
  853. err = -ENXIO;
  854. goto err_request;
  855. }
  856. dev = alloc_etherdev(sizeof(struct au1000_private));
  857. if (!dev) {
  858. dev_err(&pdev->dev, "alloc_etherdev failed\n");
  859. err = -ENOMEM;
  860. goto err_alloc;
  861. }
  862. SET_NETDEV_DEV(dev, &pdev->dev);
  863. platform_set_drvdata(pdev, dev);
  864. aup = netdev_priv(dev);
  865. spin_lock_init(&aup->lock);
  866. aup->msg_enable = (au1000_debug < 4 ? AU1000_DEF_MSG_ENABLE : au1000_debug);
  867. /* Allocate the data buffers */
  868. /* Snooping works fine with eth on all au1xxx */
  869. aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
  870. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  871. &aup->dma_addr, 0);
  872. if (!aup->vaddr) {
  873. dev_err(&pdev->dev, "failed to allocate data buffers\n");
  874. err = -ENOMEM;
  875. goto err_vaddr;
  876. }
  877. /* aup->mac is the base address of the MAC's registers */
  878. aup->mac = (volatile mac_reg_t *)ioremap_nocache(base->start, resource_size(base));
  879. if (!aup->mac) {
  880. dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
  881. err = -ENXIO;
  882. goto err_remap1;
  883. }
  884. /* Setup some variables for quick register address access */
  885. aup->enable = (volatile u32 *)ioremap_nocache(macen->start, resource_size(macen));
  886. if (!aup->enable) {
  887. dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
  888. err = -ENXIO;
  889. goto err_remap2;
  890. }
  891. aup->mac_id = pdev->id;
  892. if (pdev->id == 0)
  893. au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
  894. else if (pdev->id == 1)
  895. au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
  896. /* set a random MAC now in case platform_data doesn't provide one */
  897. random_ether_addr(dev->dev_addr);
  898. *aup->enable = 0;
  899. aup->mac_enabled = 0;
  900. pd = pdev->dev.platform_data;
  901. if (!pd) {
  902. dev_info(&pdev->dev, "no platform_data passed, PHY search on MAC0\n");
  903. aup->phy1_search_mac0 = 1;
  904. } else {
  905. if (is_valid_ether_addr(pd->mac))
  906. memcpy(dev->dev_addr, pd->mac, 6);
  907. aup->phy_static_config = pd->phy_static_config;
  908. aup->phy_search_highest_addr = pd->phy_search_highest_addr;
  909. aup->phy1_search_mac0 = pd->phy1_search_mac0;
  910. aup->phy_addr = pd->phy_addr;
  911. aup->phy_busid = pd->phy_busid;
  912. aup->phy_irq = pd->phy_irq;
  913. }
  914. if (aup->phy_busid && aup->phy_busid > 0) {
  915. dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII"
  916. "bus not supported yet\n");
  917. err = -ENODEV;
  918. goto err_mdiobus_alloc;
  919. }
  920. aup->mii_bus = mdiobus_alloc();
  921. if (aup->mii_bus == NULL) {
  922. dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
  923. err = -ENOMEM;
  924. goto err_mdiobus_alloc;
  925. }
  926. aup->mii_bus->priv = dev;
  927. aup->mii_bus->read = au1000_mdiobus_read;
  928. aup->mii_bus->write = au1000_mdiobus_write;
  929. aup->mii_bus->reset = au1000_mdiobus_reset;
  930. aup->mii_bus->name = "au1000_eth_mii";
  931. snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
  932. aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  933. if (aup->mii_bus->irq == NULL)
  934. goto err_out;
  935. for (i = 0; i < PHY_MAX_ADDR; ++i)
  936. aup->mii_bus->irq[i] = PHY_POLL;
  937. /* if known, set corresponding PHY IRQs */
  938. if (aup->phy_static_config)
  939. if (aup->phy_irq && aup->phy_busid == aup->mac_id)
  940. aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
  941. err = mdiobus_register(aup->mii_bus);
  942. if (err) {
  943. dev_err(&pdev->dev, "failed to register MDIO bus\n");
  944. goto err_mdiobus_reg;
  945. }
  946. if (au1000_mii_probe(dev) != 0)
  947. goto err_out;
  948. pDBfree = NULL;
  949. /* setup the data buffer descriptors and attach a buffer to each one */
  950. pDB = aup->db;
  951. for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
  952. pDB->pnext = pDBfree;
  953. pDBfree = pDB;
  954. pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
  955. pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
  956. pDB++;
  957. }
  958. aup->pDBfree = pDBfree;
  959. for (i = 0; i < NUM_RX_DMA; i++) {
  960. pDB = au1000_GetFreeDB(aup);
  961. if (!pDB) {
  962. goto err_out;
  963. }
  964. aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  965. aup->rx_db_inuse[i] = pDB;
  966. }
  967. for (i = 0; i < NUM_TX_DMA; i++) {
  968. pDB = au1000_GetFreeDB(aup);
  969. if (!pDB) {
  970. goto err_out;
  971. }
  972. aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  973. aup->tx_dma_ring[i]->len = 0;
  974. aup->tx_db_inuse[i] = pDB;
  975. }
  976. dev->base_addr = base->start;
  977. dev->irq = irq;
  978. dev->netdev_ops = &au1000_netdev_ops;
  979. SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
  980. dev->watchdog_timeo = ETH_TX_TIMEOUT;
  981. /*
  982. * The boot code uses the ethernet controller, so reset it to start
  983. * fresh. au1000_init() expects that the device is in reset state.
  984. */
  985. au1000_reset_mac(dev);
  986. err = register_netdev(dev);
  987. if (err) {
  988. netdev_err(dev, "Cannot register net device, aborting.\n");
  989. goto err_out;
  990. }
  991. netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
  992. (unsigned long)base->start, irq);
  993. if (version_printed++ == 0)
  994. printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
  995. return 0;
  996. err_out:
  997. if (aup->mii_bus != NULL)
  998. mdiobus_unregister(aup->mii_bus);
  999. /* here we should have a valid dev plus aup-> register addresses
  1000. * so we can reset the mac properly.*/
  1001. au1000_reset_mac(dev);
  1002. for (i = 0; i < NUM_RX_DMA; i++) {
  1003. if (aup->rx_db_inuse[i])
  1004. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1005. }
  1006. for (i = 0; i < NUM_TX_DMA; i++) {
  1007. if (aup->tx_db_inuse[i])
  1008. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1009. }
  1010. err_mdiobus_reg:
  1011. mdiobus_free(aup->mii_bus);
  1012. err_mdiobus_alloc:
  1013. iounmap(aup->enable);
  1014. err_remap2:
  1015. iounmap(aup->mac);
  1016. err_remap1:
  1017. dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1018. (void *)aup->vaddr, aup->dma_addr);
  1019. err_vaddr:
  1020. free_netdev(dev);
  1021. err_alloc:
  1022. release_mem_region(macen->start, resource_size(macen));
  1023. err_request:
  1024. release_mem_region(base->start, resource_size(base));
  1025. out:
  1026. return err;
  1027. }
  1028. static int __devexit au1000_remove(struct platform_device *pdev)
  1029. {
  1030. struct net_device *dev = platform_get_drvdata(pdev);
  1031. struct au1000_private *aup = netdev_priv(dev);
  1032. int i;
  1033. struct resource *base, *macen;
  1034. platform_set_drvdata(pdev, NULL);
  1035. unregister_netdev(dev);
  1036. mdiobus_unregister(aup->mii_bus);
  1037. mdiobus_free(aup->mii_bus);
  1038. for (i = 0; i < NUM_RX_DMA; i++)
  1039. if (aup->rx_db_inuse[i])
  1040. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1041. for (i = 0; i < NUM_TX_DMA; i++)
  1042. if (aup->tx_db_inuse[i])
  1043. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1044. dma_free_noncoherent(NULL, MAX_BUF_SIZE *
  1045. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1046. (void *)aup->vaddr, aup->dma_addr);
  1047. iounmap(aup->mac);
  1048. iounmap(aup->enable);
  1049. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1050. release_mem_region(base->start, resource_size(base));
  1051. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1052. release_mem_region(macen->start, resource_size(macen));
  1053. free_netdev(dev);
  1054. return 0;
  1055. }
  1056. static struct platform_driver au1000_eth_driver = {
  1057. .probe = au1000_probe,
  1058. .remove = __devexit_p(au1000_remove),
  1059. .driver = {
  1060. .name = "au1000-eth",
  1061. .owner = THIS_MODULE,
  1062. },
  1063. };
  1064. MODULE_ALIAS("platform:au1000-eth");
  1065. static int __init au1000_init_module(void)
  1066. {
  1067. return platform_driver_register(&au1000_eth_driver);
  1068. }
  1069. static void __exit au1000_exit_module(void)
  1070. {
  1071. platform_driver_unregister(&au1000_eth_driver);
  1072. }
  1073. module_init(au1000_init_module);
  1074. module_exit(au1000_exit_module);