nv17_tv.c 23 KB

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  1. /*
  2. * Copyright (C) 2009 Francisco Jerez.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "drmP.h"
  27. #include "drm_crtc_helper.h"
  28. #include "nouveau_drv.h"
  29. #include "nouveau_encoder.h"
  30. #include "nouveau_connector.h"
  31. #include "nouveau_crtc.h"
  32. #include "nouveau_hw.h"
  33. #include "nv17_tv.h"
  34. static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
  35. {
  36. struct drm_device *dev = encoder->dev;
  37. struct drm_nouveau_private *dev_priv = dev->dev_private;
  38. struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
  39. uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
  40. uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
  41. fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
  42. uint32_t sample = 0;
  43. int head;
  44. #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
  45. testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
  46. if (dev_priv->vbios.tvdactestval)
  47. testval = dev_priv->vbios.tvdactestval;
  48. dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
  49. head = (dacclk & 0x100) >> 8;
  50. /* Save the previous state. */
  51. gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1);
  52. gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0);
  53. fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
  54. fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
  55. fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
  56. fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
  57. test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
  58. ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
  59. ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
  60. ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
  61. /* Prepare the DAC for load detection. */
  62. gpio->set(dev, DCB_GPIO_TVDAC1, true);
  63. gpio->set(dev, DCB_GPIO_TVDAC0, true);
  64. NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
  65. NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
  66. NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
  67. NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
  68. NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
  69. NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
  70. NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
  71. NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
  72. NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
  73. NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
  74. NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  75. (dacclk & ~0xff) | 0x22);
  76. msleep(1);
  77. NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  78. (dacclk & ~0xff) | 0x21);
  79. NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
  80. NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
  81. /* Sample pin 0x4 (usually S-video luma). */
  82. NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
  83. msleep(20);
  84. sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
  85. & 0x4 << 28;
  86. /* Sample the remaining pins. */
  87. NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
  88. msleep(20);
  89. sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
  90. & 0xa << 28;
  91. /* Restore the previous state. */
  92. NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
  93. NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
  94. NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
  95. NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
  96. NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
  97. NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
  98. NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
  99. NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
  100. NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
  101. gpio->set(dev, DCB_GPIO_TVDAC1, gpio1);
  102. gpio->set(dev, DCB_GPIO_TVDAC0, gpio0);
  103. return sample;
  104. }
  105. static bool
  106. get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
  107. {
  108. /* Zotac FX5200 */
  109. if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) ||
  110. nv_match_device(dev, 0x0322, 0x19da, 0x2035)) {
  111. *pin_mask = 0xc;
  112. return false;
  113. }
  114. /* MSI nForce2 IGP */
  115. if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) {
  116. *pin_mask = 0xc;
  117. return false;
  118. }
  119. return true;
  120. }
  121. static enum drm_connector_status
  122. nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
  123. {
  124. struct drm_device *dev = encoder->dev;
  125. struct drm_nouveau_private *dev_priv = dev->dev_private;
  126. struct drm_mode_config *conf = &dev->mode_config;
  127. struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
  128. struct dcb_entry *dcb = tv_enc->base.dcb;
  129. bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
  130. if (nv04_dac_in_use(encoder))
  131. return connector_status_disconnected;
  132. if (reliable) {
  133. if (dev_priv->chipset == 0x42 ||
  134. dev_priv->chipset == 0x43)
  135. tv_enc->pin_mask =
  136. nv42_tv_sample_load(encoder) >> 28 & 0xe;
  137. else
  138. tv_enc->pin_mask =
  139. nv17_dac_sample_load(encoder) >> 28 & 0xe;
  140. }
  141. switch (tv_enc->pin_mask) {
  142. case 0x2:
  143. case 0x4:
  144. tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
  145. break;
  146. case 0xc:
  147. tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
  148. break;
  149. case 0xe:
  150. if (dcb->tvconf.has_component_output)
  151. tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
  152. else
  153. tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
  154. break;
  155. default:
  156. tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
  157. break;
  158. }
  159. drm_connector_property_set_value(connector,
  160. conf->tv_subconnector_property,
  161. tv_enc->subconnector);
  162. if (!reliable) {
  163. return connector_status_unknown;
  164. } else if (tv_enc->subconnector) {
  165. NV_INFO(dev, "Load detected on output %c\n",
  166. '@' + ffs(dcb->or));
  167. return connector_status_connected;
  168. } else {
  169. return connector_status_disconnected;
  170. }
  171. }
  172. static const struct {
  173. int hdisplay;
  174. int vdisplay;
  175. } modes[] = {
  176. { 640, 400 },
  177. { 640, 480 },
  178. { 720, 480 },
  179. { 720, 576 },
  180. { 800, 600 },
  181. { 1024, 768 },
  182. { 1280, 720 },
  183. { 1280, 1024 },
  184. { 1920, 1080 }
  185. };
  186. static int nv17_tv_get_modes(struct drm_encoder *encoder,
  187. struct drm_connector *connector)
  188. {
  189. struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
  190. struct drm_display_mode *mode;
  191. struct drm_display_mode *output_mode;
  192. int n = 0;
  193. int i;
  194. if (tv_norm->kind != CTV_ENC_MODE) {
  195. struct drm_display_mode *tv_mode;
  196. for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
  197. mode = drm_mode_duplicate(encoder->dev, tv_mode);
  198. mode->clock = tv_norm->tv_enc_mode.vrefresh *
  199. mode->htotal / 1000 *
  200. mode->vtotal / 1000;
  201. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  202. mode->clock *= 2;
  203. if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
  204. mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
  205. mode->type |= DRM_MODE_TYPE_PREFERRED;
  206. drm_mode_probed_add(connector, mode);
  207. n++;
  208. }
  209. return n;
  210. }
  211. /* tv_norm->kind == CTV_ENC_MODE */
  212. output_mode = &tv_norm->ctv_enc_mode.mode;
  213. for (i = 0; i < ARRAY_SIZE(modes); i++) {
  214. if (modes[i].hdisplay > output_mode->hdisplay ||
  215. modes[i].vdisplay > output_mode->vdisplay)
  216. continue;
  217. if (modes[i].hdisplay == output_mode->hdisplay &&
  218. modes[i].vdisplay == output_mode->vdisplay) {
  219. mode = drm_mode_duplicate(encoder->dev, output_mode);
  220. mode->type |= DRM_MODE_TYPE_PREFERRED;
  221. } else {
  222. mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
  223. modes[i].vdisplay, 60, false,
  224. output_mode->flags & DRM_MODE_FLAG_INTERLACE,
  225. false);
  226. }
  227. /* CVT modes are sometimes unsuitable... */
  228. if (output_mode->hdisplay <= 720
  229. || output_mode->hdisplay >= 1920) {
  230. mode->htotal = output_mode->htotal;
  231. mode->hsync_start = (mode->hdisplay + (mode->htotal
  232. - mode->hdisplay) * 9 / 10) & ~7;
  233. mode->hsync_end = mode->hsync_start + 8;
  234. }
  235. if (output_mode->vdisplay >= 1024) {
  236. mode->vtotal = output_mode->vtotal;
  237. mode->vsync_start = output_mode->vsync_start;
  238. mode->vsync_end = output_mode->vsync_end;
  239. }
  240. mode->type |= DRM_MODE_TYPE_DRIVER;
  241. drm_mode_probed_add(connector, mode);
  242. n++;
  243. }
  244. return n;
  245. }
  246. static int nv17_tv_mode_valid(struct drm_encoder *encoder,
  247. struct drm_display_mode *mode)
  248. {
  249. struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
  250. if (tv_norm->kind == CTV_ENC_MODE) {
  251. struct drm_display_mode *output_mode =
  252. &tv_norm->ctv_enc_mode.mode;
  253. if (mode->clock > 400000)
  254. return MODE_CLOCK_HIGH;
  255. if (mode->hdisplay > output_mode->hdisplay ||
  256. mode->vdisplay > output_mode->vdisplay)
  257. return MODE_BAD;
  258. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
  259. (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
  260. return MODE_NO_INTERLACE;
  261. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  262. return MODE_NO_DBLESCAN;
  263. } else {
  264. const int vsync_tolerance = 600;
  265. if (mode->clock > 70000)
  266. return MODE_CLOCK_HIGH;
  267. if (abs(drm_mode_vrefresh(mode) * 1000 -
  268. tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
  269. return MODE_VSYNC;
  270. /* The encoder takes care of the actual interlacing */
  271. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  272. return MODE_NO_INTERLACE;
  273. }
  274. return MODE_OK;
  275. }
  276. static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
  277. struct drm_display_mode *mode,
  278. struct drm_display_mode *adjusted_mode)
  279. {
  280. struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
  281. if (nv04_dac_in_use(encoder))
  282. return false;
  283. if (tv_norm->kind == CTV_ENC_MODE)
  284. adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
  285. else
  286. adjusted_mode->clock = 90000;
  287. return true;
  288. }
  289. static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
  290. {
  291. struct drm_device *dev = encoder->dev;
  292. struct drm_nouveau_private *dev_priv = dev->dev_private;
  293. struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
  294. struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
  295. struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
  296. if (nouveau_encoder(encoder)->last_dpms == mode)
  297. return;
  298. nouveau_encoder(encoder)->last_dpms = mode;
  299. NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
  300. mode, nouveau_encoder(encoder)->dcb->index);
  301. regs->ptv_200 &= ~1;
  302. if (tv_norm->kind == CTV_ENC_MODE) {
  303. nv04_dfp_update_fp_control(encoder, mode);
  304. } else {
  305. nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
  306. if (mode == DRM_MODE_DPMS_ON)
  307. regs->ptv_200 |= 1;
  308. }
  309. nv_load_ptv(dev, regs, 200);
  310. gpio->set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
  311. gpio->set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
  312. nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
  313. }
  314. static void nv17_tv_prepare(struct drm_encoder *encoder)
  315. {
  316. struct drm_device *dev = encoder->dev;
  317. struct drm_nouveau_private *dev_priv = dev->dev_private;
  318. struct drm_encoder_helper_funcs *helper = encoder->helper_private;
  319. struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
  320. int head = nouveau_crtc(encoder->crtc)->index;
  321. uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
  322. NV_CIO_CRE_LCD__INDEX];
  323. uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
  324. nv04_dac_output_offset(encoder);
  325. uint32_t dacclk;
  326. helper->dpms(encoder, DRM_MODE_DPMS_OFF);
  327. nv04_dfp_disable(dev, head);
  328. /* Unbind any FP encoders from this head if we need the FP
  329. * stuff enabled. */
  330. if (tv_norm->kind == CTV_ENC_MODE) {
  331. struct drm_encoder *enc;
  332. list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
  333. struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
  334. if ((dcb->type == OUTPUT_TMDS ||
  335. dcb->type == OUTPUT_LVDS) &&
  336. !enc->crtc &&
  337. nv04_dfp_get_bound_head(dev, dcb) == head) {
  338. nv04_dfp_bind_head(dev, dcb, head ^ 1,
  339. dev_priv->vbios.fp.dual_link);
  340. }
  341. }
  342. }
  343. /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
  344. * at LCD__INDEX which we don't alter
  345. */
  346. if (!(*cr_lcd & 0x44)) {
  347. if (tv_norm->kind == CTV_ENC_MODE)
  348. *cr_lcd = 0x1 | (head ? 0x0 : 0x8);
  349. else
  350. *cr_lcd = 0;
  351. }
  352. /* Set the DACCLK register */
  353. dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
  354. if (dev_priv->card_type == NV_40)
  355. dacclk |= 0x1a << 16;
  356. if (tv_norm->kind == CTV_ENC_MODE) {
  357. dacclk |= 0x20;
  358. if (head)
  359. dacclk |= 0x100;
  360. else
  361. dacclk &= ~0x100;
  362. } else {
  363. dacclk |= 0x10;
  364. }
  365. NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
  366. }
  367. static void nv17_tv_mode_set(struct drm_encoder *encoder,
  368. struct drm_display_mode *drm_mode,
  369. struct drm_display_mode *adjusted_mode)
  370. {
  371. struct drm_device *dev = encoder->dev;
  372. struct drm_nouveau_private *dev_priv = dev->dev_private;
  373. int head = nouveau_crtc(encoder->crtc)->index;
  374. struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
  375. struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
  376. struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
  377. int i;
  378. regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
  379. regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
  380. regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
  381. regs->tv_setup = 1;
  382. regs->ramdac_8c0 = 0x0;
  383. if (tv_norm->kind == TV_ENC_MODE) {
  384. tv_regs->ptv_200 = 0x13111100;
  385. if (head)
  386. tv_regs->ptv_200 |= 0x10;
  387. tv_regs->ptv_20c = 0x808010;
  388. tv_regs->ptv_304 = 0x2d00000;
  389. tv_regs->ptv_600 = 0x0;
  390. tv_regs->ptv_60c = 0x0;
  391. tv_regs->ptv_610 = 0x1e00000;
  392. if (tv_norm->tv_enc_mode.vdisplay == 576) {
  393. tv_regs->ptv_508 = 0x1200000;
  394. tv_regs->ptv_614 = 0x33;
  395. } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
  396. tv_regs->ptv_508 = 0xf00000;
  397. tv_regs->ptv_614 = 0x13;
  398. }
  399. if (dev_priv->card_type >= NV_30) {
  400. tv_regs->ptv_500 = 0xe8e0;
  401. tv_regs->ptv_504 = 0x1710;
  402. tv_regs->ptv_604 = 0x0;
  403. tv_regs->ptv_608 = 0x0;
  404. } else {
  405. if (tv_norm->tv_enc_mode.vdisplay == 576) {
  406. tv_regs->ptv_604 = 0x20;
  407. tv_regs->ptv_608 = 0x10;
  408. tv_regs->ptv_500 = 0x19710;
  409. tv_regs->ptv_504 = 0x68f0;
  410. } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
  411. tv_regs->ptv_604 = 0x10;
  412. tv_regs->ptv_608 = 0x20;
  413. tv_regs->ptv_500 = 0x4b90;
  414. tv_regs->ptv_504 = 0x1b480;
  415. }
  416. }
  417. for (i = 0; i < 0x40; i++)
  418. tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
  419. } else {
  420. struct drm_display_mode *output_mode =
  421. &tv_norm->ctv_enc_mode.mode;
  422. /* The registers in PRAMDAC+0xc00 control some timings and CSC
  423. * parameters for the CTV encoder (It's only used for "HD" TV
  424. * modes, I don't think I have enough working to guess what
  425. * they exactly mean...), it's probably connected at the
  426. * output of the FP encoder, but it also needs the analog
  427. * encoder in its OR enabled and routed to the head it's
  428. * using. It's enabled with the DACCLK register, bits [5:4].
  429. */
  430. for (i = 0; i < 38; i++)
  431. regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
  432. regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
  433. regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
  434. regs->fp_horiz_regs[FP_SYNC_START] =
  435. output_mode->hsync_start - 1;
  436. regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
  437. regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
  438. max((output_mode->hdisplay-600)/40 - 1, 1);
  439. regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
  440. regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
  441. regs->fp_vert_regs[FP_SYNC_START] =
  442. output_mode->vsync_start - 1;
  443. regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
  444. regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
  445. regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
  446. NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
  447. NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
  448. if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
  449. regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
  450. if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
  451. regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
  452. regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
  453. NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
  454. NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
  455. NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
  456. NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
  457. NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
  458. NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
  459. regs->fp_debug_2 = 0;
  460. regs->fp_margin_color = 0x801080;
  461. }
  462. }
  463. static void nv17_tv_commit(struct drm_encoder *encoder)
  464. {
  465. struct drm_device *dev = encoder->dev;
  466. struct drm_nouveau_private *dev_priv = dev->dev_private;
  467. struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
  468. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  469. struct drm_encoder_helper_funcs *helper = encoder->helper_private;
  470. if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
  471. nv17_tv_update_rescaler(encoder);
  472. nv17_tv_update_properties(encoder);
  473. } else {
  474. nv17_ctv_update_rescaler(encoder);
  475. }
  476. nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
  477. /* This could use refinement for flatpanels, but it should work */
  478. if (dev_priv->chipset < 0x44)
  479. NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
  480. nv04_dac_output_offset(encoder),
  481. 0xf0000000);
  482. else
  483. NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
  484. nv04_dac_output_offset(encoder),
  485. 0x00100000);
  486. helper->dpms(encoder, DRM_MODE_DPMS_ON);
  487. NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
  488. drm_get_connector_name(
  489. &nouveau_encoder_connector_get(nv_encoder)->base),
  490. nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
  491. }
  492. static void nv17_tv_save(struct drm_encoder *encoder)
  493. {
  494. struct drm_device *dev = encoder->dev;
  495. struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
  496. nouveau_encoder(encoder)->restore.output =
  497. NVReadRAMDAC(dev, 0,
  498. NV_PRAMDAC_DACCLK +
  499. nv04_dac_output_offset(encoder));
  500. nv17_tv_state_save(dev, &tv_enc->saved_state);
  501. tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
  502. }
  503. static void nv17_tv_restore(struct drm_encoder *encoder)
  504. {
  505. struct drm_device *dev = encoder->dev;
  506. NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
  507. nv04_dac_output_offset(encoder),
  508. nouveau_encoder(encoder)->restore.output);
  509. nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
  510. nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
  511. }
  512. static int nv17_tv_create_resources(struct drm_encoder *encoder,
  513. struct drm_connector *connector)
  514. {
  515. struct drm_device *dev = encoder->dev;
  516. struct drm_mode_config *conf = &dev->mode_config;
  517. struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
  518. struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
  519. int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
  520. NUM_LD_TV_NORMS;
  521. int i;
  522. if (nouveau_tv_norm) {
  523. for (i = 0; i < num_tv_norms; i++) {
  524. if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
  525. tv_enc->tv_norm = i;
  526. break;
  527. }
  528. }
  529. if (i == num_tv_norms)
  530. NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
  531. nouveau_tv_norm);
  532. }
  533. drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
  534. drm_connector_attach_property(connector,
  535. conf->tv_select_subconnector_property,
  536. tv_enc->select_subconnector);
  537. drm_connector_attach_property(connector,
  538. conf->tv_subconnector_property,
  539. tv_enc->subconnector);
  540. drm_connector_attach_property(connector,
  541. conf->tv_mode_property,
  542. tv_enc->tv_norm);
  543. drm_connector_attach_property(connector,
  544. conf->tv_flicker_reduction_property,
  545. tv_enc->flicker);
  546. drm_connector_attach_property(connector,
  547. conf->tv_saturation_property,
  548. tv_enc->saturation);
  549. drm_connector_attach_property(connector,
  550. conf->tv_hue_property,
  551. tv_enc->hue);
  552. drm_connector_attach_property(connector,
  553. conf->tv_overscan_property,
  554. tv_enc->overscan);
  555. return 0;
  556. }
  557. static int nv17_tv_set_property(struct drm_encoder *encoder,
  558. struct drm_connector *connector,
  559. struct drm_property *property,
  560. uint64_t val)
  561. {
  562. struct drm_mode_config *conf = &encoder->dev->mode_config;
  563. struct drm_crtc *crtc = encoder->crtc;
  564. struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
  565. struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
  566. bool modes_changed = false;
  567. if (property == conf->tv_overscan_property) {
  568. tv_enc->overscan = val;
  569. if (encoder->crtc) {
  570. if (tv_norm->kind == CTV_ENC_MODE)
  571. nv17_ctv_update_rescaler(encoder);
  572. else
  573. nv17_tv_update_rescaler(encoder);
  574. }
  575. } else if (property == conf->tv_saturation_property) {
  576. if (tv_norm->kind != TV_ENC_MODE)
  577. return -EINVAL;
  578. tv_enc->saturation = val;
  579. nv17_tv_update_properties(encoder);
  580. } else if (property == conf->tv_hue_property) {
  581. if (tv_norm->kind != TV_ENC_MODE)
  582. return -EINVAL;
  583. tv_enc->hue = val;
  584. nv17_tv_update_properties(encoder);
  585. } else if (property == conf->tv_flicker_reduction_property) {
  586. if (tv_norm->kind != TV_ENC_MODE)
  587. return -EINVAL;
  588. tv_enc->flicker = val;
  589. if (encoder->crtc)
  590. nv17_tv_update_rescaler(encoder);
  591. } else if (property == conf->tv_mode_property) {
  592. if (connector->dpms != DRM_MODE_DPMS_OFF)
  593. return -EINVAL;
  594. tv_enc->tv_norm = val;
  595. modes_changed = true;
  596. } else if (property == conf->tv_select_subconnector_property) {
  597. if (tv_norm->kind != TV_ENC_MODE)
  598. return -EINVAL;
  599. tv_enc->select_subconnector = val;
  600. nv17_tv_update_properties(encoder);
  601. } else {
  602. return -EINVAL;
  603. }
  604. if (modes_changed) {
  605. drm_helper_probe_single_connector_modes(connector, 0, 0);
  606. /* Disable the crtc to ensure a full modeset is
  607. * performed whenever it's turned on again. */
  608. if (crtc) {
  609. struct drm_mode_set modeset = {
  610. .crtc = crtc,
  611. };
  612. crtc->funcs->set_config(&modeset);
  613. }
  614. }
  615. return 0;
  616. }
  617. static void nv17_tv_destroy(struct drm_encoder *encoder)
  618. {
  619. struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
  620. NV_DEBUG_KMS(encoder->dev, "\n");
  621. drm_encoder_cleanup(encoder);
  622. kfree(tv_enc);
  623. }
  624. static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
  625. .dpms = nv17_tv_dpms,
  626. .save = nv17_tv_save,
  627. .restore = nv17_tv_restore,
  628. .mode_fixup = nv17_tv_mode_fixup,
  629. .prepare = nv17_tv_prepare,
  630. .commit = nv17_tv_commit,
  631. .mode_set = nv17_tv_mode_set,
  632. .detect = nv17_tv_detect,
  633. };
  634. static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
  635. .get_modes = nv17_tv_get_modes,
  636. .mode_valid = nv17_tv_mode_valid,
  637. .create_resources = nv17_tv_create_resources,
  638. .set_property = nv17_tv_set_property,
  639. };
  640. static struct drm_encoder_funcs nv17_tv_funcs = {
  641. .destroy = nv17_tv_destroy,
  642. };
  643. int
  644. nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
  645. {
  646. struct drm_device *dev = connector->dev;
  647. struct drm_encoder *encoder;
  648. struct nv17_tv_encoder *tv_enc = NULL;
  649. tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
  650. if (!tv_enc)
  651. return -ENOMEM;
  652. tv_enc->overscan = 50;
  653. tv_enc->flicker = 50;
  654. tv_enc->saturation = 50;
  655. tv_enc->hue = 0;
  656. tv_enc->tv_norm = TV_NORM_PAL;
  657. tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
  658. tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
  659. tv_enc->pin_mask = 0;
  660. encoder = to_drm_encoder(&tv_enc->base);
  661. tv_enc->base.dcb = entry;
  662. tv_enc->base.or = ffs(entry->or) - 1;
  663. drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
  664. drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
  665. to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
  666. encoder->possible_crtcs = entry->heads;
  667. encoder->possible_clones = 0;
  668. nv17_tv_create_resources(encoder, connector);
  669. drm_mode_connector_attach_encoder(connector, encoder);
  670. return 0;
  671. }