ohci.c 85 KB

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  1. /*
  2. * Driver for OHCI 1394 controllers
  3. *
  4. * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. */
  20. #include <linux/bug.h>
  21. #include <linux/compiler.h>
  22. #include <linux/delay.h>
  23. #include <linux/device.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/firewire.h>
  26. #include <linux/firewire-constants.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/io.h>
  30. #include <linux/kernel.h>
  31. #include <linux/list.h>
  32. #include <linux/mm.h>
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/mutex.h>
  36. #include <linux/pci.h>
  37. #include <linux/pci_ids.h>
  38. #include <linux/slab.h>
  39. #include <linux/spinlock.h>
  40. #include <linux/string.h>
  41. #include <linux/time.h>
  42. #include <asm/byteorder.h>
  43. #include <asm/page.h>
  44. #include <asm/system.h>
  45. #ifdef CONFIG_PPC_PMAC
  46. #include <asm/pmac_feature.h>
  47. #endif
  48. #include "core.h"
  49. #include "ohci.h"
  50. #define DESCRIPTOR_OUTPUT_MORE 0
  51. #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
  52. #define DESCRIPTOR_INPUT_MORE (2 << 12)
  53. #define DESCRIPTOR_INPUT_LAST (3 << 12)
  54. #define DESCRIPTOR_STATUS (1 << 11)
  55. #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
  56. #define DESCRIPTOR_PING (1 << 7)
  57. #define DESCRIPTOR_YY (1 << 6)
  58. #define DESCRIPTOR_NO_IRQ (0 << 4)
  59. #define DESCRIPTOR_IRQ_ERROR (1 << 4)
  60. #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
  61. #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
  62. #define DESCRIPTOR_WAIT (3 << 0)
  63. struct descriptor {
  64. __le16 req_count;
  65. __le16 control;
  66. __le32 data_address;
  67. __le32 branch_address;
  68. __le16 res_count;
  69. __le16 transfer_status;
  70. } __attribute__((aligned(16)));
  71. #define CONTROL_SET(regs) (regs)
  72. #define CONTROL_CLEAR(regs) ((regs) + 4)
  73. #define COMMAND_PTR(regs) ((regs) + 12)
  74. #define CONTEXT_MATCH(regs) ((regs) + 16)
  75. struct ar_buffer {
  76. struct descriptor descriptor;
  77. struct ar_buffer *next;
  78. __le32 data[0];
  79. };
  80. struct ar_context {
  81. struct fw_ohci *ohci;
  82. struct ar_buffer *current_buffer;
  83. struct ar_buffer *last_buffer;
  84. void *pointer;
  85. u32 regs;
  86. struct tasklet_struct tasklet;
  87. };
  88. struct context;
  89. typedef int (*descriptor_callback_t)(struct context *ctx,
  90. struct descriptor *d,
  91. struct descriptor *last);
  92. /*
  93. * A buffer that contains a block of DMA-able coherent memory used for
  94. * storing a portion of a DMA descriptor program.
  95. */
  96. struct descriptor_buffer {
  97. struct list_head list;
  98. dma_addr_t buffer_bus;
  99. size_t buffer_size;
  100. size_t used;
  101. struct descriptor buffer[0];
  102. };
  103. struct context {
  104. struct fw_ohci *ohci;
  105. u32 regs;
  106. int total_allocation;
  107. /*
  108. * List of page-sized buffers for storing DMA descriptors.
  109. * Head of list contains buffers in use and tail of list contains
  110. * free buffers.
  111. */
  112. struct list_head buffer_list;
  113. /*
  114. * Pointer to a buffer inside buffer_list that contains the tail
  115. * end of the current DMA program.
  116. */
  117. struct descriptor_buffer *buffer_tail;
  118. /*
  119. * The descriptor containing the branch address of the first
  120. * descriptor that has not yet been filled by the device.
  121. */
  122. struct descriptor *last;
  123. /*
  124. * The last descriptor in the DMA program. It contains the branch
  125. * address that must be updated upon appending a new descriptor.
  126. */
  127. struct descriptor *prev;
  128. descriptor_callback_t callback;
  129. struct tasklet_struct tasklet;
  130. };
  131. #define IT_HEADER_SY(v) ((v) << 0)
  132. #define IT_HEADER_TCODE(v) ((v) << 4)
  133. #define IT_HEADER_CHANNEL(v) ((v) << 8)
  134. #define IT_HEADER_TAG(v) ((v) << 14)
  135. #define IT_HEADER_SPEED(v) ((v) << 16)
  136. #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
  137. struct iso_context {
  138. struct fw_iso_context base;
  139. struct context context;
  140. int excess_bytes;
  141. void *header;
  142. size_t header_length;
  143. };
  144. #define CONFIG_ROM_SIZE 1024
  145. struct fw_ohci {
  146. struct fw_card card;
  147. __iomem char *registers;
  148. int node_id;
  149. int generation;
  150. int request_generation; /* for timestamping incoming requests */
  151. unsigned quirks;
  152. unsigned int pri_req_max;
  153. u32 bus_time;
  154. bool is_root;
  155. bool csr_state_setclear_abdicate;
  156. /*
  157. * Spinlock for accessing fw_ohci data. Never call out of
  158. * this driver with this lock held.
  159. */
  160. spinlock_t lock;
  161. struct mutex phy_reg_mutex;
  162. struct ar_context ar_request_ctx;
  163. struct ar_context ar_response_ctx;
  164. struct context at_request_ctx;
  165. struct context at_response_ctx;
  166. u32 it_context_mask; /* unoccupied IT contexts */
  167. struct iso_context *it_context_list;
  168. u64 ir_context_channels; /* unoccupied channels */
  169. u32 ir_context_mask; /* unoccupied IR contexts */
  170. struct iso_context *ir_context_list;
  171. u64 mc_channels; /* channels in use by the multichannel IR context */
  172. bool mc_allocated;
  173. __be32 *config_rom;
  174. dma_addr_t config_rom_bus;
  175. __be32 *next_config_rom;
  176. dma_addr_t next_config_rom_bus;
  177. __be32 next_header;
  178. __le32 *self_id_cpu;
  179. dma_addr_t self_id_bus;
  180. struct tasklet_struct bus_reset_tasklet;
  181. u32 self_id_buffer[512];
  182. };
  183. static inline struct fw_ohci *fw_ohci(struct fw_card *card)
  184. {
  185. return container_of(card, struct fw_ohci, card);
  186. }
  187. #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
  188. #define IR_CONTEXT_BUFFER_FILL 0x80000000
  189. #define IR_CONTEXT_ISOCH_HEADER 0x40000000
  190. #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
  191. #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
  192. #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
  193. #define CONTEXT_RUN 0x8000
  194. #define CONTEXT_WAKE 0x1000
  195. #define CONTEXT_DEAD 0x0800
  196. #define CONTEXT_ACTIVE 0x0400
  197. #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
  198. #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
  199. #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
  200. #define OHCI1394_REGISTER_SIZE 0x800
  201. #define OHCI_LOOP_COUNT 500
  202. #define OHCI1394_PCI_HCI_Control 0x40
  203. #define SELF_ID_BUF_SIZE 0x800
  204. #define OHCI_TCODE_PHY_PACKET 0x0e
  205. #define OHCI_VERSION_1_1 0x010010
  206. static char ohci_driver_name[] = KBUILD_MODNAME;
  207. #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
  208. #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
  209. #define QUIRK_CYCLE_TIMER 1
  210. #define QUIRK_RESET_PACKET 2
  211. #define QUIRK_BE_HEADERS 4
  212. #define QUIRK_NO_1394A 8
  213. #define QUIRK_NO_MSI 16
  214. /* In case of multiple matches in ohci_quirks[], only the first one is used. */
  215. static const struct {
  216. unsigned short vendor, device, flags;
  217. } ohci_quirks[] = {
  218. {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
  219. QUIRK_RESET_PACKET |
  220. QUIRK_NO_1394A},
  221. {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
  222. {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
  223. {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
  224. {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
  225. {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
  226. {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
  227. };
  228. /* This overrides anything that was found in ohci_quirks[]. */
  229. static int param_quirks;
  230. module_param_named(quirks, param_quirks, int, 0644);
  231. MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
  232. ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
  233. ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
  234. ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
  235. ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
  236. ", disable MSI = " __stringify(QUIRK_NO_MSI)
  237. ")");
  238. #define OHCI_PARAM_DEBUG_AT_AR 1
  239. #define OHCI_PARAM_DEBUG_SELFIDS 2
  240. #define OHCI_PARAM_DEBUG_IRQS 4
  241. #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
  242. #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
  243. static int param_debug;
  244. module_param_named(debug, param_debug, int, 0644);
  245. MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
  246. ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
  247. ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
  248. ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
  249. ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
  250. ", or a combination, or all = -1)");
  251. static void log_irqs(u32 evt)
  252. {
  253. if (likely(!(param_debug &
  254. (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
  255. return;
  256. if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
  257. !(evt & OHCI1394_busReset))
  258. return;
  259. fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
  260. evt & OHCI1394_selfIDComplete ? " selfID" : "",
  261. evt & OHCI1394_RQPkt ? " AR_req" : "",
  262. evt & OHCI1394_RSPkt ? " AR_resp" : "",
  263. evt & OHCI1394_reqTxComplete ? " AT_req" : "",
  264. evt & OHCI1394_respTxComplete ? " AT_resp" : "",
  265. evt & OHCI1394_isochRx ? " IR" : "",
  266. evt & OHCI1394_isochTx ? " IT" : "",
  267. evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
  268. evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
  269. evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
  270. evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
  271. evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
  272. evt & OHCI1394_busReset ? " busReset" : "",
  273. evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
  274. OHCI1394_RSPkt | OHCI1394_reqTxComplete |
  275. OHCI1394_respTxComplete | OHCI1394_isochRx |
  276. OHCI1394_isochTx | OHCI1394_postedWriteErr |
  277. OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
  278. OHCI1394_cycleInconsistent |
  279. OHCI1394_regAccessFail | OHCI1394_busReset)
  280. ? " ?" : "");
  281. }
  282. static const char *speed[] = {
  283. [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
  284. };
  285. static const char *power[] = {
  286. [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
  287. [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
  288. };
  289. static const char port[] = { '.', '-', 'p', 'c', };
  290. static char _p(u32 *s, int shift)
  291. {
  292. return port[*s >> shift & 3];
  293. }
  294. static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
  295. {
  296. if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
  297. return;
  298. fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
  299. self_id_count, generation, node_id);
  300. for (; self_id_count--; ++s)
  301. if ((*s & 1 << 23) == 0)
  302. fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
  303. "%s gc=%d %s %s%s%s\n",
  304. *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
  305. speed[*s >> 14 & 3], *s >> 16 & 63,
  306. power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
  307. *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
  308. else
  309. fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
  310. *s, *s >> 24 & 63,
  311. _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
  312. _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
  313. }
  314. static const char *evts[] = {
  315. [0x00] = "evt_no_status", [0x01] = "-reserved-",
  316. [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
  317. [0x04] = "evt_underrun", [0x05] = "evt_overrun",
  318. [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
  319. [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
  320. [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
  321. [0x0c] = "-reserved-", [0x0d] = "-reserved-",
  322. [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
  323. [0x10] = "-reserved-", [0x11] = "ack_complete",
  324. [0x12] = "ack_pending ", [0x13] = "-reserved-",
  325. [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
  326. [0x16] = "ack_busy_B", [0x17] = "-reserved-",
  327. [0x18] = "-reserved-", [0x19] = "-reserved-",
  328. [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
  329. [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
  330. [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
  331. [0x20] = "pending/cancelled",
  332. };
  333. static const char *tcodes[] = {
  334. [0x0] = "QW req", [0x1] = "BW req",
  335. [0x2] = "W resp", [0x3] = "-reserved-",
  336. [0x4] = "QR req", [0x5] = "BR req",
  337. [0x6] = "QR resp", [0x7] = "BR resp",
  338. [0x8] = "cycle start", [0x9] = "Lk req",
  339. [0xa] = "async stream packet", [0xb] = "Lk resp",
  340. [0xc] = "-reserved-", [0xd] = "-reserved-",
  341. [0xe] = "link internal", [0xf] = "-reserved-",
  342. };
  343. static const char *phys[] = {
  344. [0x0] = "phy config packet", [0x1] = "link-on packet",
  345. [0x2] = "self-id packet", [0x3] = "-reserved-",
  346. };
  347. static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
  348. {
  349. int tcode = header[0] >> 4 & 0xf;
  350. char specific[12];
  351. if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
  352. return;
  353. if (unlikely(evt >= ARRAY_SIZE(evts)))
  354. evt = 0x1f;
  355. if (evt == OHCI1394_evt_bus_reset) {
  356. fw_notify("A%c evt_bus_reset, generation %d\n",
  357. dir, (header[2] >> 16) & 0xff);
  358. return;
  359. }
  360. if (header[0] == ~header[1]) {
  361. fw_notify("A%c %s, %s, %08x\n",
  362. dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
  363. return;
  364. }
  365. switch (tcode) {
  366. case 0x0: case 0x6: case 0x8:
  367. snprintf(specific, sizeof(specific), " = %08x",
  368. be32_to_cpu((__force __be32)header[3]));
  369. break;
  370. case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
  371. snprintf(specific, sizeof(specific), " %x,%x",
  372. header[3] >> 16, header[3] & 0xffff);
  373. break;
  374. default:
  375. specific[0] = '\0';
  376. }
  377. switch (tcode) {
  378. case 0xe: case 0xa:
  379. fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
  380. break;
  381. case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
  382. fw_notify("A%c spd %x tl %02x, "
  383. "%04x -> %04x, %s, "
  384. "%s, %04x%08x%s\n",
  385. dir, speed, header[0] >> 10 & 0x3f,
  386. header[1] >> 16, header[0] >> 16, evts[evt],
  387. tcodes[tcode], header[1] & 0xffff, header[2], specific);
  388. break;
  389. default:
  390. fw_notify("A%c spd %x tl %02x, "
  391. "%04x -> %04x, %s, "
  392. "%s%s\n",
  393. dir, speed, header[0] >> 10 & 0x3f,
  394. header[1] >> 16, header[0] >> 16, evts[evt],
  395. tcodes[tcode], specific);
  396. }
  397. }
  398. #else
  399. #define param_debug 0
  400. static inline void log_irqs(u32 evt) {}
  401. static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
  402. static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
  403. #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
  404. static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
  405. {
  406. writel(data, ohci->registers + offset);
  407. }
  408. static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
  409. {
  410. return readl(ohci->registers + offset);
  411. }
  412. static inline void flush_writes(const struct fw_ohci *ohci)
  413. {
  414. /* Do a dummy read to flush writes. */
  415. reg_read(ohci, OHCI1394_Version);
  416. }
  417. static int read_phy_reg(struct fw_ohci *ohci, int addr)
  418. {
  419. u32 val;
  420. int i;
  421. reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
  422. for (i = 0; i < 3 + 100; i++) {
  423. val = reg_read(ohci, OHCI1394_PhyControl);
  424. if (val & OHCI1394_PhyControl_ReadDone)
  425. return OHCI1394_PhyControl_ReadData(val);
  426. /*
  427. * Try a few times without waiting. Sleeping is necessary
  428. * only when the link/PHY interface is busy.
  429. */
  430. if (i >= 3)
  431. msleep(1);
  432. }
  433. fw_error("failed to read phy reg\n");
  434. return -EBUSY;
  435. }
  436. static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
  437. {
  438. int i;
  439. reg_write(ohci, OHCI1394_PhyControl,
  440. OHCI1394_PhyControl_Write(addr, val));
  441. for (i = 0; i < 3 + 100; i++) {
  442. val = reg_read(ohci, OHCI1394_PhyControl);
  443. if (!(val & OHCI1394_PhyControl_WritePending))
  444. return 0;
  445. if (i >= 3)
  446. msleep(1);
  447. }
  448. fw_error("failed to write phy reg\n");
  449. return -EBUSY;
  450. }
  451. static int update_phy_reg(struct fw_ohci *ohci, int addr,
  452. int clear_bits, int set_bits)
  453. {
  454. int ret = read_phy_reg(ohci, addr);
  455. if (ret < 0)
  456. return ret;
  457. /*
  458. * The interrupt status bits are cleared by writing a one bit.
  459. * Avoid clearing them unless explicitly requested in set_bits.
  460. */
  461. if (addr == 5)
  462. clear_bits |= PHY_INT_STATUS_BITS;
  463. return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
  464. }
  465. static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
  466. {
  467. int ret;
  468. ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
  469. if (ret < 0)
  470. return ret;
  471. return read_phy_reg(ohci, addr);
  472. }
  473. static int ohci_read_phy_reg(struct fw_card *card, int addr)
  474. {
  475. struct fw_ohci *ohci = fw_ohci(card);
  476. int ret;
  477. mutex_lock(&ohci->phy_reg_mutex);
  478. ret = read_phy_reg(ohci, addr);
  479. mutex_unlock(&ohci->phy_reg_mutex);
  480. return ret;
  481. }
  482. static int ohci_update_phy_reg(struct fw_card *card, int addr,
  483. int clear_bits, int set_bits)
  484. {
  485. struct fw_ohci *ohci = fw_ohci(card);
  486. int ret;
  487. mutex_lock(&ohci->phy_reg_mutex);
  488. ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
  489. mutex_unlock(&ohci->phy_reg_mutex);
  490. return ret;
  491. }
  492. static int ar_context_add_page(struct ar_context *ctx)
  493. {
  494. struct device *dev = ctx->ohci->card.device;
  495. struct ar_buffer *ab;
  496. dma_addr_t uninitialized_var(ab_bus);
  497. size_t offset;
  498. ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
  499. if (ab == NULL)
  500. return -ENOMEM;
  501. ab->next = NULL;
  502. memset(&ab->descriptor, 0, sizeof(ab->descriptor));
  503. ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
  504. DESCRIPTOR_STATUS |
  505. DESCRIPTOR_BRANCH_ALWAYS);
  506. offset = offsetof(struct ar_buffer, data);
  507. ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
  508. ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
  509. ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
  510. ab->descriptor.branch_address = 0;
  511. wmb(); /* finish init of new descriptors before branch_address update */
  512. ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
  513. ctx->last_buffer->next = ab;
  514. ctx->last_buffer = ab;
  515. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  516. flush_writes(ctx->ohci);
  517. return 0;
  518. }
  519. static void ar_context_release(struct ar_context *ctx)
  520. {
  521. struct ar_buffer *ab, *ab_next;
  522. size_t offset;
  523. dma_addr_t ab_bus;
  524. for (ab = ctx->current_buffer; ab; ab = ab_next) {
  525. ab_next = ab->next;
  526. offset = offsetof(struct ar_buffer, data);
  527. ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
  528. dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
  529. ab, ab_bus);
  530. }
  531. }
  532. #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
  533. #define cond_le32_to_cpu(v) \
  534. (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
  535. #else
  536. #define cond_le32_to_cpu(v) le32_to_cpu(v)
  537. #endif
  538. static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
  539. {
  540. struct fw_ohci *ohci = ctx->ohci;
  541. struct fw_packet p;
  542. u32 status, length, tcode;
  543. int evt;
  544. p.header[0] = cond_le32_to_cpu(buffer[0]);
  545. p.header[1] = cond_le32_to_cpu(buffer[1]);
  546. p.header[2] = cond_le32_to_cpu(buffer[2]);
  547. tcode = (p.header[0] >> 4) & 0x0f;
  548. switch (tcode) {
  549. case TCODE_WRITE_QUADLET_REQUEST:
  550. case TCODE_READ_QUADLET_RESPONSE:
  551. p.header[3] = (__force __u32) buffer[3];
  552. p.header_length = 16;
  553. p.payload_length = 0;
  554. break;
  555. case TCODE_READ_BLOCK_REQUEST :
  556. p.header[3] = cond_le32_to_cpu(buffer[3]);
  557. p.header_length = 16;
  558. p.payload_length = 0;
  559. break;
  560. case TCODE_WRITE_BLOCK_REQUEST:
  561. case TCODE_READ_BLOCK_RESPONSE:
  562. case TCODE_LOCK_REQUEST:
  563. case TCODE_LOCK_RESPONSE:
  564. p.header[3] = cond_le32_to_cpu(buffer[3]);
  565. p.header_length = 16;
  566. p.payload_length = p.header[3] >> 16;
  567. break;
  568. case TCODE_WRITE_RESPONSE:
  569. case TCODE_READ_QUADLET_REQUEST:
  570. case OHCI_TCODE_PHY_PACKET:
  571. p.header_length = 12;
  572. p.payload_length = 0;
  573. break;
  574. default:
  575. /* FIXME: Stop context, discard everything, and restart? */
  576. p.header_length = 0;
  577. p.payload_length = 0;
  578. }
  579. p.payload = (void *) buffer + p.header_length;
  580. /* FIXME: What to do about evt_* errors? */
  581. length = (p.header_length + p.payload_length + 3) / 4;
  582. status = cond_le32_to_cpu(buffer[length]);
  583. evt = (status >> 16) & 0x1f;
  584. p.ack = evt - 16;
  585. p.speed = (status >> 21) & 0x7;
  586. p.timestamp = status & 0xffff;
  587. p.generation = ohci->request_generation;
  588. log_ar_at_event('R', p.speed, p.header, evt);
  589. /*
  590. * Several controllers, notably from NEC and VIA, forget to
  591. * write ack_complete status at PHY packet reception.
  592. */
  593. if (evt == OHCI1394_evt_no_status &&
  594. (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
  595. p.ack = ACK_COMPLETE;
  596. /*
  597. * The OHCI bus reset handler synthesizes a PHY packet with
  598. * the new generation number when a bus reset happens (see
  599. * section 8.4.2.3). This helps us determine when a request
  600. * was received and make sure we send the response in the same
  601. * generation. We only need this for requests; for responses
  602. * we use the unique tlabel for finding the matching
  603. * request.
  604. *
  605. * Alas some chips sometimes emit bus reset packets with a
  606. * wrong generation. We set the correct generation for these
  607. * at a slightly incorrect time (in bus_reset_tasklet).
  608. */
  609. if (evt == OHCI1394_evt_bus_reset) {
  610. if (!(ohci->quirks & QUIRK_RESET_PACKET))
  611. ohci->request_generation = (p.header[2] >> 16) & 0xff;
  612. } else if (ctx == &ohci->ar_request_ctx) {
  613. fw_core_handle_request(&ohci->card, &p);
  614. } else {
  615. fw_core_handle_response(&ohci->card, &p);
  616. }
  617. return buffer + length + 1;
  618. }
  619. static void ar_context_tasklet(unsigned long data)
  620. {
  621. struct ar_context *ctx = (struct ar_context *)data;
  622. struct fw_ohci *ohci = ctx->ohci;
  623. struct ar_buffer *ab;
  624. struct descriptor *d;
  625. void *buffer, *end;
  626. ab = ctx->current_buffer;
  627. d = &ab->descriptor;
  628. if (d->res_count == 0) {
  629. size_t size, rest, offset;
  630. dma_addr_t start_bus;
  631. void *start;
  632. /*
  633. * This descriptor is finished and we may have a
  634. * packet split across this and the next buffer. We
  635. * reuse the page for reassembling the split packet.
  636. */
  637. offset = offsetof(struct ar_buffer, data);
  638. start = buffer = ab;
  639. start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
  640. ab = ab->next;
  641. d = &ab->descriptor;
  642. size = buffer + PAGE_SIZE - ctx->pointer;
  643. rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
  644. memmove(buffer, ctx->pointer, size);
  645. memcpy(buffer + size, ab->data, rest);
  646. ctx->current_buffer = ab;
  647. ctx->pointer = (void *) ab->data + rest;
  648. end = buffer + size + rest;
  649. while (buffer < end)
  650. buffer = handle_ar_packet(ctx, buffer);
  651. dma_free_coherent(ohci->card.device, PAGE_SIZE,
  652. start, start_bus);
  653. ar_context_add_page(ctx);
  654. } else {
  655. buffer = ctx->pointer;
  656. ctx->pointer = end =
  657. (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
  658. while (buffer < end)
  659. buffer = handle_ar_packet(ctx, buffer);
  660. }
  661. }
  662. static int ar_context_init(struct ar_context *ctx,
  663. struct fw_ohci *ohci, u32 regs)
  664. {
  665. struct ar_buffer ab;
  666. ctx->regs = regs;
  667. ctx->ohci = ohci;
  668. ctx->last_buffer = &ab;
  669. tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
  670. ar_context_add_page(ctx);
  671. ar_context_add_page(ctx);
  672. ctx->current_buffer = ab.next;
  673. ctx->pointer = ctx->current_buffer->data;
  674. return 0;
  675. }
  676. static void ar_context_run(struct ar_context *ctx)
  677. {
  678. struct ar_buffer *ab = ctx->current_buffer;
  679. dma_addr_t ab_bus;
  680. size_t offset;
  681. offset = offsetof(struct ar_buffer, data);
  682. ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
  683. reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
  684. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
  685. flush_writes(ctx->ohci);
  686. }
  687. static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
  688. {
  689. int b, key;
  690. b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
  691. key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
  692. /* figure out which descriptor the branch address goes in */
  693. if (z == 2 && (b == 3 || key == 2))
  694. return d;
  695. else
  696. return d + z - 1;
  697. }
  698. static void context_tasklet(unsigned long data)
  699. {
  700. struct context *ctx = (struct context *) data;
  701. struct descriptor *d, *last;
  702. u32 address;
  703. int z;
  704. struct descriptor_buffer *desc;
  705. desc = list_entry(ctx->buffer_list.next,
  706. struct descriptor_buffer, list);
  707. last = ctx->last;
  708. while (last->branch_address != 0) {
  709. struct descriptor_buffer *old_desc = desc;
  710. address = le32_to_cpu(last->branch_address);
  711. z = address & 0xf;
  712. address &= ~0xf;
  713. /* If the branch address points to a buffer outside of the
  714. * current buffer, advance to the next buffer. */
  715. if (address < desc->buffer_bus ||
  716. address >= desc->buffer_bus + desc->used)
  717. desc = list_entry(desc->list.next,
  718. struct descriptor_buffer, list);
  719. d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
  720. last = find_branch_descriptor(d, z);
  721. if (!ctx->callback(ctx, d, last))
  722. break;
  723. if (old_desc != desc) {
  724. /* If we've advanced to the next buffer, move the
  725. * previous buffer to the free list. */
  726. unsigned long flags;
  727. old_desc->used = 0;
  728. spin_lock_irqsave(&ctx->ohci->lock, flags);
  729. list_move_tail(&old_desc->list, &ctx->buffer_list);
  730. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  731. }
  732. ctx->last = last;
  733. }
  734. }
  735. /*
  736. * Allocate a new buffer and add it to the list of free buffers for this
  737. * context. Must be called with ohci->lock held.
  738. */
  739. static int context_add_buffer(struct context *ctx)
  740. {
  741. struct descriptor_buffer *desc;
  742. dma_addr_t uninitialized_var(bus_addr);
  743. int offset;
  744. /*
  745. * 16MB of descriptors should be far more than enough for any DMA
  746. * program. This will catch run-away userspace or DoS attacks.
  747. */
  748. if (ctx->total_allocation >= 16*1024*1024)
  749. return -ENOMEM;
  750. desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
  751. &bus_addr, GFP_ATOMIC);
  752. if (!desc)
  753. return -ENOMEM;
  754. offset = (void *)&desc->buffer - (void *)desc;
  755. desc->buffer_size = PAGE_SIZE - offset;
  756. desc->buffer_bus = bus_addr + offset;
  757. desc->used = 0;
  758. list_add_tail(&desc->list, &ctx->buffer_list);
  759. ctx->total_allocation += PAGE_SIZE;
  760. return 0;
  761. }
  762. static int context_init(struct context *ctx, struct fw_ohci *ohci,
  763. u32 regs, descriptor_callback_t callback)
  764. {
  765. ctx->ohci = ohci;
  766. ctx->regs = regs;
  767. ctx->total_allocation = 0;
  768. INIT_LIST_HEAD(&ctx->buffer_list);
  769. if (context_add_buffer(ctx) < 0)
  770. return -ENOMEM;
  771. ctx->buffer_tail = list_entry(ctx->buffer_list.next,
  772. struct descriptor_buffer, list);
  773. tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
  774. ctx->callback = callback;
  775. /*
  776. * We put a dummy descriptor in the buffer that has a NULL
  777. * branch address and looks like it's been sent. That way we
  778. * have a descriptor to append DMA programs to.
  779. */
  780. memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
  781. ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
  782. ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
  783. ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
  784. ctx->last = ctx->buffer_tail->buffer;
  785. ctx->prev = ctx->buffer_tail->buffer;
  786. return 0;
  787. }
  788. static void context_release(struct context *ctx)
  789. {
  790. struct fw_card *card = &ctx->ohci->card;
  791. struct descriptor_buffer *desc, *tmp;
  792. list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
  793. dma_free_coherent(card->device, PAGE_SIZE, desc,
  794. desc->buffer_bus -
  795. ((void *)&desc->buffer - (void *)desc));
  796. }
  797. /* Must be called with ohci->lock held */
  798. static struct descriptor *context_get_descriptors(struct context *ctx,
  799. int z, dma_addr_t *d_bus)
  800. {
  801. struct descriptor *d = NULL;
  802. struct descriptor_buffer *desc = ctx->buffer_tail;
  803. if (z * sizeof(*d) > desc->buffer_size)
  804. return NULL;
  805. if (z * sizeof(*d) > desc->buffer_size - desc->used) {
  806. /* No room for the descriptor in this buffer, so advance to the
  807. * next one. */
  808. if (desc->list.next == &ctx->buffer_list) {
  809. /* If there is no free buffer next in the list,
  810. * allocate one. */
  811. if (context_add_buffer(ctx) < 0)
  812. return NULL;
  813. }
  814. desc = list_entry(desc->list.next,
  815. struct descriptor_buffer, list);
  816. ctx->buffer_tail = desc;
  817. }
  818. d = desc->buffer + desc->used / sizeof(*d);
  819. memset(d, 0, z * sizeof(*d));
  820. *d_bus = desc->buffer_bus + desc->used;
  821. return d;
  822. }
  823. static void context_run(struct context *ctx, u32 extra)
  824. {
  825. struct fw_ohci *ohci = ctx->ohci;
  826. reg_write(ohci, COMMAND_PTR(ctx->regs),
  827. le32_to_cpu(ctx->last->branch_address));
  828. reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
  829. reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
  830. flush_writes(ohci);
  831. }
  832. static void context_append(struct context *ctx,
  833. struct descriptor *d, int z, int extra)
  834. {
  835. dma_addr_t d_bus;
  836. struct descriptor_buffer *desc = ctx->buffer_tail;
  837. d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
  838. desc->used += (z + extra) * sizeof(*d);
  839. wmb(); /* finish init of new descriptors before branch_address update */
  840. ctx->prev->branch_address = cpu_to_le32(d_bus | z);
  841. ctx->prev = find_branch_descriptor(d, z);
  842. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  843. flush_writes(ctx->ohci);
  844. }
  845. static void context_stop(struct context *ctx)
  846. {
  847. u32 reg;
  848. int i;
  849. reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
  850. flush_writes(ctx->ohci);
  851. for (i = 0; i < 10; i++) {
  852. reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
  853. if ((reg & CONTEXT_ACTIVE) == 0)
  854. return;
  855. mdelay(1);
  856. }
  857. fw_error("Error: DMA context still active (0x%08x)\n", reg);
  858. }
  859. struct driver_data {
  860. struct fw_packet *packet;
  861. };
  862. /*
  863. * This function apppends a packet to the DMA queue for transmission.
  864. * Must always be called with the ochi->lock held to ensure proper
  865. * generation handling and locking around packet queue manipulation.
  866. */
  867. static int at_context_queue_packet(struct context *ctx,
  868. struct fw_packet *packet)
  869. {
  870. struct fw_ohci *ohci = ctx->ohci;
  871. dma_addr_t d_bus, uninitialized_var(payload_bus);
  872. struct driver_data *driver_data;
  873. struct descriptor *d, *last;
  874. __le32 *header;
  875. int z, tcode;
  876. u32 reg;
  877. d = context_get_descriptors(ctx, 4, &d_bus);
  878. if (d == NULL) {
  879. packet->ack = RCODE_SEND_ERROR;
  880. return -1;
  881. }
  882. d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
  883. d[0].res_count = cpu_to_le16(packet->timestamp);
  884. /*
  885. * The DMA format for asyncronous link packets is different
  886. * from the IEEE1394 layout, so shift the fields around
  887. * accordingly. If header_length is 8, it's a PHY packet, to
  888. * which we need to prepend an extra quadlet.
  889. */
  890. header = (__le32 *) &d[1];
  891. switch (packet->header_length) {
  892. case 16:
  893. case 12:
  894. header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
  895. (packet->speed << 16));
  896. header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
  897. (packet->header[0] & 0xffff0000));
  898. header[2] = cpu_to_le32(packet->header[2]);
  899. tcode = (packet->header[0] >> 4) & 0x0f;
  900. if (TCODE_IS_BLOCK_PACKET(tcode))
  901. header[3] = cpu_to_le32(packet->header[3]);
  902. else
  903. header[3] = (__force __le32) packet->header[3];
  904. d[0].req_count = cpu_to_le16(packet->header_length);
  905. break;
  906. case 8:
  907. header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
  908. (packet->speed << 16));
  909. header[1] = cpu_to_le32(packet->header[0]);
  910. header[2] = cpu_to_le32(packet->header[1]);
  911. d[0].req_count = cpu_to_le16(12);
  912. if (is_ping_packet(packet->header))
  913. d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
  914. break;
  915. case 4:
  916. header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
  917. (packet->speed << 16));
  918. header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
  919. d[0].req_count = cpu_to_le16(8);
  920. break;
  921. default:
  922. /* BUG(); */
  923. packet->ack = RCODE_SEND_ERROR;
  924. return -1;
  925. }
  926. driver_data = (struct driver_data *) &d[3];
  927. driver_data->packet = packet;
  928. packet->driver_data = driver_data;
  929. if (packet->payload_length > 0) {
  930. payload_bus =
  931. dma_map_single(ohci->card.device, packet->payload,
  932. packet->payload_length, DMA_TO_DEVICE);
  933. if (dma_mapping_error(ohci->card.device, payload_bus)) {
  934. packet->ack = RCODE_SEND_ERROR;
  935. return -1;
  936. }
  937. packet->payload_bus = payload_bus;
  938. packet->payload_mapped = true;
  939. d[2].req_count = cpu_to_le16(packet->payload_length);
  940. d[2].data_address = cpu_to_le32(payload_bus);
  941. last = &d[2];
  942. z = 3;
  943. } else {
  944. last = &d[0];
  945. z = 2;
  946. }
  947. last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
  948. DESCRIPTOR_IRQ_ALWAYS |
  949. DESCRIPTOR_BRANCH_ALWAYS);
  950. /*
  951. * If the controller and packet generations don't match, we need to
  952. * bail out and try again. If IntEvent.busReset is set, the AT context
  953. * is halted, so appending to the context and trying to run it is
  954. * futile. Most controllers do the right thing and just flush the AT
  955. * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
  956. * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
  957. * up stalling out. So we just bail out in software and try again
  958. * later, and everyone is happy.
  959. * FIXME: Document how the locking works.
  960. */
  961. if (ohci->generation != packet->generation ||
  962. reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
  963. if (packet->payload_mapped)
  964. dma_unmap_single(ohci->card.device, payload_bus,
  965. packet->payload_length, DMA_TO_DEVICE);
  966. packet->ack = RCODE_GENERATION;
  967. return -1;
  968. }
  969. context_append(ctx, d, z, 4 - z);
  970. /* If the context isn't already running, start it up. */
  971. reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
  972. if ((reg & CONTEXT_RUN) == 0)
  973. context_run(ctx, 0);
  974. return 0;
  975. }
  976. static int handle_at_packet(struct context *context,
  977. struct descriptor *d,
  978. struct descriptor *last)
  979. {
  980. struct driver_data *driver_data;
  981. struct fw_packet *packet;
  982. struct fw_ohci *ohci = context->ohci;
  983. int evt;
  984. if (last->transfer_status == 0)
  985. /* This descriptor isn't done yet, stop iteration. */
  986. return 0;
  987. driver_data = (struct driver_data *) &d[3];
  988. packet = driver_data->packet;
  989. if (packet == NULL)
  990. /* This packet was cancelled, just continue. */
  991. return 1;
  992. if (packet->payload_mapped)
  993. dma_unmap_single(ohci->card.device, packet->payload_bus,
  994. packet->payload_length, DMA_TO_DEVICE);
  995. evt = le16_to_cpu(last->transfer_status) & 0x1f;
  996. packet->timestamp = le16_to_cpu(last->res_count);
  997. log_ar_at_event('T', packet->speed, packet->header, evt);
  998. switch (evt) {
  999. case OHCI1394_evt_timeout:
  1000. /* Async response transmit timed out. */
  1001. packet->ack = RCODE_CANCELLED;
  1002. break;
  1003. case OHCI1394_evt_flushed:
  1004. /*
  1005. * The packet was flushed should give same error as
  1006. * when we try to use a stale generation count.
  1007. */
  1008. packet->ack = RCODE_GENERATION;
  1009. break;
  1010. case OHCI1394_evt_missing_ack:
  1011. /*
  1012. * Using a valid (current) generation count, but the
  1013. * node is not on the bus or not sending acks.
  1014. */
  1015. packet->ack = RCODE_NO_ACK;
  1016. break;
  1017. case ACK_COMPLETE + 0x10:
  1018. case ACK_PENDING + 0x10:
  1019. case ACK_BUSY_X + 0x10:
  1020. case ACK_BUSY_A + 0x10:
  1021. case ACK_BUSY_B + 0x10:
  1022. case ACK_DATA_ERROR + 0x10:
  1023. case ACK_TYPE_ERROR + 0x10:
  1024. packet->ack = evt - 0x10;
  1025. break;
  1026. default:
  1027. packet->ack = RCODE_SEND_ERROR;
  1028. break;
  1029. }
  1030. packet->callback(packet, &ohci->card, packet->ack);
  1031. return 1;
  1032. }
  1033. #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
  1034. #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
  1035. #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
  1036. #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
  1037. #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
  1038. static void handle_local_rom(struct fw_ohci *ohci,
  1039. struct fw_packet *packet, u32 csr)
  1040. {
  1041. struct fw_packet response;
  1042. int tcode, length, i;
  1043. tcode = HEADER_GET_TCODE(packet->header[0]);
  1044. if (TCODE_IS_BLOCK_PACKET(tcode))
  1045. length = HEADER_GET_DATA_LENGTH(packet->header[3]);
  1046. else
  1047. length = 4;
  1048. i = csr - CSR_CONFIG_ROM;
  1049. if (i + length > CONFIG_ROM_SIZE) {
  1050. fw_fill_response(&response, packet->header,
  1051. RCODE_ADDRESS_ERROR, NULL, 0);
  1052. } else if (!TCODE_IS_READ_REQUEST(tcode)) {
  1053. fw_fill_response(&response, packet->header,
  1054. RCODE_TYPE_ERROR, NULL, 0);
  1055. } else {
  1056. fw_fill_response(&response, packet->header, RCODE_COMPLETE,
  1057. (void *) ohci->config_rom + i, length);
  1058. }
  1059. fw_core_handle_response(&ohci->card, &response);
  1060. }
  1061. static void handle_local_lock(struct fw_ohci *ohci,
  1062. struct fw_packet *packet, u32 csr)
  1063. {
  1064. struct fw_packet response;
  1065. int tcode, length, ext_tcode, sel, try;
  1066. __be32 *payload, lock_old;
  1067. u32 lock_arg, lock_data;
  1068. tcode = HEADER_GET_TCODE(packet->header[0]);
  1069. length = HEADER_GET_DATA_LENGTH(packet->header[3]);
  1070. payload = packet->payload;
  1071. ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
  1072. if (tcode == TCODE_LOCK_REQUEST &&
  1073. ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
  1074. lock_arg = be32_to_cpu(payload[0]);
  1075. lock_data = be32_to_cpu(payload[1]);
  1076. } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
  1077. lock_arg = 0;
  1078. lock_data = 0;
  1079. } else {
  1080. fw_fill_response(&response, packet->header,
  1081. RCODE_TYPE_ERROR, NULL, 0);
  1082. goto out;
  1083. }
  1084. sel = (csr - CSR_BUS_MANAGER_ID) / 4;
  1085. reg_write(ohci, OHCI1394_CSRData, lock_data);
  1086. reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
  1087. reg_write(ohci, OHCI1394_CSRControl, sel);
  1088. for (try = 0; try < 20; try++)
  1089. if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
  1090. lock_old = cpu_to_be32(reg_read(ohci,
  1091. OHCI1394_CSRData));
  1092. fw_fill_response(&response, packet->header,
  1093. RCODE_COMPLETE,
  1094. &lock_old, sizeof(lock_old));
  1095. goto out;
  1096. }
  1097. fw_error("swap not done (CSR lock timeout)\n");
  1098. fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
  1099. out:
  1100. fw_core_handle_response(&ohci->card, &response);
  1101. }
  1102. static void handle_local_request(struct context *ctx, struct fw_packet *packet)
  1103. {
  1104. u64 offset, csr;
  1105. if (ctx == &ctx->ohci->at_request_ctx) {
  1106. packet->ack = ACK_PENDING;
  1107. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1108. }
  1109. offset =
  1110. ((unsigned long long)
  1111. HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
  1112. packet->header[2];
  1113. csr = offset - CSR_REGISTER_BASE;
  1114. /* Handle config rom reads. */
  1115. if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
  1116. handle_local_rom(ctx->ohci, packet, csr);
  1117. else switch (csr) {
  1118. case CSR_BUS_MANAGER_ID:
  1119. case CSR_BANDWIDTH_AVAILABLE:
  1120. case CSR_CHANNELS_AVAILABLE_HI:
  1121. case CSR_CHANNELS_AVAILABLE_LO:
  1122. handle_local_lock(ctx->ohci, packet, csr);
  1123. break;
  1124. default:
  1125. if (ctx == &ctx->ohci->at_request_ctx)
  1126. fw_core_handle_request(&ctx->ohci->card, packet);
  1127. else
  1128. fw_core_handle_response(&ctx->ohci->card, packet);
  1129. break;
  1130. }
  1131. if (ctx == &ctx->ohci->at_response_ctx) {
  1132. packet->ack = ACK_COMPLETE;
  1133. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1134. }
  1135. }
  1136. static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
  1137. {
  1138. unsigned long flags;
  1139. int ret;
  1140. spin_lock_irqsave(&ctx->ohci->lock, flags);
  1141. if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
  1142. ctx->ohci->generation == packet->generation) {
  1143. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  1144. handle_local_request(ctx, packet);
  1145. return;
  1146. }
  1147. ret = at_context_queue_packet(ctx, packet);
  1148. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  1149. if (ret < 0)
  1150. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1151. }
  1152. static u32 cycle_timer_ticks(u32 cycle_timer)
  1153. {
  1154. u32 ticks;
  1155. ticks = cycle_timer & 0xfff;
  1156. ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
  1157. ticks += (3072 * 8000) * (cycle_timer >> 25);
  1158. return ticks;
  1159. }
  1160. /*
  1161. * Some controllers exhibit one or more of the following bugs when updating the
  1162. * iso cycle timer register:
  1163. * - When the lowest six bits are wrapping around to zero, a read that happens
  1164. * at the same time will return garbage in the lowest ten bits.
  1165. * - When the cycleOffset field wraps around to zero, the cycleCount field is
  1166. * not incremented for about 60 ns.
  1167. * - Occasionally, the entire register reads zero.
  1168. *
  1169. * To catch these, we read the register three times and ensure that the
  1170. * difference between each two consecutive reads is approximately the same, i.e.
  1171. * less than twice the other. Furthermore, any negative difference indicates an
  1172. * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
  1173. * execute, so we have enough precision to compute the ratio of the differences.)
  1174. */
  1175. static u32 get_cycle_time(struct fw_ohci *ohci)
  1176. {
  1177. u32 c0, c1, c2;
  1178. u32 t0, t1, t2;
  1179. s32 diff01, diff12;
  1180. int i;
  1181. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1182. if (ohci->quirks & QUIRK_CYCLE_TIMER) {
  1183. i = 0;
  1184. c1 = c2;
  1185. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1186. do {
  1187. c0 = c1;
  1188. c1 = c2;
  1189. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1190. t0 = cycle_timer_ticks(c0);
  1191. t1 = cycle_timer_ticks(c1);
  1192. t2 = cycle_timer_ticks(c2);
  1193. diff01 = t1 - t0;
  1194. diff12 = t2 - t1;
  1195. } while ((diff01 <= 0 || diff12 <= 0 ||
  1196. diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
  1197. && i++ < 20);
  1198. }
  1199. return c2;
  1200. }
  1201. /*
  1202. * This function has to be called at least every 64 seconds. The bus_time
  1203. * field stores not only the upper 25 bits of the BUS_TIME register but also
  1204. * the most significant bit of the cycle timer in bit 6 so that we can detect
  1205. * changes in this bit.
  1206. */
  1207. static u32 update_bus_time(struct fw_ohci *ohci)
  1208. {
  1209. u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
  1210. if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
  1211. ohci->bus_time += 0x40;
  1212. return ohci->bus_time | cycle_time_seconds;
  1213. }
  1214. static void bus_reset_tasklet(unsigned long data)
  1215. {
  1216. struct fw_ohci *ohci = (struct fw_ohci *)data;
  1217. int self_id_count, i, j, reg;
  1218. int generation, new_generation;
  1219. unsigned long flags;
  1220. void *free_rom = NULL;
  1221. dma_addr_t free_rom_bus = 0;
  1222. bool is_new_root;
  1223. reg = reg_read(ohci, OHCI1394_NodeID);
  1224. if (!(reg & OHCI1394_NodeID_idValid)) {
  1225. fw_notify("node ID not valid, new bus reset in progress\n");
  1226. return;
  1227. }
  1228. if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
  1229. fw_notify("malconfigured bus\n");
  1230. return;
  1231. }
  1232. ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
  1233. OHCI1394_NodeID_nodeNumber);
  1234. is_new_root = (reg & OHCI1394_NodeID_root) != 0;
  1235. if (!(ohci->is_root && is_new_root))
  1236. reg_write(ohci, OHCI1394_LinkControlSet,
  1237. OHCI1394_LinkControl_cycleMaster);
  1238. ohci->is_root = is_new_root;
  1239. reg = reg_read(ohci, OHCI1394_SelfIDCount);
  1240. if (reg & OHCI1394_SelfIDCount_selfIDError) {
  1241. fw_notify("inconsistent self IDs\n");
  1242. return;
  1243. }
  1244. /*
  1245. * The count in the SelfIDCount register is the number of
  1246. * bytes in the self ID receive buffer. Since we also receive
  1247. * the inverted quadlets and a header quadlet, we shift one
  1248. * bit extra to get the actual number of self IDs.
  1249. */
  1250. self_id_count = (reg >> 3) & 0xff;
  1251. if (self_id_count == 0 || self_id_count > 252) {
  1252. fw_notify("inconsistent self IDs\n");
  1253. return;
  1254. }
  1255. generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
  1256. rmb();
  1257. for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
  1258. if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
  1259. fw_notify("inconsistent self IDs\n");
  1260. return;
  1261. }
  1262. ohci->self_id_buffer[j] =
  1263. cond_le32_to_cpu(ohci->self_id_cpu[i]);
  1264. }
  1265. rmb();
  1266. /*
  1267. * Check the consistency of the self IDs we just read. The
  1268. * problem we face is that a new bus reset can start while we
  1269. * read out the self IDs from the DMA buffer. If this happens,
  1270. * the DMA buffer will be overwritten with new self IDs and we
  1271. * will read out inconsistent data. The OHCI specification
  1272. * (section 11.2) recommends a technique similar to
  1273. * linux/seqlock.h, where we remember the generation of the
  1274. * self IDs in the buffer before reading them out and compare
  1275. * it to the current generation after reading them out. If
  1276. * the two generations match we know we have a consistent set
  1277. * of self IDs.
  1278. */
  1279. new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
  1280. if (new_generation != generation) {
  1281. fw_notify("recursive bus reset detected, "
  1282. "discarding self ids\n");
  1283. return;
  1284. }
  1285. /* FIXME: Document how the locking works. */
  1286. spin_lock_irqsave(&ohci->lock, flags);
  1287. ohci->generation = generation;
  1288. context_stop(&ohci->at_request_ctx);
  1289. context_stop(&ohci->at_response_ctx);
  1290. reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
  1291. if (ohci->quirks & QUIRK_RESET_PACKET)
  1292. ohci->request_generation = generation;
  1293. /*
  1294. * This next bit is unrelated to the AT context stuff but we
  1295. * have to do it under the spinlock also. If a new config rom
  1296. * was set up before this reset, the old one is now no longer
  1297. * in use and we can free it. Update the config rom pointers
  1298. * to point to the current config rom and clear the
  1299. * next_config_rom pointer so a new update can take place.
  1300. */
  1301. if (ohci->next_config_rom != NULL) {
  1302. if (ohci->next_config_rom != ohci->config_rom) {
  1303. free_rom = ohci->config_rom;
  1304. free_rom_bus = ohci->config_rom_bus;
  1305. }
  1306. ohci->config_rom = ohci->next_config_rom;
  1307. ohci->config_rom_bus = ohci->next_config_rom_bus;
  1308. ohci->next_config_rom = NULL;
  1309. /*
  1310. * Restore config_rom image and manually update
  1311. * config_rom registers. Writing the header quadlet
  1312. * will indicate that the config rom is ready, so we
  1313. * do that last.
  1314. */
  1315. reg_write(ohci, OHCI1394_BusOptions,
  1316. be32_to_cpu(ohci->config_rom[2]));
  1317. ohci->config_rom[0] = ohci->next_header;
  1318. reg_write(ohci, OHCI1394_ConfigROMhdr,
  1319. be32_to_cpu(ohci->next_header));
  1320. }
  1321. #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
  1322. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
  1323. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
  1324. #endif
  1325. spin_unlock_irqrestore(&ohci->lock, flags);
  1326. if (free_rom)
  1327. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1328. free_rom, free_rom_bus);
  1329. log_selfids(ohci->node_id, generation,
  1330. self_id_count, ohci->self_id_buffer);
  1331. fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
  1332. self_id_count, ohci->self_id_buffer,
  1333. ohci->csr_state_setclear_abdicate);
  1334. ohci->csr_state_setclear_abdicate = false;
  1335. }
  1336. static irqreturn_t irq_handler(int irq, void *data)
  1337. {
  1338. struct fw_ohci *ohci = data;
  1339. u32 event, iso_event;
  1340. int i;
  1341. event = reg_read(ohci, OHCI1394_IntEventClear);
  1342. if (!event || !~event)
  1343. return IRQ_NONE;
  1344. /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
  1345. reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
  1346. log_irqs(event);
  1347. if (event & OHCI1394_selfIDComplete)
  1348. tasklet_schedule(&ohci->bus_reset_tasklet);
  1349. if (event & OHCI1394_RQPkt)
  1350. tasklet_schedule(&ohci->ar_request_ctx.tasklet);
  1351. if (event & OHCI1394_RSPkt)
  1352. tasklet_schedule(&ohci->ar_response_ctx.tasklet);
  1353. if (event & OHCI1394_reqTxComplete)
  1354. tasklet_schedule(&ohci->at_request_ctx.tasklet);
  1355. if (event & OHCI1394_respTxComplete)
  1356. tasklet_schedule(&ohci->at_response_ctx.tasklet);
  1357. iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
  1358. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
  1359. while (iso_event) {
  1360. i = ffs(iso_event) - 1;
  1361. tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
  1362. iso_event &= ~(1 << i);
  1363. }
  1364. iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
  1365. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
  1366. while (iso_event) {
  1367. i = ffs(iso_event) - 1;
  1368. tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
  1369. iso_event &= ~(1 << i);
  1370. }
  1371. if (unlikely(event & OHCI1394_regAccessFail))
  1372. fw_error("Register access failure - "
  1373. "please notify linux1394-devel@lists.sf.net\n");
  1374. if (unlikely(event & OHCI1394_postedWriteErr))
  1375. fw_error("PCI posted write error\n");
  1376. if (unlikely(event & OHCI1394_cycleTooLong)) {
  1377. if (printk_ratelimit())
  1378. fw_notify("isochronous cycle too long\n");
  1379. reg_write(ohci, OHCI1394_LinkControlSet,
  1380. OHCI1394_LinkControl_cycleMaster);
  1381. }
  1382. if (unlikely(event & OHCI1394_cycleInconsistent)) {
  1383. /*
  1384. * We need to clear this event bit in order to make
  1385. * cycleMatch isochronous I/O work. In theory we should
  1386. * stop active cycleMatch iso contexts now and restart
  1387. * them at least two cycles later. (FIXME?)
  1388. */
  1389. if (printk_ratelimit())
  1390. fw_notify("isochronous cycle inconsistent\n");
  1391. }
  1392. if (event & OHCI1394_cycle64Seconds) {
  1393. spin_lock(&ohci->lock);
  1394. update_bus_time(ohci);
  1395. spin_unlock(&ohci->lock);
  1396. }
  1397. return IRQ_HANDLED;
  1398. }
  1399. static int software_reset(struct fw_ohci *ohci)
  1400. {
  1401. int i;
  1402. reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
  1403. for (i = 0; i < OHCI_LOOP_COUNT; i++) {
  1404. if ((reg_read(ohci, OHCI1394_HCControlSet) &
  1405. OHCI1394_HCControl_softReset) == 0)
  1406. return 0;
  1407. msleep(1);
  1408. }
  1409. return -EBUSY;
  1410. }
  1411. static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
  1412. {
  1413. size_t size = length * 4;
  1414. memcpy(dest, src, size);
  1415. if (size < CONFIG_ROM_SIZE)
  1416. memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
  1417. }
  1418. static int configure_1394a_enhancements(struct fw_ohci *ohci)
  1419. {
  1420. bool enable_1394a;
  1421. int ret, clear, set, offset;
  1422. /* Check if the driver should configure link and PHY. */
  1423. if (!(reg_read(ohci, OHCI1394_HCControlSet) &
  1424. OHCI1394_HCControl_programPhyEnable))
  1425. return 0;
  1426. /* Paranoia: check whether the PHY supports 1394a, too. */
  1427. enable_1394a = false;
  1428. ret = read_phy_reg(ohci, 2);
  1429. if (ret < 0)
  1430. return ret;
  1431. if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
  1432. ret = read_paged_phy_reg(ohci, 1, 8);
  1433. if (ret < 0)
  1434. return ret;
  1435. if (ret >= 1)
  1436. enable_1394a = true;
  1437. }
  1438. if (ohci->quirks & QUIRK_NO_1394A)
  1439. enable_1394a = false;
  1440. /* Configure PHY and link consistently. */
  1441. if (enable_1394a) {
  1442. clear = 0;
  1443. set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
  1444. } else {
  1445. clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
  1446. set = 0;
  1447. }
  1448. ret = update_phy_reg(ohci, 5, clear, set);
  1449. if (ret < 0)
  1450. return ret;
  1451. if (enable_1394a)
  1452. offset = OHCI1394_HCControlSet;
  1453. else
  1454. offset = OHCI1394_HCControlClear;
  1455. reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
  1456. /* Clean up: configuration has been taken care of. */
  1457. reg_write(ohci, OHCI1394_HCControlClear,
  1458. OHCI1394_HCControl_programPhyEnable);
  1459. return 0;
  1460. }
  1461. static int ohci_enable(struct fw_card *card,
  1462. const __be32 *config_rom, size_t length)
  1463. {
  1464. struct fw_ohci *ohci = fw_ohci(card);
  1465. struct pci_dev *dev = to_pci_dev(card->device);
  1466. u32 lps, seconds, version, irqs;
  1467. int i, ret;
  1468. if (software_reset(ohci)) {
  1469. fw_error("Failed to reset ohci card.\n");
  1470. return -EBUSY;
  1471. }
  1472. /*
  1473. * Now enable LPS, which we need in order to start accessing
  1474. * most of the registers. In fact, on some cards (ALI M5251),
  1475. * accessing registers in the SClk domain without LPS enabled
  1476. * will lock up the machine. Wait 50msec to make sure we have
  1477. * full link enabled. However, with some cards (well, at least
  1478. * a JMicron PCIe card), we have to try again sometimes.
  1479. */
  1480. reg_write(ohci, OHCI1394_HCControlSet,
  1481. OHCI1394_HCControl_LPS |
  1482. OHCI1394_HCControl_postedWriteEnable);
  1483. flush_writes(ohci);
  1484. for (lps = 0, i = 0; !lps && i < 3; i++) {
  1485. msleep(50);
  1486. lps = reg_read(ohci, OHCI1394_HCControlSet) &
  1487. OHCI1394_HCControl_LPS;
  1488. }
  1489. if (!lps) {
  1490. fw_error("Failed to set Link Power Status\n");
  1491. return -EIO;
  1492. }
  1493. reg_write(ohci, OHCI1394_HCControlClear,
  1494. OHCI1394_HCControl_noByteSwapData);
  1495. reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
  1496. reg_write(ohci, OHCI1394_LinkControlSet,
  1497. OHCI1394_LinkControl_rcvSelfID |
  1498. OHCI1394_LinkControl_rcvPhyPkt |
  1499. OHCI1394_LinkControl_cycleTimerEnable |
  1500. OHCI1394_LinkControl_cycleMaster);
  1501. reg_write(ohci, OHCI1394_ATRetries,
  1502. OHCI1394_MAX_AT_REQ_RETRIES |
  1503. (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
  1504. (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
  1505. (200 << 16));
  1506. seconds = lower_32_bits(get_seconds());
  1507. reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
  1508. ohci->bus_time = seconds & ~0x3f;
  1509. version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
  1510. if (version >= OHCI_VERSION_1_1) {
  1511. reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
  1512. 0xfffffffe);
  1513. card->broadcast_channel_auto_allocated = true;
  1514. }
  1515. /* Get implemented bits of the priority arbitration request counter. */
  1516. reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
  1517. ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
  1518. reg_write(ohci, OHCI1394_FairnessControl, 0);
  1519. card->priority_budget_implemented = ohci->pri_req_max != 0;
  1520. ar_context_run(&ohci->ar_request_ctx);
  1521. ar_context_run(&ohci->ar_response_ctx);
  1522. reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
  1523. reg_write(ohci, OHCI1394_IntEventClear, ~0);
  1524. reg_write(ohci, OHCI1394_IntMaskClear, ~0);
  1525. ret = configure_1394a_enhancements(ohci);
  1526. if (ret < 0)
  1527. return ret;
  1528. /* Activate link_on bit and contender bit in our self ID packets.*/
  1529. ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
  1530. if (ret < 0)
  1531. return ret;
  1532. /*
  1533. * When the link is not yet enabled, the atomic config rom
  1534. * update mechanism described below in ohci_set_config_rom()
  1535. * is not active. We have to update ConfigRomHeader and
  1536. * BusOptions manually, and the write to ConfigROMmap takes
  1537. * effect immediately. We tie this to the enabling of the
  1538. * link, so we have a valid config rom before enabling - the
  1539. * OHCI requires that ConfigROMhdr and BusOptions have valid
  1540. * values before enabling.
  1541. *
  1542. * However, when the ConfigROMmap is written, some controllers
  1543. * always read back quadlets 0 and 2 from the config rom to
  1544. * the ConfigRomHeader and BusOptions registers on bus reset.
  1545. * They shouldn't do that in this initial case where the link
  1546. * isn't enabled. This means we have to use the same
  1547. * workaround here, setting the bus header to 0 and then write
  1548. * the right values in the bus reset tasklet.
  1549. */
  1550. if (config_rom) {
  1551. ohci->next_config_rom =
  1552. dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1553. &ohci->next_config_rom_bus,
  1554. GFP_KERNEL);
  1555. if (ohci->next_config_rom == NULL)
  1556. return -ENOMEM;
  1557. copy_config_rom(ohci->next_config_rom, config_rom, length);
  1558. } else {
  1559. /*
  1560. * In the suspend case, config_rom is NULL, which
  1561. * means that we just reuse the old config rom.
  1562. */
  1563. ohci->next_config_rom = ohci->config_rom;
  1564. ohci->next_config_rom_bus = ohci->config_rom_bus;
  1565. }
  1566. ohci->next_header = ohci->next_config_rom[0];
  1567. ohci->next_config_rom[0] = 0;
  1568. reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
  1569. reg_write(ohci, OHCI1394_BusOptions,
  1570. be32_to_cpu(ohci->next_config_rom[2]));
  1571. reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
  1572. reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
  1573. if (!(ohci->quirks & QUIRK_NO_MSI))
  1574. pci_enable_msi(dev);
  1575. if (request_irq(dev->irq, irq_handler,
  1576. pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
  1577. ohci_driver_name, ohci)) {
  1578. fw_error("Failed to allocate interrupt %d.\n", dev->irq);
  1579. pci_disable_msi(dev);
  1580. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1581. ohci->config_rom, ohci->config_rom_bus);
  1582. return -EIO;
  1583. }
  1584. irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
  1585. OHCI1394_RQPkt | OHCI1394_RSPkt |
  1586. OHCI1394_isochTx | OHCI1394_isochRx |
  1587. OHCI1394_postedWriteErr |
  1588. OHCI1394_selfIDComplete |
  1589. OHCI1394_regAccessFail |
  1590. OHCI1394_cycle64Seconds |
  1591. OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
  1592. OHCI1394_masterIntEnable;
  1593. if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
  1594. irqs |= OHCI1394_busReset;
  1595. reg_write(ohci, OHCI1394_IntMaskSet, irqs);
  1596. reg_write(ohci, OHCI1394_HCControlSet,
  1597. OHCI1394_HCControl_linkEnable |
  1598. OHCI1394_HCControl_BIBimageValid);
  1599. flush_writes(ohci);
  1600. /* We are ready to go, reset bus to finish initialization. */
  1601. fw_schedule_bus_reset(&ohci->card, false, true);
  1602. return 0;
  1603. }
  1604. static int ohci_set_config_rom(struct fw_card *card,
  1605. const __be32 *config_rom, size_t length)
  1606. {
  1607. struct fw_ohci *ohci;
  1608. unsigned long flags;
  1609. int ret = -EBUSY;
  1610. __be32 *next_config_rom;
  1611. dma_addr_t uninitialized_var(next_config_rom_bus);
  1612. ohci = fw_ohci(card);
  1613. /*
  1614. * When the OHCI controller is enabled, the config rom update
  1615. * mechanism is a bit tricky, but easy enough to use. See
  1616. * section 5.5.6 in the OHCI specification.
  1617. *
  1618. * The OHCI controller caches the new config rom address in a
  1619. * shadow register (ConfigROMmapNext) and needs a bus reset
  1620. * for the changes to take place. When the bus reset is
  1621. * detected, the controller loads the new values for the
  1622. * ConfigRomHeader and BusOptions registers from the specified
  1623. * config rom and loads ConfigROMmap from the ConfigROMmapNext
  1624. * shadow register. All automatically and atomically.
  1625. *
  1626. * Now, there's a twist to this story. The automatic load of
  1627. * ConfigRomHeader and BusOptions doesn't honor the
  1628. * noByteSwapData bit, so with a be32 config rom, the
  1629. * controller will load be32 values in to these registers
  1630. * during the atomic update, even on litte endian
  1631. * architectures. The workaround we use is to put a 0 in the
  1632. * header quadlet; 0 is endian agnostic and means that the
  1633. * config rom isn't ready yet. In the bus reset tasklet we
  1634. * then set up the real values for the two registers.
  1635. *
  1636. * We use ohci->lock to avoid racing with the code that sets
  1637. * ohci->next_config_rom to NULL (see bus_reset_tasklet).
  1638. */
  1639. next_config_rom =
  1640. dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1641. &next_config_rom_bus, GFP_KERNEL);
  1642. if (next_config_rom == NULL)
  1643. return -ENOMEM;
  1644. spin_lock_irqsave(&ohci->lock, flags);
  1645. if (ohci->next_config_rom == NULL) {
  1646. ohci->next_config_rom = next_config_rom;
  1647. ohci->next_config_rom_bus = next_config_rom_bus;
  1648. copy_config_rom(ohci->next_config_rom, config_rom, length);
  1649. ohci->next_header = config_rom[0];
  1650. ohci->next_config_rom[0] = 0;
  1651. reg_write(ohci, OHCI1394_ConfigROMmap,
  1652. ohci->next_config_rom_bus);
  1653. ret = 0;
  1654. }
  1655. spin_unlock_irqrestore(&ohci->lock, flags);
  1656. /*
  1657. * Now initiate a bus reset to have the changes take
  1658. * effect. We clean up the old config rom memory and DMA
  1659. * mappings in the bus reset tasklet, since the OHCI
  1660. * controller could need to access it before the bus reset
  1661. * takes effect.
  1662. */
  1663. if (ret == 0)
  1664. fw_schedule_bus_reset(&ohci->card, true, true);
  1665. else
  1666. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1667. next_config_rom, next_config_rom_bus);
  1668. return ret;
  1669. }
  1670. static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
  1671. {
  1672. struct fw_ohci *ohci = fw_ohci(card);
  1673. at_context_transmit(&ohci->at_request_ctx, packet);
  1674. }
  1675. static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
  1676. {
  1677. struct fw_ohci *ohci = fw_ohci(card);
  1678. at_context_transmit(&ohci->at_response_ctx, packet);
  1679. }
  1680. static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
  1681. {
  1682. struct fw_ohci *ohci = fw_ohci(card);
  1683. struct context *ctx = &ohci->at_request_ctx;
  1684. struct driver_data *driver_data = packet->driver_data;
  1685. int ret = -ENOENT;
  1686. tasklet_disable(&ctx->tasklet);
  1687. if (packet->ack != 0)
  1688. goto out;
  1689. if (packet->payload_mapped)
  1690. dma_unmap_single(ohci->card.device, packet->payload_bus,
  1691. packet->payload_length, DMA_TO_DEVICE);
  1692. log_ar_at_event('T', packet->speed, packet->header, 0x20);
  1693. driver_data->packet = NULL;
  1694. packet->ack = RCODE_CANCELLED;
  1695. packet->callback(packet, &ohci->card, packet->ack);
  1696. ret = 0;
  1697. out:
  1698. tasklet_enable(&ctx->tasklet);
  1699. return ret;
  1700. }
  1701. static int ohci_enable_phys_dma(struct fw_card *card,
  1702. int node_id, int generation)
  1703. {
  1704. #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
  1705. return 0;
  1706. #else
  1707. struct fw_ohci *ohci = fw_ohci(card);
  1708. unsigned long flags;
  1709. int n, ret = 0;
  1710. /*
  1711. * FIXME: Make sure this bitmask is cleared when we clear the busReset
  1712. * interrupt bit. Clear physReqResourceAllBuses on bus reset.
  1713. */
  1714. spin_lock_irqsave(&ohci->lock, flags);
  1715. if (ohci->generation != generation) {
  1716. ret = -ESTALE;
  1717. goto out;
  1718. }
  1719. /*
  1720. * Note, if the node ID contains a non-local bus ID, physical DMA is
  1721. * enabled for _all_ nodes on remote buses.
  1722. */
  1723. n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
  1724. if (n < 32)
  1725. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
  1726. else
  1727. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
  1728. flush_writes(ohci);
  1729. out:
  1730. spin_unlock_irqrestore(&ohci->lock, flags);
  1731. return ret;
  1732. #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
  1733. }
  1734. static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
  1735. {
  1736. struct fw_ohci *ohci = fw_ohci(card);
  1737. unsigned long flags;
  1738. u32 value;
  1739. switch (csr_offset) {
  1740. case CSR_STATE_CLEAR:
  1741. case CSR_STATE_SET:
  1742. if (ohci->is_root &&
  1743. (reg_read(ohci, OHCI1394_LinkControlSet) &
  1744. OHCI1394_LinkControl_cycleMaster))
  1745. value = CSR_STATE_BIT_CMSTR;
  1746. else
  1747. value = 0;
  1748. if (ohci->csr_state_setclear_abdicate)
  1749. value |= CSR_STATE_BIT_ABDICATE;
  1750. return value;
  1751. case CSR_NODE_IDS:
  1752. return reg_read(ohci, OHCI1394_NodeID) << 16;
  1753. case CSR_CYCLE_TIME:
  1754. return get_cycle_time(ohci);
  1755. case CSR_BUS_TIME:
  1756. /*
  1757. * We might be called just after the cycle timer has wrapped
  1758. * around but just before the cycle64Seconds handler, so we
  1759. * better check here, too, if the bus time needs to be updated.
  1760. */
  1761. spin_lock_irqsave(&ohci->lock, flags);
  1762. value = update_bus_time(ohci);
  1763. spin_unlock_irqrestore(&ohci->lock, flags);
  1764. return value;
  1765. case CSR_BUSY_TIMEOUT:
  1766. value = reg_read(ohci, OHCI1394_ATRetries);
  1767. return (value >> 4) & 0x0ffff00f;
  1768. case CSR_PRIORITY_BUDGET:
  1769. return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
  1770. (ohci->pri_req_max << 8);
  1771. default:
  1772. WARN_ON(1);
  1773. return 0;
  1774. }
  1775. }
  1776. static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
  1777. {
  1778. struct fw_ohci *ohci = fw_ohci(card);
  1779. unsigned long flags;
  1780. switch (csr_offset) {
  1781. case CSR_STATE_CLEAR:
  1782. if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
  1783. reg_write(ohci, OHCI1394_LinkControlClear,
  1784. OHCI1394_LinkControl_cycleMaster);
  1785. flush_writes(ohci);
  1786. }
  1787. if (value & CSR_STATE_BIT_ABDICATE)
  1788. ohci->csr_state_setclear_abdicate = false;
  1789. break;
  1790. case CSR_STATE_SET:
  1791. if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
  1792. reg_write(ohci, OHCI1394_LinkControlSet,
  1793. OHCI1394_LinkControl_cycleMaster);
  1794. flush_writes(ohci);
  1795. }
  1796. if (value & CSR_STATE_BIT_ABDICATE)
  1797. ohci->csr_state_setclear_abdicate = true;
  1798. break;
  1799. case CSR_NODE_IDS:
  1800. reg_write(ohci, OHCI1394_NodeID, value >> 16);
  1801. flush_writes(ohci);
  1802. break;
  1803. case CSR_CYCLE_TIME:
  1804. reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
  1805. reg_write(ohci, OHCI1394_IntEventSet,
  1806. OHCI1394_cycleInconsistent);
  1807. flush_writes(ohci);
  1808. break;
  1809. case CSR_BUS_TIME:
  1810. spin_lock_irqsave(&ohci->lock, flags);
  1811. ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
  1812. spin_unlock_irqrestore(&ohci->lock, flags);
  1813. break;
  1814. case CSR_BUSY_TIMEOUT:
  1815. value = (value & 0xf) | ((value & 0xf) << 4) |
  1816. ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
  1817. reg_write(ohci, OHCI1394_ATRetries, value);
  1818. flush_writes(ohci);
  1819. break;
  1820. case CSR_PRIORITY_BUDGET:
  1821. reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
  1822. flush_writes(ohci);
  1823. break;
  1824. default:
  1825. WARN_ON(1);
  1826. break;
  1827. }
  1828. }
  1829. static void copy_iso_headers(struct iso_context *ctx, void *p)
  1830. {
  1831. int i = ctx->header_length;
  1832. if (i + ctx->base.header_size > PAGE_SIZE)
  1833. return;
  1834. /*
  1835. * The iso header is byteswapped to little endian by
  1836. * the controller, but the remaining header quadlets
  1837. * are big endian. We want to present all the headers
  1838. * as big endian, so we have to swap the first quadlet.
  1839. */
  1840. if (ctx->base.header_size > 0)
  1841. *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
  1842. if (ctx->base.header_size > 4)
  1843. *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
  1844. if (ctx->base.header_size > 8)
  1845. memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
  1846. ctx->header_length += ctx->base.header_size;
  1847. }
  1848. static int handle_ir_packet_per_buffer(struct context *context,
  1849. struct descriptor *d,
  1850. struct descriptor *last)
  1851. {
  1852. struct iso_context *ctx =
  1853. container_of(context, struct iso_context, context);
  1854. struct descriptor *pd;
  1855. __le32 *ir_header;
  1856. void *p;
  1857. for (pd = d; pd <= last; pd++)
  1858. if (pd->transfer_status)
  1859. break;
  1860. if (pd > last)
  1861. /* Descriptor(s) not done yet, stop iteration */
  1862. return 0;
  1863. p = last + 1;
  1864. copy_iso_headers(ctx, p);
  1865. if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
  1866. ir_header = (__le32 *) p;
  1867. ctx->base.callback.sc(&ctx->base,
  1868. le32_to_cpu(ir_header[0]) & 0xffff,
  1869. ctx->header_length, ctx->header,
  1870. ctx->base.callback_data);
  1871. ctx->header_length = 0;
  1872. }
  1873. return 1;
  1874. }
  1875. /* d == last because each descriptor block is only a single descriptor. */
  1876. static int handle_ir_buffer_fill(struct context *context,
  1877. struct descriptor *d,
  1878. struct descriptor *last)
  1879. {
  1880. struct iso_context *ctx =
  1881. container_of(context, struct iso_context, context);
  1882. if (!last->transfer_status)
  1883. /* Descriptor(s) not done yet, stop iteration */
  1884. return 0;
  1885. if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
  1886. ctx->base.callback.mc(&ctx->base,
  1887. le32_to_cpu(last->data_address) +
  1888. le16_to_cpu(last->req_count) -
  1889. le16_to_cpu(last->res_count),
  1890. ctx->base.callback_data);
  1891. return 1;
  1892. }
  1893. static int handle_it_packet(struct context *context,
  1894. struct descriptor *d,
  1895. struct descriptor *last)
  1896. {
  1897. struct iso_context *ctx =
  1898. container_of(context, struct iso_context, context);
  1899. int i;
  1900. struct descriptor *pd;
  1901. for (pd = d; pd <= last; pd++)
  1902. if (pd->transfer_status)
  1903. break;
  1904. if (pd > last)
  1905. /* Descriptor(s) not done yet, stop iteration */
  1906. return 0;
  1907. i = ctx->header_length;
  1908. if (i + 4 < PAGE_SIZE) {
  1909. /* Present this value as big-endian to match the receive code */
  1910. *(__be32 *)(ctx->header + i) = cpu_to_be32(
  1911. ((u32)le16_to_cpu(pd->transfer_status) << 16) |
  1912. le16_to_cpu(pd->res_count));
  1913. ctx->header_length += 4;
  1914. }
  1915. if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
  1916. ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
  1917. ctx->header_length, ctx->header,
  1918. ctx->base.callback_data);
  1919. ctx->header_length = 0;
  1920. }
  1921. return 1;
  1922. }
  1923. static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
  1924. {
  1925. u32 hi = channels >> 32, lo = channels;
  1926. reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
  1927. reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
  1928. reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
  1929. reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
  1930. mmiowb();
  1931. ohci->mc_channels = channels;
  1932. }
  1933. static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
  1934. int type, int channel, size_t header_size)
  1935. {
  1936. struct fw_ohci *ohci = fw_ohci(card);
  1937. struct iso_context *uninitialized_var(ctx);
  1938. descriptor_callback_t uninitialized_var(callback);
  1939. u64 *uninitialized_var(channels);
  1940. u32 *uninitialized_var(mask), uninitialized_var(regs);
  1941. unsigned long flags;
  1942. int index, ret = -EBUSY;
  1943. spin_lock_irqsave(&ohci->lock, flags);
  1944. switch (type) {
  1945. case FW_ISO_CONTEXT_TRANSMIT:
  1946. mask = &ohci->it_context_mask;
  1947. callback = handle_it_packet;
  1948. index = ffs(*mask) - 1;
  1949. if (index >= 0) {
  1950. *mask &= ~(1 << index);
  1951. regs = OHCI1394_IsoXmitContextBase(index);
  1952. ctx = &ohci->it_context_list[index];
  1953. }
  1954. break;
  1955. case FW_ISO_CONTEXT_RECEIVE:
  1956. channels = &ohci->ir_context_channels;
  1957. mask = &ohci->ir_context_mask;
  1958. callback = handle_ir_packet_per_buffer;
  1959. index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
  1960. if (index >= 0) {
  1961. *channels &= ~(1ULL << channel);
  1962. *mask &= ~(1 << index);
  1963. regs = OHCI1394_IsoRcvContextBase(index);
  1964. ctx = &ohci->ir_context_list[index];
  1965. }
  1966. break;
  1967. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  1968. mask = &ohci->ir_context_mask;
  1969. callback = handle_ir_buffer_fill;
  1970. index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
  1971. if (index >= 0) {
  1972. ohci->mc_allocated = true;
  1973. *mask &= ~(1 << index);
  1974. regs = OHCI1394_IsoRcvContextBase(index);
  1975. ctx = &ohci->ir_context_list[index];
  1976. }
  1977. break;
  1978. default:
  1979. index = -1;
  1980. ret = -ENOSYS;
  1981. }
  1982. spin_unlock_irqrestore(&ohci->lock, flags);
  1983. if (index < 0)
  1984. return ERR_PTR(ret);
  1985. memset(ctx, 0, sizeof(*ctx));
  1986. ctx->header_length = 0;
  1987. ctx->header = (void *) __get_free_page(GFP_KERNEL);
  1988. if (ctx->header == NULL) {
  1989. ret = -ENOMEM;
  1990. goto out;
  1991. }
  1992. ret = context_init(&ctx->context, ohci, regs, callback);
  1993. if (ret < 0)
  1994. goto out_with_header;
  1995. if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
  1996. set_multichannel_mask(ohci, 0);
  1997. return &ctx->base;
  1998. out_with_header:
  1999. free_page((unsigned long)ctx->header);
  2000. out:
  2001. spin_lock_irqsave(&ohci->lock, flags);
  2002. switch (type) {
  2003. case FW_ISO_CONTEXT_RECEIVE:
  2004. *channels |= 1ULL << channel;
  2005. break;
  2006. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2007. ohci->mc_allocated = false;
  2008. break;
  2009. }
  2010. *mask |= 1 << index;
  2011. spin_unlock_irqrestore(&ohci->lock, flags);
  2012. return ERR_PTR(ret);
  2013. }
  2014. static int ohci_start_iso(struct fw_iso_context *base,
  2015. s32 cycle, u32 sync, u32 tags)
  2016. {
  2017. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2018. struct fw_ohci *ohci = ctx->context.ohci;
  2019. u32 control = IR_CONTEXT_ISOCH_HEADER, match;
  2020. int index;
  2021. switch (ctx->base.type) {
  2022. case FW_ISO_CONTEXT_TRANSMIT:
  2023. index = ctx - ohci->it_context_list;
  2024. match = 0;
  2025. if (cycle >= 0)
  2026. match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
  2027. (cycle & 0x7fff) << 16;
  2028. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
  2029. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
  2030. context_run(&ctx->context, match);
  2031. break;
  2032. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2033. control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
  2034. /* fall through */
  2035. case FW_ISO_CONTEXT_RECEIVE:
  2036. index = ctx - ohci->ir_context_list;
  2037. match = (tags << 28) | (sync << 8) | ctx->base.channel;
  2038. if (cycle >= 0) {
  2039. match |= (cycle & 0x07fff) << 12;
  2040. control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
  2041. }
  2042. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
  2043. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
  2044. reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
  2045. context_run(&ctx->context, control);
  2046. break;
  2047. }
  2048. return 0;
  2049. }
  2050. static int ohci_stop_iso(struct fw_iso_context *base)
  2051. {
  2052. struct fw_ohci *ohci = fw_ohci(base->card);
  2053. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2054. int index;
  2055. switch (ctx->base.type) {
  2056. case FW_ISO_CONTEXT_TRANSMIT:
  2057. index = ctx - ohci->it_context_list;
  2058. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
  2059. break;
  2060. case FW_ISO_CONTEXT_RECEIVE:
  2061. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2062. index = ctx - ohci->ir_context_list;
  2063. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
  2064. break;
  2065. }
  2066. flush_writes(ohci);
  2067. context_stop(&ctx->context);
  2068. return 0;
  2069. }
  2070. static void ohci_free_iso_context(struct fw_iso_context *base)
  2071. {
  2072. struct fw_ohci *ohci = fw_ohci(base->card);
  2073. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2074. unsigned long flags;
  2075. int index;
  2076. ohci_stop_iso(base);
  2077. context_release(&ctx->context);
  2078. free_page((unsigned long)ctx->header);
  2079. spin_lock_irqsave(&ohci->lock, flags);
  2080. switch (base->type) {
  2081. case FW_ISO_CONTEXT_TRANSMIT:
  2082. index = ctx - ohci->it_context_list;
  2083. ohci->it_context_mask |= 1 << index;
  2084. break;
  2085. case FW_ISO_CONTEXT_RECEIVE:
  2086. index = ctx - ohci->ir_context_list;
  2087. ohci->ir_context_mask |= 1 << index;
  2088. ohci->ir_context_channels |= 1ULL << base->channel;
  2089. break;
  2090. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2091. index = ctx - ohci->ir_context_list;
  2092. ohci->ir_context_mask |= 1 << index;
  2093. ohci->ir_context_channels |= ohci->mc_channels;
  2094. ohci->mc_channels = 0;
  2095. ohci->mc_allocated = false;
  2096. break;
  2097. }
  2098. spin_unlock_irqrestore(&ohci->lock, flags);
  2099. }
  2100. static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
  2101. {
  2102. struct fw_ohci *ohci = fw_ohci(base->card);
  2103. unsigned long flags;
  2104. int ret;
  2105. switch (base->type) {
  2106. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2107. spin_lock_irqsave(&ohci->lock, flags);
  2108. /* Don't allow multichannel to grab other contexts' channels. */
  2109. if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
  2110. *channels = ohci->ir_context_channels;
  2111. ret = -EBUSY;
  2112. } else {
  2113. set_multichannel_mask(ohci, *channels);
  2114. ret = 0;
  2115. }
  2116. spin_unlock_irqrestore(&ohci->lock, flags);
  2117. break;
  2118. default:
  2119. ret = -EINVAL;
  2120. }
  2121. return ret;
  2122. }
  2123. static int queue_iso_transmit(struct iso_context *ctx,
  2124. struct fw_iso_packet *packet,
  2125. struct fw_iso_buffer *buffer,
  2126. unsigned long payload)
  2127. {
  2128. struct descriptor *d, *last, *pd;
  2129. struct fw_iso_packet *p;
  2130. __le32 *header;
  2131. dma_addr_t d_bus, page_bus;
  2132. u32 z, header_z, payload_z, irq;
  2133. u32 payload_index, payload_end_index, next_page_index;
  2134. int page, end_page, i, length, offset;
  2135. p = packet;
  2136. payload_index = payload;
  2137. if (p->skip)
  2138. z = 1;
  2139. else
  2140. z = 2;
  2141. if (p->header_length > 0)
  2142. z++;
  2143. /* Determine the first page the payload isn't contained in. */
  2144. end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
  2145. if (p->payload_length > 0)
  2146. payload_z = end_page - (payload_index >> PAGE_SHIFT);
  2147. else
  2148. payload_z = 0;
  2149. z += payload_z;
  2150. /* Get header size in number of descriptors. */
  2151. header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
  2152. d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
  2153. if (d == NULL)
  2154. return -ENOMEM;
  2155. if (!p->skip) {
  2156. d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
  2157. d[0].req_count = cpu_to_le16(8);
  2158. /*
  2159. * Link the skip address to this descriptor itself. This causes
  2160. * a context to skip a cycle whenever lost cycles or FIFO
  2161. * overruns occur, without dropping the data. The application
  2162. * should then decide whether this is an error condition or not.
  2163. * FIXME: Make the context's cycle-lost behaviour configurable?
  2164. */
  2165. d[0].branch_address = cpu_to_le32(d_bus | z);
  2166. header = (__le32 *) &d[1];
  2167. header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
  2168. IT_HEADER_TAG(p->tag) |
  2169. IT_HEADER_TCODE(TCODE_STREAM_DATA) |
  2170. IT_HEADER_CHANNEL(ctx->base.channel) |
  2171. IT_HEADER_SPEED(ctx->base.speed));
  2172. header[1] =
  2173. cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
  2174. p->payload_length));
  2175. }
  2176. if (p->header_length > 0) {
  2177. d[2].req_count = cpu_to_le16(p->header_length);
  2178. d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
  2179. memcpy(&d[z], p->header, p->header_length);
  2180. }
  2181. pd = d + z - payload_z;
  2182. payload_end_index = payload_index + p->payload_length;
  2183. for (i = 0; i < payload_z; i++) {
  2184. page = payload_index >> PAGE_SHIFT;
  2185. offset = payload_index & ~PAGE_MASK;
  2186. next_page_index = (page + 1) << PAGE_SHIFT;
  2187. length =
  2188. min(next_page_index, payload_end_index) - payload_index;
  2189. pd[i].req_count = cpu_to_le16(length);
  2190. page_bus = page_private(buffer->pages[page]);
  2191. pd[i].data_address = cpu_to_le32(page_bus + offset);
  2192. payload_index += length;
  2193. }
  2194. if (p->interrupt)
  2195. irq = DESCRIPTOR_IRQ_ALWAYS;
  2196. else
  2197. irq = DESCRIPTOR_NO_IRQ;
  2198. last = z == 2 ? d : d + z - 1;
  2199. last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
  2200. DESCRIPTOR_STATUS |
  2201. DESCRIPTOR_BRANCH_ALWAYS |
  2202. irq);
  2203. context_append(&ctx->context, d, z, header_z);
  2204. return 0;
  2205. }
  2206. static int queue_iso_packet_per_buffer(struct iso_context *ctx,
  2207. struct fw_iso_packet *packet,
  2208. struct fw_iso_buffer *buffer,
  2209. unsigned long payload)
  2210. {
  2211. struct descriptor *d, *pd;
  2212. dma_addr_t d_bus, page_bus;
  2213. u32 z, header_z, rest;
  2214. int i, j, length;
  2215. int page, offset, packet_count, header_size, payload_per_buffer;
  2216. /*
  2217. * The OHCI controller puts the isochronous header and trailer in the
  2218. * buffer, so we need at least 8 bytes.
  2219. */
  2220. packet_count = packet->header_length / ctx->base.header_size;
  2221. header_size = max(ctx->base.header_size, (size_t)8);
  2222. /* Get header size in number of descriptors. */
  2223. header_z = DIV_ROUND_UP(header_size, sizeof(*d));
  2224. page = payload >> PAGE_SHIFT;
  2225. offset = payload & ~PAGE_MASK;
  2226. payload_per_buffer = packet->payload_length / packet_count;
  2227. for (i = 0; i < packet_count; i++) {
  2228. /* d points to the header descriptor */
  2229. z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
  2230. d = context_get_descriptors(&ctx->context,
  2231. z + header_z, &d_bus);
  2232. if (d == NULL)
  2233. return -ENOMEM;
  2234. d->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2235. DESCRIPTOR_INPUT_MORE);
  2236. if (packet->skip && i == 0)
  2237. d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
  2238. d->req_count = cpu_to_le16(header_size);
  2239. d->res_count = d->req_count;
  2240. d->transfer_status = 0;
  2241. d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
  2242. rest = payload_per_buffer;
  2243. pd = d;
  2244. for (j = 1; j < z; j++) {
  2245. pd++;
  2246. pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2247. DESCRIPTOR_INPUT_MORE);
  2248. if (offset + rest < PAGE_SIZE)
  2249. length = rest;
  2250. else
  2251. length = PAGE_SIZE - offset;
  2252. pd->req_count = cpu_to_le16(length);
  2253. pd->res_count = pd->req_count;
  2254. pd->transfer_status = 0;
  2255. page_bus = page_private(buffer->pages[page]);
  2256. pd->data_address = cpu_to_le32(page_bus + offset);
  2257. offset = (offset + length) & ~PAGE_MASK;
  2258. rest -= length;
  2259. if (offset == 0)
  2260. page++;
  2261. }
  2262. pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2263. DESCRIPTOR_INPUT_LAST |
  2264. DESCRIPTOR_BRANCH_ALWAYS);
  2265. if (packet->interrupt && i == packet_count - 1)
  2266. pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
  2267. context_append(&ctx->context, d, z, header_z);
  2268. }
  2269. return 0;
  2270. }
  2271. static int queue_iso_buffer_fill(struct iso_context *ctx,
  2272. struct fw_iso_packet *packet,
  2273. struct fw_iso_buffer *buffer,
  2274. unsigned long payload)
  2275. {
  2276. struct descriptor *d;
  2277. dma_addr_t d_bus, page_bus;
  2278. int page, offset, rest, z, i, length;
  2279. page = payload >> PAGE_SHIFT;
  2280. offset = payload & ~PAGE_MASK;
  2281. rest = packet->payload_length;
  2282. /* We need one descriptor for each page in the buffer. */
  2283. z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
  2284. if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
  2285. return -EFAULT;
  2286. for (i = 0; i < z; i++) {
  2287. d = context_get_descriptors(&ctx->context, 1, &d_bus);
  2288. if (d == NULL)
  2289. return -ENOMEM;
  2290. d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
  2291. DESCRIPTOR_BRANCH_ALWAYS);
  2292. if (packet->skip && i == 0)
  2293. d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
  2294. if (packet->interrupt && i == z - 1)
  2295. d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
  2296. if (offset + rest < PAGE_SIZE)
  2297. length = rest;
  2298. else
  2299. length = PAGE_SIZE - offset;
  2300. d->req_count = cpu_to_le16(length);
  2301. d->res_count = d->req_count;
  2302. d->transfer_status = 0;
  2303. page_bus = page_private(buffer->pages[page]);
  2304. d->data_address = cpu_to_le32(page_bus + offset);
  2305. rest -= length;
  2306. offset = 0;
  2307. page++;
  2308. context_append(&ctx->context, d, 1, 0);
  2309. }
  2310. return 0;
  2311. }
  2312. static int ohci_queue_iso(struct fw_iso_context *base,
  2313. struct fw_iso_packet *packet,
  2314. struct fw_iso_buffer *buffer,
  2315. unsigned long payload)
  2316. {
  2317. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2318. unsigned long flags;
  2319. int ret = -ENOSYS;
  2320. spin_lock_irqsave(&ctx->context.ohci->lock, flags);
  2321. switch (base->type) {
  2322. case FW_ISO_CONTEXT_TRANSMIT:
  2323. ret = queue_iso_transmit(ctx, packet, buffer, payload);
  2324. break;
  2325. case FW_ISO_CONTEXT_RECEIVE:
  2326. ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
  2327. break;
  2328. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2329. ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
  2330. break;
  2331. }
  2332. spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
  2333. return ret;
  2334. }
  2335. static const struct fw_card_driver ohci_driver = {
  2336. .enable = ohci_enable,
  2337. .read_phy_reg = ohci_read_phy_reg,
  2338. .update_phy_reg = ohci_update_phy_reg,
  2339. .set_config_rom = ohci_set_config_rom,
  2340. .send_request = ohci_send_request,
  2341. .send_response = ohci_send_response,
  2342. .cancel_packet = ohci_cancel_packet,
  2343. .enable_phys_dma = ohci_enable_phys_dma,
  2344. .read_csr = ohci_read_csr,
  2345. .write_csr = ohci_write_csr,
  2346. .allocate_iso_context = ohci_allocate_iso_context,
  2347. .free_iso_context = ohci_free_iso_context,
  2348. .set_iso_channels = ohci_set_iso_channels,
  2349. .queue_iso = ohci_queue_iso,
  2350. .start_iso = ohci_start_iso,
  2351. .stop_iso = ohci_stop_iso,
  2352. };
  2353. #ifdef CONFIG_PPC_PMAC
  2354. static void pmac_ohci_on(struct pci_dev *dev)
  2355. {
  2356. if (machine_is(powermac)) {
  2357. struct device_node *ofn = pci_device_to_OF_node(dev);
  2358. if (ofn) {
  2359. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
  2360. pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
  2361. }
  2362. }
  2363. }
  2364. static void pmac_ohci_off(struct pci_dev *dev)
  2365. {
  2366. if (machine_is(powermac)) {
  2367. struct device_node *ofn = pci_device_to_OF_node(dev);
  2368. if (ofn) {
  2369. pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
  2370. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
  2371. }
  2372. }
  2373. }
  2374. #else
  2375. static inline void pmac_ohci_on(struct pci_dev *dev) {}
  2376. static inline void pmac_ohci_off(struct pci_dev *dev) {}
  2377. #endif /* CONFIG_PPC_PMAC */
  2378. static int __devinit pci_probe(struct pci_dev *dev,
  2379. const struct pci_device_id *ent)
  2380. {
  2381. struct fw_ohci *ohci;
  2382. u32 bus_options, max_receive, link_speed, version, link_enh;
  2383. u64 guid;
  2384. int i, err, n_ir, n_it;
  2385. size_t size;
  2386. ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
  2387. if (ohci == NULL) {
  2388. err = -ENOMEM;
  2389. goto fail;
  2390. }
  2391. fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
  2392. pmac_ohci_on(dev);
  2393. err = pci_enable_device(dev);
  2394. if (err) {
  2395. fw_error("Failed to enable OHCI hardware\n");
  2396. goto fail_free;
  2397. }
  2398. pci_set_master(dev);
  2399. pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
  2400. pci_set_drvdata(dev, ohci);
  2401. spin_lock_init(&ohci->lock);
  2402. mutex_init(&ohci->phy_reg_mutex);
  2403. tasklet_init(&ohci->bus_reset_tasklet,
  2404. bus_reset_tasklet, (unsigned long)ohci);
  2405. err = pci_request_region(dev, 0, ohci_driver_name);
  2406. if (err) {
  2407. fw_error("MMIO resource unavailable\n");
  2408. goto fail_disable;
  2409. }
  2410. ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
  2411. if (ohci->registers == NULL) {
  2412. fw_error("Failed to remap registers\n");
  2413. err = -ENXIO;
  2414. goto fail_iomem;
  2415. }
  2416. for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
  2417. if (ohci_quirks[i].vendor == dev->vendor &&
  2418. (ohci_quirks[i].device == dev->device ||
  2419. ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
  2420. ohci->quirks = ohci_quirks[i].flags;
  2421. break;
  2422. }
  2423. if (param_quirks)
  2424. ohci->quirks = param_quirks;
  2425. /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
  2426. if (dev->vendor == PCI_VENDOR_ID_TI) {
  2427. pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
  2428. /* adjust latency of ATx FIFO: use 1.7 KB threshold */
  2429. link_enh &= ~TI_LinkEnh_atx_thresh_mask;
  2430. link_enh |= TI_LinkEnh_atx_thresh_1_7K;
  2431. /* use priority arbitration for asynchronous responses */
  2432. link_enh |= TI_LinkEnh_enab_unfair;
  2433. /* required for aPhyEnhanceEnable to work */
  2434. link_enh |= TI_LinkEnh_enab_accel;
  2435. pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
  2436. }
  2437. ar_context_init(&ohci->ar_request_ctx, ohci,
  2438. OHCI1394_AsReqRcvContextControlSet);
  2439. ar_context_init(&ohci->ar_response_ctx, ohci,
  2440. OHCI1394_AsRspRcvContextControlSet);
  2441. context_init(&ohci->at_request_ctx, ohci,
  2442. OHCI1394_AsReqTrContextControlSet, handle_at_packet);
  2443. context_init(&ohci->at_response_ctx, ohci,
  2444. OHCI1394_AsRspTrContextControlSet, handle_at_packet);
  2445. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
  2446. ohci->ir_context_channels = ~0ULL;
  2447. ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
  2448. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
  2449. n_ir = hweight32(ohci->ir_context_mask);
  2450. size = sizeof(struct iso_context) * n_ir;
  2451. ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
  2452. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
  2453. ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
  2454. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
  2455. n_it = hweight32(ohci->it_context_mask);
  2456. size = sizeof(struct iso_context) * n_it;
  2457. ohci->it_context_list = kzalloc(size, GFP_KERNEL);
  2458. if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
  2459. err = -ENOMEM;
  2460. goto fail_contexts;
  2461. }
  2462. /* self-id dma buffer allocation */
  2463. ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
  2464. SELF_ID_BUF_SIZE,
  2465. &ohci->self_id_bus,
  2466. GFP_KERNEL);
  2467. if (ohci->self_id_cpu == NULL) {
  2468. err = -ENOMEM;
  2469. goto fail_contexts;
  2470. }
  2471. bus_options = reg_read(ohci, OHCI1394_BusOptions);
  2472. max_receive = (bus_options >> 12) & 0xf;
  2473. link_speed = bus_options & 0x7;
  2474. guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
  2475. reg_read(ohci, OHCI1394_GUIDLo);
  2476. err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
  2477. if (err)
  2478. goto fail_self_id;
  2479. version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
  2480. fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
  2481. "%d IR + %d IT contexts, quirks 0x%x\n",
  2482. dev_name(&dev->dev), version >> 16, version & 0xff,
  2483. n_ir, n_it, ohci->quirks);
  2484. return 0;
  2485. fail_self_id:
  2486. dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
  2487. ohci->self_id_cpu, ohci->self_id_bus);
  2488. fail_contexts:
  2489. kfree(ohci->ir_context_list);
  2490. kfree(ohci->it_context_list);
  2491. context_release(&ohci->at_response_ctx);
  2492. context_release(&ohci->at_request_ctx);
  2493. ar_context_release(&ohci->ar_response_ctx);
  2494. ar_context_release(&ohci->ar_request_ctx);
  2495. pci_iounmap(dev, ohci->registers);
  2496. fail_iomem:
  2497. pci_release_region(dev, 0);
  2498. fail_disable:
  2499. pci_disable_device(dev);
  2500. fail_free:
  2501. kfree(&ohci->card);
  2502. pmac_ohci_off(dev);
  2503. fail:
  2504. if (err == -ENOMEM)
  2505. fw_error("Out of memory\n");
  2506. return err;
  2507. }
  2508. static void pci_remove(struct pci_dev *dev)
  2509. {
  2510. struct fw_ohci *ohci;
  2511. ohci = pci_get_drvdata(dev);
  2512. reg_write(ohci, OHCI1394_IntMaskClear, ~0);
  2513. flush_writes(ohci);
  2514. fw_core_remove_card(&ohci->card);
  2515. /*
  2516. * FIXME: Fail all pending packets here, now that the upper
  2517. * layers can't queue any more.
  2518. */
  2519. software_reset(ohci);
  2520. free_irq(dev->irq, ohci);
  2521. if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
  2522. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  2523. ohci->next_config_rom, ohci->next_config_rom_bus);
  2524. if (ohci->config_rom)
  2525. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  2526. ohci->config_rom, ohci->config_rom_bus);
  2527. dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
  2528. ohci->self_id_cpu, ohci->self_id_bus);
  2529. ar_context_release(&ohci->ar_request_ctx);
  2530. ar_context_release(&ohci->ar_response_ctx);
  2531. context_release(&ohci->at_request_ctx);
  2532. context_release(&ohci->at_response_ctx);
  2533. kfree(ohci->it_context_list);
  2534. kfree(ohci->ir_context_list);
  2535. pci_disable_msi(dev);
  2536. pci_iounmap(dev, ohci->registers);
  2537. pci_release_region(dev, 0);
  2538. pci_disable_device(dev);
  2539. kfree(&ohci->card);
  2540. pmac_ohci_off(dev);
  2541. fw_notify("Removed fw-ohci device.\n");
  2542. }
  2543. #ifdef CONFIG_PM
  2544. static int pci_suspend(struct pci_dev *dev, pm_message_t state)
  2545. {
  2546. struct fw_ohci *ohci = pci_get_drvdata(dev);
  2547. int err;
  2548. software_reset(ohci);
  2549. free_irq(dev->irq, ohci);
  2550. pci_disable_msi(dev);
  2551. err = pci_save_state(dev);
  2552. if (err) {
  2553. fw_error("pci_save_state failed\n");
  2554. return err;
  2555. }
  2556. err = pci_set_power_state(dev, pci_choose_state(dev, state));
  2557. if (err)
  2558. fw_error("pci_set_power_state failed with %d\n", err);
  2559. pmac_ohci_off(dev);
  2560. return 0;
  2561. }
  2562. static int pci_resume(struct pci_dev *dev)
  2563. {
  2564. struct fw_ohci *ohci = pci_get_drvdata(dev);
  2565. int err;
  2566. pmac_ohci_on(dev);
  2567. pci_set_power_state(dev, PCI_D0);
  2568. pci_restore_state(dev);
  2569. err = pci_enable_device(dev);
  2570. if (err) {
  2571. fw_error("pci_enable_device failed\n");
  2572. return err;
  2573. }
  2574. return ohci_enable(&ohci->card, NULL, 0);
  2575. }
  2576. #endif
  2577. static const struct pci_device_id pci_table[] = {
  2578. { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
  2579. { }
  2580. };
  2581. MODULE_DEVICE_TABLE(pci, pci_table);
  2582. static struct pci_driver fw_ohci_pci_driver = {
  2583. .name = ohci_driver_name,
  2584. .id_table = pci_table,
  2585. .probe = pci_probe,
  2586. .remove = pci_remove,
  2587. #ifdef CONFIG_PM
  2588. .resume = pci_resume,
  2589. .suspend = pci_suspend,
  2590. #endif
  2591. };
  2592. MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
  2593. MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
  2594. MODULE_LICENSE("GPL");
  2595. /* Provide a module alias so root-on-sbp2 initrds don't break. */
  2596. #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
  2597. MODULE_ALIAS("ohci1394");
  2598. #endif
  2599. static int __init fw_ohci_init(void)
  2600. {
  2601. return pci_register_driver(&fw_ohci_pci_driver);
  2602. }
  2603. static void __exit fw_ohci_cleanup(void)
  2604. {
  2605. pci_unregister_driver(&fw_ohci_pci_driver);
  2606. }
  2607. module_init(fw_ohci_init);
  2608. module_exit(fw_ohci_cleanup);