Kconfig 8.1 KB

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  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. #
  6. menuconfig EDAC
  7. bool "EDAC (Error Detection And Correction) reporting"
  8. depends on HAS_IOMEM
  9. depends on X86 || PPC
  10. help
  11. EDAC is designed to report errors in the core system.
  12. These are low-level errors that are reported in the CPU or
  13. supporting chipset or other subsystems:
  14. memory errors, cache errors, PCI errors, thermal throttling, etc..
  15. If unsure, select 'Y'.
  16. If this code is reporting problems on your system, please
  17. see the EDAC project web pages for more information at:
  18. <http://bluesmoke.sourceforge.net/>
  19. and:
  20. <http://buttersideup.com/edacwiki>
  21. There is also a mailing list for the EDAC project, which can
  22. be found via the sourceforge page.
  23. if EDAC
  24. comment "Reporting subsystems"
  25. config EDAC_DEBUG
  26. bool "Debugging"
  27. help
  28. This turns on debugging information for the entire EDAC
  29. sub-system. You can insert module with "debug_level=x", current
  30. there're four debug levels (x=0,1,2,3 from low to high).
  31. Usually you should select 'N'.
  32. config EDAC_DECODE_MCE
  33. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  34. depends on CPU_SUP_AMD && X86_MCE
  35. default y
  36. ---help---
  37. Enable this option if you want to decode Machine Check Exceptions
  38. occuring on your machine in human-readable form.
  39. You should definitely say Y here in case you want to decode MCEs
  40. which occur really early upon boot, before the module infrastructure
  41. has been initialized.
  42. config EDAC_MM_EDAC
  43. tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  44. help
  45. Some systems are able to detect and correct errors in main
  46. memory. EDAC can report statistics on memory error
  47. detection and correction (EDAC - or commonly referred to ECC
  48. errors). EDAC will also try to decode where these errors
  49. occurred so that a particular failing memory module can be
  50. replaced. If unsure, select 'Y'.
  51. config EDAC_MCE
  52. bool
  53. config EDAC_AMD64
  54. tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
  55. depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
  56. help
  57. Support for error detection and correction on the AMD 64
  58. Families of Memory Controllers (K8, F10h and F11h)
  59. config EDAC_AMD64_ERROR_INJECTION
  60. bool "Sysfs Error Injection facilities"
  61. depends on EDAC_AMD64
  62. help
  63. Recent Opterons (Family 10h and later) provide for Memory Error
  64. Injection into the ECC detection circuits. The amd64_edac module
  65. allows the operator/user to inject Uncorrectable and Correctable
  66. errors into DRAM.
  67. When enabled, in each of the respective memory controller directories
  68. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  69. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  70. - inject_word (0..8, 16-bit word of 16-byte section),
  71. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  72. In addition, there are two control files, inject_read and inject_write,
  73. which trigger the DRAM ECC Read and Write respectively.
  74. config EDAC_AMD76X
  75. tristate "AMD 76x (760, 762, 768)"
  76. depends on EDAC_MM_EDAC && PCI && X86_32
  77. help
  78. Support for error detection and correction on the AMD 76x
  79. series of chipsets used with the Athlon processor.
  80. config EDAC_E7XXX
  81. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  82. depends on EDAC_MM_EDAC && PCI && X86_32
  83. help
  84. Support for error detection and correction on the Intel
  85. E7205, E7500, E7501 and E7505 server chipsets.
  86. config EDAC_E752X
  87. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  88. depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
  89. help
  90. Support for error detection and correction on the Intel
  91. E7520, E7525, E7320 server chipsets.
  92. config EDAC_I82443BXGX
  93. tristate "Intel 82443BX/GX (440BX/GX)"
  94. depends on EDAC_MM_EDAC && PCI && X86_32
  95. depends on BROKEN
  96. help
  97. Support for error detection and correction on the Intel
  98. 82443BX/GX memory controllers (440BX/GX chipsets).
  99. config EDAC_I82875P
  100. tristate "Intel 82875p (D82875P, E7210)"
  101. depends on EDAC_MM_EDAC && PCI && X86_32
  102. help
  103. Support for error detection and correction on the Intel
  104. DP82785P and E7210 server chipsets.
  105. config EDAC_I82975X
  106. tristate "Intel 82975x (D82975x)"
  107. depends on EDAC_MM_EDAC && PCI && X86
  108. help
  109. Support for error detection and correction on the Intel
  110. DP82975x server chipsets.
  111. config EDAC_I3000
  112. tristate "Intel 3000/3010"
  113. depends on EDAC_MM_EDAC && PCI && X86
  114. help
  115. Support for error detection and correction on the Intel
  116. 3000 and 3010 server chipsets.
  117. config EDAC_I3200
  118. tristate "Intel 3200"
  119. depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
  120. help
  121. Support for error detection and correction on the Intel
  122. 3200 and 3210 server chipsets.
  123. config EDAC_X38
  124. tristate "Intel X38"
  125. depends on EDAC_MM_EDAC && PCI && X86
  126. help
  127. Support for error detection and correction on the Intel
  128. X38 server chipsets.
  129. config EDAC_I5400
  130. tristate "Intel 5400 (Seaburg) chipsets"
  131. depends on EDAC_MM_EDAC && PCI && X86
  132. help
  133. Support for error detection and correction the Intel
  134. i5400 MCH chipset (Seaburg).
  135. config EDAC_I7CORE
  136. tristate "Intel i7 Core (Nehalem) processors"
  137. depends on EDAC_MM_EDAC && PCI && X86
  138. select EDAC_MCE
  139. help
  140. Support for error detection and correction the Intel
  141. i7 Core (Nehalem) Integrated Memory Controller that exists on
  142. newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
  143. and Xeon 55xx processors.
  144. config EDAC_I82860
  145. tristate "Intel 82860"
  146. depends on EDAC_MM_EDAC && PCI && X86_32
  147. help
  148. Support for error detection and correction on the Intel
  149. 82860 chipset.
  150. config EDAC_R82600
  151. tristate "Radisys 82600 embedded chipset"
  152. depends on EDAC_MM_EDAC && PCI && X86_32
  153. help
  154. Support for error detection and correction on the Radisys
  155. 82600 embedded chipset.
  156. config EDAC_I5000
  157. tristate "Intel Greencreek/Blackford chipset"
  158. depends on EDAC_MM_EDAC && X86 && PCI
  159. help
  160. Support for error detection and correction the Intel
  161. Greekcreek/Blackford chipsets.
  162. config EDAC_I5100
  163. tristate "Intel San Clemente MCH"
  164. depends on EDAC_MM_EDAC && X86 && PCI
  165. help
  166. Support for error detection and correction the Intel
  167. San Clemente MCH.
  168. config EDAC_MPC85XX
  169. tristate "Freescale MPC83xx / MPC85xx"
  170. depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
  171. help
  172. Support for error detection and correction on the Freescale
  173. MPC8349, MPC8560, MPC8540, MPC8548
  174. config EDAC_MV64X60
  175. tristate "Marvell MV64x60"
  176. depends on EDAC_MM_EDAC && MV64X60
  177. help
  178. Support for error detection and correction on the Marvell
  179. MV64360 and MV64460 chipsets.
  180. config EDAC_PASEMI
  181. tristate "PA Semi PWRficient"
  182. depends on EDAC_MM_EDAC && PCI
  183. depends on PPC_PASEMI
  184. help
  185. Support for error detection and correction on PA Semi
  186. PWRficient.
  187. config EDAC_CELL
  188. tristate "Cell Broadband Engine memory controller"
  189. depends on EDAC_MM_EDAC && PPC_CELL_COMMON
  190. help
  191. Support for error detection and correction on the
  192. Cell Broadband Engine internal memory controller
  193. on platform without a hypervisor
  194. config EDAC_PPC4XX
  195. tristate "PPC4xx IBM DDR2 Memory Controller"
  196. depends on EDAC_MM_EDAC && 4xx
  197. help
  198. This enables support for EDAC on the ECC memory used
  199. with the IBM DDR2 memory controller found in various
  200. PowerPC 4xx embedded processors such as the 405EX[r],
  201. 440SP, 440SPe, 460EX, 460GT and 460SX.
  202. config EDAC_AMD8131
  203. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  204. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  205. help
  206. Support for error detection and correction on the
  207. AMD8131 HyperTransport PCI-X Tunnel chip.
  208. Note, add more Kconfig dependency if it's adopted
  209. on some machine other than Maple.
  210. config EDAC_AMD8111
  211. tristate "AMD8111 HyperTransport I/O Hub"
  212. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  213. help
  214. Support for error detection and correction on the
  215. AMD8111 HyperTransport I/O Hub chip.
  216. Note, add more Kconfig dependency if it's adopted
  217. on some machine other than Maple.
  218. config EDAC_CPC925
  219. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  220. depends on EDAC_MM_EDAC && PPC64
  221. help
  222. Support for error detection and correction on the
  223. IBM CPC925 Bridge and Memory Controller, which is
  224. a companion chip to the PowerPC 970 family of
  225. processors.
  226. endif # EDAC