powertv-usb.c 11 KB

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  1. /*
  2. * powertv-usb.c
  3. *
  4. * Description: ASIC-specific USB device setup and shutdown
  5. *
  6. * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  7. * Copyright (C) 2009 Cisco Systems, Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22. *
  23. * Author: Ken Eppinett
  24. * David Schleef <ds@schleef.org>
  25. *
  26. * NOTE: The bootloader allocates persistent memory at an address which is
  27. * 16 MiB below the end of the highest address in KSEG0. All fixed
  28. * address memory reservations must avoid this region.
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/ioport.h>
  32. #include <linux/platform_device.h>
  33. #include <asm/mach-powertv/asic.h>
  34. #include <asm/mach-powertv/interrupts.h>
  35. /* misc_clk_ctl1 values */
  36. #define MCC1_30MHZ_POWERUP_SELECT (1 << 14)
  37. #define MCC1_DIV9 (1 << 13)
  38. #define MCC1_ETHMIPS_POWERUP_SELECT (1 << 11)
  39. #define MCC1_USB_POWERUP_SELECT (1 << 1)
  40. #define MCC1_CLOCK108_POWERUP_SELECT (1 << 0)
  41. /* Possible values for clock select */
  42. #define MCC1_USB_CLOCK_HIGH_Z (0 << 4)
  43. #define MCC1_USB_CLOCK_48MHZ (1 << 4)
  44. #define MCC1_USB_CLOCK_24MHZ (2 << 4)
  45. #define MCC1_USB_CLOCK_6MHZ (3 << 4)
  46. #define MCC1_CONFIG (MCC1_30MHZ_POWERUP_SELECT | \
  47. MCC1_DIV9 | \
  48. MCC1_ETHMIPS_POWERUP_SELECT | \
  49. MCC1_USB_POWERUP_SELECT | \
  50. MCC1_CLOCK108_POWERUP_SELECT)
  51. /* misc_clk_ctl2 values */
  52. #define MCC2_GMII_GCLK_TO_PAD (1 << 31)
  53. #define MCC2_ETHER125_0_CLOCK_SELECT (1 << 29)
  54. #define MCC2_RMII_0_CLOCK_SELECT (1 << 28)
  55. #define MCC2_GMII_TX0_CLOCK_SELECT (1 << 27)
  56. #define MCC2_GMII_RX0_CLOCK_SELECT (1 << 26)
  57. #define MCC2_ETHER125_1_CLOCK_SELECT (1 << 24)
  58. #define MCC2_RMII_1_CLOCK_SELECT (1 << 23)
  59. #define MCC2_GMII_TX1_CLOCK_SELECT (1 << 22)
  60. #define MCC2_GMII_RX1_CLOCK_SELECT (1 << 21)
  61. #define MCC2_ETHER125_2_CLOCK_SELECT (1 << 19)
  62. #define MCC2_RMII_2_CLOCK_SELECT (1 << 18)
  63. #define MCC2_GMII_TX2_CLOCK_SELECT (1 << 17)
  64. #define MCC2_GMII_RX2_CLOCK_SELECT (1 << 16)
  65. #define ETHER_CLK_CONFIG (MCC2_GMII_GCLK_TO_PAD | \
  66. MCC2_ETHER125_0_CLOCK_SELECT | \
  67. MCC2_RMII_0_CLOCK_SELECT | \
  68. MCC2_GMII_TX0_CLOCK_SELECT | \
  69. MCC2_GMII_RX0_CLOCK_SELECT | \
  70. MCC2_ETHER125_1_CLOCK_SELECT | \
  71. MCC2_RMII_1_CLOCK_SELECT | \
  72. MCC2_GMII_TX1_CLOCK_SELECT | \
  73. MCC2_GMII_RX1_CLOCK_SELECT | \
  74. MCC2_ETHER125_2_CLOCK_SELECT | \
  75. MCC2_RMII_2_CLOCK_SELECT | \
  76. MCC2_GMII_TX2_CLOCK_SELECT | \
  77. MCC2_GMII_RX2_CLOCK_SELECT)
  78. /* misc_clk_ctl2 definitions for Gaia */
  79. #define FSX4A_REF_SELECT (1 << 16)
  80. #define FSX4B_REF_SELECT (1 << 17)
  81. #define FSX4C_REF_SELECT (1 << 18)
  82. #define DDR_PLL_REF_SELECT (1 << 19)
  83. #define MIPS_PLL_REF_SELECT (1 << 20)
  84. /* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */
  85. #define QAM_FS_SDIV_SHIFT 29
  86. #define QAM_FS_MD_SHIFT 24
  87. #define QAM_FS_MD_MASK 0x1f /* Cut down to 5 bits */
  88. #define QAM_FS_PE_SHIFT 8
  89. #define QAM_FS_DISABLE_DIVIDE_BY_3 (1 << 5)
  90. #define QAM_FS_ENABLE_PROGRAM (1 << 4)
  91. #define QAM_FS_ENABLE_OUTPUT (1 << 3)
  92. #define QAM_FS_SELECT_TEST_BYPASS (1 << 2)
  93. #define QAM_FS_DISABLE_DIGITAL_STANDBY (1 << 1)
  94. #define QAM_FS_CHOOSE_FS (1 << 0)
  95. /* Definitions for fs432x4a_ctl register */
  96. #define QAM_FS_NSDIV_54MHZ (1 << 2)
  97. /* Definitions for bcm1_usb2_ctl register */
  98. #define BCM1_USB2_CTL_BISTOK (1 << 11)
  99. #define BCM1_USB2_CTL_PORT2_SHIFT_JK (1 << 7)
  100. #define BCM1_USB2_CTL_PORT1_SHIFT_JK (1 << 6)
  101. #define BCM1_USB2_CTL_PORT2_FAST_EDGE (1 << 5)
  102. #define BCM1_USB2_CTL_PORT1_FAST_EDGE (1 << 4)
  103. #define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH (1 << 1)
  104. #define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH (1 << 0)
  105. /* Definitions for crt_spare register */
  106. #define CRT_SPARE_PORT2_SHIFT_JK (1 << 21)
  107. #define CRT_SPARE_PORT1_SHIFT_JK (1 << 20)
  108. #define CRT_SPARE_PORT2_FAST_EDGE (1 << 19)
  109. #define CRT_SPARE_PORT1_FAST_EDGE (1 << 18)
  110. #define CRT_SPARE_DIVIDE_BY_9_FROM_432 (1 << 17)
  111. #define CRT_SPARE_USB_DIVIDE_BY_9 (1 << 16)
  112. /* Definitions for usb2_stbus_obc register */
  113. #define USB_STBUS_OBC_STORE32_LOAD32 0x3
  114. /* Definitions for usb2_stbus_mess_size register */
  115. #define USB2_STBUS_MESS_SIZE_2 0x1 /* 2 packets */
  116. /* Definitions for usb2_stbus_chunk_size register */
  117. #define USB2_STBUS_CHUNK_SIZE_2 0x1 /* 2 packets */
  118. /* Definitions for usb2_strap register */
  119. #define USB2_STRAP_HFREQ_SELECT 0x1
  120. /*
  121. * USB Host Resource Definition
  122. */
  123. static struct resource ehci_resources[] = {
  124. {
  125. .parent = &asic_resource,
  126. .start = 0,
  127. .end = 0xff,
  128. .flags = IORESOURCE_MEM,
  129. },
  130. {
  131. .start = irq_usbehci,
  132. .end = irq_usbehci,
  133. .flags = IORESOURCE_IRQ,
  134. },
  135. };
  136. static u64 ehci_dmamask = 0xffffffffULL;
  137. static struct platform_device ehci_device = {
  138. .name = "powertv-ehci",
  139. .id = 0,
  140. .num_resources = 2,
  141. .resource = ehci_resources,
  142. .dev = {
  143. .dma_mask = &ehci_dmamask,
  144. .coherent_dma_mask = 0xffffffff,
  145. },
  146. };
  147. static struct resource ohci_resources[] = {
  148. {
  149. .parent = &asic_resource,
  150. .start = 0,
  151. .end = 0xff,
  152. .flags = IORESOURCE_MEM,
  153. },
  154. {
  155. .start = irq_usbohci,
  156. .end = irq_usbohci,
  157. .flags = IORESOURCE_IRQ,
  158. },
  159. };
  160. static u64 ohci_dmamask = 0xffffffffULL;
  161. static struct platform_device ohci_device = {
  162. .name = "powertv-ohci",
  163. .id = 0,
  164. .num_resources = 2,
  165. .resource = ohci_resources,
  166. .dev = {
  167. .dma_mask = &ohci_dmamask,
  168. .coherent_dma_mask = 0xffffffff,
  169. },
  170. };
  171. static unsigned usb_users;
  172. static DEFINE_SPINLOCK(usb_regs_lock);
  173. /*
  174. *
  175. * fs_update - set frequency synthesizer for USB
  176. * @pe_bits Phase tap setting
  177. * @md_bits Coarse selector bus for algorithm of phase tap
  178. * @sdiv_bits Output divider setting
  179. * @disable_div_by_3 Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero
  180. * @standby Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero
  181. *
  182. * QAM frequency selection code, which affects the frequency at which USB
  183. * runs. The frequency is calculated as:
  184. * 2^15 * ndiv * Fin
  185. * Fout = ------------------------------------------------------------
  186. * (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
  187. * where:
  188. * Fin 54 MHz
  189. * ndiv QAM_FS_NSDIV_54MHZ ? 8 : 16
  190. * sdiv 1 << (sdiv_bits + 1)
  191. * ipe Same as pe_bits
  192. * md A five-bit, two's-complement integer (range [-16, 15]), which
  193. * is the lower 5 bits of md_bits.
  194. */
  195. static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
  196. u32 disable_div_by_3, u32 standby)
  197. {
  198. u32 val;
  199. val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
  200. ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
  201. (pe_bits << QAM_FS_PE_SHIFT) |
  202. QAM_FS_ENABLE_OUTPUT |
  203. standby |
  204. disable_div_by_3);
  205. asic_write(val, fs432x4b4_usb_ctl);
  206. asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
  207. asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
  208. fs432x4b4_usb_ctl);
  209. }
  210. /*
  211. * usb_eye_configure - for optimizing the shape USB eye waveform
  212. * @set: Bits to set in the register
  213. * @clear: Bits to clear in the register; each bit with a one will
  214. * be set in the register, zero bits will not be modified
  215. */
  216. static void usb_eye_configure(u32 set, u32 clear)
  217. {
  218. u32 old;
  219. old = asic_read(crt_spare);
  220. old |= set;
  221. old &= ~clear;
  222. asic_write(old, crt_spare);
  223. }
  224. /*
  225. * platform_configure_usb - usb configuration based on platform type.
  226. */
  227. static void platform_configure_usb(void)
  228. {
  229. u32 bcm1_usb2_ctl_value;
  230. enum asic_type asic_type;
  231. unsigned long flags;
  232. spin_lock_irqsave(&usb_regs_lock, flags);
  233. usb_users++;
  234. if (usb_users != 1) {
  235. spin_unlock_irqrestore(&usb_regs_lock, flags);
  236. return;
  237. }
  238. asic_type = platform_get_asic();
  239. switch (asic_type) {
  240. case ASIC_ZEUS:
  241. fs_update(0x0000, -15, 0x02, 0, 0);
  242. bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
  243. BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
  244. break;
  245. case ASIC_CRONUS:
  246. case ASIC_CRONUSLITE:
  247. usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
  248. fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
  249. QAM_FS_DISABLE_DIGITAL_STANDBY);
  250. bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
  251. BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
  252. break;
  253. case ASIC_CALLIOPE:
  254. fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
  255. QAM_FS_DISABLE_DIGITAL_STANDBY);
  256. switch (platform_get_family()) {
  257. case FAMILY_1500VZE:
  258. break;
  259. case FAMILY_1500VZF:
  260. usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
  261. CRT_SPARE_PORT1_SHIFT_JK |
  262. CRT_SPARE_PORT2_FAST_EDGE |
  263. CRT_SPARE_PORT1_FAST_EDGE, 0);
  264. break;
  265. default:
  266. usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
  267. CRT_SPARE_PORT1_SHIFT_JK, 0);
  268. break;
  269. }
  270. bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
  271. BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
  272. BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
  273. break;
  274. case ASIC_GAIA:
  275. fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
  276. QAM_FS_DISABLE_DIGITAL_STANDBY);
  277. bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
  278. BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
  279. BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
  280. break;
  281. default:
  282. pr_err("Unknown ASIC type: %d\n", asic_type);
  283. bcm1_usb2_ctl_value = 0;
  284. break;
  285. }
  286. /* turn on USB power */
  287. asic_write(0, usb2_strap);
  288. /* Enable all OHCI interrupts */
  289. asic_write(bcm1_usb2_ctl_value, usb2_control);
  290. /* usb2_stbus_obc store32/load32 */
  291. asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
  292. /* usb2_stbus_mess_size 2 packets */
  293. asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
  294. /* usb2_stbus_chunk_size 2 packets */
  295. asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
  296. spin_unlock_irqrestore(&usb_regs_lock, flags);
  297. }
  298. static void platform_unconfigure_usb(void)
  299. {
  300. unsigned long flags;
  301. spin_lock_irqsave(&usb_regs_lock, flags);
  302. usb_users--;
  303. if (usb_users == 0)
  304. asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
  305. spin_unlock_irqrestore(&usb_regs_lock, flags);
  306. }
  307. /*
  308. * Set up the USB EHCI interface
  309. */
  310. void platform_configure_usb_ehci()
  311. {
  312. platform_configure_usb();
  313. }
  314. EXPORT_SYMBOL(platform_configure_usb_ehci);
  315. /*
  316. * Set up the USB OHCI interface
  317. */
  318. void platform_configure_usb_ohci()
  319. {
  320. platform_configure_usb();
  321. }
  322. EXPORT_SYMBOL(platform_configure_usb_ohci);
  323. /*
  324. * Shut the USB EHCI interface down
  325. */
  326. void platform_unconfigure_usb_ehci()
  327. {
  328. platform_unconfigure_usb();
  329. }
  330. EXPORT_SYMBOL(platform_unconfigure_usb_ehci);
  331. /*
  332. * Shut the USB OHCI interface down
  333. */
  334. void platform_unconfigure_usb_ohci()
  335. {
  336. platform_unconfigure_usb();
  337. }
  338. EXPORT_SYMBOL(platform_unconfigure_usb_ohci);
  339. /**
  340. * platform_devices_init - sets up USB device resourse.
  341. */
  342. int __init platform_usb_devices_init(struct platform_device **ehci_dev,
  343. struct platform_device **ohci_dev)
  344. {
  345. *ehci_dev = &ehci_device;
  346. ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
  347. ehci_resources[0].end += ehci_resources[0].start;
  348. *ohci_dev = &ohci_device;
  349. ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
  350. ohci_resources[0].end += ohci_resources[0].start;
  351. return 0;
  352. }