minotaur.c 13 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2008-2009 Cambridge Signal Processing
  4. * 2005 National ICT Australia (NICTA)
  5. * Aidan Williams <aidan@nicta.com.au>
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <linux/device.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/mtd/mtd.h>
  12. #include <linux/mtd/partitions.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  16. #include <linux/usb/isp1362.h>
  17. #endif
  18. #include <linux/ata_platform.h>
  19. #include <linux/irq.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/usb/sl811.h>
  22. #include <asm/dma.h>
  23. #include <asm/bfin5xx_spi.h>
  24. #include <asm/reboot.h>
  25. #include <asm/portmux.h>
  26. #include <linux/spi/ad7877.h>
  27. /*
  28. * Name the Board for the /proc/cpuinfo
  29. */
  30. const char bfin_board_name[] = "CamSig Minotaur BF537";
  31. #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
  32. static struct resource bfin_pcmcia_cf_resources[] = {
  33. {
  34. .start = 0x20310000, /* IO PORT */
  35. .end = 0x20312000,
  36. .flags = IORESOURCE_MEM,
  37. }, {
  38. .start = 0x20311000, /* Attribute Memory */
  39. .end = 0x20311FFF,
  40. .flags = IORESOURCE_MEM,
  41. }, {
  42. .start = IRQ_PF4,
  43. .end = IRQ_PF4,
  44. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
  45. }, {
  46. .start = IRQ_PF6, /* Card Detect PF6 */
  47. .end = IRQ_PF6,
  48. .flags = IORESOURCE_IRQ,
  49. },
  50. };
  51. static struct platform_device bfin_pcmcia_cf_device = {
  52. .name = "bfin_cf_pcmcia",
  53. .id = -1,
  54. .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
  55. .resource = bfin_pcmcia_cf_resources,
  56. };
  57. #endif
  58. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  59. static struct platform_device rtc_device = {
  60. .name = "rtc-bfin",
  61. .id = -1,
  62. };
  63. #endif
  64. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  65. static struct platform_device bfin_mii_bus = {
  66. .name = "bfin_mii_bus",
  67. };
  68. static struct platform_device bfin_mac_device = {
  69. .name = "bfin_mac",
  70. .dev.platform_data = &bfin_mii_bus,
  71. };
  72. #endif
  73. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  74. static struct resource net2272_bfin_resources[] = {
  75. {
  76. .start = 0x20300000,
  77. .end = 0x20300000 + 0x100,
  78. .flags = IORESOURCE_MEM,
  79. }, {
  80. .start = IRQ_PF7,
  81. .end = IRQ_PF7,
  82. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  83. },
  84. };
  85. static struct platform_device net2272_bfin_device = {
  86. .name = "net2272",
  87. .id = -1,
  88. .num_resources = ARRAY_SIZE(net2272_bfin_resources),
  89. .resource = net2272_bfin_resources,
  90. };
  91. #endif
  92. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  93. /* all SPI peripherals info goes here */
  94. #if defined(CONFIG_MTD_M25P80) \
  95. || defined(CONFIG_MTD_M25P80_MODULE)
  96. /* Partition sizes */
  97. #define FLASH_SIZE 0x00400000
  98. #define PSIZE_UBOOT 0x00030000
  99. #define PSIZE_INITRAMFS 0x00240000
  100. static struct mtd_partition bfin_spi_flash_partitions[] = {
  101. {
  102. .name = "bootloader(spi)",
  103. .size = PSIZE_UBOOT,
  104. .offset = 0x000000,
  105. .mask_flags = MTD_CAP_ROM
  106. }, {
  107. .name = "initramfs(spi)",
  108. .size = PSIZE_INITRAMFS,
  109. .offset = PSIZE_UBOOT
  110. }, {
  111. .name = "opt(spi)",
  112. .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
  113. .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
  114. }
  115. };
  116. static struct flash_platform_data bfin_spi_flash_data = {
  117. .name = "m25p80",
  118. .parts = bfin_spi_flash_partitions,
  119. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  120. .type = "m25p64",
  121. };
  122. /* SPI flash chip (m25p64) */
  123. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  124. .enable_dma = 0, /* use dma transfer with this chip*/
  125. .bits_per_word = 8,
  126. };
  127. #endif
  128. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  129. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  130. .enable_dma = 0,
  131. .bits_per_word = 8,
  132. };
  133. #endif
  134. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  135. #if defined(CONFIG_MTD_M25P80) \
  136. || defined(CONFIG_MTD_M25P80_MODULE)
  137. {
  138. /* the modalias must be the same as spi device driver name */
  139. .modalias = "m25p80", /* Name of spi_driver for this device */
  140. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  141. .bus_num = 0, /* Framework bus number */
  142. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  143. .platform_data = &bfin_spi_flash_data,
  144. .controller_data = &spi_flash_chip_info,
  145. .mode = SPI_MODE_3,
  146. },
  147. #endif
  148. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  149. {
  150. .modalias = "mmc_spi",
  151. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  152. .bus_num = 0,
  153. .chip_select = 5,
  154. .controller_data = &mmc_spi_chip_info,
  155. .mode = SPI_MODE_3,
  156. },
  157. #endif
  158. };
  159. /* SPI controller data */
  160. static struct bfin5xx_spi_master bfin_spi0_info = {
  161. .num_chipselect = 8,
  162. .enable_dma = 1, /* master has the ability to do dma transfer */
  163. };
  164. /* SPI (0) */
  165. static struct resource bfin_spi0_resource[] = {
  166. [0] = {
  167. .start = SPI0_REGBASE,
  168. .end = SPI0_REGBASE + 0xFF,
  169. .flags = IORESOURCE_MEM,
  170. },
  171. [1] = {
  172. .start = CH_SPI,
  173. .end = CH_SPI,
  174. .flags = IORESOURCE_DMA,
  175. },
  176. [2] = {
  177. .start = IRQ_SPI,
  178. .end = IRQ_SPI,
  179. .flags = IORESOURCE_IRQ,
  180. },
  181. };
  182. static struct platform_device bfin_spi0_device = {
  183. .name = "bfin-spi",
  184. .id = 0, /* Bus number */
  185. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  186. .resource = bfin_spi0_resource,
  187. .dev = {
  188. .platform_data = &bfin_spi0_info, /* Passed to driver */
  189. },
  190. };
  191. #endif /* spi master and devices */
  192. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  193. #ifdef CONFIG_SERIAL_BFIN_UART0
  194. static struct resource bfin_uart0_resources[] = {
  195. {
  196. .start = UART0_THR,
  197. .end = UART0_GCTL+2,
  198. .flags = IORESOURCE_MEM,
  199. },
  200. {
  201. .start = IRQ_UART0_RX,
  202. .end = IRQ_UART0_RX+1,
  203. .flags = IORESOURCE_IRQ,
  204. },
  205. {
  206. .start = IRQ_UART0_ERROR,
  207. .end = IRQ_UART0_ERROR,
  208. .flags = IORESOURCE_IRQ,
  209. },
  210. {
  211. .start = CH_UART0_TX,
  212. .end = CH_UART0_TX,
  213. .flags = IORESOURCE_DMA,
  214. },
  215. {
  216. .start = CH_UART0_RX,
  217. .end = CH_UART0_RX,
  218. .flags = IORESOURCE_DMA,
  219. },
  220. };
  221. unsigned short bfin_uart0_peripherals[] = {
  222. P_UART0_TX, P_UART0_RX, 0
  223. };
  224. static struct platform_device bfin_uart0_device = {
  225. .name = "bfin-uart",
  226. .id = 0,
  227. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  228. .resource = bfin_uart0_resources,
  229. .dev = {
  230. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  231. },
  232. };
  233. #endif
  234. #ifdef CONFIG_SERIAL_BFIN_UART1
  235. static struct resource bfin_uart1_resources[] = {
  236. {
  237. .start = UART1_THR,
  238. .end = UART1_GCTL+2,
  239. .flags = IORESOURCE_MEM,
  240. },
  241. {
  242. .start = IRQ_UART1_RX,
  243. .end = IRQ_UART1_RX+1,
  244. .flags = IORESOURCE_IRQ,
  245. },
  246. {
  247. .start = IRQ_UART1_ERROR,
  248. .end = IRQ_UART1_ERROR,
  249. .flags = IORESOURCE_IRQ,
  250. },
  251. {
  252. .start = CH_UART1_TX,
  253. .end = CH_UART1_TX,
  254. .flags = IORESOURCE_DMA,
  255. },
  256. {
  257. .start = CH_UART1_RX,
  258. .end = CH_UART1_RX,
  259. .flags = IORESOURCE_DMA,
  260. },
  261. };
  262. unsigned short bfin_uart1_peripherals[] = {
  263. P_UART1_TX, P_UART1_RX, 0
  264. };
  265. static struct platform_device bfin_uart1_device = {
  266. .name = "bfin-uart",
  267. .id = 1,
  268. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  269. .resource = bfin_uart1_resources,
  270. .dev = {
  271. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  272. },
  273. };
  274. #endif
  275. #endif
  276. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  277. #ifdef CONFIG_BFIN_SIR0
  278. static struct resource bfin_sir0_resources[] = {
  279. {
  280. .start = 0xFFC00400,
  281. .end = 0xFFC004FF,
  282. .flags = IORESOURCE_MEM,
  283. },
  284. {
  285. .start = IRQ_UART0_RX,
  286. .end = IRQ_UART0_RX+1,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. {
  290. .start = CH_UART0_RX,
  291. .end = CH_UART0_RX+1,
  292. .flags = IORESOURCE_DMA,
  293. },
  294. };
  295. static struct platform_device bfin_sir0_device = {
  296. .name = "bfin_sir",
  297. .id = 0,
  298. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  299. .resource = bfin_sir0_resources,
  300. };
  301. #endif
  302. #ifdef CONFIG_BFIN_SIR1
  303. static struct resource bfin_sir1_resources[] = {
  304. {
  305. .start = 0xFFC02000,
  306. .end = 0xFFC020FF,
  307. .flags = IORESOURCE_MEM,
  308. },
  309. {
  310. .start = IRQ_UART1_RX,
  311. .end = IRQ_UART1_RX+1,
  312. .flags = IORESOURCE_IRQ,
  313. },
  314. {
  315. .start = CH_UART1_RX,
  316. .end = CH_UART1_RX+1,
  317. .flags = IORESOURCE_DMA,
  318. },
  319. };
  320. static struct platform_device bfin_sir1_device = {
  321. .name = "bfin_sir",
  322. .id = 1,
  323. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  324. .resource = bfin_sir1_resources,
  325. };
  326. #endif
  327. #endif
  328. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  329. static struct resource bfin_twi0_resource[] = {
  330. [0] = {
  331. .start = TWI0_REGBASE,
  332. .end = TWI0_REGBASE + 0xFF,
  333. .flags = IORESOURCE_MEM,
  334. },
  335. [1] = {
  336. .start = IRQ_TWI,
  337. .end = IRQ_TWI,
  338. .flags = IORESOURCE_IRQ,
  339. },
  340. };
  341. static struct platform_device i2c_bfin_twi_device = {
  342. .name = "i2c-bfin-twi",
  343. .id = 0,
  344. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  345. .resource = bfin_twi0_resource,
  346. };
  347. #endif
  348. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  349. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  350. static struct resource bfin_sport0_uart_resources[] = {
  351. {
  352. .start = SPORT0_TCR1,
  353. .end = SPORT0_MRCS3+4,
  354. .flags = IORESOURCE_MEM,
  355. },
  356. {
  357. .start = IRQ_SPORT0_RX,
  358. .end = IRQ_SPORT0_RX+1,
  359. .flags = IORESOURCE_IRQ,
  360. },
  361. {
  362. .start = IRQ_SPORT0_ERROR,
  363. .end = IRQ_SPORT0_ERROR,
  364. .flags = IORESOURCE_IRQ,
  365. },
  366. };
  367. unsigned short bfin_sport0_peripherals[] = {
  368. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  369. P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
  370. };
  371. static struct platform_device bfin_sport0_uart_device = {
  372. .name = "bfin-sport-uart",
  373. .id = 0,
  374. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  375. .resource = bfin_sport0_uart_resources,
  376. .dev = {
  377. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  378. },
  379. };
  380. #endif
  381. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  382. static struct resource bfin_sport1_uart_resources[] = {
  383. {
  384. .start = SPORT1_TCR1,
  385. .end = SPORT1_MRCS3+4,
  386. .flags = IORESOURCE_MEM,
  387. },
  388. {
  389. .start = IRQ_SPORT1_RX,
  390. .end = IRQ_SPORT1_RX+1,
  391. .flags = IORESOURCE_IRQ,
  392. },
  393. {
  394. .start = IRQ_SPORT1_ERROR,
  395. .end = IRQ_SPORT1_ERROR,
  396. .flags = IORESOURCE_IRQ,
  397. },
  398. };
  399. unsigned short bfin_sport1_peripherals[] = {
  400. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  401. P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
  402. };
  403. static struct platform_device bfin_sport1_uart_device = {
  404. .name = "bfin-sport-uart",
  405. .id = 1,
  406. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  407. .resource = bfin_sport1_uart_resources,
  408. .dev = {
  409. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  410. },
  411. };
  412. #endif
  413. #endif
  414. static struct platform_device *minotaur_devices[] __initdata = {
  415. #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
  416. &bfin_pcmcia_cf_device,
  417. #endif
  418. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  419. &rtc_device,
  420. #endif
  421. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  422. &bfin_mii_bus,
  423. &bfin_mac_device,
  424. #endif
  425. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  426. &net2272_bfin_device,
  427. #endif
  428. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  429. &bfin_spi0_device,
  430. #endif
  431. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  432. #ifdef CONFIG_SERIAL_BFIN_UART0
  433. &bfin_uart0_device,
  434. #endif
  435. #ifdef CONFIG_SERIAL_BFIN_UART1
  436. &bfin_uart1_device,
  437. #endif
  438. #endif
  439. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  440. #ifdef CONFIG_BFIN_SIR0
  441. &bfin_sir0_device,
  442. #endif
  443. #ifdef CONFIG_BFIN_SIR1
  444. &bfin_sir1_device,
  445. #endif
  446. #endif
  447. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  448. &i2c_bfin_twi_device,
  449. #endif
  450. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  451. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  452. &bfin_sport0_uart_device,
  453. #endif
  454. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  455. &bfin_sport1_uart_device,
  456. #endif
  457. #endif
  458. };
  459. static int __init minotaur_init(void)
  460. {
  461. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  462. platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
  463. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  464. spi_register_board_info(bfin_spi_board_info,
  465. ARRAY_SIZE(bfin_spi_board_info));
  466. #endif
  467. return 0;
  468. }
  469. arch_initcall(minotaur_init);
  470. static struct platform_device *minotaur_early_devices[] __initdata = {
  471. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  472. #ifdef CONFIG_SERIAL_BFIN_UART0
  473. &bfin_uart0_device,
  474. #endif
  475. #ifdef CONFIG_SERIAL_BFIN_UART1
  476. &bfin_uart1_device,
  477. #endif
  478. #endif
  479. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  480. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  481. &bfin_sport0_uart_device,
  482. #endif
  483. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  484. &bfin_sport1_uart_device,
  485. #endif
  486. #endif
  487. };
  488. void __init native_machine_early_platform_add_devices(void)
  489. {
  490. printk(KERN_INFO "register early platform devices\n");
  491. early_platform_add_devices(minotaur_early_devices,
  492. ARRAY_SIZE(minotaur_early_devices));
  493. }
  494. void native_machine_restart(char *cmd)
  495. {
  496. /* workaround reboot hang when booting from SPI */
  497. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  498. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  499. }