time.c 6.0 KB

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  1. /*
  2. * arch/arm/plat-spear/time.c
  3. *
  4. * Copyright (C) 2009 ST Microelectronics
  5. * Shiraz Hashim<shiraz.hashim@st.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clockchips.h>
  13. #include <linux/clocksource.h>
  14. #include <linux/err.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/kernel.h>
  19. #include <linux/time.h>
  20. #include <linux/irq.h>
  21. #include <asm/mach/time.h>
  22. #include <mach/irqs.h>
  23. #include <mach/hardware.h>
  24. #include <mach/spear.h>
  25. #include <mach/generic.h>
  26. /*
  27. * We would use TIMER0 and TIMER1 as clockevent and clocksource.
  28. * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
  29. * they share same functional clock. Any change in one's functional clock will
  30. * also affect other timer.
  31. */
  32. #define CLKEVT 0 /* gpt0, channel0 as clockevent */
  33. #define CLKSRC 1 /* gpt0, channel1 as clocksource */
  34. /* Register offsets, x is channel number */
  35. #define CR(x) ((x) * 0x80 + 0x80)
  36. #define IR(x) ((x) * 0x80 + 0x84)
  37. #define LOAD(x) ((x) * 0x80 + 0x88)
  38. #define COUNT(x) ((x) * 0x80 + 0x8C)
  39. /* Reg bit definitions */
  40. #define CTRL_INT_ENABLE 0x0100
  41. #define CTRL_ENABLE 0x0020
  42. #define CTRL_ONE_SHOT 0x0010
  43. #define CTRL_PRESCALER1 0x0
  44. #define CTRL_PRESCALER2 0x1
  45. #define CTRL_PRESCALER4 0x2
  46. #define CTRL_PRESCALER8 0x3
  47. #define CTRL_PRESCALER16 0x4
  48. #define CTRL_PRESCALER32 0x5
  49. #define CTRL_PRESCALER64 0x6
  50. #define CTRL_PRESCALER128 0x7
  51. #define CTRL_PRESCALER256 0x8
  52. #define INT_STATUS 0x1
  53. /*
  54. * Minimum clocksource/clockevent timer range in seconds
  55. */
  56. #define SPEAR_MIN_RANGE 4
  57. static __iomem void *gpt_base;
  58. static struct clk *gpt_clk;
  59. static void clockevent_set_mode(enum clock_event_mode mode,
  60. struct clock_event_device *clk_event_dev);
  61. static int clockevent_next_event(unsigned long evt,
  62. struct clock_event_device *clk_event_dev);
  63. static cycle_t clocksource_read_cycles(struct clocksource *cs)
  64. {
  65. return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
  66. }
  67. static struct clocksource clksrc = {
  68. .name = "tmr1",
  69. .rating = 200, /* its a pretty decent clock */
  70. .read = clocksource_read_cycles,
  71. .mask = 0xFFFF, /* 16 bits */
  72. .mult = 0, /* to be computed */
  73. .shift = 0, /* to be computed */
  74. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  75. };
  76. static void spear_clocksource_init(void)
  77. {
  78. u32 tick_rate;
  79. u16 val;
  80. /* program the prescaler (/256)*/
  81. writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
  82. /* find out actual clock driving Timer */
  83. tick_rate = clk_get_rate(gpt_clk);
  84. tick_rate >>= CTRL_PRESCALER256;
  85. writew(0xFFFF, gpt_base + LOAD(CLKSRC));
  86. val = readw(gpt_base + CR(CLKSRC));
  87. val &= ~CTRL_ONE_SHOT; /* autoreload mode */
  88. val |= CTRL_ENABLE ;
  89. writew(val, gpt_base + CR(CLKSRC));
  90. clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE);
  91. /* register the clocksource */
  92. clocksource_register(&clksrc);
  93. }
  94. static struct clock_event_device clkevt = {
  95. .name = "tmr0",
  96. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  97. .set_mode = clockevent_set_mode,
  98. .set_next_event = clockevent_next_event,
  99. .shift = 0, /* to be computed */
  100. };
  101. static void clockevent_set_mode(enum clock_event_mode mode,
  102. struct clock_event_device *clk_event_dev)
  103. {
  104. u32 period;
  105. u16 val;
  106. /* stop the timer */
  107. val = readw(gpt_base + CR(CLKEVT));
  108. val &= ~CTRL_ENABLE;
  109. writew(val, gpt_base + CR(CLKEVT));
  110. switch (mode) {
  111. case CLOCK_EVT_MODE_PERIODIC:
  112. period = clk_get_rate(gpt_clk) / HZ;
  113. period >>= CTRL_PRESCALER16;
  114. writew(period, gpt_base + LOAD(CLKEVT));
  115. val = readw(gpt_base + CR(CLKEVT));
  116. val &= ~CTRL_ONE_SHOT;
  117. val |= CTRL_ENABLE | CTRL_INT_ENABLE;
  118. writew(val, gpt_base + CR(CLKEVT));
  119. break;
  120. case CLOCK_EVT_MODE_ONESHOT:
  121. val = readw(gpt_base + CR(CLKEVT));
  122. val |= CTRL_ONE_SHOT;
  123. writew(val, gpt_base + CR(CLKEVT));
  124. break;
  125. case CLOCK_EVT_MODE_UNUSED:
  126. case CLOCK_EVT_MODE_SHUTDOWN:
  127. case CLOCK_EVT_MODE_RESUME:
  128. break;
  129. default:
  130. pr_err("Invalid mode requested\n");
  131. break;
  132. }
  133. }
  134. static int clockevent_next_event(unsigned long cycles,
  135. struct clock_event_device *clk_event_dev)
  136. {
  137. u16 val;
  138. writew(cycles, gpt_base + LOAD(CLKEVT));
  139. val = readw(gpt_base + CR(CLKEVT));
  140. val |= CTRL_ENABLE | CTRL_INT_ENABLE;
  141. writew(val, gpt_base + CR(CLKEVT));
  142. return 0;
  143. }
  144. static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
  145. {
  146. struct clock_event_device *evt = &clkevt;
  147. writew(INT_STATUS, gpt_base + IR(CLKEVT));
  148. evt->event_handler(evt);
  149. return IRQ_HANDLED;
  150. }
  151. static struct irqaction spear_timer_irq = {
  152. .name = "timer",
  153. .flags = IRQF_DISABLED | IRQF_TIMER,
  154. .handler = spear_timer_interrupt
  155. };
  156. static void __init spear_clockevent_init(void)
  157. {
  158. u32 tick_rate;
  159. /* program the prescaler */
  160. writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
  161. tick_rate = clk_get_rate(gpt_clk);
  162. tick_rate >>= CTRL_PRESCALER16;
  163. clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
  164. clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
  165. &clkevt);
  166. clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
  167. clkevt.cpumask = cpumask_of(0);
  168. clockevents_register_device(&clkevt);
  169. setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
  170. }
  171. void __init spear_setup_timer(void)
  172. {
  173. struct clk *pll3_clk;
  174. if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
  175. pr_err("%s:cannot get IO addr\n", __func__);
  176. return;
  177. }
  178. gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
  179. if (!gpt_base) {
  180. pr_err("%s:ioremap failed for gpt\n", __func__);
  181. goto err_mem;
  182. }
  183. gpt_clk = clk_get_sys("gpt0", NULL);
  184. if (!gpt_clk) {
  185. pr_err("%s:couldn't get clk for gpt\n", __func__);
  186. goto err_iomap;
  187. }
  188. pll3_clk = clk_get(NULL, "pll3_48m_clk");
  189. if (!pll3_clk) {
  190. pr_err("%s:couldn't get PLL3 as parent for gpt\n", __func__);
  191. goto err_iomap;
  192. }
  193. clk_set_parent(gpt_clk, pll3_clk);
  194. spear_clockevent_init();
  195. spear_clocksource_init();
  196. return;
  197. err_iomap:
  198. iounmap(gpt_base);
  199. err_mem:
  200. release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
  201. }
  202. struct sys_timer spear_sys_timer = {
  203. .init = spear_setup_timer,
  204. };