gpio-config.c 6.0 KB

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  1. /* linux/arch/arm/plat-s3c/gpio-config.c
  2. *
  3. * Copyright 2008 Openmoko, Inc.
  4. * Copyright 2008-2010 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. * http://armlinux.simtec.co.uk/
  7. *
  8. * S3C series GPIO configuration core
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/gpio.h>
  17. #include <linux/io.h>
  18. #include <plat/gpio-core.h>
  19. #include <plat/gpio-cfg.h>
  20. #include <plat/gpio-cfg-helpers.h>
  21. int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
  22. {
  23. struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
  24. unsigned long flags;
  25. int offset;
  26. int ret;
  27. if (!chip)
  28. return -EINVAL;
  29. offset = pin - chip->chip.base;
  30. s3c_gpio_lock(chip, flags);
  31. ret = s3c_gpio_do_setcfg(chip, offset, config);
  32. s3c_gpio_unlock(chip, flags);
  33. return ret;
  34. }
  35. EXPORT_SYMBOL(s3c_gpio_cfgpin);
  36. unsigned s3c_gpio_getcfg(unsigned int pin)
  37. {
  38. struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
  39. unsigned long flags;
  40. unsigned ret = 0;
  41. int offset;
  42. if (chip) {
  43. offset = pin - chip->chip.base;
  44. s3c_gpio_lock(chip, flags);
  45. ret = s3c_gpio_do_getcfg(chip, offset);
  46. s3c_gpio_unlock(chip, flags);
  47. }
  48. return ret;
  49. }
  50. EXPORT_SYMBOL(s3c_gpio_getcfg);
  51. int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
  52. {
  53. struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
  54. unsigned long flags;
  55. int offset, ret;
  56. if (!chip)
  57. return -EINVAL;
  58. offset = pin - chip->chip.base;
  59. s3c_gpio_lock(chip, flags);
  60. ret = s3c_gpio_do_setpull(chip, offset, pull);
  61. s3c_gpio_unlock(chip, flags);
  62. return ret;
  63. }
  64. EXPORT_SYMBOL(s3c_gpio_setpull);
  65. #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
  66. int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
  67. unsigned int off, unsigned int cfg)
  68. {
  69. void __iomem *reg = chip->base;
  70. unsigned int shift = off;
  71. u32 con;
  72. if (s3c_gpio_is_cfg_special(cfg)) {
  73. cfg &= 0xf;
  74. /* Map output to 0, and SFN2 to 1 */
  75. cfg -= 1;
  76. if (cfg > 1)
  77. return -EINVAL;
  78. cfg <<= shift;
  79. }
  80. con = __raw_readl(reg);
  81. con &= ~(0x1 << shift);
  82. con |= cfg;
  83. __raw_writel(con, reg);
  84. return 0;
  85. }
  86. unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
  87. unsigned int off)
  88. {
  89. u32 con;
  90. con = __raw_readl(chip->base);
  91. con >>= off;
  92. con &= 1;
  93. con++;
  94. return S3C_GPIO_SFN(con);
  95. }
  96. int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
  97. unsigned int off, unsigned int cfg)
  98. {
  99. void __iomem *reg = chip->base;
  100. unsigned int shift = off * 2;
  101. u32 con;
  102. if (s3c_gpio_is_cfg_special(cfg)) {
  103. cfg &= 0xf;
  104. if (cfg > 3)
  105. return -EINVAL;
  106. cfg <<= shift;
  107. }
  108. con = __raw_readl(reg);
  109. con &= ~(0x3 << shift);
  110. con |= cfg;
  111. __raw_writel(con, reg);
  112. return 0;
  113. }
  114. unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
  115. unsigned int off)
  116. {
  117. u32 con;
  118. con = __raw_readl(chip->base);
  119. con >>= off * 2;
  120. con &= 3;
  121. /* this conversion works for IN and OUT as well as special mode */
  122. return S3C_GPIO_SPECIAL(con);
  123. }
  124. #endif
  125. #ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
  126. int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
  127. unsigned int off, unsigned int cfg)
  128. {
  129. void __iomem *reg = chip->base;
  130. unsigned int shift = (off & 7) * 4;
  131. u32 con;
  132. if (off < 8 && chip->chip.ngpio > 8)
  133. reg -= 4;
  134. if (s3c_gpio_is_cfg_special(cfg)) {
  135. cfg &= 0xf;
  136. cfg <<= shift;
  137. }
  138. con = __raw_readl(reg);
  139. con &= ~(0xf << shift);
  140. con |= cfg;
  141. __raw_writel(con, reg);
  142. return 0;
  143. }
  144. unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
  145. unsigned int off)
  146. {
  147. void __iomem *reg = chip->base;
  148. unsigned int shift = (off & 7) * 4;
  149. u32 con;
  150. if (off < 8 && chip->chip.ngpio > 8)
  151. reg -= 4;
  152. con = __raw_readl(reg);
  153. con >>= shift;
  154. con &= 0xf;
  155. /* this conversion works for IN and OUT as well as special mode */
  156. return S3C_GPIO_SPECIAL(con);
  157. }
  158. #endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
  159. #ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
  160. int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
  161. unsigned int off, s3c_gpio_pull_t pull)
  162. {
  163. void __iomem *reg = chip->base + 0x08;
  164. int shift = off * 2;
  165. u32 pup;
  166. pup = __raw_readl(reg);
  167. pup &= ~(3 << shift);
  168. pup |= pull << shift;
  169. __raw_writel(pup, reg);
  170. return 0;
  171. }
  172. s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
  173. unsigned int off)
  174. {
  175. void __iomem *reg = chip->base + 0x08;
  176. int shift = off * 2;
  177. u32 pup = __raw_readl(reg);
  178. pup >>= shift;
  179. pup &= 0x3;
  180. return (__force s3c_gpio_pull_t)pup;
  181. }
  182. #endif
  183. #ifdef CONFIG_S3C_GPIO_PULL_UP
  184. int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
  185. unsigned int off, s3c_gpio_pull_t pull)
  186. {
  187. void __iomem *reg = chip->base + 0x08;
  188. u32 pup = __raw_readl(reg);
  189. pup = __raw_readl(reg);
  190. if (pup == S3C_GPIO_PULL_UP)
  191. pup &= ~(1 << off);
  192. else if (pup == S3C_GPIO_PULL_NONE)
  193. pup |= (1 << off);
  194. else
  195. return -EINVAL;
  196. __raw_writel(pup, reg);
  197. return 0;
  198. }
  199. s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
  200. unsigned int off)
  201. {
  202. void __iomem *reg = chip->base + 0x08;
  203. u32 pup = __raw_readl(reg);
  204. pup &= (1 << off);
  205. return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
  206. }
  207. #endif /* CONFIG_S3C_GPIO_PULL_UP */
  208. #ifdef CONFIG_S5P_GPIO_DRVSTR
  209. s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
  210. {
  211. struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
  212. unsigned int off;
  213. void __iomem *reg;
  214. int shift;
  215. u32 drvstr;
  216. if (!chip)
  217. return -EINVAL;
  218. off = chip->chip.base - pin;
  219. shift = off * 2;
  220. reg = chip->base + 0x0C;
  221. drvstr = __raw_readl(reg);
  222. drvstr = 0xffff & (0x3 << shift);
  223. drvstr = drvstr >> shift;
  224. return (__force s5p_gpio_drvstr_t)drvstr;
  225. }
  226. EXPORT_SYMBOL(s5p_gpio_get_drvstr);
  227. int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
  228. {
  229. struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
  230. unsigned int off;
  231. void __iomem *reg;
  232. int shift;
  233. u32 tmp;
  234. if (!chip)
  235. return -EINVAL;
  236. off = chip->chip.base - pin;
  237. shift = off * 2;
  238. reg = chip->base + 0x0C;
  239. tmp = __raw_readl(reg);
  240. tmp |= drvstr << shift;
  241. __raw_writel(tmp, reg);
  242. return 0;
  243. }
  244. EXPORT_SYMBOL(s5p_gpio_set_drvstr);
  245. #endif /* CONFIG_S5P_GPIO_DRVSTR */