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linux-vybrid_pu...
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arch
/
arm
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plat-s3c24xx
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include
/
plat
/
regs-dma.h

regs-dma.h 5.1 KB
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  1. /* arch/arm/mach-s3c2410/include/mach/dma.h
    2. 

  2.  *
    3. 

  3.  * Copyright (C) 2003-2006 Simtec Electronics
    4. 

  4.  *	Ben Dooks <ben@simtec.co.uk>
    5. 

  5.  *
    6. 

  6.  * Samsung S3C24XX DMA support
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11. */
    12. 

  12. 

  13. /* DMA Register definitions */
    14. 

  14. 

  15. #define S3C2410_DMA_DISRC		(0x00)
    16. 

  16. #define S3C2410_DMA_DISRCC		(0x04)
    17. 

  17. #define S3C2410_DMA_DIDST		(0x08)
    18. 

  18. #define S3C2410_DMA_DIDSTC		(0x0C)
    19. 

  19. #define S3C2410_DMA_DCON		(0x10)
    20. 

  20. #define S3C2410_DMA_DSTAT		(0x14)
    21. 

  21. #define S3C2410_DMA_DCSRC		(0x18)
    22. 

  22. #define S3C2410_DMA_DCDST		(0x1C)
    23. 

  23. #define S3C2410_DMA_DMASKTRIG		(0x20)
    24. 

  24. #define S3C2412_DMA_DMAREQSEL		(0x24)
    25. 

  25. #define S3C2443_DMA_DMAREQSEL		(0x24)
    26. 

  26. 

  27. #define S3C2410_DISRCC_INC		(1<<0)
    28. 

  28. #define S3C2410_DISRCC_APB		(1<<1)
    29. 

  29. 

  30. #define S3C2410_DMASKTRIG_STOP		(1<<2)
    31. 

  31. #define S3C2410_DMASKTRIG_ON		(1<<1)
    32. 

  32. #define S3C2410_DMASKTRIG_SWTRIG	(1<<0)
    33. 

  33. 

  34. #define S3C2410_DCON_DEMAND		(0<<31)
    35. 

  35. #define S3C2410_DCON_HANDSHAKE		(1<<31)
    36. 

  36. #define S3C2410_DCON_SYNC_PCLK		(0<<30)
    37. 

  37. #define S3C2410_DCON_SYNC_HCLK		(1<<30)
    38. 

  38. 

  39. #define S3C2410_DCON_INTREQ		(1<<29)
    40. 

  40. 

  41. #define S3C2410_DCON_CH0_XDREQ0		(0<<24)
    42. 

  42. #define S3C2410_DCON_CH0_UART0		(1<<24)
    43. 

  43. #define S3C2410_DCON_CH0_SDI		(2<<24)
    44. 

  44. #define S3C2410_DCON_CH0_TIMER		(3<<24)
    45. 

  45. #define S3C2410_DCON_CH0_USBEP1		(4<<24)
    46. 

  46. 

  47. #define S3C2410_DCON_CH1_XDREQ1		(0<<24)
    48. 

  48. #define S3C2410_DCON_CH1_UART1		(1<<24)
    49. 

  49. #define S3C2410_DCON_CH1_I2SSDI		(2<<24)
    50. 

  50. #define S3C2410_DCON_CH1_SPI		(3<<24)
    51. 

  51. #define S3C2410_DCON_CH1_USBEP2		(4<<24)
    52. 

  52. 

  53. #define S3C2410_DCON_CH2_I2SSDO		(0<<24)
    54. 

  54. #define S3C2410_DCON_CH2_I2SSDI		(1<<24)
    55. 

  55. #define S3C2410_DCON_CH2_SDI		(2<<24)
    56. 

  56. #define S3C2410_DCON_CH2_TIMER		(3<<24)
    57. 

  57. #define S3C2410_DCON_CH2_USBEP3		(4<<24)
    58. 

  58. 

  59. #define S3C2410_DCON_CH3_UART2		(0<<24)
    60. 

  60. #define S3C2410_DCON_CH3_SDI		(1<<24)
    61. 

  61. #define S3C2410_DCON_CH3_SPI		(2<<24)
    62. 

  62. #define S3C2410_DCON_CH3_TIMER		(3<<24)
    63. 

  63. #define S3C2410_DCON_CH3_USBEP4		(4<<24)
    64. 

  64. 

  65. #define S3C2410_DCON_SRCSHIFT		(24)
    66. 

  66. #define S3C2410_DCON_SRCMASK		(7<<24)
    67. 

  67. 

  68. #define S3C2410_DCON_BYTE		(0<<20)
    69. 

  69. #define S3C2410_DCON_HALFWORD		(1<<20)
    70. 

  70. #define S3C2410_DCON_WORD		(2<<20)
    71. 

  71. 

  72. #define S3C2410_DCON_AUTORELOAD		(0<<22)
    73. 

  73. #define S3C2410_DCON_NORELOAD		(1<<22)
    74. 

  74. #define S3C2410_DCON_HWTRIG		(1<<23)
    75. 

  75. 

  76. #ifdef CONFIG_CPU_S3C2440
    77. 

  77. #define S3C2440_DIDSTC_CHKINT		(1<<2)
    78. 

  78. 

  79. #define S3C2440_DCON_CH0_I2SSDO		(5<<24)
    80. 

  80. #define S3C2440_DCON_CH0_PCMIN		(6<<24)
    81. 

  81. 

  82. #define S3C2440_DCON_CH1_PCMOUT		(5<<24)
    83. 

  83. #define S3C2440_DCON_CH1_SDI		(6<<24)
    84. 

  84. 

  85. #define S3C2440_DCON_CH2_PCMIN		(5<<24)
    86. 

  86. #define S3C2440_DCON_CH2_MICIN		(6<<24)
    87. 

  87. 

  88. #define S3C2440_DCON_CH3_MICIN		(5<<24)
    89. 

  89. #define S3C2440_DCON_CH3_PCMOUT		(6<<24)
    90. 

  90. #endif
    91. 

  91. 

  92. #ifdef CONFIG_CPU_S3C2412
    93. 

  93. 

  94. #define S3C2412_DMAREQSEL_SRC(x)	((x)<<1)
    95. 

  95. 

  96. #define S3C2412_DMAREQSEL_HW		(1)
    97. 

  97. 

  98. #define S3C2412_DMAREQSEL_SPI0TX	S3C2412_DMAREQSEL_SRC(0)
    99. 

  99. #define S3C2412_DMAREQSEL_SPI0RX	S3C2412_DMAREQSEL_SRC(1)
    100. 

  100. #define S3C2412_DMAREQSEL_SPI1TX	S3C2412_DMAREQSEL_SRC(2)
    101. 

  101. #define S3C2412_DMAREQSEL_SPI1RX	S3C2412_DMAREQSEL_SRC(3)
    102. 

  102. #define S3C2412_DMAREQSEL_I2STX		S3C2412_DMAREQSEL_SRC(4)
    103. 

  103. #define S3C2412_DMAREQSEL_I2SRX		S3C2412_DMAREQSEL_SRC(5)
    104. 

  104. #define S3C2412_DMAREQSEL_TIMER		S3C2412_DMAREQSEL_SRC(9)
    105. 

  105. #define S3C2412_DMAREQSEL_SDI		S3C2412_DMAREQSEL_SRC(10)
    106. 

  106. #define S3C2412_DMAREQSEL_USBEP1	S3C2412_DMAREQSEL_SRC(13)
    107. 

  107. #define S3C2412_DMAREQSEL_USBEP2	S3C2412_DMAREQSEL_SRC(14)
    108. 

  108. #define S3C2412_DMAREQSEL_USBEP3	S3C2412_DMAREQSEL_SRC(15)
    109. 

  109. #define S3C2412_DMAREQSEL_USBEP4	S3C2412_DMAREQSEL_SRC(16)
    110. 

  110. #define S3C2412_DMAREQSEL_XDREQ0	S3C2412_DMAREQSEL_SRC(17)
    111. 

  111. #define S3C2412_DMAREQSEL_XDREQ1	S3C2412_DMAREQSEL_SRC(18)
    112. 

  112. #define S3C2412_DMAREQSEL_UART0_0	S3C2412_DMAREQSEL_SRC(19)
    113. 

  113. #define S3C2412_DMAREQSEL_UART0_1	S3C2412_DMAREQSEL_SRC(20)
    114. 

  114. #define S3C2412_DMAREQSEL_UART1_0	S3C2412_DMAREQSEL_SRC(21)
    115. 

  115. #define S3C2412_DMAREQSEL_UART1_1	S3C2412_DMAREQSEL_SRC(22)
    116. 

  116. #define S3C2412_DMAREQSEL_UART2_0	S3C2412_DMAREQSEL_SRC(23)
    117. 

  117. #define S3C2412_DMAREQSEL_UART2_1	S3C2412_DMAREQSEL_SRC(24)
    118. 

  118. 

  119. #endif
    120. 

  120. 

  121. #define S3C2443_DMAREQSEL_SRC(x)	((x)<<1)
    122. 

  122. 

  123. #define S3C2443_DMAREQSEL_HW		(1)
    124. 

  124. 

  125. #define S3C2443_DMAREQSEL_SPI0TX	S3C2443_DMAREQSEL_SRC(0)
    126. 

  126. #define S3C2443_DMAREQSEL_SPI0RX	S3C2443_DMAREQSEL_SRC(1)
    127. 

  127. #define S3C2443_DMAREQSEL_SPI1TX	S3C2443_DMAREQSEL_SRC(2)
    128. 

  128. #define S3C2443_DMAREQSEL_SPI1RX	S3C2443_DMAREQSEL_SRC(3)
    129. 

  129. #define S3C2443_DMAREQSEL_I2STX		S3C2443_DMAREQSEL_SRC(4)
    130. 

  130. #define S3C2443_DMAREQSEL_I2SRX		S3C2443_DMAREQSEL_SRC(5)
    131. 

  131. #define S3C2443_DMAREQSEL_TIMER		S3C2443_DMAREQSEL_SRC(9)
    132. 

  132. #define S3C2443_DMAREQSEL_SDI		S3C2443_DMAREQSEL_SRC(10)
    133. 

  133. #define S3C2443_DMAREQSEL_XDREQ0	S3C2443_DMAREQSEL_SRC(17)
    134. 

  134. #define S3C2443_DMAREQSEL_XDREQ1	S3C2443_DMAREQSEL_SRC(18)
    135. 

  135. #define S3C2443_DMAREQSEL_UART0_0	S3C2443_DMAREQSEL_SRC(19)
    136. 

  136. #define S3C2443_DMAREQSEL_UART0_1	S3C2443_DMAREQSEL_SRC(20)
    137. 

  137. #define S3C2443_DMAREQSEL_UART1_0	S3C2443_DMAREQSEL_SRC(21)
    138. 

  138. #define S3C2443_DMAREQSEL_UART1_1	S3C2443_DMAREQSEL_SRC(22)
    139. 

  139. #define S3C2443_DMAREQSEL_UART2_0	S3C2443_DMAREQSEL_SRC(23)
    140. 

  140. #define S3C2443_DMAREQSEL_UART2_1	S3C2443_DMAREQSEL_SRC(24)
    141. 

  141. #define S3C2443_DMAREQSEL_UART3_0	S3C2443_DMAREQSEL_SRC(25)
    142. 

  142. #define S3C2443_DMAREQSEL_UART3_1	S3C2443_DMAREQSEL_SRC(26)
    143. 

  143. #define S3C2443_DMAREQSEL_PCMOUT	S3C2443_DMAREQSEL_SRC(27)
    144. 

  144. #define S3C2443_DMAREQSEL_PCMIN 	S3C2443_DMAREQSEL_SRC(28)
    145. 

  145. #define S3C2443_DMAREQSEL_MICIN		S3C2443_DMAREQSEL_SRC(29)
    146.