proc-arm740.S 4.3 KB

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  1. /*
  2. * linux/arch/arm/mm/arm740.S: utility functions for ARM740
  3. *
  4. * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/linkage.h>
  12. #include <linux/init.h>
  13. #include <asm/assembler.h>
  14. #include <asm/asm-offsets.h>
  15. #include <asm/hwcap.h>
  16. #include <asm/pgtable-hwdef.h>
  17. #include <asm/pgtable.h>
  18. #include <asm/ptrace.h>
  19. .text
  20. /*
  21. * cpu_arm740_proc_init()
  22. * cpu_arm740_do_idle()
  23. * cpu_arm740_dcache_clean_area()
  24. * cpu_arm740_switch_mm()
  25. *
  26. * These are not required.
  27. */
  28. ENTRY(cpu_arm740_proc_init)
  29. ENTRY(cpu_arm740_do_idle)
  30. ENTRY(cpu_arm740_dcache_clean_area)
  31. ENTRY(cpu_arm740_switch_mm)
  32. mov pc, lr
  33. /*
  34. * cpu_arm740_proc_fin()
  35. */
  36. ENTRY(cpu_arm740_proc_fin)
  37. mrc p15, 0, r0, c1, c0, 0
  38. bic r0, r0, #0x3f000000 @ bank/f/lock/s
  39. bic r0, r0, #0x0000000c @ w-buffer/cache
  40. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  41. mov pc, lr
  42. /*
  43. * cpu_arm740_reset(loc)
  44. * Params : r0 = address to jump to
  45. * Notes : This sets up everything for a reset
  46. */
  47. ENTRY(cpu_arm740_reset)
  48. mov ip, #0
  49. mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
  50. mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
  51. bic ip, ip, #0x0000000c @ ............wc..
  52. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  53. mov pc, r0
  54. __INIT
  55. .type __arm740_setup, #function
  56. __arm740_setup:
  57. mov r0, #0
  58. mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
  59. mcr p15, 0, r0, c6, c3 @ disable area 3~7
  60. mcr p15, 0, r0, c6, c4
  61. mcr p15, 0, r0, c6, c5
  62. mcr p15, 0, r0, c6, c6
  63. mcr p15, 0, r0, c6, c7
  64. mov r0, #0x0000003F @ base = 0, size = 4GB
  65. mcr p15, 0, r0, c6, c0 @ set area 0, default
  66. ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
  67. ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
  68. mov r2, #10 @ 11 is the minimum (4KB)
  69. 1: add r2, r2, #1 @ area size *= 2
  70. mov r1, r1, lsr #1
  71. bne 1b @ count not zero r-shift
  72. orr r0, r0, r2, lsl #1 @ the area register value
  73. orr r0, r0, #1 @ set enable bit
  74. mcr p15, 0, r0, c6, c1 @ set area 1, RAM
  75. ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
  76. ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
  77. mov r2, #10 @ 11 is the minimum (4KB)
  78. 1: add r2, r2, #1 @ area size *= 2
  79. mov r1, r1, lsr #1
  80. bne 1b @ count not zero r-shift
  81. orr r0, r0, r2, lsl #1 @ the area register value
  82. orr r0, r0, #1 @ set enable bit
  83. mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
  84. mov r0, #0x06
  85. mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
  86. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  87. mov r0, #0x00 @ disable whole write buffer
  88. #else
  89. mov r0, #0x02 @ Region 1 write bufferred
  90. #endif
  91. mcr p15, 0, r0, c3, c0
  92. mov r0, #0x10000
  93. sub r0, r0, #1 @ r0 = 0xffff
  94. mcr p15, 0, r0, c5, c0 @ all read/write access
  95. mrc p15, 0, r0, c1, c0 @ get control register
  96. bic r0, r0, #0x3F000000 @ set to standard caching mode
  97. @ need some benchmark
  98. orr r0, r0, #0x0000000d @ MPU/Cache/WB
  99. mov pc, lr
  100. .size __arm740_setup, . - __arm740_setup
  101. __INITDATA
  102. /*
  103. * Purpose : Function pointers used to access above functions - all calls
  104. * come through these
  105. */
  106. .type arm740_processor_functions, #object
  107. ENTRY(arm740_processor_functions)
  108. .word v4t_late_abort
  109. .word legacy_pabort
  110. .word cpu_arm740_proc_init
  111. .word cpu_arm740_proc_fin
  112. .word cpu_arm740_reset
  113. .word cpu_arm740_do_idle
  114. .word cpu_arm740_dcache_clean_area
  115. .word cpu_arm740_switch_mm
  116. .word 0 @ cpu_*_set_pte
  117. .size arm740_processor_functions, . - arm740_processor_functions
  118. .section ".rodata"
  119. .type cpu_arch_name, #object
  120. cpu_arch_name:
  121. .asciz "armv4"
  122. .size cpu_arch_name, . - cpu_arch_name
  123. .type cpu_elf_name, #object
  124. cpu_elf_name:
  125. .asciz "v4"
  126. .size cpu_elf_name, . - cpu_elf_name
  127. .type cpu_arm740_name, #object
  128. cpu_arm740_name:
  129. .ascii "ARM740T"
  130. .size cpu_arm740_name, . - cpu_arm740_name
  131. .align
  132. .section ".proc.info.init", #alloc, #execinstr
  133. .type __arm740_proc_info,#object
  134. __arm740_proc_info:
  135. .long 0x41807400
  136. .long 0xfffffff0
  137. .long 0
  138. b __arm740_setup
  139. .long cpu_arch_name
  140. .long cpu_elf_name
  141. .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
  142. .long cpu_arm740_name
  143. .long arm740_processor_functions
  144. .long 0
  145. .long 0
  146. .long v3_cache_fns @ cache model
  147. .size __arm740_proc_info, . - __arm740_proc_info