cpu.c 2.4 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  5. * License terms: GNU General Public License (GPL) version 2
  6. */
  7. #include <linux/platform_device.h>
  8. #include <linux/amba/bus.h>
  9. #include <linux/io.h>
  10. #include <linux/clk.h>
  11. #include <asm/hardware/cache-l2x0.h>
  12. #include <asm/hardware/gic.h>
  13. #include <asm/mach/map.h>
  14. #include <asm/localtimer.h>
  15. #include <plat/mtu.h>
  16. #include <mach/hardware.h>
  17. #include <mach/setup.h>
  18. #include <mach/devices.h>
  19. #include "clock.h"
  20. static struct map_desc ux500_io_desc[] __initdata = {
  21. __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K),
  22. __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K),
  23. __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K),
  24. __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K),
  25. __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K),
  26. __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K),
  27. __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K),
  28. __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K),
  29. __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K),
  30. __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K),
  31. __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K),
  32. __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K),
  33. __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K),
  34. __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K),
  35. __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
  36. };
  37. static struct amba_device *ux500_amba_devs[] __initdata = {
  38. &ux500_pl031_device,
  39. };
  40. void __init ux500_map_io(void)
  41. {
  42. iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
  43. }
  44. void __init ux500_init_devices(void)
  45. {
  46. amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs));
  47. }
  48. void __init ux500_init_irq(void)
  49. {
  50. gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
  51. gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
  52. /*
  53. * Init clocks here so that they are available for system timer
  54. * initialization.
  55. */
  56. clk_init();
  57. }
  58. #ifdef CONFIG_CACHE_L2X0
  59. static int ux500_l2x0_init(void)
  60. {
  61. void __iomem *l2x0_base;
  62. l2x0_base = __io_address(UX500_L2CC_BASE);
  63. /* 64KB way size, 8 way associativity, force WA */
  64. l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
  65. return 0;
  66. }
  67. early_initcall(ux500_l2x0_init);
  68. #endif
  69. static void __init ux500_timer_init(void)
  70. {
  71. #ifdef CONFIG_LOCAL_TIMERS
  72. /* Setup the local timer base */
  73. twd_base = __io_address(UX500_TWD_BASE);
  74. #endif
  75. /* Setup the MTU base */
  76. if (cpu_is_u8500ed())
  77. mtu_base = __io_address(U8500_MTU0_BASE_ED);
  78. else
  79. mtu_base = __io_address(UX500_MTU0_BASE);
  80. nmdk_timer_init();
  81. }
  82. struct sys_timer ux500_timer = {
  83. .init = ux500_timer_init,
  84. };