dev-spi.c 4.2 KB

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  1. /* linux/arch/arm/mach-s5p6440/dev-spi.c
  2. *
  3. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  4. * Jaswinder Singh <jassi.brar@samsung.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/gpio.h>
  13. #include <mach/dma.h>
  14. #include <mach/map.h>
  15. #include <mach/irqs.h>
  16. #include <mach/spi-clocks.h>
  17. #include <plat/s3c64xx-spi.h>
  18. #include <plat/gpio-cfg.h>
  19. static char *spi_src_clks[] = {
  20. [S5P6440_SPI_SRCCLK_PCLK] = "pclk",
  21. [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
  22. };
  23. /* SPI Controller platform_devices */
  24. /* Since we emulate multi-cs capability, we do not touch the CS.
  25. * The emulated CS is toggled by board specific mechanism, as it can
  26. * be either some immediate GPIO or some signal out of some other
  27. * chip in between ... or some yet another way.
  28. * We simply do not assume anything about CS.
  29. */
  30. static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
  31. {
  32. switch (pdev->id) {
  33. case 0:
  34. s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
  35. s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
  36. s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
  37. s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
  38. s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
  39. s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
  40. break;
  41. case 1:
  42. s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
  43. s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
  44. s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
  45. s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
  46. s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
  47. s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
  48. break;
  49. default:
  50. dev_err(&pdev->dev, "Invalid SPI Controller number!");
  51. return -EINVAL;
  52. }
  53. return 0;
  54. }
  55. static struct resource s5p6440_spi0_resource[] = {
  56. [0] = {
  57. .start = S5P6440_PA_SPI0,
  58. .end = S5P6440_PA_SPI0 + 0x100 - 1,
  59. .flags = IORESOURCE_MEM,
  60. },
  61. [1] = {
  62. .start = DMACH_SPI0_TX,
  63. .end = DMACH_SPI0_TX,
  64. .flags = IORESOURCE_DMA,
  65. },
  66. [2] = {
  67. .start = DMACH_SPI0_RX,
  68. .end = DMACH_SPI0_RX,
  69. .flags = IORESOURCE_DMA,
  70. },
  71. [3] = {
  72. .start = IRQ_SPI0,
  73. .end = IRQ_SPI0,
  74. .flags = IORESOURCE_IRQ,
  75. },
  76. };
  77. static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
  78. .cfg_gpio = s5p6440_spi_cfg_gpio,
  79. .fifo_lvl_mask = 0x1ff,
  80. .rx_lvl_offset = 15,
  81. };
  82. static u64 spi_dmamask = DMA_BIT_MASK(32);
  83. struct platform_device s5p6440_device_spi0 = {
  84. .name = "s3c64xx-spi",
  85. .id = 0,
  86. .num_resources = ARRAY_SIZE(s5p6440_spi0_resource),
  87. .resource = s5p6440_spi0_resource,
  88. .dev = {
  89. .dma_mask = &spi_dmamask,
  90. .coherent_dma_mask = DMA_BIT_MASK(32),
  91. .platform_data = &s5p6440_spi0_pdata,
  92. },
  93. };
  94. static struct resource s5p6440_spi1_resource[] = {
  95. [0] = {
  96. .start = S5P6440_PA_SPI1,
  97. .end = S5P6440_PA_SPI1 + 0x100 - 1,
  98. .flags = IORESOURCE_MEM,
  99. },
  100. [1] = {
  101. .start = DMACH_SPI1_TX,
  102. .end = DMACH_SPI1_TX,
  103. .flags = IORESOURCE_DMA,
  104. },
  105. [2] = {
  106. .start = DMACH_SPI1_RX,
  107. .end = DMACH_SPI1_RX,
  108. .flags = IORESOURCE_DMA,
  109. },
  110. [3] = {
  111. .start = IRQ_SPI1,
  112. .end = IRQ_SPI1,
  113. .flags = IORESOURCE_IRQ,
  114. },
  115. };
  116. static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
  117. .cfg_gpio = s5p6440_spi_cfg_gpio,
  118. .fifo_lvl_mask = 0x7f,
  119. .rx_lvl_offset = 15,
  120. };
  121. struct platform_device s5p6440_device_spi1 = {
  122. .name = "s3c64xx-spi",
  123. .id = 1,
  124. .num_resources = ARRAY_SIZE(s5p6440_spi1_resource),
  125. .resource = s5p6440_spi1_resource,
  126. .dev = {
  127. .dma_mask = &spi_dmamask,
  128. .coherent_dma_mask = DMA_BIT_MASK(32),
  129. .platform_data = &s5p6440_spi1_pdata,
  130. },
  131. };
  132. void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
  133. {
  134. struct s3c64xx_spi_info *pd;
  135. /* Reject invalid configuration */
  136. if (!num_cs || src_clk_nr < 0
  137. || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
  138. printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
  139. return;
  140. }
  141. switch (cntrlr) {
  142. case 0:
  143. pd = &s5p6440_spi0_pdata;
  144. break;
  145. case 1:
  146. pd = &s5p6440_spi1_pdata;
  147. break;
  148. default:
  149. printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
  150. __func__, cntrlr);
  151. return;
  152. }
  153. pd->num_cs = num_cs;
  154. pd->src_clk_nr = src_clk_nr;
  155. pd->src_clk_name = spi_src_clks[src_clk_nr];
  156. }