pm.c 4.4 KB

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  1. /* linux/arch/arm/mach-s3c2410/pm.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/init.h>
  23. #include <linux/suspend.h>
  24. #include <linux/errno.h>
  25. #include <linux/time.h>
  26. #include <linux/sysdev.h>
  27. #include <linux/gpio.h>
  28. #include <linux/io.h>
  29. #include <mach/hardware.h>
  30. #include <asm/mach-types.h>
  31. #include <mach/regs-gpio.h>
  32. #include <mach/h1940.h>
  33. #include <plat/cpu.h>
  34. #include <plat/pm.h>
  35. static void s3c2410_pm_prepare(void)
  36. {
  37. /* ensure at least GSTATUS3 has the resume address */
  38. __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
  39. S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
  40. S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
  41. if (machine_is_h1940()) {
  42. void *base = phys_to_virt(H1940_SUSPEND_CHECK);
  43. unsigned long ptr;
  44. unsigned long calc = 0;
  45. /* generate check for the bootloader to check on resume */
  46. for (ptr = 0; ptr < 0x40000; ptr += 0x400)
  47. calc += __raw_readl(base+ptr);
  48. __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
  49. }
  50. /* RX3715 and RX1950 use similar to H1940 code and the
  51. * same offsets for resume and checksum pointers */
  52. if (machine_is_rx3715() || machine_is_rx1950()) {
  53. void *base = phys_to_virt(H1940_SUSPEND_CHECK);
  54. unsigned long ptr;
  55. unsigned long calc = 0;
  56. /* generate check for the bootloader to check on resume */
  57. for (ptr = 0; ptr < 0x40000; ptr += 0x4)
  58. calc += __raw_readl(base+ptr);
  59. __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
  60. }
  61. if ( machine_is_aml_m5900() )
  62. s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
  63. if (machine_is_rx1950()) {
  64. /* According to S3C2442 user's manual, page 7-17,
  65. * when the system is operating in NAND boot mode,
  66. * the hardware pin configuration - EINT[23:21] –
  67. * must be set as input for starting up after
  68. * wakeup from sleep mode
  69. */
  70. s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
  71. s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
  72. s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
  73. }
  74. }
  75. static int s3c2410_pm_resume(struct sys_device *dev)
  76. {
  77. unsigned long tmp;
  78. /* unset the return-from-sleep flag, to ensure reset */
  79. tmp = __raw_readl(S3C2410_GSTATUS2);
  80. tmp &= S3C2410_GSTATUS2_OFFRESET;
  81. __raw_writel(tmp, S3C2410_GSTATUS2);
  82. if ( machine_is_aml_m5900() )
  83. s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
  84. return 0;
  85. }
  86. static int s3c2410_pm_add(struct sys_device *dev)
  87. {
  88. pm_cpu_prep = s3c2410_pm_prepare;
  89. pm_cpu_sleep = s3c2410_cpu_suspend;
  90. return 0;
  91. }
  92. #if defined(CONFIG_CPU_S3C2410)
  93. static struct sysdev_driver s3c2410_pm_driver = {
  94. .add = s3c2410_pm_add,
  95. .resume = s3c2410_pm_resume,
  96. };
  97. /* register ourselves */
  98. static int __init s3c2410_pm_drvinit(void)
  99. {
  100. return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver);
  101. }
  102. arch_initcall(s3c2410_pm_drvinit);
  103. static struct sysdev_driver s3c2410a_pm_driver = {
  104. .add = s3c2410_pm_add,
  105. .resume = s3c2410_pm_resume,
  106. };
  107. static int __init s3c2410a_pm_drvinit(void)
  108. {
  109. return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver);
  110. }
  111. arch_initcall(s3c2410a_pm_drvinit);
  112. #endif
  113. #if defined(CONFIG_CPU_S3C2440)
  114. static struct sysdev_driver s3c2440_pm_driver = {
  115. .add = s3c2410_pm_add,
  116. .resume = s3c2410_pm_resume,
  117. };
  118. static int __init s3c2440_pm_drvinit(void)
  119. {
  120. return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver);
  121. }
  122. arch_initcall(s3c2440_pm_drvinit);
  123. #endif
  124. #if defined(CONFIG_CPU_S3C2442)
  125. static struct sysdev_driver s3c2442_pm_driver = {
  126. .add = s3c2410_pm_add,
  127. .resume = s3c2410_pm_resume,
  128. };
  129. static int __init s3c2442_pm_drvinit(void)
  130. {
  131. return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver);
  132. }
  133. arch_initcall(s3c2442_pm_drvinit);
  134. #endif