mach-vr1000.c 9.4 KB

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  1. /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
  2. *
  3. * Copyright (c) 2003-2008 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Machine support for Thorcom VR1000 board. Designed for Thorcom by
  7. * Simtec Electronics, http://www.simtec.co.uk/
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/types.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/list.h>
  18. #include <linux/timer.h>
  19. #include <linux/init.h>
  20. #include <linux/gpio.h>
  21. #include <linux/dm9000.h>
  22. #include <linux/i2c.h>
  23. #include <linux/serial.h>
  24. #include <linux/tty.h>
  25. #include <linux/serial_8250.h>
  26. #include <linux/serial_reg.h>
  27. #include <linux/io.h>
  28. #include <asm/mach/arch.h>
  29. #include <asm/mach/map.h>
  30. #include <asm/mach/irq.h>
  31. #include <mach/bast-map.h>
  32. #include <mach/vr1000-map.h>
  33. #include <mach/vr1000-irq.h>
  34. #include <mach/vr1000-cpld.h>
  35. #include <mach/hardware.h>
  36. #include <asm/irq.h>
  37. #include <asm/mach-types.h>
  38. #include <plat/regs-serial.h>
  39. #include <mach/regs-gpio.h>
  40. #include <mach/leds-gpio.h>
  41. #include <plat/clock.h>
  42. #include <plat/devs.h>
  43. #include <plat/cpu.h>
  44. #include <plat/iic.h>
  45. #include <plat/audio-simtec.h>
  46. #include "usb-simtec.h"
  47. #include "nor-simtec.h"
  48. /* macros for virtual address mods for the io space entries */
  49. #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  50. #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  51. #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  52. #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  53. /* macros to modify the physical addresses for io space */
  54. #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  55. #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  56. #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  57. #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  58. static struct map_desc vr1000_iodesc[] __initdata = {
  59. /* ISA IO areas */
  60. {
  61. .virtual = (u32)S3C24XX_VA_ISA_BYTE,
  62. .pfn = PA_CS2(BAST_PA_ISAIO),
  63. .length = SZ_16M,
  64. .type = MT_DEVICE,
  65. }, {
  66. .virtual = (u32)S3C24XX_VA_ISA_WORD,
  67. .pfn = PA_CS3(BAST_PA_ISAIO),
  68. .length = SZ_16M,
  69. .type = MT_DEVICE,
  70. },
  71. /* CPLD control registers, and external interrupt controls */
  72. {
  73. .virtual = (u32)VR1000_VA_CTRL1,
  74. .pfn = __phys_to_pfn(VR1000_PA_CTRL1),
  75. .length = SZ_1M,
  76. .type = MT_DEVICE,
  77. }, {
  78. .virtual = (u32)VR1000_VA_CTRL2,
  79. .pfn = __phys_to_pfn(VR1000_PA_CTRL2),
  80. .length = SZ_1M,
  81. .type = MT_DEVICE,
  82. }, {
  83. .virtual = (u32)VR1000_VA_CTRL3,
  84. .pfn = __phys_to_pfn(VR1000_PA_CTRL3),
  85. .length = SZ_1M,
  86. .type = MT_DEVICE,
  87. }, {
  88. .virtual = (u32)VR1000_VA_CTRL4,
  89. .pfn = __phys_to_pfn(VR1000_PA_CTRL4),
  90. .length = SZ_1M,
  91. .type = MT_DEVICE,
  92. },
  93. };
  94. #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  95. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  96. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  97. /* uart clock source(s) */
  98. static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
  99. [0] = {
  100. .name = "uclk",
  101. .divisor = 1,
  102. .min_baud = 0,
  103. .max_baud = 0,
  104. },
  105. [1] = {
  106. .name = "pclk",
  107. .divisor = 1,
  108. .min_baud = 0,
  109. .max_baud = 0.
  110. }
  111. };
  112. static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
  113. [0] = {
  114. .hwport = 0,
  115. .flags = 0,
  116. .ucon = UCON,
  117. .ulcon = ULCON,
  118. .ufcon = UFCON,
  119. .clocks = vr1000_serial_clocks,
  120. .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
  121. },
  122. [1] = {
  123. .hwport = 1,
  124. .flags = 0,
  125. .ucon = UCON,
  126. .ulcon = ULCON,
  127. .ufcon = UFCON,
  128. .clocks = vr1000_serial_clocks,
  129. .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
  130. },
  131. /* port 2 is not actually used */
  132. [2] = {
  133. .hwport = 2,
  134. .flags = 0,
  135. .ucon = UCON,
  136. .ulcon = ULCON,
  137. .ufcon = UFCON,
  138. .clocks = vr1000_serial_clocks,
  139. .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
  140. }
  141. };
  142. /* definitions for the vr1000 extra 16550 serial ports */
  143. #define VR1000_BAUDBASE (3692307)
  144. #define VR1000_SERIAL_MAPBASE(x) (VR1000_PA_SERIAL + 0x80 + ((x) << 5))
  145. static struct plat_serial8250_port serial_platform_data[] = {
  146. [0] = {
  147. .mapbase = VR1000_SERIAL_MAPBASE(0),
  148. .irq = IRQ_VR1000_SERIAL + 0,
  149. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  150. .iotype = UPIO_MEM,
  151. .regshift = 0,
  152. .uartclk = VR1000_BAUDBASE,
  153. },
  154. [1] = {
  155. .mapbase = VR1000_SERIAL_MAPBASE(1),
  156. .irq = IRQ_VR1000_SERIAL + 1,
  157. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  158. .iotype = UPIO_MEM,
  159. .regshift = 0,
  160. .uartclk = VR1000_BAUDBASE,
  161. },
  162. [2] = {
  163. .mapbase = VR1000_SERIAL_MAPBASE(2),
  164. .irq = IRQ_VR1000_SERIAL + 2,
  165. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  166. .iotype = UPIO_MEM,
  167. .regshift = 0,
  168. .uartclk = VR1000_BAUDBASE,
  169. },
  170. [3] = {
  171. .mapbase = VR1000_SERIAL_MAPBASE(3),
  172. .irq = IRQ_VR1000_SERIAL + 3,
  173. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  174. .iotype = UPIO_MEM,
  175. .regshift = 0,
  176. .uartclk = VR1000_BAUDBASE,
  177. },
  178. { },
  179. };
  180. static struct platform_device serial_device = {
  181. .name = "serial8250",
  182. .id = PLAT8250_DEV_PLATFORM,
  183. .dev = {
  184. .platform_data = serial_platform_data,
  185. },
  186. };
  187. /* DM9000 ethernet devices */
  188. static struct resource vr1000_dm9k0_resource[] = {
  189. [0] = {
  190. .start = S3C2410_CS5 + VR1000_PA_DM9000,
  191. .end = S3C2410_CS5 + VR1000_PA_DM9000 + 3,
  192. .flags = IORESOURCE_MEM
  193. },
  194. [1] = {
  195. .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x40,
  196. .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x7f,
  197. .flags = IORESOURCE_MEM
  198. },
  199. [2] = {
  200. .start = IRQ_VR1000_DM9000A,
  201. .end = IRQ_VR1000_DM9000A,
  202. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  203. }
  204. };
  205. static struct resource vr1000_dm9k1_resource[] = {
  206. [0] = {
  207. .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x80,
  208. .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x83,
  209. .flags = IORESOURCE_MEM
  210. },
  211. [1] = {
  212. .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0,
  213. .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0xFF,
  214. .flags = IORESOURCE_MEM
  215. },
  216. [2] = {
  217. .start = IRQ_VR1000_DM9000N,
  218. .end = IRQ_VR1000_DM9000N,
  219. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  220. }
  221. };
  222. /* for the moment we limit ourselves to 16bit IO until some
  223. * better IO routines can be written and tested
  224. */
  225. static struct dm9000_plat_data vr1000_dm9k_platdata = {
  226. .flags = DM9000_PLATF_16BITONLY,
  227. };
  228. static struct platform_device vr1000_dm9k0 = {
  229. .name = "dm9000",
  230. .id = 0,
  231. .num_resources = ARRAY_SIZE(vr1000_dm9k0_resource),
  232. .resource = vr1000_dm9k0_resource,
  233. .dev = {
  234. .platform_data = &vr1000_dm9k_platdata,
  235. }
  236. };
  237. static struct platform_device vr1000_dm9k1 = {
  238. .name = "dm9000",
  239. .id = 1,
  240. .num_resources = ARRAY_SIZE(vr1000_dm9k1_resource),
  241. .resource = vr1000_dm9k1_resource,
  242. .dev = {
  243. .platform_data = &vr1000_dm9k_platdata,
  244. }
  245. };
  246. /* LEDS */
  247. static struct s3c24xx_led_platdata vr1000_led1_pdata = {
  248. .name = "led1",
  249. .gpio = S3C2410_GPB(0),
  250. .def_trigger = "",
  251. };
  252. static struct s3c24xx_led_platdata vr1000_led2_pdata = {
  253. .name = "led2",
  254. .gpio = S3C2410_GPB(1),
  255. .def_trigger = "",
  256. };
  257. static struct s3c24xx_led_platdata vr1000_led3_pdata = {
  258. .name = "led3",
  259. .gpio = S3C2410_GPB(2),
  260. .def_trigger = "",
  261. };
  262. static struct platform_device vr1000_led1 = {
  263. .name = "s3c24xx_led",
  264. .id = 1,
  265. .dev = {
  266. .platform_data = &vr1000_led1_pdata,
  267. },
  268. };
  269. static struct platform_device vr1000_led2 = {
  270. .name = "s3c24xx_led",
  271. .id = 2,
  272. .dev = {
  273. .platform_data = &vr1000_led2_pdata,
  274. },
  275. };
  276. static struct platform_device vr1000_led3 = {
  277. .name = "s3c24xx_led",
  278. .id = 3,
  279. .dev = {
  280. .platform_data = &vr1000_led3_pdata,
  281. },
  282. };
  283. /* I2C devices. */
  284. static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
  285. {
  286. I2C_BOARD_INFO("tlv320aic23", 0x1a),
  287. }, {
  288. I2C_BOARD_INFO("tmp101", 0x48),
  289. }, {
  290. I2C_BOARD_INFO("m41st87", 0x68),
  291. },
  292. };
  293. /* devices for this board */
  294. static struct platform_device *vr1000_devices[] __initdata = {
  295. &s3c_device_ohci,
  296. &s3c_device_lcd,
  297. &s3c_device_wdt,
  298. &s3c_device_i2c0,
  299. &s3c_device_adc,
  300. &serial_device,
  301. &vr1000_dm9k0,
  302. &vr1000_dm9k1,
  303. &vr1000_led1,
  304. &vr1000_led2,
  305. &vr1000_led3,
  306. };
  307. static struct clk *vr1000_clocks[] __initdata = {
  308. &s3c24xx_dclk0,
  309. &s3c24xx_dclk1,
  310. &s3c24xx_clkout0,
  311. &s3c24xx_clkout1,
  312. &s3c24xx_uclk,
  313. };
  314. static void vr1000_power_off(void)
  315. {
  316. gpio_direction_output(S3C2410_GPB(9), 1);
  317. }
  318. static void __init vr1000_map_io(void)
  319. {
  320. /* initialise clock sources */
  321. s3c24xx_dclk0.parent = &clk_upll;
  322. s3c24xx_dclk0.rate = 12*1000*1000;
  323. s3c24xx_dclk1.parent = NULL;
  324. s3c24xx_dclk1.rate = 3692307;
  325. s3c24xx_clkout0.parent = &s3c24xx_dclk0;
  326. s3c24xx_clkout1.parent = &s3c24xx_dclk1;
  327. s3c24xx_uclk.parent = &s3c24xx_clkout1;
  328. s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks));
  329. pm_power_off = vr1000_power_off;
  330. s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
  331. s3c24xx_init_clocks(0);
  332. s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
  333. }
  334. static void __init vr1000_init(void)
  335. {
  336. s3c_i2c0_set_platdata(NULL);
  337. platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
  338. i2c_register_board_info(0, vr1000_i2c_devs,
  339. ARRAY_SIZE(vr1000_i2c_devs));
  340. nor_simtec_init();
  341. simtec_audio_add(NULL, true, NULL);
  342. WARN_ON(gpio_request(S3C2410_GPB(9), "power off"));
  343. }
  344. MACHINE_START(VR1000, "Thorcom-VR1000")
  345. /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
  346. .phys_io = S3C2410_PA_UART,
  347. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  348. .boot_params = S3C2410_SDRAM_PA + 0x100,
  349. .map_io = vr1000_map_io,
  350. .init_machine = vr1000_init,
  351. .init_irq = s3c24xx_init_irq,
  352. .timer = &s3c24xx_timer,
  353. MACHINE_END