realview_eb.c 14 KB

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  1. /*
  2. * linux/arch/arm/mach-realview/realview_eb.c
  3. *
  4. * Copyright (C) 2004 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/init.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/sysdev.h>
  24. #include <linux/amba/bus.h>
  25. #include <linux/amba/pl061.h>
  26. #include <linux/amba/mmci.h>
  27. #include <linux/amba/pl022.h>
  28. #include <linux/io.h>
  29. #include <mach/hardware.h>
  30. #include <asm/irq.h>
  31. #include <asm/leds.h>
  32. #include <asm/mach-types.h>
  33. #include <asm/pmu.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/hardware/gic.h>
  36. #include <asm/hardware/cache-l2x0.h>
  37. #include <asm/localtimer.h>
  38. #include <asm/mach/arch.h>
  39. #include <asm/mach/map.h>
  40. #include <asm/mach/time.h>
  41. #include <mach/board-eb.h>
  42. #include <mach/irqs.h>
  43. #include "core.h"
  44. static struct map_desc realview_eb_io_desc[] __initdata = {
  45. {
  46. .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
  47. .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
  48. .length = SZ_4K,
  49. .type = MT_DEVICE,
  50. }, {
  51. .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
  52. .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
  53. .length = SZ_4K,
  54. .type = MT_DEVICE,
  55. }, {
  56. .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
  57. .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
  58. .length = SZ_4K,
  59. .type = MT_DEVICE,
  60. }, {
  61. .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
  62. .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
  63. .length = SZ_4K,
  64. .type = MT_DEVICE,
  65. }, {
  66. .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
  67. .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
  68. .length = SZ_4K,
  69. .type = MT_DEVICE,
  70. }, {
  71. .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
  72. .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
  73. .length = SZ_4K,
  74. .type = MT_DEVICE,
  75. },
  76. #ifdef CONFIG_DEBUG_LL
  77. {
  78. .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
  79. .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
  80. .length = SZ_4K,
  81. .type = MT_DEVICE,
  82. }
  83. #endif
  84. };
  85. static struct map_desc realview_eb11mp_io_desc[] __initdata = {
  86. {
  87. .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
  88. .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
  89. .length = SZ_4K,
  90. .type = MT_DEVICE,
  91. }, {
  92. .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
  93. .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
  94. .length = SZ_4K,
  95. .type = MT_DEVICE,
  96. }, {
  97. .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
  98. .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
  99. .length = SZ_8K,
  100. .type = MT_DEVICE,
  101. }
  102. };
  103. static void __init realview_eb_map_io(void)
  104. {
  105. iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
  106. if (core_tile_eb11mp() || core_tile_a9mp())
  107. iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
  108. }
  109. static struct pl061_platform_data gpio0_plat_data = {
  110. .gpio_base = 0,
  111. .irq_base = -1,
  112. };
  113. static struct pl061_platform_data gpio1_plat_data = {
  114. .gpio_base = 8,
  115. .irq_base = -1,
  116. };
  117. static struct pl061_platform_data gpio2_plat_data = {
  118. .gpio_base = 16,
  119. .irq_base = -1,
  120. };
  121. static struct pl022_ssp_controller ssp0_plat_data = {
  122. .bus_id = 0,
  123. .enable_dma = 0,
  124. .num_chipselect = 1,
  125. };
  126. /*
  127. * RealView EB AMBA devices
  128. */
  129. /*
  130. * These devices are connected via the core APB bridge
  131. */
  132. #define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ }
  133. #define GPIO2_DMA { 0, 0 }
  134. #define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ }
  135. #define GPIO3_DMA { 0, 0 }
  136. #define AACI_IRQ { IRQ_EB_AACI, NO_IRQ }
  137. #define AACI_DMA { 0x80, 0x81 }
  138. #define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
  139. #define MMCI0_DMA { 0x84, 0 }
  140. #define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ }
  141. #define KMI0_DMA { 0, 0 }
  142. #define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ }
  143. #define KMI1_DMA { 0, 0 }
  144. /*
  145. * These devices are connected directly to the multi-layer AHB switch
  146. */
  147. #define EB_SMC_IRQ { NO_IRQ, NO_IRQ }
  148. #define EB_SMC_DMA { 0, 0 }
  149. #define MPMC_IRQ { NO_IRQ, NO_IRQ }
  150. #define MPMC_DMA { 0, 0 }
  151. #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
  152. #define EB_CLCD_DMA { 0, 0 }
  153. #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
  154. #define DMAC_DMA { 0, 0 }
  155. /*
  156. * These devices are connected via the core APB bridge
  157. */
  158. #define SCTL_IRQ { NO_IRQ, NO_IRQ }
  159. #define SCTL_DMA { 0, 0 }
  160. #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
  161. #define EB_WATCHDOG_DMA { 0, 0 }
  162. #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
  163. #define EB_GPIO0_DMA { 0, 0 }
  164. #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
  165. #define GPIO1_DMA { 0, 0 }
  166. #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
  167. #define EB_RTC_DMA { 0, 0 }
  168. /*
  169. * These devices are connected via the DMA APB bridge
  170. */
  171. #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
  172. #define SCI_DMA { 7, 6 }
  173. #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
  174. #define EB_UART0_DMA { 15, 14 }
  175. #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
  176. #define EB_UART1_DMA { 13, 12 }
  177. #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
  178. #define EB_UART2_DMA { 11, 10 }
  179. #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
  180. #define EB_UART3_DMA { 0x86, 0x87 }
  181. #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
  182. #define EB_SSP_DMA { 9, 8 }
  183. /* FPGA Primecells */
  184. AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
  185. AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
  186. AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
  187. AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
  188. AMBA_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
  189. /* DevChip Primecells */
  190. AMBA_DEVICE(smc, "dev:smc", EB_SMC, NULL);
  191. AMBA_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data);
  192. AMBA_DEVICE(dmac, "dev:dmac", DMAC, NULL);
  193. AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL);
  194. AMBA_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL);
  195. AMBA_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
  196. AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
  197. AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
  198. AMBA_DEVICE(rtc, "dev:rtc", EB_RTC, NULL);
  199. AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL);
  200. AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
  201. AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
  202. AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
  203. AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data);
  204. static struct amba_device *amba_devs[] __initdata = {
  205. &dmac_device,
  206. &uart0_device,
  207. &uart1_device,
  208. &uart2_device,
  209. &uart3_device,
  210. &smc_device,
  211. &clcd_device,
  212. &sctl_device,
  213. &wdog_device,
  214. &gpio0_device,
  215. &gpio1_device,
  216. &gpio2_device,
  217. &rtc_device,
  218. &sci0_device,
  219. &ssp0_device,
  220. &aaci_device,
  221. &mmc0_device,
  222. &kmi0_device,
  223. &kmi1_device,
  224. };
  225. /*
  226. * RealView EB platform devices
  227. */
  228. static struct resource realview_eb_flash_resource = {
  229. .start = REALVIEW_EB_FLASH_BASE,
  230. .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
  231. .flags = IORESOURCE_MEM,
  232. };
  233. static struct resource realview_eb_eth_resources[] = {
  234. [0] = {
  235. .start = REALVIEW_EB_ETH_BASE,
  236. .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
  237. .flags = IORESOURCE_MEM,
  238. },
  239. [1] = {
  240. .start = IRQ_EB_ETH,
  241. .end = IRQ_EB_ETH,
  242. .flags = IORESOURCE_IRQ,
  243. },
  244. };
  245. /*
  246. * Detect and register the correct Ethernet device. RealView/EB rev D
  247. * platforms use the newer SMSC LAN9118 Ethernet chip
  248. */
  249. static int eth_device_register(void)
  250. {
  251. void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
  252. const char *name = NULL;
  253. u32 idrev;
  254. if (!eth_addr)
  255. return -ENOMEM;
  256. idrev = readl(eth_addr + 0x50);
  257. if ((idrev & 0xFFFF0000) != 0x01180000)
  258. /* SMSC LAN9118 not present, use LAN91C111 instead */
  259. name = "smc91x";
  260. iounmap(eth_addr);
  261. return realview_eth_register(name, realview_eb_eth_resources);
  262. }
  263. static struct resource realview_eb_isp1761_resources[] = {
  264. [0] = {
  265. .start = REALVIEW_EB_USB_BASE,
  266. .end = REALVIEW_EB_USB_BASE + SZ_128K - 1,
  267. .flags = IORESOURCE_MEM,
  268. },
  269. [1] = {
  270. .start = IRQ_EB_USB,
  271. .end = IRQ_EB_USB,
  272. .flags = IORESOURCE_IRQ,
  273. },
  274. };
  275. static struct resource pmu_resources[] = {
  276. [0] = {
  277. .start = IRQ_EB11MP_PMU_CPU0,
  278. .end = IRQ_EB11MP_PMU_CPU0,
  279. .flags = IORESOURCE_IRQ,
  280. },
  281. [1] = {
  282. .start = IRQ_EB11MP_PMU_CPU1,
  283. .end = IRQ_EB11MP_PMU_CPU1,
  284. .flags = IORESOURCE_IRQ,
  285. },
  286. [2] = {
  287. .start = IRQ_EB11MP_PMU_CPU2,
  288. .end = IRQ_EB11MP_PMU_CPU2,
  289. .flags = IORESOURCE_IRQ,
  290. },
  291. [3] = {
  292. .start = IRQ_EB11MP_PMU_CPU3,
  293. .end = IRQ_EB11MP_PMU_CPU3,
  294. .flags = IORESOURCE_IRQ,
  295. },
  296. };
  297. static struct platform_device pmu_device = {
  298. .name = "arm-pmu",
  299. .id = ARM_PMU_DEVICE_CPU,
  300. .num_resources = ARRAY_SIZE(pmu_resources),
  301. .resource = pmu_resources,
  302. };
  303. static struct resource char_lcd_resources[] = {
  304. {
  305. .start = REALVIEW_CHAR_LCD_BASE,
  306. .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
  307. .flags = IORESOURCE_MEM,
  308. },
  309. {
  310. .start = IRQ_EB_CHARLCD,
  311. .end = IRQ_EB_CHARLCD,
  312. .flags = IORESOURCE_IRQ,
  313. },
  314. };
  315. static struct platform_device char_lcd_device = {
  316. .name = "arm-charlcd",
  317. .id = -1,
  318. .num_resources = ARRAY_SIZE(char_lcd_resources),
  319. .resource = char_lcd_resources,
  320. };
  321. static void __init gic_init_irq(void)
  322. {
  323. if (core_tile_eb11mp() || core_tile_a9mp()) {
  324. unsigned int pldctrl;
  325. /* new irq mode */
  326. writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
  327. pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
  328. pldctrl |= 0x00800000;
  329. writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
  330. writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
  331. /* core tile GIC, primary */
  332. gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
  333. gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
  334. gic_cpu_init(0, gic_cpu_base_addr);
  335. #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
  336. /* board GIC, secondary */
  337. gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
  338. gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
  339. gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
  340. #endif
  341. } else {
  342. /* board GIC, primary */
  343. gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
  344. gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
  345. gic_cpu_init(0, gic_cpu_base_addr);
  346. }
  347. }
  348. /*
  349. * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
  350. */
  351. static void realview_eb11mp_fixup(void)
  352. {
  353. /* AMBA devices */
  354. dmac_device.irq[0] = IRQ_EB11MP_DMA;
  355. uart0_device.irq[0] = IRQ_EB11MP_UART0;
  356. uart1_device.irq[0] = IRQ_EB11MP_UART1;
  357. uart2_device.irq[0] = IRQ_EB11MP_UART2;
  358. uart3_device.irq[0] = IRQ_EB11MP_UART3;
  359. clcd_device.irq[0] = IRQ_EB11MP_CLCD;
  360. wdog_device.irq[0] = IRQ_EB11MP_WDOG;
  361. gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
  362. gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
  363. gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
  364. rtc_device.irq[0] = IRQ_EB11MP_RTC;
  365. sci0_device.irq[0] = IRQ_EB11MP_SCI;
  366. ssp0_device.irq[0] = IRQ_EB11MP_SSP;
  367. aaci_device.irq[0] = IRQ_EB11MP_AACI;
  368. mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
  369. mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
  370. kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
  371. kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
  372. /* platform devices */
  373. realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
  374. realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
  375. realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB;
  376. realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB;
  377. }
  378. static void __init realview_eb_timer_init(void)
  379. {
  380. unsigned int timer_irq;
  381. timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
  382. timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
  383. timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
  384. timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
  385. if (core_tile_eb11mp() || core_tile_a9mp()) {
  386. #ifdef CONFIG_LOCAL_TIMERS
  387. twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE);
  388. #endif
  389. timer_irq = IRQ_EB11MP_TIMER0_1;
  390. } else
  391. timer_irq = IRQ_EB_TIMER0_1;
  392. realview_timer_init(timer_irq);
  393. }
  394. static struct sys_timer realview_eb_timer = {
  395. .init = realview_eb_timer_init,
  396. };
  397. static void realview_eb_reset(char mode)
  398. {
  399. void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
  400. void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
  401. /*
  402. * To reset, we hit the on-board reset register
  403. * in the system FPGA
  404. */
  405. __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
  406. if (core_tile_eb11mp())
  407. __raw_writel(0x0008, reset_ctrl);
  408. }
  409. static void __init realview_eb_init(void)
  410. {
  411. int i;
  412. if (core_tile_eb11mp() || core_tile_a9mp()) {
  413. realview_eb11mp_fixup();
  414. #ifdef CONFIG_CACHE_L2X0
  415. /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
  416. * Bits: .... ...0 0111 1001 0000 .... .... .... */
  417. l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
  418. #endif
  419. platform_device_register(&pmu_device);
  420. }
  421. realview_flash_register(&realview_eb_flash_resource, 1);
  422. platform_device_register(&realview_i2c_device);
  423. platform_device_register(&char_lcd_device);
  424. eth_device_register();
  425. realview_usb_register(realview_eb_isp1761_resources);
  426. for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
  427. struct amba_device *d = amba_devs[i];
  428. amba_device_register(d, &iomem_resource);
  429. }
  430. #ifdef CONFIG_LEDS
  431. leds_event = realview_leds_event;
  432. #endif
  433. realview_reset = realview_eb_reset;
  434. }
  435. MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
  436. /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
  437. .phys_io = REALVIEW_EB_UART0_BASE & SECTION_MASK,
  438. .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
  439. .boot_params = PHYS_OFFSET + 0x00000100,
  440. .fixup = realview_fixup,
  441. .map_io = realview_eb_map_io,
  442. .init_irq = gic_init_irq,
  443. .timer = &realview_eb_timer,
  444. .init_machine = realview_eb_init,
  445. MACHINE_END