pm-debug.c 14 KB

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  1. /*
  2. * OMAP Power Management debug routines
  3. *
  4. * Copyright (C) 2005 Texas Instruments, Inc.
  5. * Copyright (C) 2006-2008 Nokia Corporation
  6. *
  7. * Written by:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Tony Lindgren
  10. * Juha Yrjola
  11. * Amit Kucheria <amit.kucheria@nokia.com>
  12. * Igor Stoppa <igor.stoppa@nokia.com>
  13. * Jouni Hogander
  14. *
  15. * Based on pm.c for omap2
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License version 2 as
  19. * published by the Free Software Foundation.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/sched.h>
  23. #include <linux/clk.h>
  24. #include <linux/err.h>
  25. #include <linux/io.h>
  26. #include <linux/module.h>
  27. #include <linux/slab.h>
  28. #include <plat/clock.h>
  29. #include <plat/board.h>
  30. #include <plat/powerdomain.h>
  31. #include <plat/clockdomain.h>
  32. #include "prm.h"
  33. #include "cm.h"
  34. #include "pm.h"
  35. int omap2_pm_debug;
  36. #define DUMP_PRM_MOD_REG(mod, reg) \
  37. regs[reg_count].name = #mod "." #reg; \
  38. regs[reg_count++].val = prm_read_mod_reg(mod, reg)
  39. #define DUMP_CM_MOD_REG(mod, reg) \
  40. regs[reg_count].name = #mod "." #reg; \
  41. regs[reg_count++].val = cm_read_mod_reg(mod, reg)
  42. #define DUMP_PRM_REG(reg) \
  43. regs[reg_count].name = #reg; \
  44. regs[reg_count++].val = __raw_readl(reg)
  45. #define DUMP_CM_REG(reg) \
  46. regs[reg_count].name = #reg; \
  47. regs[reg_count++].val = __raw_readl(reg)
  48. #define DUMP_INTC_REG(reg, off) \
  49. regs[reg_count].name = #reg; \
  50. regs[reg_count++].val = \
  51. __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
  52. void omap2_pm_dump(int mode, int resume, unsigned int us)
  53. {
  54. struct reg {
  55. const char *name;
  56. u32 val;
  57. } regs[32];
  58. int reg_count = 0, i;
  59. const char *s1 = NULL, *s2 = NULL;
  60. if (!resume) {
  61. #if 0
  62. /* MPU */
  63. DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
  64. DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
  65. DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
  66. DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
  67. DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
  68. #endif
  69. #if 0
  70. /* INTC */
  71. DUMP_INTC_REG(INTC_MIR0, 0x0084);
  72. DUMP_INTC_REG(INTC_MIR1, 0x00a4);
  73. DUMP_INTC_REG(INTC_MIR2, 0x00c4);
  74. #endif
  75. #if 0
  76. DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
  77. if (cpu_is_omap24xx()) {
  78. DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  79. DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  80. OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
  81. DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  82. OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
  83. }
  84. DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
  85. DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
  86. DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
  87. DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
  88. DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
  89. DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
  90. DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
  91. #endif
  92. #if 0
  93. /* DSP */
  94. if (cpu_is_omap24xx()) {
  95. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
  96. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
  97. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
  98. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
  99. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
  100. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
  101. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
  102. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
  103. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
  104. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
  105. }
  106. #endif
  107. } else {
  108. DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
  109. if (cpu_is_omap24xx())
  110. DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
  111. DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
  112. DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
  113. #if 1
  114. DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
  115. DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
  116. DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
  117. #endif
  118. }
  119. switch (mode) {
  120. case 0:
  121. s1 = "full";
  122. s2 = "retention";
  123. break;
  124. case 1:
  125. s1 = "MPU";
  126. s2 = "retention";
  127. break;
  128. case 2:
  129. s1 = "MPU";
  130. s2 = "idle";
  131. break;
  132. }
  133. if (!resume)
  134. #ifdef CONFIG_NO_HZ
  135. printk(KERN_INFO
  136. "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
  137. jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
  138. jiffies));
  139. #else
  140. printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
  141. #endif
  142. else
  143. printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
  144. us / 1000, us % 1000);
  145. for (i = 0; i < reg_count; i++)
  146. printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
  147. }
  148. #ifdef CONFIG_DEBUG_FS
  149. #include <linux/debugfs.h>
  150. #include <linux/seq_file.h>
  151. static void pm_dbg_regset_store(u32 *ptr);
  152. struct dentry *pm_dbg_dir;
  153. static int pm_dbg_init_done;
  154. static int __init pm_dbg_init(void);
  155. enum {
  156. DEBUG_FILE_COUNTERS = 0,
  157. DEBUG_FILE_TIMERS,
  158. };
  159. struct pm_module_def {
  160. char name[8]; /* Name of the module */
  161. short type; /* CM or PRM */
  162. unsigned short offset;
  163. int low; /* First register address on this module */
  164. int high; /* Last register address on this module */
  165. };
  166. #define MOD_CM 0
  167. #define MOD_PRM 1
  168. static const struct pm_module_def *pm_dbg_reg_modules;
  169. static const struct pm_module_def omap3_pm_reg_modules[] = {
  170. { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
  171. { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
  172. { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
  173. { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
  174. { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
  175. { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
  176. { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
  177. { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
  178. { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
  179. { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
  180. { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
  181. { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
  182. { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
  183. { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
  184. { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
  185. { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
  186. { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
  187. { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
  188. { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
  189. { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
  190. { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
  191. { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
  192. { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
  193. { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
  194. { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
  195. { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
  196. { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
  197. { "", 0, 0, 0, 0 },
  198. };
  199. #define PM_DBG_MAX_REG_SETS 4
  200. static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
  201. static int pm_dbg_get_regset_size(void)
  202. {
  203. static int regset_size;
  204. if (regset_size == 0) {
  205. int i = 0;
  206. while (pm_dbg_reg_modules[i].name[0] != 0) {
  207. regset_size += pm_dbg_reg_modules[i].high +
  208. 4 - pm_dbg_reg_modules[i].low;
  209. i++;
  210. }
  211. }
  212. return regset_size;
  213. }
  214. static int pm_dbg_show_regs(struct seq_file *s, void *unused)
  215. {
  216. int i, j;
  217. unsigned long val;
  218. int reg_set = (int)s->private;
  219. u32 *ptr;
  220. void *store = NULL;
  221. int regs;
  222. int linefeed;
  223. if (reg_set == 0) {
  224. store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
  225. ptr = store;
  226. pm_dbg_regset_store(ptr);
  227. } else {
  228. ptr = pm_dbg_reg_set[reg_set - 1];
  229. }
  230. i = 0;
  231. while (pm_dbg_reg_modules[i].name[0] != 0) {
  232. regs = 0;
  233. linefeed = 0;
  234. if (pm_dbg_reg_modules[i].type == MOD_CM)
  235. seq_printf(s, "MOD: CM_%s (%08x)\n",
  236. pm_dbg_reg_modules[i].name,
  237. (u32)(OMAP3430_CM_BASE +
  238. pm_dbg_reg_modules[i].offset));
  239. else
  240. seq_printf(s, "MOD: PRM_%s (%08x)\n",
  241. pm_dbg_reg_modules[i].name,
  242. (u32)(OMAP3430_PRM_BASE +
  243. pm_dbg_reg_modules[i].offset));
  244. for (j = pm_dbg_reg_modules[i].low;
  245. j <= pm_dbg_reg_modules[i].high; j += 4) {
  246. val = *(ptr++);
  247. if (val != 0) {
  248. regs++;
  249. if (linefeed) {
  250. seq_printf(s, "\n");
  251. linefeed = 0;
  252. }
  253. seq_printf(s, " %02x => %08lx", j, val);
  254. if (regs % 4 == 0)
  255. linefeed = 1;
  256. }
  257. }
  258. seq_printf(s, "\n");
  259. i++;
  260. }
  261. if (store != NULL)
  262. kfree(store);
  263. return 0;
  264. }
  265. static void pm_dbg_regset_store(u32 *ptr)
  266. {
  267. int i, j;
  268. u32 val;
  269. i = 0;
  270. while (pm_dbg_reg_modules[i].name[0] != 0) {
  271. for (j = pm_dbg_reg_modules[i].low;
  272. j <= pm_dbg_reg_modules[i].high; j += 4) {
  273. if (pm_dbg_reg_modules[i].type == MOD_CM)
  274. val = cm_read_mod_reg(
  275. pm_dbg_reg_modules[i].offset, j);
  276. else
  277. val = prm_read_mod_reg(
  278. pm_dbg_reg_modules[i].offset, j);
  279. *(ptr++) = val;
  280. }
  281. i++;
  282. }
  283. }
  284. int pm_dbg_regset_save(int reg_set)
  285. {
  286. if (pm_dbg_reg_set[reg_set-1] == NULL)
  287. return -EINVAL;
  288. pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
  289. return 0;
  290. }
  291. static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
  292. "OFF",
  293. "RET",
  294. "INA",
  295. "ON"
  296. };
  297. void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
  298. {
  299. s64 t;
  300. if (!pm_dbg_init_done)
  301. return ;
  302. /* Update timer for previous state */
  303. t = sched_clock();
  304. pwrdm->state_timer[prev] += t - pwrdm->timer;
  305. pwrdm->timer = t;
  306. }
  307. static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
  308. {
  309. struct seq_file *s = (struct seq_file *)user;
  310. if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
  311. strcmp(clkdm->name, "wkup_clkdm") == 0 ||
  312. strncmp(clkdm->name, "dpll", 4) == 0)
  313. return 0;
  314. seq_printf(s, "%s->%s (%d)", clkdm->name,
  315. clkdm->pwrdm.ptr->name,
  316. atomic_read(&clkdm->usecount));
  317. seq_printf(s, "\n");
  318. return 0;
  319. }
  320. static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
  321. {
  322. struct seq_file *s = (struct seq_file *)user;
  323. int i;
  324. if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
  325. strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
  326. strncmp(pwrdm->name, "dpll", 4) == 0)
  327. return 0;
  328. if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
  329. printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
  330. pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
  331. seq_printf(s, "%s (%s)", pwrdm->name,
  332. pwrdm_state_names[pwrdm->state]);
  333. for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
  334. seq_printf(s, ",%s:%d", pwrdm_state_names[i],
  335. pwrdm->state_counter[i]);
  336. seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter);
  337. for (i = 0; i < pwrdm->banks; i++)
  338. seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1,
  339. pwrdm->ret_mem_off_counter[i]);
  340. seq_printf(s, "\n");
  341. return 0;
  342. }
  343. static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
  344. {
  345. struct seq_file *s = (struct seq_file *)user;
  346. int i;
  347. if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
  348. strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
  349. strncmp(pwrdm->name, "dpll", 4) == 0)
  350. return 0;
  351. pwrdm_state_switch(pwrdm);
  352. seq_printf(s, "%s (%s)", pwrdm->name,
  353. pwrdm_state_names[pwrdm->state]);
  354. for (i = 0; i < 4; i++)
  355. seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
  356. pwrdm->state_timer[i]);
  357. seq_printf(s, "\n");
  358. return 0;
  359. }
  360. static int pm_dbg_show_counters(struct seq_file *s, void *unused)
  361. {
  362. pwrdm_for_each(pwrdm_dbg_show_counter, s);
  363. clkdm_for_each(clkdm_dbg_show_counter, s);
  364. return 0;
  365. }
  366. static int pm_dbg_show_timers(struct seq_file *s, void *unused)
  367. {
  368. pwrdm_for_each(pwrdm_dbg_show_timer, s);
  369. return 0;
  370. }
  371. static int pm_dbg_open(struct inode *inode, struct file *file)
  372. {
  373. switch ((int)inode->i_private) {
  374. case DEBUG_FILE_COUNTERS:
  375. return single_open(file, pm_dbg_show_counters,
  376. &inode->i_private);
  377. case DEBUG_FILE_TIMERS:
  378. default:
  379. return single_open(file, pm_dbg_show_timers,
  380. &inode->i_private);
  381. };
  382. }
  383. static int pm_dbg_reg_open(struct inode *inode, struct file *file)
  384. {
  385. return single_open(file, pm_dbg_show_regs, inode->i_private);
  386. }
  387. static const struct file_operations debug_fops = {
  388. .open = pm_dbg_open,
  389. .read = seq_read,
  390. .llseek = seq_lseek,
  391. .release = single_release,
  392. };
  393. static const struct file_operations debug_reg_fops = {
  394. .open = pm_dbg_reg_open,
  395. .read = seq_read,
  396. .llseek = seq_lseek,
  397. .release = single_release,
  398. };
  399. int pm_dbg_regset_init(int reg_set)
  400. {
  401. char name[2];
  402. if (!pm_dbg_init_done)
  403. pm_dbg_init();
  404. if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
  405. pm_dbg_reg_set[reg_set-1] != NULL)
  406. return -EINVAL;
  407. pm_dbg_reg_set[reg_set-1] =
  408. kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
  409. if (pm_dbg_reg_set[reg_set-1] == NULL)
  410. return -ENOMEM;
  411. if (pm_dbg_dir != NULL) {
  412. sprintf(name, "%d", reg_set);
  413. (void) debugfs_create_file(name, S_IRUGO,
  414. pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
  415. }
  416. return 0;
  417. }
  418. static int pwrdm_suspend_get(void *data, u64 *val)
  419. {
  420. int ret;
  421. ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
  422. *val = ret;
  423. if (ret >= 0)
  424. return 0;
  425. return *val;
  426. }
  427. static int pwrdm_suspend_set(void *data, u64 val)
  428. {
  429. return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
  430. }
  431. DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
  432. pwrdm_suspend_set, "%llu\n");
  433. static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
  434. {
  435. int i;
  436. s64 t;
  437. struct dentry *d;
  438. t = sched_clock();
  439. for (i = 0; i < 4; i++)
  440. pwrdm->state_timer[i] = 0;
  441. pwrdm->timer = t;
  442. if (strncmp(pwrdm->name, "dpll", 4) == 0)
  443. return 0;
  444. d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
  445. (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
  446. (void *)pwrdm, &pwrdm_suspend_fops);
  447. return 0;
  448. }
  449. static int option_get(void *data, u64 *val)
  450. {
  451. u32 *option = data;
  452. *val = *option;
  453. return 0;
  454. }
  455. static int option_set(void *data, u64 val)
  456. {
  457. u32 *option = data;
  458. if (option == &wakeup_timer_milliseconds && val >= 1000)
  459. return -EINVAL;
  460. *option = val;
  461. if (option == &enable_off_mode)
  462. omap3_pm_off_mode_enable(val);
  463. return 0;
  464. }
  465. DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
  466. static int __init pm_dbg_init(void)
  467. {
  468. int i;
  469. struct dentry *d;
  470. char name[2];
  471. if (pm_dbg_init_done)
  472. return 0;
  473. if (cpu_is_omap34xx())
  474. pm_dbg_reg_modules = omap3_pm_reg_modules;
  475. else {
  476. printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
  477. return -ENODEV;
  478. }
  479. d = debugfs_create_dir("pm_debug", NULL);
  480. if (IS_ERR(d))
  481. return PTR_ERR(d);
  482. (void) debugfs_create_file("count", S_IRUGO,
  483. d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
  484. (void) debugfs_create_file("time", S_IRUGO,
  485. d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
  486. pwrdm_for_each(pwrdms_setup, (void *)d);
  487. pm_dbg_dir = debugfs_create_dir("registers", d);
  488. if (IS_ERR(pm_dbg_dir))
  489. return PTR_ERR(pm_dbg_dir);
  490. (void) debugfs_create_file("current", S_IRUGO,
  491. pm_dbg_dir, (void *)0, &debug_reg_fops);
  492. for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
  493. if (pm_dbg_reg_set[i] != NULL) {
  494. sprintf(name, "%d", i+1);
  495. (void) debugfs_create_file(name, S_IRUGO,
  496. pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
  497. }
  498. (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
  499. &enable_off_mode, &pm_dbg_option_fops);
  500. (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
  501. &sleep_while_idle, &pm_dbg_option_fops);
  502. (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
  503. &wakeup_timer_seconds, &pm_dbg_option_fops);
  504. pm_dbg_init_done = 1;
  505. return 0;
  506. }
  507. arch_initcall(pm_dbg_init);
  508. #endif