dpll3xxx.c 15 KB

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  1. /*
  2. * OMAP3/4 - specific DPLL control functions
  3. *
  4. * Copyright (C) 2009-2010 Texas Instruments, Inc.
  5. * Copyright (C) 2009-2010 Nokia Corporation
  6. *
  7. * Written by Paul Walmsley
  8. * Testing and integration fixes by Jouni Högander
  9. *
  10. * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
  11. * Menon
  12. *
  13. * Parts of this code are based on code written by
  14. * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/device.h>
  22. #include <linux/list.h>
  23. #include <linux/errno.h>
  24. #include <linux/delay.h>
  25. #include <linux/clk.h>
  26. #include <linux/io.h>
  27. #include <linux/bitops.h>
  28. #include <plat/cpu.h>
  29. #include <plat/clock.h>
  30. #include <asm/clkdev.h>
  31. #include "clock.h"
  32. #include "prm.h"
  33. #include "prm-regbits-34xx.h"
  34. #include "cm.h"
  35. #include "cm-regbits-34xx.h"
  36. /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
  37. #define DPLL_AUTOIDLE_DISABLE 0x0
  38. #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
  39. #define MAX_DPLL_WAIT_TRIES 1000000
  40. /* Private functions */
  41. /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
  42. static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
  43. {
  44. const struct dpll_data *dd;
  45. u32 v;
  46. dd = clk->dpll_data;
  47. v = __raw_readl(dd->control_reg);
  48. v &= ~dd->enable_mask;
  49. v |= clken_bits << __ffs(dd->enable_mask);
  50. __raw_writel(v, dd->control_reg);
  51. }
  52. /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
  53. static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
  54. {
  55. const struct dpll_data *dd;
  56. int i = 0;
  57. int ret = -EINVAL;
  58. dd = clk->dpll_data;
  59. state <<= __ffs(dd->idlest_mask);
  60. while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
  61. i < MAX_DPLL_WAIT_TRIES) {
  62. i++;
  63. udelay(1);
  64. }
  65. if (i == MAX_DPLL_WAIT_TRIES) {
  66. printk(KERN_ERR "clock: %s failed transition to '%s'\n",
  67. clk->name, (state) ? "locked" : "bypassed");
  68. } else {
  69. pr_debug("clock: %s transition to '%s' in %d loops\n",
  70. clk->name, (state) ? "locked" : "bypassed", i);
  71. ret = 0;
  72. }
  73. return ret;
  74. }
  75. /* From 3430 TRM ES2 4.7.6.2 */
  76. static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
  77. {
  78. unsigned long fint;
  79. u16 f = 0;
  80. fint = clk->dpll_data->clk_ref->rate / n;
  81. pr_debug("clock: fint is %lu\n", fint);
  82. if (fint >= 750000 && fint <= 1000000)
  83. f = 0x3;
  84. else if (fint > 1000000 && fint <= 1250000)
  85. f = 0x4;
  86. else if (fint > 1250000 && fint <= 1500000)
  87. f = 0x5;
  88. else if (fint > 1500000 && fint <= 1750000)
  89. f = 0x6;
  90. else if (fint > 1750000 && fint <= 2100000)
  91. f = 0x7;
  92. else if (fint > 7500000 && fint <= 10000000)
  93. f = 0xB;
  94. else if (fint > 10000000 && fint <= 12500000)
  95. f = 0xC;
  96. else if (fint > 12500000 && fint <= 15000000)
  97. f = 0xD;
  98. else if (fint > 15000000 && fint <= 17500000)
  99. f = 0xE;
  100. else if (fint > 17500000 && fint <= 21000000)
  101. f = 0xF;
  102. else
  103. pr_debug("clock: unknown freqsel setting for %d\n", n);
  104. return f;
  105. }
  106. /*
  107. * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
  108. * @clk: pointer to a DPLL struct clk
  109. *
  110. * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
  111. * readiness before returning. Will save and restore the DPLL's
  112. * autoidle state across the enable, per the CDP code. If the DPLL
  113. * locked successfully, return 0; if the DPLL did not lock in the time
  114. * allotted, or DPLL3 was passed in, return -EINVAL.
  115. */
  116. static int _omap3_noncore_dpll_lock(struct clk *clk)
  117. {
  118. u8 ai;
  119. int r;
  120. pr_debug("clock: locking DPLL %s\n", clk->name);
  121. ai = omap3_dpll_autoidle_read(clk);
  122. omap3_dpll_deny_idle(clk);
  123. _omap3_dpll_write_clken(clk, DPLL_LOCKED);
  124. r = _omap3_wait_dpll_status(clk, 1);
  125. if (ai)
  126. omap3_dpll_allow_idle(clk);
  127. return r;
  128. }
  129. /*
  130. * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
  131. * @clk: pointer to a DPLL struct clk
  132. *
  133. * Instructs a non-CORE DPLL to enter low-power bypass mode. In
  134. * bypass mode, the DPLL's rate is set equal to its parent clock's
  135. * rate. Waits for the DPLL to report readiness before returning.
  136. * Will save and restore the DPLL's autoidle state across the enable,
  137. * per the CDP code. If the DPLL entered bypass mode successfully,
  138. * return 0; if the DPLL did not enter bypass in the time allotted, or
  139. * DPLL3 was passed in, or the DPLL does not support low-power bypass,
  140. * return -EINVAL.
  141. */
  142. static int _omap3_noncore_dpll_bypass(struct clk *clk)
  143. {
  144. int r;
  145. u8 ai;
  146. if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
  147. return -EINVAL;
  148. pr_debug("clock: configuring DPLL %s for low-power bypass\n",
  149. clk->name);
  150. ai = omap3_dpll_autoidle_read(clk);
  151. _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
  152. r = _omap3_wait_dpll_status(clk, 0);
  153. if (ai)
  154. omap3_dpll_allow_idle(clk);
  155. else
  156. omap3_dpll_deny_idle(clk);
  157. return r;
  158. }
  159. /*
  160. * _omap3_noncore_dpll_stop - instruct a DPLL to stop
  161. * @clk: pointer to a DPLL struct clk
  162. *
  163. * Instructs a non-CORE DPLL to enter low-power stop. Will save and
  164. * restore the DPLL's autoidle state across the stop, per the CDP
  165. * code. If DPLL3 was passed in, or the DPLL does not support
  166. * low-power stop, return -EINVAL; otherwise, return 0.
  167. */
  168. static int _omap3_noncore_dpll_stop(struct clk *clk)
  169. {
  170. u8 ai;
  171. if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
  172. return -EINVAL;
  173. pr_debug("clock: stopping DPLL %s\n", clk->name);
  174. ai = omap3_dpll_autoidle_read(clk);
  175. _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
  176. if (ai)
  177. omap3_dpll_allow_idle(clk);
  178. else
  179. omap3_dpll_deny_idle(clk);
  180. return 0;
  181. }
  182. /**
  183. * lookup_dco_sddiv - Set j-type DPLL4 compensation variables
  184. * @clk: pointer to a DPLL struct clk
  185. * @dco: digital control oscillator selector
  186. * @sd_div: target sigma-delta divider
  187. * @m: DPLL multiplier to set
  188. * @n: DPLL divider to set
  189. *
  190. * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
  191. *
  192. * XXX This code is not needed for 3430/AM35xx; can it be optimized
  193. * out in non-multi-OMAP builds for those chips?
  194. */
  195. static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m,
  196. u8 n)
  197. {
  198. unsigned long fint, clkinp, sd; /* watch out for overflow */
  199. int mod1, mod2;
  200. clkinp = clk->parent->rate;
  201. fint = (clkinp / n) * m;
  202. if (fint < 1000000000)
  203. *dco = 2;
  204. else
  205. *dco = 4;
  206. /*
  207. * target sigma-delta to near 250MHz
  208. * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
  209. */
  210. clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
  211. mod1 = (clkinp * m) % (250 * n);
  212. sd = (clkinp * m) / (250 * n);
  213. mod2 = sd % 10;
  214. sd /= 10;
  215. if (mod1 || mod2)
  216. sd++;
  217. *sd_div = sd;
  218. }
  219. /*
  220. * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
  221. * @clk: struct clk * of DPLL to set
  222. * @m: DPLL multiplier to set
  223. * @n: DPLL divider to set
  224. * @freqsel: FREQSEL value to set
  225. *
  226. * Program the DPLL with the supplied M, N values, and wait for the DPLL to
  227. * lock.. Returns -EINVAL upon error, or 0 upon success.
  228. */
  229. static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
  230. {
  231. struct dpll_data *dd = clk->dpll_data;
  232. u32 v;
  233. /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
  234. _omap3_noncore_dpll_bypass(clk);
  235. /*
  236. * Set jitter correction. No jitter correction for OMAP4 and 3630
  237. * since freqsel field is no longer present
  238. */
  239. if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
  240. v = __raw_readl(dd->control_reg);
  241. v &= ~dd->freqsel_mask;
  242. v |= freqsel << __ffs(dd->freqsel_mask);
  243. __raw_writel(v, dd->control_reg);
  244. }
  245. /* Set DPLL multiplier, divider */
  246. v = __raw_readl(dd->mult_div1_reg);
  247. v &= ~(dd->mult_mask | dd->div1_mask);
  248. v |= m << __ffs(dd->mult_mask);
  249. v |= (n - 1) << __ffs(dd->div1_mask);
  250. /*
  251. * XXX This code is not needed for 3430/AM35XX; can it be optimized
  252. * out in non-multi-OMAP builds for those chips?
  253. */
  254. if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) {
  255. u8 dco, sd_div;
  256. lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
  257. /* XXX This probably will need revision for OMAP4 */
  258. v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
  259. | OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
  260. v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK);
  261. v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
  262. }
  263. __raw_writel(v, dd->mult_div1_reg);
  264. /* We let the clock framework set the other output dividers later */
  265. /* REVISIT: Set ramp-up delay? */
  266. _omap3_noncore_dpll_lock(clk);
  267. return 0;
  268. }
  269. /* Public functions */
  270. /**
  271. * omap3_dpll_recalc - recalculate DPLL rate
  272. * @clk: DPLL struct clk
  273. *
  274. * Recalculate and propagate the DPLL rate.
  275. */
  276. unsigned long omap3_dpll_recalc(struct clk *clk)
  277. {
  278. return omap2_get_dpll_rate(clk);
  279. }
  280. /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
  281. /**
  282. * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
  283. * @clk: pointer to a DPLL struct clk
  284. *
  285. * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
  286. * The choice of modes depends on the DPLL's programmed rate: if it is
  287. * the same as the DPLL's parent clock, it will enter bypass;
  288. * otherwise, it will enter lock. This code will wait for the DPLL to
  289. * indicate readiness before returning, unless the DPLL takes too long
  290. * to enter the target state. Intended to be used as the struct clk's
  291. * enable function. If DPLL3 was passed in, or the DPLL does not
  292. * support low-power stop, or if the DPLL took too long to enter
  293. * bypass or lock, return -EINVAL; otherwise, return 0.
  294. */
  295. int omap3_noncore_dpll_enable(struct clk *clk)
  296. {
  297. int r;
  298. struct dpll_data *dd;
  299. dd = clk->dpll_data;
  300. if (!dd)
  301. return -EINVAL;
  302. if (clk->rate == dd->clk_bypass->rate) {
  303. WARN_ON(clk->parent != dd->clk_bypass);
  304. r = _omap3_noncore_dpll_bypass(clk);
  305. } else {
  306. WARN_ON(clk->parent != dd->clk_ref);
  307. r = _omap3_noncore_dpll_lock(clk);
  308. }
  309. /*
  310. *FIXME: this is dubious - if clk->rate has changed, what about
  311. * propagating?
  312. */
  313. if (!r)
  314. clk->rate = omap2_get_dpll_rate(clk);
  315. return r;
  316. }
  317. /**
  318. * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
  319. * @clk: pointer to a DPLL struct clk
  320. *
  321. * Instructs a non-CORE DPLL to enter low-power stop. This function is
  322. * intended for use in struct clkops. No return value.
  323. */
  324. void omap3_noncore_dpll_disable(struct clk *clk)
  325. {
  326. _omap3_noncore_dpll_stop(clk);
  327. }
  328. /* Non-CORE DPLL rate set code */
  329. /**
  330. * omap3_noncore_dpll_set_rate - set non-core DPLL rate
  331. * @clk: struct clk * of DPLL to set
  332. * @rate: rounded target rate
  333. *
  334. * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
  335. * low-power bypass, and the target rate is the bypass source clock
  336. * rate, then configure the DPLL for bypass. Otherwise, round the
  337. * target rate if it hasn't been done already, then program and lock
  338. * the DPLL. Returns -EINVAL upon error, or 0 upon success.
  339. */
  340. int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
  341. {
  342. struct clk *new_parent = NULL;
  343. u16 freqsel = 0;
  344. struct dpll_data *dd;
  345. int ret;
  346. if (!clk || !rate)
  347. return -EINVAL;
  348. dd = clk->dpll_data;
  349. if (!dd)
  350. return -EINVAL;
  351. if (rate == omap2_get_dpll_rate(clk))
  352. return 0;
  353. /*
  354. * Ensure both the bypass and ref clocks are enabled prior to
  355. * doing anything; we need the bypass clock running to reprogram
  356. * the DPLL.
  357. */
  358. omap2_clk_enable(dd->clk_bypass);
  359. omap2_clk_enable(dd->clk_ref);
  360. if (dd->clk_bypass->rate == rate &&
  361. (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
  362. pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
  363. ret = _omap3_noncore_dpll_bypass(clk);
  364. if (!ret)
  365. new_parent = dd->clk_bypass;
  366. } else {
  367. if (dd->last_rounded_rate != rate)
  368. omap2_dpll_round_rate(clk, rate);
  369. if (dd->last_rounded_rate == 0)
  370. return -EINVAL;
  371. /* No freqsel on OMAP4 and OMAP3630 */
  372. if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
  373. freqsel = _omap3_dpll_compute_freqsel(clk,
  374. dd->last_rounded_n);
  375. if (!freqsel)
  376. WARN_ON(1);
  377. }
  378. pr_debug("clock: %s: set rate: locking rate to %lu.\n",
  379. clk->name, rate);
  380. ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
  381. dd->last_rounded_n, freqsel);
  382. if (!ret)
  383. new_parent = dd->clk_ref;
  384. }
  385. if (!ret) {
  386. /*
  387. * Switch the parent clock in the hierarchy, and make sure
  388. * that the new parent's usecount is correct. Note: we
  389. * enable the new parent before disabling the old to avoid
  390. * any unnecessary hardware disable->enable transitions.
  391. */
  392. if (clk->usecount) {
  393. omap2_clk_enable(new_parent);
  394. omap2_clk_disable(clk->parent);
  395. }
  396. clk_reparent(clk, new_parent);
  397. clk->rate = rate;
  398. }
  399. omap2_clk_disable(dd->clk_ref);
  400. omap2_clk_disable(dd->clk_bypass);
  401. return 0;
  402. }
  403. /* DPLL autoidle read/set code */
  404. /**
  405. * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
  406. * @clk: struct clk * of the DPLL to read
  407. *
  408. * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
  409. * -EINVAL if passed a null pointer or if the struct clk does not
  410. * appear to refer to a DPLL.
  411. */
  412. u32 omap3_dpll_autoidle_read(struct clk *clk)
  413. {
  414. const struct dpll_data *dd;
  415. u32 v;
  416. if (!clk || !clk->dpll_data)
  417. return -EINVAL;
  418. dd = clk->dpll_data;
  419. v = __raw_readl(dd->autoidle_reg);
  420. v &= dd->autoidle_mask;
  421. v >>= __ffs(dd->autoidle_mask);
  422. return v;
  423. }
  424. /**
  425. * omap3_dpll_allow_idle - enable DPLL autoidle bits
  426. * @clk: struct clk * of the DPLL to operate on
  427. *
  428. * Enable DPLL automatic idle control. This automatic idle mode
  429. * switching takes effect only when the DPLL is locked, at least on
  430. * OMAP3430. The DPLL will enter low-power stop when its downstream
  431. * clocks are gated. No return value.
  432. */
  433. void omap3_dpll_allow_idle(struct clk *clk)
  434. {
  435. const struct dpll_data *dd;
  436. u32 v;
  437. if (!clk || !clk->dpll_data)
  438. return;
  439. dd = clk->dpll_data;
  440. /*
  441. * REVISIT: CORE DPLL can optionally enter low-power bypass
  442. * by writing 0x5 instead of 0x1. Add some mechanism to
  443. * optionally enter this mode.
  444. */
  445. v = __raw_readl(dd->autoidle_reg);
  446. v &= ~dd->autoidle_mask;
  447. v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
  448. __raw_writel(v, dd->autoidle_reg);
  449. }
  450. /**
  451. * omap3_dpll_deny_idle - prevent DPLL from automatically idling
  452. * @clk: struct clk * of the DPLL to operate on
  453. *
  454. * Disable DPLL automatic idle control. No return value.
  455. */
  456. void omap3_dpll_deny_idle(struct clk *clk)
  457. {
  458. const struct dpll_data *dd;
  459. u32 v;
  460. if (!clk || !clk->dpll_data)
  461. return;
  462. dd = clk->dpll_data;
  463. v = __raw_readl(dd->autoidle_reg);
  464. v &= ~dd->autoidle_mask;
  465. v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
  466. __raw_writel(v, dd->autoidle_reg);
  467. }
  468. /* Clock control for DPLL outputs */
  469. /**
  470. * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
  471. * @clk: DPLL output struct clk
  472. *
  473. * Using parent clock DPLL data, look up DPLL state. If locked, set our
  474. * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
  475. */
  476. unsigned long omap3_clkoutx2_recalc(struct clk *clk)
  477. {
  478. const struct dpll_data *dd;
  479. unsigned long rate;
  480. u32 v;
  481. struct clk *pclk;
  482. /* Walk up the parents of clk, looking for a DPLL */
  483. pclk = clk->parent;
  484. while (pclk && !pclk->dpll_data)
  485. pclk = pclk->parent;
  486. /* clk does not have a DPLL as a parent? */
  487. WARN_ON(!pclk);
  488. dd = pclk->dpll_data;
  489. WARN_ON(!dd->enable_mask);
  490. v = __raw_readl(dd->control_reg) & dd->enable_mask;
  491. v >>= __ffs(dd->enable_mask);
  492. if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
  493. rate = clk->parent->rate;
  494. else
  495. rate = clk->parent->rate * 2;
  496. return rate;
  497. }