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cm44xx.h

cm44xx.h 38 KB
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  1. /*
    2. 

  2.  * OMAP44xx CM1 & CM2 instance offset macros
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2009-2010 Texas Instruments, Inc.
    5. 

  5.  * Copyright (C) 2009-2010 Nokia Corporation
    6. 

  6.  *
    7. 

  7.  * Paul Walmsley (paul@pwsan.com)
    8. 

  8.  * Rajendra Nayak (rnayak@ti.com)
    9. 

  9.  * Benoit Cousson (b-cousson@ti.com)
    10. 

  10.  *
    11. 

  11.  * This file is automatically generated from the OMAP hardware databases.
    12. 

  12.  * We respectfully ask that any modifications to this file be coordinated
    13. 

  13.  * with the public linux-omap@vger.kernel.org mailing list and the
    14. 

  14.  * authors above to ensure that the autogeneration scripts are kept
    15. 

  15.  * up-to-date with the file contents.
    16. 

  16.  *
    17. 

  17.  * This program is free software; you can redistribute it and/or modify
    18. 

  18.  * it under the terms of the GNU General Public License version 2 as
    19. 

  19.  * published by the Free Software Foundation.
    20. 

  20.  */
    21. 

  21. 

  22. #ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H
    23. 

  23. #define __ARCH_ARM_MACH_OMAP2_CM44XX_H
    24. 

  24. 

  25. 

  26. /* CM1 */
    27. 

  27. 

  28. /* CM1.OCP_SOCKET_CM1 register offsets */
    29. 

  29. #define OMAP4_REVISION_CM1_OFFSET			0x0000
    30. 

  30. #define OMAP4430_REVISION_CM1				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
    31. 

  31. #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET		0x0040
    32. 

  32. #define OMAP4430_CM_CM1_PROFILING_CLKCTRL		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
    33. 

  33. 

  34. /* CM1.CKGEN_CM1 register offsets */
    35. 

  35. #define OMAP4_CM_CLKSEL_CORE_OFFSET			0x0000
    36. 

  36. #define OMAP4430_CM_CLKSEL_CORE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
    37. 

  37. #define OMAP4_CM_CLKSEL_ABE_OFFSET			0x0008
    38. 

  38. #define OMAP4430_CM_CLKSEL_ABE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
    39. 

  39. #define OMAP4_CM_DLL_CTRL_OFFSET			0x0010
    40. 

  40. #define OMAP4430_CM_DLL_CTRL				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
    41. 

  41. #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET		0x0020
    42. 

  42. #define OMAP4430_CM_CLKMODE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
    43. 

  43. #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET		0x0024
    44. 

  44. #define OMAP4430_CM_IDLEST_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
    45. 

  45. #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0028
    46. 

  46. #define OMAP4430_CM_AUTOIDLE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
    47. 

  47. #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET		0x002c
    48. 

  48. #define OMAP4430_CM_CLKSEL_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
    49. 

  49. #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET		0x0030
    50. 

  50. #define OMAP4430_CM_DIV_M2_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
    51. 

  51. #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET		0x0034
    52. 

  52. #define OMAP4430_CM_DIV_M3_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
    53. 

  53. #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET		0x0038
    54. 

  54. #define OMAP4430_CM_DIV_M4_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
    55. 

  55. #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET		0x003c
    56. 

  56. #define OMAP4430_CM_DIV_M5_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
    57. 

  57. #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET		0x0040
    58. 

  58. #define OMAP4430_CM_DIV_M6_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
    59. 

  59. #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET		0x0044
    60. 

  60. #define OMAP4430_CM_DIV_M7_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
    61. 

  61. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0048
    62. 

  62. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
    63. 

  63. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x004c
    64. 

  64. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
    65. 

  65. #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET		0x0050
    66. 

  66. #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
    67. 

  67. #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET		0x0060
    68. 

  68. #define OMAP4430_CM_CLKMODE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
    69. 

  69. #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET			0x0064
    70. 

  70. #define OMAP4430_CM_IDLEST_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
    71. 

  71. #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x0068
    72. 

  72. #define OMAP4430_CM_AUTOIDLE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
    73. 

  73. #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET			0x006c
    74. 

  74. #define OMAP4430_CM_CLKSEL_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
    75. 

  75. #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET			0x0070
    76. 

  76. #define OMAP4430_CM_DIV_M2_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
    77. 

  77. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET		0x0088
    78. 

  78. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
    79. 

  79. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET		0x008c
    80. 

  80. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
    81. 

  81. #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET			0x009c
    82. 

  82. #define OMAP4430_CM_BYPCLK_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
    83. 

  83. #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET		0x00a0
    84. 

  84. #define OMAP4430_CM_CLKMODE_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
    85. 

  85. #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET			0x00a4
    86. 

  86. #define OMAP4430_CM_IDLEST_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
    87. 

  87. #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET		0x00a8
    88. 

  88. #define OMAP4430_CM_AUTOIDLE_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
    89. 

  89. #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET			0x00ac
    90. 

  90. #define OMAP4430_CM_CLKSEL_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
    91. 

  91. #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET			0x00b8
    92. 

  92. #define OMAP4430_CM_DIV_M4_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
    93. 

  93. #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET			0x00bc
    94. 

  94. #define OMAP4430_CM_DIV_M5_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
    95. 

  95. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET		0x00c8
    96. 

  96. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
    97. 

  97. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET		0x00cc
    98. 

  98. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
    99. 

  99. #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET			0x00dc
    100. 

  100. #define OMAP4430_CM_BYPCLK_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
    101. 

  101. #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET		0x00e0
    102. 

  102. #define OMAP4430_CM_CLKMODE_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
    103. 

  103. #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET			0x00e4
    104. 

  104. #define OMAP4430_CM_IDLEST_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
    105. 

  105. #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET		0x00e8
    106. 

  106. #define OMAP4430_CM_AUTOIDLE_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
    107. 

  107. #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET			0x00ec
    108. 

  108. #define OMAP4430_CM_CLKSEL_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
    109. 

  109. #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET			0x00f0
    110. 

  110. #define OMAP4430_CM_DIV_M2_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
    111. 

  111. #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET			0x00f4
    112. 

  112. #define OMAP4430_CM_DIV_M3_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
    113. 

  113. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET		0x0108
    114. 

  114. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
    115. 

  115. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET		0x010c
    116. 

  116. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
    117. 

  117. #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET		0x0120
    118. 

  118. #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
    119. 

  119. #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET		0x0124
    120. 

  120. #define OMAP4430_CM_IDLEST_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
    121. 

  121. #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET		0x0128
    122. 

  122. #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
    123. 

  123. #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET		0x012c
    124. 

  124. #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
    125. 

  125. #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET		0x0130
    126. 

  126. #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
    127. 

  127. #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET		0x0138
    128. 

  128. #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
    129. 

  129. #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET		0x013c
    130. 

  130. #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
    131. 

  131. #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET		0x0140
    132. 

  132. #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
    133. 

  133. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET	0x0148
    134. 

  134. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
    135. 

  135. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET	0x014c
    136. 

  136. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
    137. 

  137. #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET		0x0160
    138. 

  138. #define OMAP4430_CM_SHADOW_FREQ_CONFIG1			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
    139. 

  139. #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET		0x0164
    140. 

  140. #define OMAP4430_CM_SHADOW_FREQ_CONFIG2			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
    141. 

  141. #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET			0x0170
    142. 

  142. #define OMAP4430_CM_DYN_DEP_PRESCAL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
    143. 

  143. #define OMAP4_CM_RESTORE_ST_OFFSET			0x0180
    144. 

  144. #define OMAP4430_CM_RESTORE_ST				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
    145. 

  145. 

  146. /* CM1.MPU_CM1 register offsets */
    147. 

  147. #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET			0x0000
    148. 

  148. #define OMAP4430_CM_MPU_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
    149. 

  149. #define OMAP4_CM_MPU_STATICDEP_OFFSET			0x0004
    150. 

  150. #define OMAP4430_CM_MPU_STATICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
    151. 

  151. #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET			0x0008
    152. 

  152. #define OMAP4430_CM_MPU_DYNAMICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
    153. 

  153. #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET			0x0020
    154. 

  154. #define OMAP4430_CM_MPU_MPU_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
    155. 

  155. 

  156. /* CM1.TESLA_CM1 register offsets */
    157. 

  157. #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET			0x0000
    158. 

  158. #define OMAP4430_CM_TESLA_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
    159. 

  159. #define OMAP4_CM_TESLA_STATICDEP_OFFSET			0x0004
    160. 

  160. #define OMAP4430_CM_TESLA_STATICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
    161. 

  161. #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET		0x0008
    162. 

  162. #define OMAP4430_CM_TESLA_DYNAMICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
    163. 

  163. #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET		0x0020
    164. 

  164. #define OMAP4430_CM_TESLA_TESLA_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
    165. 

  165. 

  166. /* CM1.ABE_CM1 register offsets */
    167. 

  167. #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET			0x0000
    168. 

  168. #define OMAP4430_CM1_ABE_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
    169. 

  169. #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET		0x0020
    170. 

  170. #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
    171. 

  171. #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET		0x0028
    172. 

  172. #define OMAP4430_CM1_ABE_AESS_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
    173. 

  173. #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET		0x0030
    174. 

  174. #define OMAP4430_CM1_ABE_PDM_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
    175. 

  175. #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET		0x0038
    176. 

  176. #define OMAP4430_CM1_ABE_DMIC_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
    177. 

  177. #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET		0x0040
    178. 

  178. #define OMAP4430_CM1_ABE_MCASP_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
    179. 

  179. #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET		0x0048
    180. 

  180. #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
    181. 

  181. #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET		0x0050
    182. 

  182. #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
    183. 

  183. #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET		0x0058
    184. 

  184. #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
    185. 

  185. #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET		0x0060
    186. 

  186. #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
    187. 

  187. #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET		0x0068
    188. 

  188. #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
    189. 

  189. #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET		0x0070
    190. 

  190. #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
    191. 

  191. #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET		0x0078
    192. 

  192. #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
    193. 

  193. #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET		0x0080
    194. 

  194. #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
    195. 

  195. #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET		0x0088
    196. 

  196. #define OMAP4430_CM1_ABE_WDT3_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
    197. 

  197. 

  198. /* CM2 */
    199. 

  199. 

  200. /* CM2.OCP_SOCKET_CM2 register offsets */
    201. 

  201. #define OMAP4_REVISION_CM2_OFFSET			0x0000
    202. 

  202. #define OMAP4430_REVISION_CM2				OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
    203. 

  203. #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET		0x0040
    204. 

  204. #define OMAP4430_CM_CM2_PROFILING_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
    205. 

  205. 

  206. /* CM2.CKGEN_CM2 register offsets */
    207. 

  207. #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET		0x0000
    208. 

  208. #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
    209. 

  209. #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET		0x0004
    210. 

  210. #define OMAP4430_CM_CLKSEL_USB_60MHZ			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
    211. 

  211. #define OMAP4_CM_SCALE_FCLK_OFFSET			0x0008
    212. 

  212. #define OMAP4430_CM_SCALE_FCLK				OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
    213. 

  213. #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET			0x0010
    214. 

  214. #define OMAP4430_CM_CORE_DVFS_PERF1			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
    215. 

  215. #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET			0x0014
    216. 

  216. #define OMAP4430_CM_CORE_DVFS_PERF2			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
    217. 

  217. #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET			0x0018
    218. 

  218. #define OMAP4430_CM_CORE_DVFS_PERF3			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
    219. 

  219. #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET			0x001c
    220. 

  220. #define OMAP4430_CM_CORE_DVFS_PERF4			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
    221. 

  221. #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET		0x0024
    222. 

  222. #define OMAP4430_CM_CORE_DVFS_CURRENT			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
    223. 

  223. #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET		0x0028
    224. 

  224. #define OMAP4430_CM_IVA_DVFS_PERF_TESLA			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
    225. 

  225. #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET		0x002c
    226. 

  226. #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
    227. 

  227. #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET		0x0030
    228. 

  228. #define OMAP4430_CM_IVA_DVFS_PERF_ABE			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
    229. 

  229. #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET		0x0038
    230. 

  230. #define OMAP4430_CM_IVA_DVFS_CURRENT			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
    231. 

  231. #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET		0x0040
    232. 

  232. #define OMAP4430_CM_CLKMODE_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
    233. 

  233. #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET			0x0044
    234. 

  234. #define OMAP4430_CM_IDLEST_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
    235. 

  235. #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET		0x0048
    236. 

  236. #define OMAP4430_CM_AUTOIDLE_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
    237. 

  237. #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET			0x004c
    238. 

  238. #define OMAP4430_CM_CLKSEL_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
    239. 

  239. #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET			0x0050
    240. 

  240. #define OMAP4430_CM_DIV_M2_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
    241. 

  241. #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET			0x0054
    242. 

  242. #define OMAP4430_CM_DIV_M3_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
    243. 

  243. #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET			0x0058
    244. 

  244. #define OMAP4430_CM_DIV_M4_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
    245. 

  245. #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET			0x005c
    246. 

  246. #define OMAP4430_CM_DIV_M5_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
    247. 

  247. #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET			0x0060
    248. 

  248. #define OMAP4430_CM_DIV_M6_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
    249. 

  249. #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET			0x0064
    250. 

  250. #define OMAP4430_CM_DIV_M7_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
    251. 

  251. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET		0x0068
    252. 

  252. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
    253. 

  253. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x006c
    254. 

  254. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
    255. 

  255. #define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET		0x0070
    256. 

  256. #define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
    257. 

  257. #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET		0x0080
    258. 

  258. #define OMAP4430_CM_CLKMODE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
    259. 

  259. #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET			0x0084
    260. 

  260. #define OMAP4430_CM_IDLEST_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
    261. 

  261. #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET		0x0088
    262. 

  262. #define OMAP4430_CM_AUTOIDLE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
    263. 

  263. #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET			0x008c
    264. 

  264. #define OMAP4430_CM_CLKSEL_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
    265. 

  265. #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET			0x0090
    266. 

  266. #define OMAP4430_CM_DIV_M2_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
    267. 

  267. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET		0x00a8
    268. 

  268. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
    269. 

  269. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET		0x00ac
    270. 

  270. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
    271. 

  271. #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET		0x00b4
    272. 

  272. #define OMAP4430_CM_CLKDCOLDO_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
    273. 

  273. #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET		0x00c0
    274. 

  274. #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
    275. 

  275. #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET		0x00c4
    276. 

  276. #define OMAP4430_CM_IDLEST_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
    277. 

  277. #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET		0x00c8
    278. 

  278. #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
    279. 

  279. #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET		0x00cc
    280. 

  280. #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
    281. 

  281. #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET		0x00d0
    282. 

  282. #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
    283. 

  283. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET	0x00e8
    284. 

  284. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
    285. 

  285. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET	0x00ec
    286. 

  286. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
    287. 

  287. 

  288. /* CM2.ALWAYS_ON_CM2 register offsets */
    289. 

  289. #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET			0x0000
    290. 

  290. #define OMAP4430_CM_ALWON_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
    291. 

  291. #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET		0x0020
    292. 

  292. #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
    293. 

  293. #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET		0x0028
    294. 

  294. #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
    295. 

  295. #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET		0x0030
    296. 

  296. #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
    297. 

  297. #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET		0x0038
    298. 

  298. #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
    299. 

  299. 

  300. /* CM2.CORE_CM2 register offsets */
    301. 

  301. #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET			0x0000
    302. 

  302. #define OMAP4430_CM_L3_1_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
    303. 

  303. #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET			0x0008
    304. 

  304. #define OMAP4430_CM_L3_1_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
    305. 

  305. #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET		0x0020
    306. 

  306. #define OMAP4430_CM_L3_1_L3_1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
    307. 

  307. #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET			0x0100
    308. 

  308. #define OMAP4430_CM_L3_2_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
    309. 

  309. #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET			0x0108
    310. 

  310. #define OMAP4430_CM_L3_2_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
    311. 

  311. #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET		0x0120
    312. 

  312. #define OMAP4430_CM_L3_2_L3_2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
    313. 

  313. #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET		0x0128
    314. 

  314. #define OMAP4430_CM_L3_2_GPMC_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
    315. 

  315. #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET		0x0130
    316. 

  316. #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
    317. 

  317. #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET		0x0200
    318. 

  318. #define OMAP4430_CM_DUCATI_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
    319. 

  319. #define OMAP4_CM_DUCATI_STATICDEP_OFFSET		0x0204
    320. 

  320. #define OMAP4430_CM_DUCATI_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
    321. 

  321. #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET		0x0208
    322. 

  322. #define OMAP4430_CM_DUCATI_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
    323. 

  323. #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET		0x0220
    324. 

  324. #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
    325. 

  325. #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET			0x0300
    326. 

  326. #define OMAP4430_CM_SDMA_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
    327. 

  327. #define OMAP4_CM_SDMA_STATICDEP_OFFSET			0x0304
    328. 

  328. #define OMAP4430_CM_SDMA_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
    329. 

  329. #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET			0x0308
    330. 

  330. #define OMAP4430_CM_SDMA_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
    331. 

  331. #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET		0x0320
    332. 

  332. #define OMAP4430_CM_SDMA_SDMA_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
    333. 

  333. #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET			0x0400
    334. 

  334. #define OMAP4430_CM_MEMIF_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
    335. 

  335. #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET		0x0420
    336. 

  336. #define OMAP4430_CM_MEMIF_DMM_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
    337. 

  337. #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET		0x0428
    338. 

  338. #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
    339. 

  339. #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET		0x0430
    340. 

  340. #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
    341. 

  341. #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET		0x0438
    342. 

  342. #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
    343. 

  343. #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET		0x0440
    344. 

  344. #define OMAP4430_CM_MEMIF_DLL_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
    345. 

  345. #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET		0x0450
    346. 

  346. #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
    347. 

  347. #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET		0x0458
    348. 

  348. #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
    349. 

  349. #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET		0x0460
    350. 

  350. #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
    351. 

  351. #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET			0x0500
    352. 

  352. #define OMAP4430_CM_D2D_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
    353. 

  353. #define OMAP4_CM_D2D_STATICDEP_OFFSET			0x0504
    354. 

  354. #define OMAP4430_CM_D2D_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
    355. 

  355. #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET			0x0508
    356. 

  356. #define OMAP4430_CM_D2D_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
    357. 

  357. #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET		0x0520
    358. 

  358. #define OMAP4430_CM_D2D_SAD2D_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
    359. 

  359. #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET		0x0528
    360. 

  360. #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
    361. 

  361. #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET		0x0530
    362. 

  362. #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
    363. 

  363. #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET			0x0600
    364. 

  364. #define OMAP4430_CM_L4CFG_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
    365. 

  365. #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET		0x0608
    366. 

  366. #define OMAP4430_CM_L4CFG_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
    367. 

  367. #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET		0x0620
    368. 

  368. #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
    369. 

  369. #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET		0x0628
    370. 

  370. #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
    371. 

  371. #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET		0x0630
    372. 

  372. #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
    373. 

  373. #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET		0x0638
    374. 

  374. #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
    375. 

  375. #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET		0x0700
    376. 

  376. #define OMAP4430_CM_L3INSTR_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
    377. 

  377. #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET		0x0720
    378. 

  378. #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
    379. 

  379. #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET	0x0728
    380. 

  380. #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
    381. 

  381. #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET		0x0740
    382. 

  382. #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
    383. 

  383. 

  384. /* CM2.IVAHD_CM2 register offsets */
    385. 

  385. #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET			0x0000
    386. 

  386. #define OMAP4430_CM_IVAHD_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
    387. 

  387. #define OMAP4_CM_IVAHD_STATICDEP_OFFSET			0x0004
    388. 

  388. #define OMAP4430_CM_IVAHD_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
    389. 

  389. #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET		0x0008
    390. 

  390. #define OMAP4430_CM_IVAHD_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
    391. 

  391. #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET		0x0020
    392. 

  392. #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
    393. 

  393. #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET		0x0028
    394. 

  394. #define OMAP4430_CM_IVAHD_SL2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
    395. 

  395. 

  396. /* CM2.CAM_CM2 register offsets */
    397. 

  397. #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET			0x0000
    398. 

  398. #define OMAP4430_CM_CAM_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
    399. 

  399. #define OMAP4_CM_CAM_STATICDEP_OFFSET			0x0004
    400. 

  400. #define OMAP4430_CM_CAM_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
    401. 

  401. #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET			0x0008
    402. 

  402. #define OMAP4430_CM_CAM_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
    403. 

  403. #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET			0x0020
    404. 

  404. #define OMAP4430_CM_CAM_ISS_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
    405. 

  405. #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET		0x0028
    406. 

  406. #define OMAP4430_CM_CAM_FDIF_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
    407. 

  407. 

  408. /* CM2.DSS_CM2 register offsets */
    409. 

  409. #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET			0x0000
    410. 

  410. #define OMAP4430_CM_DSS_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
    411. 

  411. #define OMAP4_CM_DSS_STATICDEP_OFFSET			0x0004
    412. 

  412. #define OMAP4430_CM_DSS_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
    413. 

  413. #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET			0x0008
    414. 

  414. #define OMAP4430_CM_DSS_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
    415. 

  415. #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET			0x0020
    416. 

  416. #define OMAP4430_CM_DSS_DSS_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
    417. 

  417. #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET		0x0028
    418. 

  418. #define OMAP4430_CM_DSS_DEISS_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
    419. 

  419. 

  420. /* CM2.GFX_CM2 register offsets */
    421. 

  421. #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET			0x0000
    422. 

  422. #define OMAP4430_CM_GFX_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
    423. 

  423. #define OMAP4_CM_GFX_STATICDEP_OFFSET			0x0004
    424. 

  424. #define OMAP4430_CM_GFX_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
    425. 

  425. #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET			0x0008
    426. 

  426. #define OMAP4430_CM_GFX_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
    427. 

  427. #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET			0x0020
    428. 

  428. #define OMAP4430_CM_GFX_GFX_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
    429. 

  429. 

  430. /* CM2.L3INIT_CM2 register offsets */
    431. 

  431. #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET		0x0000
    432. 

  432. #define OMAP4430_CM_L3INIT_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
    433. 

  433. #define OMAP4_CM_L3INIT_STATICDEP_OFFSET		0x0004
    434. 

  434. #define OMAP4430_CM_L3INIT_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
    435. 

  435. #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET		0x0008
    436. 

  436. #define OMAP4430_CM_L3INIT_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
    437. 

  437. #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET		0x0028
    438. 

  438. #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
    439. 

  439. #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET		0x0030
    440. 

  440. #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
    441. 

  441. #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET		0x0038
    442. 

  442. #define OMAP4430_CM_L3INIT_HSI_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
    443. 

  443. #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET		0x0040
    444. 

  444. #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
    445. 

  445. #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET		0x0058
    446. 

  446. #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
    447. 

  447. #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET		0x0060
    448. 

  448. #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
    449. 

  449. #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET		0x0068
    450. 

  450. #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
    451. 

  451. #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET		0x0078
    452. 

  452. #define OMAP4430_CM_L3INIT_P1500_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
    453. 

  453. #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET		0x0080
    454. 

  454. #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
    455. 

  455. #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET		0x0088
    456. 

  456. #define OMAP4430_CM_L3INIT_SATA_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
    457. 

  457. #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET		0x0090
    458. 

  458. #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
    459. 

  459. #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET		0x0098
    460. 

  460. #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
    461. 

  461. #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET		0x00a8
    462. 

  462. #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
    463. 

  463. #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET		0x00c0
    464. 

  464. #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
    465. 

  465. #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET		0x00c8
    466. 

  466. #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
    467. 

  467. #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET	0x00d0
    468. 

  468. #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
    469. 

  469. #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET	0x00e0
    470. 

  470. #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL	OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
    471. 

  471. 

  472. /* CM2.L4PER_CM2 register offsets */
    473. 

  473. #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET			0x0000
    474. 

  474. #define OMAP4430_CM_L4PER_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
    475. 

  475. #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET		0x0008
    476. 

  476. #define OMAP4430_CM_L4PER_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
    477. 

  477. #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET		0x0020
    478. 

  478. #define OMAP4430_CM_L4PER_ADC_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
    479. 

  479. #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET		0x0028
    480. 

  480. #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
    481. 

  481. #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET		0x0030
    482. 

  482. #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
    483. 

  483. #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET		0x0038
    484. 

  484. #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
    485. 

  485. #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET		0x0040
    486. 

  486. #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
    487. 

  487. #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET		0x0048
    488. 

  488. #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
    489. 

  489. #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET		0x0050
    490. 

  490. #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
    491. 

  491. #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET		0x0058
    492. 

  492. #define OMAP4430_CM_L4PER_ELM_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
    493. 

  493. #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET		0x0060
    494. 

  494. #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
    495. 

  495. #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET		0x0068
    496. 

  496. #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
    497. 

  497. #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET		0x0070
    498. 

  498. #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
    499. 

  499. #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET		0x0078
    500. 

  500. #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
    501. 

  501. #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET		0x0080
    502. 

  502. #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
    503. 

  503. #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET		0x0088
    504. 

  504. #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
    505. 

  505. #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET		0x0090
    506. 

  506. #define OMAP4430_CM_L4PER_HECC1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
    507. 

  507. #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET		0x0098
    508. 

  508. #define OMAP4430_CM_L4PER_HECC2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
    509. 

  509. #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET		0x00a0
    510. 

  510. #define OMAP4430_CM_L4PER_I2C1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
    511. 

  511. #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET		0x00a8
    512. 

  512. #define OMAP4430_CM_L4PER_I2C2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
    513. 

  513. #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET		0x00b0
    514. 

  514. #define OMAP4430_CM_L4PER_I2C3_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
    515. 

  515. #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET		0x00b8
    516. 

  516. #define OMAP4430_CM_L4PER_I2C4_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
    517. 

  517. #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET		0x00c0
    518. 

  518. #define OMAP4430_CM_L4PER_L4PER_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
    519. 

  519. #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET		0x00d0
    520. 

  520. #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
    521. 

  521. #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET		0x00d8
    522. 

  522. #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
    523. 

  523. #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET		0x00e0
    524. 

  524. #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
    525. 

  525. #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET		0x00e8
    526. 

  526. #define OMAP4430_CM_L4PER_MGATE_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
    527. 

  527. #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET		0x00f0
    528. 

  528. #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
    529. 

  529. #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET		0x00f8
    530. 

  530. #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
    531. 

  531. #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET		0x0100
    532. 

  532. #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
    533. 

  533. #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET		0x0108
    534. 

  534. #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
    535. 

  535. #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET		0x0120
    536. 

  536. #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
    537. 

  537. #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET		0x0128
    538. 

  538. #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
    539. 

  539. #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET		0x0130
    540. 

  540. #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
    541. 

  541. #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET		0x0138
    542. 

  542. #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
    543. 

  543. #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET		0x0140
    544. 

  544. #define OMAP4430_CM_L4PER_UART1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
    545. 

  545. #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET		0x0148
    546. 

  546. #define OMAP4430_CM_L4PER_UART2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
    547. 

  547. #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET		0x0150
    548. 

  548. #define OMAP4430_CM_L4PER_UART3_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
    549. 

  549. #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET		0x0158
    550. 

  550. #define OMAP4430_CM_L4PER_UART4_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
    551. 

  551. #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET		0x0160
    552. 

  552. #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
    553. 

  553. #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET		0x0168
    554. 

  554. #define OMAP4430_CM_L4PER_I2C5_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
    555. 

  555. #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET			0x0180
    556. 

  556. #define OMAP4430_CM_L4SEC_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
    557. 

  557. #define OMAP4_CM_L4SEC_STATICDEP_OFFSET			0x0184
    558. 

  558. #define OMAP4430_CM_L4SEC_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
    559. 

  559. #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET		0x0188
    560. 

  560. #define OMAP4430_CM_L4SEC_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
    561. 

  561. #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET		0x01a0
    562. 

  562. #define OMAP4430_CM_L4SEC_AES1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
    563. 

  563. #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET		0x01a8
    564. 

  564. #define OMAP4430_CM_L4SEC_AES2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
    565. 

  565. #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET		0x01b0
    566. 

  566. #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
    567. 

  567. #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET		0x01b8
    568. 

  568. #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
    569. 

  569. #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET		0x01c0
    570. 

  570. #define OMAP4430_CM_L4SEC_RNG_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
    571. 

  571. #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET		0x01c8
    572. 

  572. #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
    573. 

  573. #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET		0x01d8
    574. 

  574. #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
    575. 

  575. 

  576. /* CM2.CEFUSE_CM2 register offsets */
    577. 

  577. #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
    578. 

  578. #define OMAP4430_CM_CEFUSE_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
    579. 

  579. #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
    580. 

  580. #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
    581. 

  581. #endif
    582.