clockdomains44xx.h 8.1 KB

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  1. /*
  2. * OMAP4 Clock domains framework
  3. *
  4. * Copyright (C) 2009 Texas Instruments, Inc.
  5. * Copyright (C) 2009 Nokia Corporation
  6. *
  7. * Abhijit Pagare (abhijitpagare@ti.com)
  8. * Benoit Cousson (b-cousson@ti.com)
  9. *
  10. * This file is automatically generated from the OMAP hardware databases.
  11. * We respectfully ask that any modifications to this file be coordinated
  12. * with the public linux-omap@vger.kernel.org mailing list and the
  13. * authors above to ensure that the autogeneration scripts are kept
  14. * up-to-date with the file contents.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. /*
  21. * To-Do List
  22. * -> Populate the Sleep/Wakeup dependencies for the domains
  23. */
  24. #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
  25. #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
  26. #include <plat/clockdomain.h>
  27. #if defined(CONFIG_ARCH_OMAP4)
  28. static struct clockdomain l4_cefuse_44xx_clkdm = {
  29. .name = "l4_cefuse_clkdm",
  30. .pwrdm = { .name = "cefuse_pwrdm" },
  31. .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL,
  32. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  33. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  34. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  35. };
  36. static struct clockdomain l4_cfg_44xx_clkdm = {
  37. .name = "l4_cfg_clkdm",
  38. .pwrdm = { .name = "core_pwrdm" },
  39. .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL,
  40. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  41. .flags = CLKDM_CAN_HWSUP,
  42. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  43. };
  44. static struct clockdomain tesla_44xx_clkdm = {
  45. .name = "tesla_clkdm",
  46. .pwrdm = { .name = "tesla_pwrdm" },
  47. .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL,
  48. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  49. .flags = CLKDM_CAN_HWSUP_SWSUP,
  50. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  51. };
  52. static struct clockdomain l3_gfx_44xx_clkdm = {
  53. .name = "l3_gfx_clkdm",
  54. .pwrdm = { .name = "gfx_pwrdm" },
  55. .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL,
  56. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  57. .flags = CLKDM_CAN_HWSUP_SWSUP,
  58. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  59. };
  60. static struct clockdomain ivahd_44xx_clkdm = {
  61. .name = "ivahd_clkdm",
  62. .pwrdm = { .name = "ivahd_pwrdm" },
  63. .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL,
  64. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  65. .flags = CLKDM_CAN_HWSUP_SWSUP,
  66. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  67. };
  68. static struct clockdomain l4_secure_44xx_clkdm = {
  69. .name = "l4_secure_clkdm",
  70. .pwrdm = { .name = "l4per_pwrdm" },
  71. .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL,
  72. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  73. .flags = CLKDM_CAN_HWSUP_SWSUP,
  74. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  75. };
  76. static struct clockdomain l4_per_44xx_clkdm = {
  77. .name = "l4_per_clkdm",
  78. .pwrdm = { .name = "l4per_pwrdm" },
  79. .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL,
  80. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  81. .flags = CLKDM_CAN_HWSUP_SWSUP,
  82. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  83. };
  84. static struct clockdomain abe_44xx_clkdm = {
  85. .name = "abe_clkdm",
  86. .pwrdm = { .name = "abe_pwrdm" },
  87. .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL,
  88. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  89. .flags = CLKDM_CAN_HWSUP_SWSUP,
  90. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  91. };
  92. static struct clockdomain l3_instr_44xx_clkdm = {
  93. .name = "l3_instr_clkdm",
  94. .pwrdm = { .name = "core_pwrdm" },
  95. .clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL,
  96. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  97. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  98. };
  99. static struct clockdomain l3_init_44xx_clkdm = {
  100. .name = "l3_init_clkdm",
  101. .pwrdm = { .name = "l3init_pwrdm" },
  102. .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL,
  103. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  104. .flags = CLKDM_CAN_HWSUP_SWSUP,
  105. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  106. };
  107. static struct clockdomain mpuss_44xx_clkdm = {
  108. .name = "mpuss_clkdm",
  109. .pwrdm = { .name = "mpu_pwrdm" },
  110. .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL,
  111. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  112. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  113. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  114. };
  115. static struct clockdomain mpu0_44xx_clkdm = {
  116. .name = "mpu0_clkdm",
  117. .pwrdm = { .name = "cpu0_pwrdm" },
  118. .clkstctrl_reg = OMAP4430_CM_CPU0_CLKSTCTRL,
  119. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  120. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  121. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  122. };
  123. static struct clockdomain mpu1_44xx_clkdm = {
  124. .name = "mpu1_clkdm",
  125. .pwrdm = { .name = "cpu1_pwrdm" },
  126. .clkstctrl_reg = OMAP4430_CM_CPU1_CLKSTCTRL,
  127. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  128. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  129. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  130. };
  131. static struct clockdomain l3_emif_44xx_clkdm = {
  132. .name = "l3_emif_clkdm",
  133. .pwrdm = { .name = "core_pwrdm" },
  134. .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL,
  135. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  136. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  137. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  138. };
  139. static struct clockdomain l4_ao_44xx_clkdm = {
  140. .name = "l4_ao_clkdm",
  141. .pwrdm = { .name = "always_on_core_pwrdm" },
  142. .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL,
  143. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  144. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  145. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  146. };
  147. static struct clockdomain ducati_44xx_clkdm = {
  148. .name = "ducati_clkdm",
  149. .pwrdm = { .name = "core_pwrdm" },
  150. .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL,
  151. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  152. .flags = CLKDM_CAN_HWSUP_SWSUP,
  153. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  154. };
  155. static struct clockdomain l3_2_44xx_clkdm = {
  156. .name = "l3_2_clkdm",
  157. .pwrdm = { .name = "core_pwrdm" },
  158. .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL,
  159. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  160. .flags = CLKDM_CAN_HWSUP,
  161. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  162. };
  163. static struct clockdomain l3_1_44xx_clkdm = {
  164. .name = "l3_1_clkdm",
  165. .pwrdm = { .name = "core_pwrdm" },
  166. .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL,
  167. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  168. .flags = CLKDM_CAN_HWSUP,
  169. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  170. };
  171. static struct clockdomain l3_d2d_44xx_clkdm = {
  172. .name = "l3_d2d_clkdm",
  173. .pwrdm = { .name = "core_pwrdm" },
  174. .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL,
  175. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  176. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  177. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  178. };
  179. static struct clockdomain iss_44xx_clkdm = {
  180. .name = "iss_clkdm",
  181. .pwrdm = { .name = "cam_pwrdm" },
  182. .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL,
  183. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  184. .flags = CLKDM_CAN_HWSUP_SWSUP,
  185. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  186. };
  187. static struct clockdomain l3_dss_44xx_clkdm = {
  188. .name = "l3_dss_clkdm",
  189. .pwrdm = { .name = "dss_pwrdm" },
  190. .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL,
  191. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  192. .flags = CLKDM_CAN_HWSUP_SWSUP,
  193. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  194. };
  195. static struct clockdomain l4_wkup_44xx_clkdm = {
  196. .name = "l4_wkup_clkdm",
  197. .pwrdm = { .name = "wkup_pwrdm" },
  198. .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL,
  199. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  200. .flags = CLKDM_CAN_HWSUP,
  201. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  202. };
  203. static struct clockdomain emu_sys_44xx_clkdm = {
  204. .name = "emu_sys_clkdm",
  205. .pwrdm = { .name = "emu_pwrdm" },
  206. .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL,
  207. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  208. .flags = CLKDM_CAN_HWSUP,
  209. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  210. };
  211. static struct clockdomain l3_dma_44xx_clkdm = {
  212. .name = "l3_dma_clkdm",
  213. .pwrdm = { .name = "core_pwrdm" },
  214. .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL,
  215. .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
  216. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  217. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  218. };
  219. #endif
  220. #endif