mach-mx31lilly.c 10 KB

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  1. /*
  2. * LILLY-1131 module support
  3. *
  4. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  5. *
  6. * based on code for other MX31 boards,
  7. *
  8. * Copyright 2005-2007 Freescale Semiconductor
  9. * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
  10. * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. */
  22. #include <linux/types.h>
  23. #include <linux/init.h>
  24. #include <linux/clk.h>
  25. #include <linux/gpio.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/smsc911x.h>
  29. #include <linux/mtd/physmap.h>
  30. #include <linux/spi/spi.h>
  31. #include <linux/mfd/mc13783.h>
  32. #include <linux/usb/otg.h>
  33. #include <linux/usb/ulpi.h>
  34. #include <asm/mach-types.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/time.h>
  37. #include <asm/mach/map.h>
  38. #include <mach/hardware.h>
  39. #include <mach/common.h>
  40. #include <mach/iomux-mx3.h>
  41. #include <mach/board-mx31lilly.h>
  42. #include <mach/mxc_ehci.h>
  43. #include <mach/ulpi.h>
  44. #include "devices-imx31.h"
  45. #include "devices.h"
  46. /*
  47. * This file contains module-specific initialization routines for LILLY-1131.
  48. * Initialization of peripherals found on the baseboard is implemented in the
  49. * appropriate baseboard support code.
  50. */
  51. /* SMSC ethernet support */
  52. static struct resource smsc91x_resources[] = {
  53. {
  54. .start = MX31_CS4_BASE_ADDR,
  55. .end = MX31_CS4_BASE_ADDR + 0xffff,
  56. .flags = IORESOURCE_MEM,
  57. },
  58. {
  59. .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
  60. .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
  61. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
  62. }
  63. };
  64. static struct smsc911x_platform_config smsc911x_config = {
  65. .phy_interface = PHY_INTERFACE_MODE_MII,
  66. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  67. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  68. .flags = SMSC911X_USE_32BIT |
  69. SMSC911X_SAVE_MAC_ADDRESS |
  70. SMSC911X_FORCE_INTERNAL_PHY,
  71. };
  72. static struct platform_device smsc91x_device = {
  73. .name = "smsc911x",
  74. .id = -1,
  75. .num_resources = ARRAY_SIZE(smsc91x_resources),
  76. .resource = smsc91x_resources,
  77. .dev = {
  78. .platform_data = &smsc911x_config,
  79. }
  80. };
  81. /* NOR flash */
  82. static struct physmap_flash_data nor_flash_data = {
  83. .width = 2,
  84. };
  85. static struct resource nor_flash_resource = {
  86. .start = 0xa0000000,
  87. .end = 0xa1ffffff,
  88. .flags = IORESOURCE_MEM,
  89. };
  90. static struct platform_device physmap_flash_device = {
  91. .name = "physmap-flash",
  92. .id = 0,
  93. .dev = {
  94. .platform_data = &nor_flash_data,
  95. },
  96. .resource = &nor_flash_resource,
  97. .num_resources = 1,
  98. };
  99. /* USB */
  100. #if defined(CONFIG_USB_ULPI)
  101. #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
  102. PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
  103. static int usbotg_init(struct platform_device *pdev)
  104. {
  105. unsigned int pins[] = {
  106. MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
  107. MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
  108. MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
  109. MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
  110. MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
  111. MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
  112. MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
  113. MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
  114. MX31_PIN_USBOTG_CLK__USBOTG_CLK,
  115. MX31_PIN_USBOTG_DIR__USBOTG_DIR,
  116. MX31_PIN_USBOTG_NXT__USBOTG_NXT,
  117. MX31_PIN_USBOTG_STP__USBOTG_STP,
  118. };
  119. mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG");
  120. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
  121. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
  122. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
  123. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
  124. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
  125. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
  126. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
  127. mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
  128. mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
  129. mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
  130. mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
  131. mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
  132. mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true);
  133. mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true);
  134. /* chip select */
  135. mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO),
  136. "USBOTG_CS");
  137. gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
  138. gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
  139. return 0;
  140. }
  141. static int usbh1_init(struct platform_device *pdev)
  142. {
  143. int pins[] = {
  144. MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
  145. MX31_PIN_CSPI1_MISO__USBH1_RXDP,
  146. MX31_PIN_CSPI1_SS0__USBH1_TXDM,
  147. MX31_PIN_CSPI1_SS1__USBH1_TXDP,
  148. MX31_PIN_CSPI1_SS2__USBH1_RCV,
  149. MX31_PIN_CSPI1_SCLK__USBH1_OEB,
  150. MX31_PIN_CSPI1_SPI_RDY__USBH1_FS,
  151. };
  152. mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1");
  153. mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
  154. mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
  155. mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
  156. mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
  157. mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
  158. mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
  159. mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
  160. mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
  161. return 0;
  162. }
  163. static int usbh2_init(struct platform_device *pdev)
  164. {
  165. int pins[] = {
  166. MX31_PIN_USBH2_DATA0__USBH2_DATA0,
  167. MX31_PIN_USBH2_DATA1__USBH2_DATA1,
  168. MX31_PIN_USBH2_CLK__USBH2_CLK,
  169. MX31_PIN_USBH2_DIR__USBH2_DIR,
  170. MX31_PIN_USBH2_NXT__USBH2_NXT,
  171. MX31_PIN_USBH2_STP__USBH2_STP,
  172. };
  173. mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
  174. mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
  175. mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
  176. mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
  177. mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
  178. mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
  179. mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
  180. mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
  181. mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
  182. mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
  183. mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
  184. mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
  185. mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
  186. mxc_iomux_set_gpr(MUX_PGP_UH2, true);
  187. /* chip select */
  188. mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
  189. "USBH2_CS");
  190. gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
  191. gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
  192. return 0;
  193. }
  194. static struct mxc_usbh_platform_data usbotg_pdata = {
  195. .init = usbotg_init,
  196. .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
  197. .flags = MXC_EHCI_POWER_PINS_ENABLED,
  198. };
  199. static struct mxc_usbh_platform_data usbh1_pdata = {
  200. .init = usbh1_init,
  201. .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
  202. .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
  203. };
  204. static struct mxc_usbh_platform_data usbh2_pdata = {
  205. .init = usbh2_init,
  206. .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
  207. .flags = MXC_EHCI_POWER_PINS_ENABLED,
  208. };
  209. static void lilly1131_usb_init(void)
  210. {
  211. usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
  212. ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
  213. usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
  214. ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
  215. mxc_register_device(&mxc_usbh1, &usbh1_pdata);
  216. mxc_register_device(&mxc_usbh2, &usbh2_pdata);
  217. }
  218. #else
  219. static inline void lilly1131_usb_init(void) {}
  220. #endif /* CONFIG_USB_ULPI */
  221. /* SPI */
  222. static int spi_internal_chipselect[] = {
  223. MXC_SPI_CS(0),
  224. MXC_SPI_CS(1),
  225. MXC_SPI_CS(2),
  226. };
  227. static const struct spi_imx_master spi0_pdata __initconst = {
  228. .chipselect = spi_internal_chipselect,
  229. .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
  230. };
  231. static const struct spi_imx_master spi1_pdata __initconst = {
  232. .chipselect = spi_internal_chipselect,
  233. .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
  234. };
  235. static struct mc13783_platform_data mc13783_pdata __initdata = {
  236. .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN,
  237. };
  238. static struct spi_board_info mc13783_dev __initdata = {
  239. .modalias = "mc13783",
  240. .max_speed_hz = 1000000,
  241. .bus_num = 1,
  242. .chip_select = 0,
  243. .platform_data = &mc13783_pdata,
  244. .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
  245. };
  246. static struct platform_device *devices[] __initdata = {
  247. &smsc91x_device,
  248. &physmap_flash_device,
  249. };
  250. static int mx31lilly_baseboard;
  251. core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
  252. static void __init mx31lilly_board_init(void)
  253. {
  254. switch (mx31lilly_baseboard) {
  255. case MX31LILLY_NOBOARD:
  256. break;
  257. case MX31LILLY_DB:
  258. mx31lilly_db_init();
  259. break;
  260. default:
  261. printk(KERN_ERR "Illegal mx31lilly_baseboard type %d\n",
  262. mx31lilly_baseboard);
  263. }
  264. mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
  265. /* SPI */
  266. mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
  267. mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
  268. mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
  269. mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
  270. mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
  271. mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
  272. mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
  273. mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
  274. mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
  275. mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
  276. mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
  277. mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
  278. mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
  279. mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
  280. imx31_add_spi_imx0(&spi0_pdata);
  281. imx31_add_spi_imx1(&spi1_pdata);
  282. spi_register_board_info(&mc13783_dev, 1);
  283. platform_add_devices(devices, ARRAY_SIZE(devices));
  284. /* USB */
  285. lilly1131_usb_init();
  286. }
  287. static void __init mx31lilly_timer_init(void)
  288. {
  289. mx31_clocks_init(26000000);
  290. }
  291. static struct sys_timer mx31lilly_timer = {
  292. .init = mx31lilly_timer_init,
  293. };
  294. MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
  295. .phys_io = MX31_AIPS1_BASE_ADDR,
  296. .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
  297. .boot_params = MX3x_PHYS_OFFSET + 0x100,
  298. .map_io = mx31_map_io,
  299. .init_irq = mx31_init_irq,
  300. .init_machine = mx31lilly_board_init,
  301. .timer = &mx31lilly_timer,
  302. MACHINE_END