홈 탐색 도움말
가입하기 로그인
phyus
/
linux-vybrid_public
8
0
포크 0
파일 이슈 0 풀 리퀘스트 0 위키
트리: 38a81da220
브랜치 태그
linux-vybrid_pu...
/
arch
/
arm
/
mach-mmp
/
include
/
mach
/
regs-apbc.h

regs-apbc.h 4.3 KB
히스토리 Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121 
  1. /*
    2. 

  2.  * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h
    3. 

  3.  *
    4. 

  4.  *   Application Peripheral Bus Clock Unit
    5. 

  5.  *
    6. 

  6.  * This program is free software; you can redistribute it and/or modify
    7. 

  7.  * it under the terms of the GNU General Public License version 2 as
    8. 

  8.  * published by the Free Software Foundation.
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __ASM_MACH_REGS_APBC_H
    12. 

  12. #define __ASM_MACH_REGS_APBC_H
    13. 

  13. 

  14. #include <mach/addr-map.h>
    15. 

  15. 

  16. #define APBC_VIRT_BASE	(APB_VIRT_BASE + 0x015000)
    17. 

  17. #define APBC_REG(x)	(APBC_VIRT_BASE + (x))
    18. 

  18. 

  19. /*
    20. 

  20.  * APB clock register offsets for PXA168
    21. 

  21.  */
    22. 

  22. #define APBC_PXA168_UART1	APBC_REG(0x000)
    23. 

  23. #define APBC_PXA168_UART2	APBC_REG(0x004)
    24. 

  24. #define APBC_PXA168_GPIO	APBC_REG(0x008)
    25. 

  25. #define APBC_PXA168_PWM1	APBC_REG(0x00c)
    26. 

  26. #define APBC_PXA168_PWM2	APBC_REG(0x010)
    27. 

  27. #define APBC_PXA168_PWM3	APBC_REG(0x014)
    28. 

  28. #define APBC_PXA168_PWM4	APBC_REG(0x018)
    29. 

  29. #define APBC_PXA168_RTC		APBC_REG(0x028)
    30. 

  30. #define APBC_PXA168_TWSI0	APBC_REG(0x02c)
    31. 

  31. #define APBC_PXA168_KPC		APBC_REG(0x030)
    32. 

  32. #define APBC_PXA168_TIMERS	APBC_REG(0x034)
    33. 

  33. #define APBC_PXA168_AIB		APBC_REG(0x03c)
    34. 

  34. #define APBC_PXA168_SW_JTAG	APBC_REG(0x040)
    35. 

  35. #define APBC_PXA168_ONEWIRE	APBC_REG(0x048)
    36. 

  36. #define APBC_PXA168_ASFAR	APBC_REG(0x050)
    37. 

  37. #define APBC_PXA168_ASSAR	APBC_REG(0x054)
    38. 

  38. #define APBC_PXA168_TWSI1	APBC_REG(0x06c)
    39. 

  39. #define APBC_PXA168_UART3	APBC_REG(0x070)
    40. 

  40. #define APBC_PXA168_AC97	APBC_REG(0x084)
    41. 

  41. #define APBC_PXA168_SSP1	APBC_REG(0x81c)
    42. 

  42. #define APBC_PXA168_SSP2	APBC_REG(0x820)
    43. 

  43. #define APBC_PXA168_SSP3	APBC_REG(0x84c)
    44. 

  44. #define APBC_PXA168_SSP4	APBC_REG(0x858)
    45. 

  45. #define APBC_PXA168_SSP5	APBC_REG(0x85c)
    46. 

  46. 

  47. /*
    48. 

  48.  * APB Clock register offsets for PXA910
    49. 

  49.  */
    50. 

  50. #define APBC_PXA910_UART0	APBC_REG(0x000)
    51. 

  51. #define APBC_PXA910_UART1	APBC_REG(0x004)
    52. 

  52. #define APBC_PXA910_GPIO	APBC_REG(0x008)
    53. 

  53. #define APBC_PXA910_PWM1	APBC_REG(0x00c)
    54. 

  54. #define APBC_PXA910_PWM2	APBC_REG(0x010)
    55. 

  55. #define APBC_PXA910_PWM3	APBC_REG(0x014)
    56. 

  56. #define APBC_PXA910_PWM4	APBC_REG(0x018)
    57. 

  57. #define APBC_PXA910_SSP1	APBC_REG(0x01c)
    58. 

  58. #define APBC_PXA910_SSP2	APBC_REG(0x020)
    59. 

  59. #define APBC_PXA910_IPC		APBC_REG(0x024)
    60. 

  60. #define APBC_PXA910_TWSI0	APBC_REG(0x02c)
    61. 

  61. #define APBC_PXA910_KPC		APBC_REG(0x030)
    62. 

  62. #define APBC_PXA910_TIMERS	APBC_REG(0x034)
    63. 

  63. #define APBC_PXA910_TBROT	APBC_REG(0x038)
    64. 

  64. #define APBC_PXA910_AIB		APBC_REG(0x03c)
    65. 

  65. #define APBC_PXA910_SW_JTAG	APBC_REG(0x040)
    66. 

  66. #define APBC_PXA910_TIMERS1	APBC_REG(0x044)
    67. 

  67. #define APBC_PXA910_ONEWIRE	APBC_REG(0x048)
    68. 

  68. #define APBC_PXA910_SSP3	APBC_REG(0x04c)
    69. 

  69. #define APBC_PXA910_ASFAR	APBC_REG(0x050)
    70. 

  70. #define APBC_PXA910_ASSAR	APBC_REG(0x054)
    71. 

  71. 

  72. /*
    73. 

  73.  * APB Clock register offsets for MMP2
    74. 

  74.  */
    75. 

  75. #define APBC_MMP2_RTC		APBC_REG(0x000)
    76. 

  76. #define APBC_MMP2_TWSI1		APBC_REG(0x004)
    77. 

  77. #define APBC_MMP2_TWSI2		APBC_REG(0x008)
    78. 

  78. #define APBC_MMP2_TWSI3		APBC_REG(0x00c)
    79. 

  79. #define APBC_MMP2_TWSI4		APBC_REG(0x010)
    80. 

  80. #define APBC_MMP2_ONEWIRE	APBC_REG(0x014)
    81. 

  81. #define APBC_MMP2_KPC		APBC_REG(0x018)
    82. 

  82. #define APBC_MMP2_TB_ROTARY	APBC_REG(0x01c)
    83. 

  83. #define APBC_MMP2_SW_JTAG	APBC_REG(0x020)
    84. 

  84. #define APBC_MMP2_TIMERS	APBC_REG(0x024)
    85. 

  85. #define APBC_MMP2_UART1		APBC_REG(0x02c)
    86. 

  86. #define APBC_MMP2_UART2		APBC_REG(0x030)
    87. 

  87. #define APBC_MMP2_UART3		APBC_REG(0x034)
    88. 

  88. #define APBC_MMP2_GPIO		APBC_REG(0x038)
    89. 

  89. #define APBC_MMP2_PWM0		APBC_REG(0x03c)
    90. 

  90. #define APBC_MMP2_PWM1		APBC_REG(0x040)
    91. 

  91. #define APBC_MMP2_PWM2		APBC_REG(0x044)
    92. 

  92. #define APBC_MMP2_PWM3		APBC_REG(0x048)
    93. 

  93. #define APBC_MMP2_SSP0		APBC_REG(0x04c)
    94. 

  94. #define APBC_MMP2_SSP1		APBC_REG(0x050)
    95. 

  95. #define APBC_MMP2_SSP2		APBC_REG(0x054)
    96. 

  96. #define APBC_MMP2_SSP3		APBC_REG(0x058)
    97. 

  97. #define APBC_MMP2_SSP4		APBC_REG(0x05c)
    98. 

  98. #define APBC_MMP2_SSP5		APBC_REG(0x060)
    99. 

  99. #define APBC_MMP2_AIB		APBC_REG(0x064)
    100. 

  100. #define APBC_MMP2_ASFAR		APBC_REG(0x068)
    101. 

  101. #define APBC_MMP2_ASSAR		APBC_REG(0x06c)
    102. 

  102. #define APBC_MMP2_USIM		APBC_REG(0x070)
    103. 

  103. #define APBC_MMP2_MPMU		APBC_REG(0x074)
    104. 

  104. #define APBC_MMP2_IPC		APBC_REG(0x078)
    105. 

  105. #define APBC_MMP2_TWSI5		APBC_REG(0x07c)
    106. 

  106. #define APBC_MMP2_TWSI6		APBC_REG(0x080)
    107. 

  107. #define APBC_MMP2_TWSI_INTSTS	APBC_REG(0x084)
    108. 

  108. #define APBC_MMP2_UART4		APBC_REG(0x088)
    109. 

  109. #define APBC_MMP2_RIPC		APBC_REG(0x08c)
    110. 

  110. #define APBC_MMP2_THSENS1	APBC_REG(0x090)	/* Thermal Sensor */
    111. 

  111. #define APBC_MMP2_THSENS_INTSTS	APBC_REG(0x0a4)
    112. 

  112. 

  113. /* Common APB clock register bit definitions */
    114. 

  114. #define APBC_APBCLK	(1 << 0)  /* APB Bus Clock Enable */
    115. 

  115. #define APBC_FNCLK	(1 << 1)  /* Functional Clock Enable */
    116. 

  116. #define APBC_RST	(1 << 2)  /* Reset Generation */
    117. 

  117. 

  118. /* Functional Clock Selection Mask */
    119. 

  119. #define APBC_FNCLKSEL(x)	(((x) & 0xf) << 4)
    120. 

  120. 

  121. #endif /* __ASM_MACH_REGS_APBC_H */
    122.