pcie.c 6.3 KB

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  1. /*
  2. * arch/arm/mach-kirkwood/pcie.c
  3. *
  4. * PCIe functions for Marvell Kirkwood SoCs
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/pci.h>
  12. #include <linux/slab.h>
  13. #include <linux/mbus.h>
  14. #include <asm/irq.h>
  15. #include <asm/mach/pci.h>
  16. #include <plat/pcie.h>
  17. #include <mach/bridge-regs.h>
  18. #include "common.h"
  19. void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
  20. {
  21. *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
  22. *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
  23. }
  24. struct pcie_port {
  25. u8 root_bus_nr;
  26. void __iomem *base;
  27. spinlock_t conf_lock;
  28. int irq;
  29. struct resource res[2];
  30. };
  31. static int pcie_port_map[2];
  32. static int num_pcie_ports;
  33. static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
  34. {
  35. struct pci_sys_data *sys = bus->sysdata;
  36. return sys->private_data;
  37. }
  38. static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
  39. {
  40. /*
  41. * Don't go out when trying to access --
  42. * 1. nonexisting device on local bus
  43. * 2. where there's no device connected (no link)
  44. */
  45. if (bus == pp->root_bus_nr && dev == 0)
  46. return 1;
  47. if (!orion_pcie_link_up(pp->base))
  48. return 0;
  49. if (bus == pp->root_bus_nr && dev != 1)
  50. return 0;
  51. return 1;
  52. }
  53. /*
  54. * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
  55. * and then reading the PCIE_CONF_DATA register. Need to make sure these
  56. * transactions are atomic.
  57. */
  58. static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  59. int size, u32 *val)
  60. {
  61. struct pcie_port *pp = bus_to_port(bus);
  62. unsigned long flags;
  63. int ret;
  64. if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
  65. *val = 0xffffffff;
  66. return PCIBIOS_DEVICE_NOT_FOUND;
  67. }
  68. spin_lock_irqsave(&pp->conf_lock, flags);
  69. ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
  70. spin_unlock_irqrestore(&pp->conf_lock, flags);
  71. return ret;
  72. }
  73. static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
  74. int where, int size, u32 val)
  75. {
  76. struct pcie_port *pp = bus_to_port(bus);
  77. unsigned long flags;
  78. int ret;
  79. if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
  80. return PCIBIOS_DEVICE_NOT_FOUND;
  81. spin_lock_irqsave(&pp->conf_lock, flags);
  82. ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
  83. spin_unlock_irqrestore(&pp->conf_lock, flags);
  84. return ret;
  85. }
  86. static struct pci_ops pcie_ops = {
  87. .read = pcie_rd_conf,
  88. .write = pcie_wr_conf,
  89. };
  90. static void __init pcie0_ioresources_init(struct pcie_port *pp)
  91. {
  92. pp->base = (void __iomem *)PCIE_VIRT_BASE;
  93. pp->irq = IRQ_KIRKWOOD_PCIE;
  94. /*
  95. * IORESOURCE_IO
  96. */
  97. pp->res[0].name = "PCIe 0 I/O Space";
  98. pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
  99. pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
  100. pp->res[0].flags = IORESOURCE_IO;
  101. /*
  102. * IORESOURCE_MEM
  103. */
  104. pp->res[1].name = "PCIe 0 MEM";
  105. pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
  106. pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
  107. pp->res[1].flags = IORESOURCE_MEM;
  108. }
  109. static void __init pcie1_ioresources_init(struct pcie_port *pp)
  110. {
  111. pp->base = (void __iomem *)PCIE1_VIRT_BASE;
  112. pp->irq = IRQ_KIRKWOOD_PCIE1;
  113. /*
  114. * IORESOURCE_IO
  115. */
  116. pp->res[0].name = "PCIe 1 I/O Space";
  117. pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
  118. pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
  119. pp->res[0].flags = IORESOURCE_IO;
  120. /*
  121. * IORESOURCE_MEM
  122. */
  123. pp->res[1].name = "PCIe 1 MEM";
  124. pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
  125. pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
  126. pp->res[1].flags = IORESOURCE_MEM;
  127. }
  128. static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
  129. {
  130. extern unsigned int kirkwood_clk_ctrl;
  131. struct pcie_port *pp;
  132. int index;
  133. if (nr >= num_pcie_ports)
  134. return 0;
  135. index = pcie_port_map[nr];
  136. printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
  137. pp = kzalloc(sizeof(*pp), GFP_KERNEL);
  138. if (!pp)
  139. panic("PCIe: failed to allocate pcie_port data");
  140. sys->private_data = pp;
  141. pp->root_bus_nr = sys->busnr;
  142. spin_lock_init(&pp->conf_lock);
  143. switch (index) {
  144. case 0:
  145. kirkwood_clk_ctrl |= CGC_PEX0;
  146. pcie0_ioresources_init(pp);
  147. break;
  148. case 1:
  149. kirkwood_clk_ctrl |= CGC_PEX1;
  150. pcie1_ioresources_init(pp);
  151. break;
  152. default:
  153. panic("PCIe setup: invalid controller %d", index);
  154. }
  155. if (request_resource(&ioport_resource, &pp->res[0]))
  156. panic("Request PCIe%d IO resource failed\n", index);
  157. if (request_resource(&iomem_resource, &pp->res[1]))
  158. panic("Request PCIe%d Memory resource failed\n", index);
  159. sys->resource[0] = &pp->res[0];
  160. sys->resource[1] = &pp->res[1];
  161. sys->resource[2] = NULL;
  162. sys->io_offset = 0;
  163. /*
  164. * Generic PCIe unit setup.
  165. */
  166. orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
  167. orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
  168. return 1;
  169. }
  170. static void __devinit rc_pci_fixup(struct pci_dev *dev)
  171. {
  172. /*
  173. * Prevent enumeration of root complex.
  174. */
  175. if (dev->bus->parent == NULL && dev->devfn == 0) {
  176. int i;
  177. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  178. dev->resource[i].start = 0;
  179. dev->resource[i].end = 0;
  180. dev->resource[i].flags = 0;
  181. }
  182. }
  183. }
  184. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
  185. static struct pci_bus __init *
  186. kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
  187. {
  188. struct pci_bus *bus;
  189. if (nr < num_pcie_ports) {
  190. bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
  191. } else {
  192. bus = NULL;
  193. BUG();
  194. }
  195. return bus;
  196. }
  197. static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  198. {
  199. struct pcie_port *pp = bus_to_port(dev->bus);
  200. return pp->irq;
  201. }
  202. static struct hw_pci kirkwood_pci __initdata = {
  203. .swizzle = pci_std_swizzle,
  204. .setup = kirkwood_pcie_setup,
  205. .scan = kirkwood_pcie_scan_bus,
  206. .map_irq = kirkwood_pcie_map_irq,
  207. };
  208. static void __init add_pcie_port(int index, unsigned long base)
  209. {
  210. printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
  211. if (orion_pcie_link_up((void __iomem *)base)) {
  212. printk(KERN_INFO "link up\n");
  213. pcie_port_map[num_pcie_ports++] = index;
  214. } else
  215. printk(KERN_INFO "link down, ignoring\n");
  216. }
  217. void __init kirkwood_pcie_init(unsigned int portmask)
  218. {
  219. if (portmask & KW_PCIE0)
  220. add_pcie_port(0, PCIE_VIRT_BASE);
  221. if (portmask & KW_PCIE1)
  222. add_pcie_port(1, PCIE1_VIRT_BASE);
  223. kirkwood_pci.nr_controllers = num_pcie_ports;
  224. pci_common_init(&kirkwood_pci);
  225. }