pci.c 6.1 KB

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  1. /*
  2. * arch/arm/mach-ixp23xx/pci.c
  3. *
  4. * PCI routines for IXP23XX based systems
  5. *
  6. * Copyright (c) 2005 MontaVista Software, Inc.
  7. *
  8. * based on original code:
  9. *
  10. * Author: Naeem Afzal <naeem.m.afzal@intel.com>
  11. * Copyright 2002-2005 Intel Corp.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/sched.h>
  19. #include <linux/kernel.h>
  20. #include <linux/pci.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/mm.h>
  23. #include <linux/init.h>
  24. #include <linux/ioport.h>
  25. #include <linux/delay.h>
  26. #include <linux/io.h>
  27. #include <asm/irq.h>
  28. #include <asm/sizes.h>
  29. #include <asm/system.h>
  30. #include <asm/mach/pci.h>
  31. #include <mach/hardware.h>
  32. extern int (*external_fault) (unsigned long, struct pt_regs *);
  33. static volatile int pci_master_aborts = 0;
  34. #ifdef DEBUG
  35. #define DBG(x...) printk(x)
  36. #else
  37. #define DBG(x...)
  38. #endif
  39. int clear_master_aborts(void);
  40. static u32
  41. *ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
  42. {
  43. u32 *paddress;
  44. /*
  45. * Must be dword aligned
  46. */
  47. where &= ~3;
  48. /*
  49. * For top bus, generate type 0, else type 1
  50. */
  51. if (!bus_nr) {
  52. if (PCI_SLOT(devfn) >= 8)
  53. return 0;
  54. paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
  55. | (1 << (PCI_SLOT(devfn) + 16))
  56. | (PCI_FUNC(devfn) << 8) | where);
  57. } else {
  58. paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
  59. | (bus_nr << 16)
  60. | (PCI_SLOT(devfn) << 11)
  61. | (PCI_FUNC(devfn) << 8) | where);
  62. }
  63. return paddress;
  64. }
  65. /*
  66. * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
  67. * 0 and 3 are not valid indexes...
  68. */
  69. static u32 bytemask[] = {
  70. /*0*/ 0,
  71. /*1*/ 0xff,
  72. /*2*/ 0xffff,
  73. /*3*/ 0,
  74. /*4*/ 0xffffffff,
  75. };
  76. static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  77. int where, int size, u32 *value)
  78. {
  79. u32 n;
  80. u32 *addr;
  81. n = where % 4;
  82. DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
  83. bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
  84. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  85. if (!addr)
  86. return PCIBIOS_DEVICE_NOT_FOUND;
  87. pci_master_aborts = 0;
  88. *value = (*addr >> (8*n)) & bytemask[size];
  89. if (pci_master_aborts) {
  90. pci_master_aborts = 0;
  91. *value = 0xffffffff;
  92. return PCIBIOS_DEVICE_NOT_FOUND;
  93. }
  94. return PCIBIOS_SUCCESSFUL;
  95. }
  96. /*
  97. * We don't do error checking on the address for writes.
  98. * It's assumed that the user checked for the device existing first
  99. * by doing a read first.
  100. */
  101. static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  102. int where, int size, u32 value)
  103. {
  104. u32 mask;
  105. u32 *addr;
  106. u32 temp;
  107. mask = ~(bytemask[size] << ((where % 0x4) * 8));
  108. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  109. if (!addr)
  110. return PCIBIOS_DEVICE_NOT_FOUND;
  111. temp = (u32) (value) << ((where % 0x4) * 8);
  112. *addr = (*addr & mask) | temp;
  113. clear_master_aborts();
  114. return PCIBIOS_SUCCESSFUL;
  115. }
  116. struct pci_ops ixp23xx_pci_ops = {
  117. .read = ixp23xx_pci_read_config,
  118. .write = ixp23xx_pci_write_config,
  119. };
  120. struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
  121. {
  122. return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
  123. }
  124. int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  125. {
  126. volatile unsigned long temp;
  127. unsigned long flags;
  128. pci_master_aborts = 1;
  129. local_irq_save(flags);
  130. temp = *IXP23XX_PCI_CONTROL;
  131. /*
  132. * master abort and cmd tgt err
  133. */
  134. if (temp & ((1 << 8) | (1 << 5)))
  135. *IXP23XX_PCI_CONTROL = temp;
  136. temp = *IXP23XX_PCI_CMDSTAT;
  137. if (temp & (1 << 29))
  138. *IXP23XX_PCI_CMDSTAT = temp;
  139. local_irq_restore(flags);
  140. /*
  141. * If it was an imprecise abort, then we need to correct the
  142. * return address to be _after_ the instruction.
  143. */
  144. if (fsr & (1 << 10))
  145. regs->ARM_pc += 4;
  146. return 0;
  147. }
  148. int clear_master_aborts(void)
  149. {
  150. volatile u32 temp;
  151. temp = *IXP23XX_PCI_CONTROL;
  152. /*
  153. * master abort and cmd tgt err
  154. */
  155. if (temp & ((1 << 8) | (1 << 5)))
  156. *IXP23XX_PCI_CONTROL = temp;
  157. temp = *IXP23XX_PCI_CMDSTAT;
  158. if (temp & (1 << 29))
  159. *IXP23XX_PCI_CMDSTAT = temp;
  160. return 0;
  161. }
  162. static void __init ixp23xx_pci_common_init(void)
  163. {
  164. #ifdef __ARMEB__
  165. *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
  166. #endif
  167. /*
  168. * ADDR_31 needs to be clear for PCI memory access to CPP memory
  169. */
  170. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
  171. *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
  172. /*
  173. * Select correct memory for PCI inbound transactions
  174. */
  175. if (ixp23xx_cpp_boot()) {
  176. *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
  177. } else {
  178. *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
  179. /*
  180. * Enable coherency on A2 silicon.
  181. */
  182. if (arch_is_coherent())
  183. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
  184. }
  185. }
  186. void __init ixp23xx_pci_preinit(void)
  187. {
  188. ixp23xx_pci_common_init();
  189. hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
  190. "PCI config cycle to non-existent device");
  191. *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
  192. }
  193. /*
  194. * Prevent PCI layer from seeing the inbound host-bridge resources
  195. */
  196. static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
  197. {
  198. int i;
  199. dev->class &= 0xff;
  200. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  201. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  202. dev->resource[i].start = 0;
  203. dev->resource[i].end = 0;
  204. dev->resource[i].flags = 0;
  205. }
  206. }
  207. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
  208. /*
  209. * IXP2300 systems often have large resource requirements, so we just
  210. * use our own resource space.
  211. */
  212. static struct resource ixp23xx_pci_mem_space = {
  213. .start = IXP23XX_PCI_MEM_START,
  214. .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
  215. .flags = IORESOURCE_MEM,
  216. .name = "PCI Mem Space"
  217. };
  218. static struct resource ixp23xx_pci_io_space = {
  219. .start = 0x00000100,
  220. .end = 0x01ffffff,
  221. .flags = IORESOURCE_IO,
  222. .name = "PCI I/O Space"
  223. };
  224. int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
  225. {
  226. if (nr >= 1)
  227. return 0;
  228. sys->resource[0] = &ixp23xx_pci_io_space;
  229. sys->resource[1] = &ixp23xx_pci_mem_space;
  230. sys->resource[2] = NULL;
  231. return 1;
  232. }
  233. void __init ixp23xx_pci_slave_init(void)
  234. {
  235. ixp23xx_pci_common_init();
  236. }