mach-pca100.c 11 KB

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  1. /*
  2. * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
  3. * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17. * MA 02110-1301, USA.
  18. */
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/i2c.h>
  22. #include <linux/i2c/at24.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/spi/eeprom.h>
  26. #include <linux/irq.h>
  27. #include <linux/delay.h>
  28. #include <linux/gpio.h>
  29. #include <linux/usb/otg.h>
  30. #include <linux/usb/ulpi.h>
  31. #include <linux/fsl_devices.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach-types.h>
  34. #include <mach/common.h>
  35. #include <mach/hardware.h>
  36. #include <mach/iomux-mx27.h>
  37. #include <asm/mach/time.h>
  38. #include <mach/audmux.h>
  39. #include <mach/ssi.h>
  40. #include <mach/mxc_nand.h>
  41. #include <mach/irqs.h>
  42. #include <mach/mmc.h>
  43. #include <mach/mxc_ehci.h>
  44. #include <mach/ulpi.h>
  45. #include <mach/imxfb.h>
  46. #include "devices-imx27.h"
  47. #include "devices.h"
  48. #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
  49. #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
  50. #define SPI1_SS0 (GPIO_PORTD + 28)
  51. #define SPI1_SS1 (GPIO_PORTD + 27)
  52. #define SD2_CD (GPIO_PORTC + 29)
  53. static int pca100_pins[] = {
  54. /* UART1 */
  55. PE12_PF_UART1_TXD,
  56. PE13_PF_UART1_RXD,
  57. PE14_PF_UART1_CTS,
  58. PE15_PF_UART1_RTS,
  59. /* SDHC */
  60. PB4_PF_SD2_D0,
  61. PB5_PF_SD2_D1,
  62. PB6_PF_SD2_D2,
  63. PB7_PF_SD2_D3,
  64. PB8_PF_SD2_CMD,
  65. PB9_PF_SD2_CLK,
  66. SD2_CD | GPIO_GPIO | GPIO_IN,
  67. /* FEC */
  68. PD0_AIN_FEC_TXD0,
  69. PD1_AIN_FEC_TXD1,
  70. PD2_AIN_FEC_TXD2,
  71. PD3_AIN_FEC_TXD3,
  72. PD4_AOUT_FEC_RX_ER,
  73. PD5_AOUT_FEC_RXD1,
  74. PD6_AOUT_FEC_RXD2,
  75. PD7_AOUT_FEC_RXD3,
  76. PD8_AF_FEC_MDIO,
  77. PD9_AIN_FEC_MDC,
  78. PD10_AOUT_FEC_CRS,
  79. PD11_AOUT_FEC_TX_CLK,
  80. PD12_AOUT_FEC_RXD0,
  81. PD13_AOUT_FEC_RX_DV,
  82. PD14_AOUT_FEC_RX_CLK,
  83. PD15_AOUT_FEC_COL,
  84. PD16_AIN_FEC_TX_ER,
  85. PF23_AIN_FEC_TX_EN,
  86. /* SSI1 */
  87. PC20_PF_SSI1_FS,
  88. PC21_PF_SSI1_RXD,
  89. PC22_PF_SSI1_TXD,
  90. PC23_PF_SSI1_CLK,
  91. /* onboard I2C */
  92. PC5_PF_I2C2_SDA,
  93. PC6_PF_I2C2_SCL,
  94. /* external I2C */
  95. PD17_PF_I2C_DATA,
  96. PD18_PF_I2C_CLK,
  97. /* SPI1 */
  98. PD25_PF_CSPI1_RDY,
  99. PD29_PF_CSPI1_SCLK,
  100. PD30_PF_CSPI1_MISO,
  101. PD31_PF_CSPI1_MOSI,
  102. /* OTG */
  103. OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
  104. PC7_PF_USBOTG_DATA5,
  105. PC8_PF_USBOTG_DATA6,
  106. PC9_PF_USBOTG_DATA0,
  107. PC10_PF_USBOTG_DATA2,
  108. PC11_PF_USBOTG_DATA1,
  109. PC12_PF_USBOTG_DATA4,
  110. PC13_PF_USBOTG_DATA3,
  111. PE0_PF_USBOTG_NXT,
  112. PE1_PF_USBOTG_STP,
  113. PE2_PF_USBOTG_DIR,
  114. PE24_PF_USBOTG_CLK,
  115. PE25_PF_USBOTG_DATA7,
  116. /* USBH2 */
  117. USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
  118. PA0_PF_USBH2_CLK,
  119. PA1_PF_USBH2_DIR,
  120. PA2_PF_USBH2_DATA7,
  121. PA3_PF_USBH2_NXT,
  122. PA4_PF_USBH2_STP,
  123. PD19_AF_USBH2_DATA4,
  124. PD20_AF_USBH2_DATA3,
  125. PD21_AF_USBH2_DATA6,
  126. PD22_AF_USBH2_DATA0,
  127. PD23_AF_USBH2_DATA2,
  128. PD24_AF_USBH2_DATA1,
  129. PD26_AF_USBH2_DATA5,
  130. /* display */
  131. PA5_PF_LSCLK,
  132. PA6_PF_LD0,
  133. PA7_PF_LD1,
  134. PA8_PF_LD2,
  135. PA9_PF_LD3,
  136. PA10_PF_LD4,
  137. PA11_PF_LD5,
  138. PA12_PF_LD6,
  139. PA13_PF_LD7,
  140. PA14_PF_LD8,
  141. PA15_PF_LD9,
  142. PA16_PF_LD10,
  143. PA17_PF_LD11,
  144. PA18_PF_LD12,
  145. PA19_PF_LD13,
  146. PA20_PF_LD14,
  147. PA21_PF_LD15,
  148. PA22_PF_LD16,
  149. PA23_PF_LD17,
  150. PA26_PF_PS,
  151. PA28_PF_HSYNC,
  152. PA29_PF_VSYNC,
  153. PA31_PF_OE_ACD,
  154. /* free GPIO */
  155. GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
  156. GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
  157. GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
  158. };
  159. static const struct imxuart_platform_data uart_pdata __initconst = {
  160. .flags = IMXUART_HAVE_RTSCTS,
  161. };
  162. static const struct mxc_nand_platform_data
  163. pca100_nand_board_info __initconst = {
  164. .width = 1,
  165. .hw_ecc = 1,
  166. };
  167. static struct platform_device *platform_devices[] __initdata = {
  168. &mxc_w1_master_device,
  169. &mxc_fec_device,
  170. &mxc_wdt,
  171. };
  172. static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
  173. .bitrate = 100000,
  174. };
  175. static struct at24_platform_data board_eeprom = {
  176. .byte_len = 4096,
  177. .page_size = 32,
  178. .flags = AT24_FLAG_ADDR16,
  179. };
  180. static struct i2c_board_info pca100_i2c_devices[] = {
  181. {
  182. I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
  183. .platform_data = &board_eeprom,
  184. }, {
  185. I2C_BOARD_INFO("rtc-pcf8563", 0x51),
  186. .type = "pcf8563"
  187. }, {
  188. I2C_BOARD_INFO("lm75", 0x4a),
  189. .type = "lm75"
  190. }
  191. };
  192. #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
  193. static struct spi_eeprom at25320 = {
  194. .name = "at25320an",
  195. .byte_len = 4096,
  196. .page_size = 32,
  197. .flags = EE_ADDR2,
  198. };
  199. static struct spi_board_info pca100_spi_board_info[] __initdata = {
  200. {
  201. .modalias = "at25",
  202. .max_speed_hz = 30000,
  203. .bus_num = 0,
  204. .chip_select = 1,
  205. .platform_data = &at25320,
  206. },
  207. };
  208. static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
  209. static const struct spi_imx_master pca100_spi0_data __initconst = {
  210. .chipselect = pca100_spi_cs,
  211. .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
  212. };
  213. #endif
  214. static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
  215. {
  216. mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
  217. gpio_set_value(GPIO_PORTC + 20, 1);
  218. udelay(2);
  219. gpio_set_value(GPIO_PORTC + 20, 0);
  220. mxc_gpio_mode(PC20_PF_SSI1_FS);
  221. msleep(2);
  222. }
  223. static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
  224. {
  225. mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */
  226. gpio_set_value(GPIO_PORTC + 20, 0);
  227. mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */
  228. gpio_set_value(GPIO_PORTC + 22, 0);
  229. mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */
  230. gpio_set_value(GPIO_PORTC + 28, 0);
  231. udelay(10);
  232. gpio_set_value(GPIO_PORTC + 28, 1);
  233. mxc_gpio_mode(PC20_PF_SSI1_FS);
  234. mxc_gpio_mode(PC22_PF_SSI1_TXD);
  235. msleep(2);
  236. }
  237. static struct imx_ssi_platform_data pca100_ssi_pdata = {
  238. .ac97_reset = pca100_ac97_cold_reset,
  239. .ac97_warm_reset = pca100_ac97_warm_reset,
  240. .flags = IMX_SSI_USE_AC97,
  241. };
  242. static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
  243. void *data)
  244. {
  245. int ret;
  246. ret = request_irq(IRQ_GPIOC(29), detect_irq,
  247. IRQF_DISABLED | IRQF_TRIGGER_FALLING,
  248. "imx-mmc-detect", data);
  249. if (ret)
  250. printk(KERN_ERR
  251. "pca100: Failed to reuest irq for sd/mmc detection\n");
  252. return ret;
  253. }
  254. static void pca100_sdhc2_exit(struct device *dev, void *data)
  255. {
  256. free_irq(IRQ_GPIOC(29), data);
  257. }
  258. static struct imxmmc_platform_data sdhc_pdata = {
  259. .init = pca100_sdhc2_init,
  260. .exit = pca100_sdhc2_exit,
  261. };
  262. #if defined(CONFIG_USB_ULPI)
  263. static int otg_phy_init(struct platform_device *pdev)
  264. {
  265. gpio_set_value(OTG_PHY_CS_GPIO, 0);
  266. return 0;
  267. }
  268. static struct mxc_usbh_platform_data otg_pdata = {
  269. .init = otg_phy_init,
  270. .portsc = MXC_EHCI_MODE_ULPI,
  271. .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
  272. };
  273. static int usbh2_phy_init(struct platform_device *pdev)
  274. {
  275. gpio_set_value(USBH2_PHY_CS_GPIO, 0);
  276. return 0;
  277. }
  278. static struct mxc_usbh_platform_data usbh2_pdata = {
  279. .init = usbh2_phy_init,
  280. .portsc = MXC_EHCI_MODE_ULPI,
  281. .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
  282. };
  283. #endif
  284. static struct fsl_usb2_platform_data otg_device_pdata = {
  285. .operating_mode = FSL_USB2_DR_DEVICE,
  286. .phy_mode = FSL_USB2_PHY_ULPI,
  287. };
  288. static int otg_mode_host;
  289. static int __init pca100_otg_mode(char *options)
  290. {
  291. if (!strcmp(options, "host"))
  292. otg_mode_host = 1;
  293. else if (!strcmp(options, "device"))
  294. otg_mode_host = 0;
  295. else
  296. pr_info("otg_mode neither \"host\" nor \"device\". "
  297. "Defaulting to device\n");
  298. return 0;
  299. }
  300. __setup("otg_mode=", pca100_otg_mode);
  301. /* framebuffer info */
  302. static struct imx_fb_videomode pca100_fb_modes[] = {
  303. {
  304. .mode = {
  305. .name = "EMERGING-ETV570G0DHU",
  306. .refresh = 60,
  307. .xres = 640,
  308. .yres = 480,
  309. .pixclock = 39722, /* in ps (25.175 MHz) */
  310. .hsync_len = 30,
  311. .left_margin = 114,
  312. .right_margin = 16,
  313. .vsync_len = 3,
  314. .upper_margin = 32,
  315. .lower_margin = 0,
  316. },
  317. /*
  318. * TFT
  319. * Pixel pol active high
  320. * HSYNC active low
  321. * VSYNC active low
  322. * use HSYNC for ACD count
  323. * line clock disable while idle
  324. * always enable line clock even if no data
  325. */
  326. .pcr = 0xf0c08080,
  327. .bpp = 16,
  328. },
  329. };
  330. static struct imx_fb_platform_data pca100_fb_data = {
  331. .mode = pca100_fb_modes,
  332. .num_modes = ARRAY_SIZE(pca100_fb_modes),
  333. .pwmr = 0x00A903FF,
  334. .lscr1 = 0x00120300,
  335. .dmacr = 0x00020010,
  336. };
  337. static void __init pca100_init(void)
  338. {
  339. int ret;
  340. /* SSI unit */
  341. mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
  342. MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
  343. MXC_AUDMUX_V1_PCR_TFCSEL(3) |
  344. MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
  345. MXC_AUDMUX_V1_PCR_RXDSEL(3));
  346. mxc_audmux_v1_configure_port(3,
  347. MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
  348. MXC_AUDMUX_V1_PCR_TFCSEL(0) |
  349. MXC_AUDMUX_V1_PCR_TFSDIR |
  350. MXC_AUDMUX_V1_PCR_RXDSEL(0));
  351. ret = mxc_gpio_setup_multiple_pins(pca100_pins,
  352. ARRAY_SIZE(pca100_pins), "PCA100");
  353. if (ret)
  354. printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
  355. mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
  356. imx27_add_imx_uart0(&uart_pdata);
  357. mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
  358. imx27_add_mxc_nand(&pca100_nand_board_info);
  359. /* only the i2c master 1 is used on this CPU card */
  360. i2c_register_board_info(1, pca100_i2c_devices,
  361. ARRAY_SIZE(pca100_i2c_devices));
  362. imx27_add_i2c_imx1(&pca100_i2c1_data);
  363. #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
  364. mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
  365. mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
  366. spi_register_board_info(pca100_spi_board_info,
  367. ARRAY_SIZE(pca100_spi_board_info));
  368. imx27_add_spi_imx0(&pca100_spi0_data);
  369. #endif
  370. gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
  371. gpio_direction_output(OTG_PHY_CS_GPIO, 1);
  372. gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
  373. gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
  374. #if defined(CONFIG_USB_ULPI)
  375. if (otg_mode_host) {
  376. otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
  377. ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
  378. mxc_register_device(&mxc_otg_host, &otg_pdata);
  379. }
  380. usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
  381. ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
  382. mxc_register_device(&mxc_usbh2, &usbh2_pdata);
  383. #endif
  384. if (!otg_mode_host) {
  385. gpio_set_value(OTG_PHY_CS_GPIO, 0);
  386. mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
  387. }
  388. mxc_register_device(&mxc_fb_device, &pca100_fb_data);
  389. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  390. }
  391. static void __init pca100_timer_init(void)
  392. {
  393. mx27_clocks_init(26000000);
  394. }
  395. static struct sys_timer pca100_timer = {
  396. .init = pca100_timer_init,
  397. };
  398. MACHINE_START(PCA100, "phyCARD-i.MX27")
  399. .phys_io = MX27_AIPI_BASE_ADDR,
  400. .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
  401. .boot_params = MX27_PHYS_OFFSET + 0x100,
  402. .map_io = mx27_map_io,
  403. .init_irq = mx27_init_irq,
  404. .init_machine = pca100_init,
  405. .timer = &pca100_timer,
  406. MACHINE_END