devices.c 15 KB

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  1. /*
  2. * Author: MontaVista Software, Inc.
  3. * <source@mvista.com>
  4. *
  5. * Based on the OMAP devices.c
  6. *
  7. * 2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. *
  12. * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  15. * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
  16. * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License
  20. * as published by the Free Software Foundation; either version 2
  21. * of the License, or (at your option) any later version.
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  30. * MA 02110-1301, USA.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/init.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/gpio.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/serial.h>
  39. #include <mach/irqs.h>
  40. #include <mach/hardware.h>
  41. #include <mach/common.h>
  42. #include <mach/mmc.h>
  43. #include "devices.h"
  44. #if defined(CONFIG_ARCH_MX1)
  45. static struct resource imx1_camera_resources[] = {
  46. {
  47. .start = 0x00224000,
  48. .end = 0x00224010,
  49. .flags = IORESOURCE_MEM,
  50. }, {
  51. .start = MX1_CSI_INT,
  52. .end = MX1_CSI_INT,
  53. .flags = IORESOURCE_IRQ,
  54. },
  55. };
  56. static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
  57. struct platform_device imx1_camera_device = {
  58. .name = "mx1-camera",
  59. .id = 0, /* This is used to put cameras on this interface */
  60. .dev = {
  61. .dma_mask = &imx1_camera_dmamask,
  62. .coherent_dma_mask = DMA_BIT_MASK(32),
  63. },
  64. .resource = imx1_camera_resources,
  65. .num_resources = ARRAY_SIZE(imx1_camera_resources),
  66. };
  67. static struct resource imx_rtc_resources[] = {
  68. {
  69. .start = 0x00204000,
  70. .end = 0x00204024,
  71. .flags = IORESOURCE_MEM,
  72. }, {
  73. .start = MX1_RTC_INT,
  74. .end = MX1_RTC_INT,
  75. .flags = IORESOURCE_IRQ,
  76. }, {
  77. .start = MX1_RTC_SAMINT,
  78. .end = MX1_RTC_SAMINT,
  79. .flags = IORESOURCE_IRQ,
  80. },
  81. };
  82. struct platform_device imx_rtc_device = {
  83. .name = "rtc-imx",
  84. .id = 0,
  85. .resource = imx_rtc_resources,
  86. .num_resources = ARRAY_SIZE(imx_rtc_resources),
  87. };
  88. static struct resource imx_wdt_resources[] = {
  89. {
  90. .start = 0x00201000,
  91. .end = 0x00201008,
  92. .flags = IORESOURCE_MEM,
  93. }, {
  94. .start = MX1_WDT_INT,
  95. .end = MX1_WDT_INT,
  96. .flags = IORESOURCE_IRQ,
  97. },
  98. };
  99. struct platform_device imx_wdt_device = {
  100. .name = "imx-wdt",
  101. .id = 0,
  102. .resource = imx_wdt_resources,
  103. .num_resources = ARRAY_SIZE(imx_wdt_resources),
  104. };
  105. static struct resource imx_usb_resources[] = {
  106. {
  107. .start = 0x00212000,
  108. .end = 0x00212148,
  109. .flags = IORESOURCE_MEM,
  110. }, {
  111. .start = MX1_USBD_INT0,
  112. .end = MX1_USBD_INT0,
  113. .flags = IORESOURCE_IRQ,
  114. }, {
  115. .start = MX1_USBD_INT1,
  116. .end = MX1_USBD_INT1,
  117. .flags = IORESOURCE_IRQ,
  118. }, {
  119. .start = MX1_USBD_INT2,
  120. .end = MX1_USBD_INT2,
  121. .flags = IORESOURCE_IRQ,
  122. }, {
  123. .start = MX1_USBD_INT3,
  124. .end = MX1_USBD_INT3,
  125. .flags = IORESOURCE_IRQ,
  126. }, {
  127. .start = MX1_USBD_INT4,
  128. .end = MX1_USBD_INT4,
  129. .flags = IORESOURCE_IRQ,
  130. }, {
  131. .start = MX1_USBD_INT5,
  132. .end = MX1_USBD_INT5,
  133. .flags = IORESOURCE_IRQ,
  134. }, {
  135. .start = MX1_USBD_INT6,
  136. .end = MX1_USBD_INT6,
  137. .flags = IORESOURCE_IRQ,
  138. },
  139. };
  140. struct platform_device imx_usb_device = {
  141. .name = "imx_udc",
  142. .id = 0,
  143. .num_resources = ARRAY_SIZE(imx_usb_resources),
  144. .resource = imx_usb_resources,
  145. };
  146. /* GPIO port description */
  147. static struct mxc_gpio_port imx_gpio_ports[] = {
  148. {
  149. .chip.label = "gpio-0",
  150. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
  151. .irq = MX1_GPIO_INT_PORTA,
  152. .virtual_irq_start = MXC_GPIO_IRQ_START,
  153. }, {
  154. .chip.label = "gpio-1",
  155. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
  156. .irq = MX1_GPIO_INT_PORTB,
  157. .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
  158. }, {
  159. .chip.label = "gpio-2",
  160. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
  161. .irq = MX1_GPIO_INT_PORTC,
  162. .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
  163. }, {
  164. .chip.label = "gpio-3",
  165. .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
  166. .irq = MX1_GPIO_INT_PORTD,
  167. .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
  168. }
  169. };
  170. int __init imx1_register_gpios(void)
  171. {
  172. return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
  173. }
  174. #endif
  175. #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
  176. #ifdef CONFIG_MACH_MX27
  177. static struct resource mx27_camera_resources[] = {
  178. {
  179. .start = MX27_CSI_BASE_ADDR,
  180. .end = MX27_CSI_BASE_ADDR + 0x1f,
  181. .flags = IORESOURCE_MEM,
  182. }, {
  183. .start = MX27_EMMA_PRP_BASE_ADDR,
  184. .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
  185. .flags = IORESOURCE_MEM,
  186. }, {
  187. .start = MX27_INT_CSI,
  188. .end = MX27_INT_CSI,
  189. .flags = IORESOURCE_IRQ,
  190. },{
  191. .start = MX27_INT_EMMAPRP,
  192. .end = MX27_INT_EMMAPRP,
  193. .flags = IORESOURCE_IRQ,
  194. },
  195. };
  196. struct platform_device mx27_camera_device = {
  197. .name = "mx2-camera",
  198. .id = 0,
  199. .num_resources = ARRAY_SIZE(mx27_camera_resources),
  200. .resource = mx27_camera_resources,
  201. .dev = {
  202. .coherent_dma_mask = 0xffffffff,
  203. },
  204. };
  205. #endif
  206. /*
  207. * General Purpose Timer
  208. * - i.MX21: 3 timers
  209. * - i.MX27: 6 timers
  210. */
  211. #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
  212. static struct resource timer ## n ##_resources[] = { \
  213. { \
  214. .start = baseaddr, \
  215. .end = baseaddr + SZ_4K - 1, \
  216. .flags = IORESOURCE_MEM, \
  217. }, { \
  218. .start = irq, \
  219. .end = irq, \
  220. .flags = IORESOURCE_IRQ, \
  221. } \
  222. }; \
  223. \
  224. struct platform_device mxc_gpt ## n = { \
  225. .name = "imx_gpt", \
  226. .id = n, \
  227. .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
  228. .resource = timer ## n ## _resources, \
  229. }
  230. /* We use gpt1 as system timer, so do not add a device for this one */
  231. DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
  232. DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
  233. #ifdef CONFIG_MACH_MX27
  234. DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
  235. DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
  236. DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
  237. #endif
  238. /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
  239. static struct resource mxc_wdt_resources[] = {
  240. {
  241. .start = MX2x_WDOG_BASE_ADDR,
  242. .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
  243. .flags = IORESOURCE_MEM,
  244. },
  245. };
  246. struct platform_device mxc_wdt = {
  247. .name = "imx2-wdt",
  248. .id = 0,
  249. .num_resources = ARRAY_SIZE(mxc_wdt_resources),
  250. .resource = mxc_wdt_resources,
  251. };
  252. static struct resource mxc_w1_master_resources[] = {
  253. {
  254. .start = MX2x_OWIRE_BASE_ADDR,
  255. .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
  256. .flags = IORESOURCE_MEM,
  257. },
  258. };
  259. struct platform_device mxc_w1_master_device = {
  260. .name = "mxc_w1",
  261. .id = 0,
  262. .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
  263. .resource = mxc_w1_master_resources,
  264. };
  265. /*
  266. * lcdc:
  267. * - i.MX1: the basic controller
  268. * - i.MX21: to be checked
  269. * - i.MX27: like i.MX1, with slightly variations
  270. */
  271. static struct resource mxc_fb[] = {
  272. {
  273. .start = MX2x_LCDC_BASE_ADDR,
  274. .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
  275. .flags = IORESOURCE_MEM,
  276. }, {
  277. .start = MX2x_INT_LCDC,
  278. .end = MX2x_INT_LCDC,
  279. .flags = IORESOURCE_IRQ,
  280. }
  281. };
  282. /* mxc lcd driver */
  283. struct platform_device mxc_fb_device = {
  284. .name = "imx-fb",
  285. .id = 0,
  286. .num_resources = ARRAY_SIZE(mxc_fb),
  287. .resource = mxc_fb,
  288. .dev = {
  289. .coherent_dma_mask = DMA_BIT_MASK(32),
  290. },
  291. };
  292. #ifdef CONFIG_MACH_MX27
  293. static struct resource mxc_fec_resources[] = {
  294. {
  295. .start = MX27_FEC_BASE_ADDR,
  296. .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
  297. .flags = IORESOURCE_MEM,
  298. }, {
  299. .start = MX27_INT_FEC,
  300. .end = MX27_INT_FEC,
  301. .flags = IORESOURCE_IRQ,
  302. },
  303. };
  304. struct platform_device mxc_fec_device = {
  305. .name = "fec",
  306. .id = 0,
  307. .num_resources = ARRAY_SIZE(mxc_fec_resources),
  308. .resource = mxc_fec_resources,
  309. };
  310. #endif
  311. static struct resource mxc_pwm_resources[] = {
  312. {
  313. .start = MX2x_PWM_BASE_ADDR,
  314. .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
  315. .flags = IORESOURCE_MEM,
  316. }, {
  317. .start = MX2x_INT_PWM,
  318. .end = MX2x_INT_PWM,
  319. .flags = IORESOURCE_IRQ,
  320. }
  321. };
  322. struct platform_device mxc_pwm_device = {
  323. .name = "mxc_pwm",
  324. .id = 0,
  325. .num_resources = ARRAY_SIZE(mxc_pwm_resources),
  326. .resource = mxc_pwm_resources,
  327. };
  328. #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
  329. static struct resource mxc_sdhc_resources ## n[] = { \
  330. { \
  331. .start = baseaddr, \
  332. .end = baseaddr + SZ_4K - 1, \
  333. .flags = IORESOURCE_MEM, \
  334. }, { \
  335. .start = irq, \
  336. .end = irq, \
  337. .flags = IORESOURCE_IRQ, \
  338. }, { \
  339. .start = dmareq, \
  340. .end = dmareq, \
  341. .flags = IORESOURCE_DMA, \
  342. }, \
  343. }; \
  344. \
  345. static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
  346. \
  347. struct platform_device mxc_sdhc_device ## n = { \
  348. .name = "mxc-mmc", \
  349. .id = n, \
  350. .dev = { \
  351. .dma_mask = &mxc_sdhc ## n ## _dmamask, \
  352. .coherent_dma_mask = DMA_BIT_MASK(32), \
  353. }, \
  354. .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
  355. .resource = mxc_sdhc_resources ## n, \
  356. }
  357. DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
  358. DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
  359. #ifdef CONFIG_MACH_MX27
  360. static struct resource otg_resources[] = {
  361. {
  362. .start = MX27_USBOTG_BASE_ADDR,
  363. .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
  364. .flags = IORESOURCE_MEM,
  365. }, {
  366. .start = MX27_INT_USB3,
  367. .end = MX27_INT_USB3,
  368. .flags = IORESOURCE_IRQ,
  369. },
  370. };
  371. static u64 otg_dmamask = DMA_BIT_MASK(32);
  372. /* OTG gadget device */
  373. struct platform_device mxc_otg_udc_device = {
  374. .name = "fsl-usb2-udc",
  375. .id = -1,
  376. .dev = {
  377. .dma_mask = &otg_dmamask,
  378. .coherent_dma_mask = DMA_BIT_MASK(32),
  379. },
  380. .resource = otg_resources,
  381. .num_resources = ARRAY_SIZE(otg_resources),
  382. };
  383. /* OTG host */
  384. struct platform_device mxc_otg_host = {
  385. .name = "mxc-ehci",
  386. .id = 0,
  387. .dev = {
  388. .coherent_dma_mask = DMA_BIT_MASK(32),
  389. .dma_mask = &otg_dmamask,
  390. },
  391. .resource = otg_resources,
  392. .num_resources = ARRAY_SIZE(otg_resources),
  393. };
  394. /* USB host 1 */
  395. static u64 usbh1_dmamask = DMA_BIT_MASK(32);
  396. static struct resource mxc_usbh1_resources[] = {
  397. {
  398. .start = MX27_USBOTG_BASE_ADDR + 0x200,
  399. .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
  400. .flags = IORESOURCE_MEM,
  401. }, {
  402. .start = MX27_INT_USB1,
  403. .end = MX27_INT_USB1,
  404. .flags = IORESOURCE_IRQ,
  405. },
  406. };
  407. struct platform_device mxc_usbh1 = {
  408. .name = "mxc-ehci",
  409. .id = 1,
  410. .dev = {
  411. .coherent_dma_mask = DMA_BIT_MASK(32),
  412. .dma_mask = &usbh1_dmamask,
  413. },
  414. .resource = mxc_usbh1_resources,
  415. .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
  416. };
  417. /* USB host 2 */
  418. static u64 usbh2_dmamask = DMA_BIT_MASK(32);
  419. static struct resource mxc_usbh2_resources[] = {
  420. {
  421. .start = MX27_USBOTG_BASE_ADDR + 0x400,
  422. .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
  423. .flags = IORESOURCE_MEM,
  424. }, {
  425. .start = MX27_INT_USB2,
  426. .end = MX27_INT_USB2,
  427. .flags = IORESOURCE_IRQ,
  428. },
  429. };
  430. struct platform_device mxc_usbh2 = {
  431. .name = "mxc-ehci",
  432. .id = 2,
  433. .dev = {
  434. .coherent_dma_mask = DMA_BIT_MASK(32),
  435. .dma_mask = &usbh2_dmamask,
  436. },
  437. .resource = mxc_usbh2_resources,
  438. .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
  439. };
  440. #endif
  441. #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
  442. { \
  443. .name = _name, \
  444. .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
  445. .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
  446. .flags = IORESOURCE_DMA, \
  447. }
  448. #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
  449. static struct resource imx_ssi_resources ## n[] = { \
  450. { \
  451. .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
  452. .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
  453. .flags = IORESOURCE_MEM, \
  454. }, { \
  455. .start = MX2x_INT_SSI1, \
  456. .end = MX2x_INT_SSI1, \
  457. .flags = IORESOURCE_IRQ, \
  458. }, \
  459. DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
  460. DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
  461. DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
  462. DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
  463. }; \
  464. \
  465. struct platform_device imx_ssi_device ## n = { \
  466. .name = "imx-ssi", \
  467. .id = n, \
  468. .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
  469. .resource = imx_ssi_resources ## n, \
  470. }
  471. DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
  472. DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
  473. /* GPIO port description */
  474. #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
  475. { \
  476. .chip.label = "gpio-" #n, \
  477. .irq = _irq, \
  478. .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
  479. n * 0x100), \
  480. .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
  481. }
  482. #define DEFINE_MXC_GPIO_PORT(SOC, n) \
  483. { \
  484. .chip.label = "gpio-" #n, \
  485. .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
  486. n * 0x100), \
  487. .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
  488. }
  489. #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
  490. static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
  491. DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
  492. DEFINE_MXC_GPIO_PORT(SOC, 1), \
  493. DEFINE_MXC_GPIO_PORT(SOC, 2), \
  494. DEFINE_MXC_GPIO_PORT(SOC, 3), \
  495. DEFINE_MXC_GPIO_PORT(SOC, 4), \
  496. DEFINE_MXC_GPIO_PORT(SOC, 5), \
  497. }
  498. #ifdef CONFIG_MACH_MX21
  499. DEFINE_MXC_GPIO_PORTS(MX21, imx21);
  500. int __init imx21_register_gpios(void)
  501. {
  502. return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
  503. }
  504. #endif
  505. #ifdef CONFIG_MACH_MX27
  506. DEFINE_MXC_GPIO_PORTS(MX27, imx27);
  507. int __init imx27_register_gpios(void)
  508. {
  509. return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
  510. }
  511. #endif
  512. #ifdef CONFIG_MACH_MX21
  513. static struct resource mx21_usbhc_resources[] = {
  514. {
  515. .start = MX21_USBOTG_BASE_ADDR,
  516. .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
  517. .flags = IORESOURCE_MEM,
  518. },
  519. {
  520. .start = MX21_INT_USBHOST,
  521. .end = MX21_INT_USBHOST,
  522. .flags = IORESOURCE_IRQ,
  523. },
  524. };
  525. struct platform_device mx21_usbhc_device = {
  526. .name = "imx21-hcd",
  527. .id = 0,
  528. .dev = {
  529. .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
  530. .coherent_dma_mask = DMA_BIT_MASK(32),
  531. },
  532. .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
  533. .resource = mx21_usbhc_resources,
  534. };
  535. #endif
  536. static struct resource imx_kpp_resources[] = {
  537. {
  538. .start = MX2x_KPP_BASE_ADDR,
  539. .end = MX2x_KPP_BASE_ADDR + 0xf,
  540. .flags = IORESOURCE_MEM
  541. }, {
  542. .start = MX2x_INT_KPP,
  543. .end = MX2x_INT_KPP,
  544. .flags = IORESOURCE_IRQ,
  545. },
  546. };
  547. struct platform_device imx_kpp_device = {
  548. .name = "imx-keypad",
  549. .id = -1,
  550. .num_resources = ARRAY_SIZE(imx_kpp_resources),
  551. .resource = imx_kpp_resources,
  552. };
  553. #endif