da850.c 29 KB

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  1. /*
  2. * TI DA850/OMAP-L138 chip specific setup
  3. *
  4. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * Derived from: arch/arm/mach-davinci/da830.c
  7. * Original Copyrights follow:
  8. *
  9. * 2009 (c) MontaVista Software, Inc. This file is licensed under
  10. * the terms of the GNU General Public License version 2. This program
  11. * is licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/clk.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/cpufreq.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <asm/mach/map.h>
  20. #include <mach/psc.h>
  21. #include <mach/irqs.h>
  22. #include <mach/cputype.h>
  23. #include <mach/common.h>
  24. #include <mach/time.h>
  25. #include <mach/da8xx.h>
  26. #include <mach/cpufreq.h>
  27. #include <mach/pm.h>
  28. #include <mach/gpio.h>
  29. #include "clock.h"
  30. #include "mux.h"
  31. /* SoC specific clock flags */
  32. #define DA850_CLK_ASYNC3 BIT(16)
  33. #define DA850_PLL1_BASE 0x01e1a000
  34. #define DA850_TIMER64P2_BASE 0x01f0c000
  35. #define DA850_TIMER64P3_BASE 0x01f0d000
  36. #define DA850_REF_FREQ 24000000
  37. #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
  38. #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
  39. #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
  40. static int da850_set_armrate(struct clk *clk, unsigned long rate);
  41. static int da850_round_armrate(struct clk *clk, unsigned long rate);
  42. static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
  43. static struct pll_data pll0_data = {
  44. .num = 1,
  45. .phys_base = DA8XX_PLL0_BASE,
  46. .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  47. };
  48. static struct clk ref_clk = {
  49. .name = "ref_clk",
  50. .rate = DA850_REF_FREQ,
  51. };
  52. static struct clk pll0_clk = {
  53. .name = "pll0",
  54. .parent = &ref_clk,
  55. .pll_data = &pll0_data,
  56. .flags = CLK_PLL,
  57. .set_rate = da850_set_pll0rate,
  58. };
  59. static struct clk pll0_aux_clk = {
  60. .name = "pll0_aux_clk",
  61. .parent = &pll0_clk,
  62. .flags = CLK_PLL | PRE_PLL,
  63. };
  64. static struct clk pll0_sysclk2 = {
  65. .name = "pll0_sysclk2",
  66. .parent = &pll0_clk,
  67. .flags = CLK_PLL,
  68. .div_reg = PLLDIV2,
  69. };
  70. static struct clk pll0_sysclk3 = {
  71. .name = "pll0_sysclk3",
  72. .parent = &pll0_clk,
  73. .flags = CLK_PLL,
  74. .div_reg = PLLDIV3,
  75. };
  76. static struct clk pll0_sysclk4 = {
  77. .name = "pll0_sysclk4",
  78. .parent = &pll0_clk,
  79. .flags = CLK_PLL,
  80. .div_reg = PLLDIV4,
  81. };
  82. static struct clk pll0_sysclk5 = {
  83. .name = "pll0_sysclk5",
  84. .parent = &pll0_clk,
  85. .flags = CLK_PLL,
  86. .div_reg = PLLDIV5,
  87. };
  88. static struct clk pll0_sysclk6 = {
  89. .name = "pll0_sysclk6",
  90. .parent = &pll0_clk,
  91. .flags = CLK_PLL,
  92. .div_reg = PLLDIV6,
  93. };
  94. static struct clk pll0_sysclk7 = {
  95. .name = "pll0_sysclk7",
  96. .parent = &pll0_clk,
  97. .flags = CLK_PLL,
  98. .div_reg = PLLDIV7,
  99. };
  100. static struct pll_data pll1_data = {
  101. .num = 2,
  102. .phys_base = DA850_PLL1_BASE,
  103. .flags = PLL_HAS_POSTDIV,
  104. };
  105. static struct clk pll1_clk = {
  106. .name = "pll1",
  107. .parent = &ref_clk,
  108. .pll_data = &pll1_data,
  109. .flags = CLK_PLL,
  110. };
  111. static struct clk pll1_aux_clk = {
  112. .name = "pll1_aux_clk",
  113. .parent = &pll1_clk,
  114. .flags = CLK_PLL | PRE_PLL,
  115. };
  116. static struct clk pll1_sysclk2 = {
  117. .name = "pll1_sysclk2",
  118. .parent = &pll1_clk,
  119. .flags = CLK_PLL,
  120. .div_reg = PLLDIV2,
  121. };
  122. static struct clk pll1_sysclk3 = {
  123. .name = "pll1_sysclk3",
  124. .parent = &pll1_clk,
  125. .flags = CLK_PLL,
  126. .div_reg = PLLDIV3,
  127. };
  128. static struct clk pll1_sysclk4 = {
  129. .name = "pll1_sysclk4",
  130. .parent = &pll1_clk,
  131. .flags = CLK_PLL,
  132. .div_reg = PLLDIV4,
  133. };
  134. static struct clk pll1_sysclk5 = {
  135. .name = "pll1_sysclk5",
  136. .parent = &pll1_clk,
  137. .flags = CLK_PLL,
  138. .div_reg = PLLDIV5,
  139. };
  140. static struct clk pll1_sysclk6 = {
  141. .name = "pll0_sysclk6",
  142. .parent = &pll0_clk,
  143. .flags = CLK_PLL,
  144. .div_reg = PLLDIV6,
  145. };
  146. static struct clk pll1_sysclk7 = {
  147. .name = "pll1_sysclk7",
  148. .parent = &pll1_clk,
  149. .flags = CLK_PLL,
  150. .div_reg = PLLDIV7,
  151. };
  152. static struct clk i2c0_clk = {
  153. .name = "i2c0",
  154. .parent = &pll0_aux_clk,
  155. };
  156. static struct clk timerp64_0_clk = {
  157. .name = "timer0",
  158. .parent = &pll0_aux_clk,
  159. };
  160. static struct clk timerp64_1_clk = {
  161. .name = "timer1",
  162. .parent = &pll0_aux_clk,
  163. };
  164. static struct clk arm_rom_clk = {
  165. .name = "arm_rom",
  166. .parent = &pll0_sysclk2,
  167. .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
  168. .flags = ALWAYS_ENABLED,
  169. };
  170. static struct clk tpcc0_clk = {
  171. .name = "tpcc0",
  172. .parent = &pll0_sysclk2,
  173. .lpsc = DA8XX_LPSC0_TPCC,
  174. .flags = ALWAYS_ENABLED | CLK_PSC,
  175. };
  176. static struct clk tptc0_clk = {
  177. .name = "tptc0",
  178. .parent = &pll0_sysclk2,
  179. .lpsc = DA8XX_LPSC0_TPTC0,
  180. .flags = ALWAYS_ENABLED,
  181. };
  182. static struct clk tptc1_clk = {
  183. .name = "tptc1",
  184. .parent = &pll0_sysclk2,
  185. .lpsc = DA8XX_LPSC0_TPTC1,
  186. .flags = ALWAYS_ENABLED,
  187. };
  188. static struct clk tpcc1_clk = {
  189. .name = "tpcc1",
  190. .parent = &pll0_sysclk2,
  191. .lpsc = DA850_LPSC1_TPCC1,
  192. .gpsc = 1,
  193. .flags = CLK_PSC | ALWAYS_ENABLED,
  194. };
  195. static struct clk tptc2_clk = {
  196. .name = "tptc2",
  197. .parent = &pll0_sysclk2,
  198. .lpsc = DA850_LPSC1_TPTC2,
  199. .gpsc = 1,
  200. .flags = ALWAYS_ENABLED,
  201. };
  202. static struct clk uart0_clk = {
  203. .name = "uart0",
  204. .parent = &pll0_sysclk2,
  205. .lpsc = DA8XX_LPSC0_UART0,
  206. };
  207. static struct clk uart1_clk = {
  208. .name = "uart1",
  209. .parent = &pll0_sysclk2,
  210. .lpsc = DA8XX_LPSC1_UART1,
  211. .gpsc = 1,
  212. .flags = DA850_CLK_ASYNC3,
  213. };
  214. static struct clk uart2_clk = {
  215. .name = "uart2",
  216. .parent = &pll0_sysclk2,
  217. .lpsc = DA8XX_LPSC1_UART2,
  218. .gpsc = 1,
  219. .flags = DA850_CLK_ASYNC3,
  220. };
  221. static struct clk aintc_clk = {
  222. .name = "aintc",
  223. .parent = &pll0_sysclk4,
  224. .lpsc = DA8XX_LPSC0_AINTC,
  225. .flags = ALWAYS_ENABLED,
  226. };
  227. static struct clk gpio_clk = {
  228. .name = "gpio",
  229. .parent = &pll0_sysclk4,
  230. .lpsc = DA8XX_LPSC1_GPIO,
  231. .gpsc = 1,
  232. };
  233. static struct clk i2c1_clk = {
  234. .name = "i2c1",
  235. .parent = &pll0_sysclk4,
  236. .lpsc = DA8XX_LPSC1_I2C,
  237. .gpsc = 1,
  238. };
  239. static struct clk emif3_clk = {
  240. .name = "emif3",
  241. .parent = &pll0_sysclk5,
  242. .lpsc = DA8XX_LPSC1_EMIF3C,
  243. .gpsc = 1,
  244. .flags = ALWAYS_ENABLED,
  245. };
  246. static struct clk arm_clk = {
  247. .name = "arm",
  248. .parent = &pll0_sysclk6,
  249. .lpsc = DA8XX_LPSC0_ARM,
  250. .flags = ALWAYS_ENABLED,
  251. .set_rate = da850_set_armrate,
  252. .round_rate = da850_round_armrate,
  253. };
  254. static struct clk rmii_clk = {
  255. .name = "rmii",
  256. .parent = &pll0_sysclk7,
  257. };
  258. static struct clk emac_clk = {
  259. .name = "emac",
  260. .parent = &pll0_sysclk4,
  261. .lpsc = DA8XX_LPSC1_CPGMAC,
  262. .gpsc = 1,
  263. };
  264. static struct clk mcasp_clk = {
  265. .name = "mcasp",
  266. .parent = &pll0_sysclk2,
  267. .lpsc = DA8XX_LPSC1_McASP0,
  268. .gpsc = 1,
  269. .flags = DA850_CLK_ASYNC3,
  270. };
  271. static struct clk lcdc_clk = {
  272. .name = "lcdc",
  273. .parent = &pll0_sysclk2,
  274. .lpsc = DA8XX_LPSC1_LCDC,
  275. .gpsc = 1,
  276. };
  277. static struct clk mmcsd_clk = {
  278. .name = "mmcsd",
  279. .parent = &pll0_sysclk2,
  280. .lpsc = DA8XX_LPSC0_MMC_SD,
  281. };
  282. static struct clk aemif_clk = {
  283. .name = "aemif",
  284. .parent = &pll0_sysclk3,
  285. .lpsc = DA8XX_LPSC0_EMIF25,
  286. .flags = ALWAYS_ENABLED,
  287. };
  288. static struct clk_lookup da850_clks[] = {
  289. CLK(NULL, "ref", &ref_clk),
  290. CLK(NULL, "pll0", &pll0_clk),
  291. CLK(NULL, "pll0_aux", &pll0_aux_clk),
  292. CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
  293. CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
  294. CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
  295. CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
  296. CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
  297. CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
  298. CLK(NULL, "pll1", &pll1_clk),
  299. CLK(NULL, "pll1_aux", &pll1_aux_clk),
  300. CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
  301. CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
  302. CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
  303. CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
  304. CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
  305. CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
  306. CLK("i2c_davinci.1", NULL, &i2c0_clk),
  307. CLK(NULL, "timer0", &timerp64_0_clk),
  308. CLK("watchdog", NULL, &timerp64_1_clk),
  309. CLK(NULL, "arm_rom", &arm_rom_clk),
  310. CLK(NULL, "tpcc0", &tpcc0_clk),
  311. CLK(NULL, "tptc0", &tptc0_clk),
  312. CLK(NULL, "tptc1", &tptc1_clk),
  313. CLK(NULL, "tpcc1", &tpcc1_clk),
  314. CLK(NULL, "tptc2", &tptc2_clk),
  315. CLK(NULL, "uart0", &uart0_clk),
  316. CLK(NULL, "uart1", &uart1_clk),
  317. CLK(NULL, "uart2", &uart2_clk),
  318. CLK(NULL, "aintc", &aintc_clk),
  319. CLK(NULL, "gpio", &gpio_clk),
  320. CLK("i2c_davinci.2", NULL, &i2c1_clk),
  321. CLK(NULL, "emif3", &emif3_clk),
  322. CLK(NULL, "arm", &arm_clk),
  323. CLK(NULL, "rmii", &rmii_clk),
  324. CLK("davinci_emac.1", NULL, &emac_clk),
  325. CLK("davinci-mcasp.0", NULL, &mcasp_clk),
  326. CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
  327. CLK("davinci_mmc.0", NULL, &mmcsd_clk),
  328. CLK(NULL, "aemif", &aemif_clk),
  329. CLK(NULL, NULL, NULL),
  330. };
  331. /*
  332. * Device specific mux setup
  333. *
  334. * soc description mux mode mode mux dbg
  335. * reg offset mask mode
  336. */
  337. static const struct mux_config da850_pins[] = {
  338. #ifdef CONFIG_DAVINCI_MUX
  339. /* UART0 function */
  340. MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
  341. MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
  342. MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
  343. MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
  344. /* UART1 function */
  345. MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
  346. MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
  347. /* UART2 function */
  348. MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
  349. MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
  350. /* I2C1 function */
  351. MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
  352. MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
  353. /* I2C0 function */
  354. MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
  355. MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
  356. /* EMAC function */
  357. MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
  358. MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
  359. MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
  360. MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
  361. MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
  362. MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
  363. MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
  364. MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
  365. MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
  366. MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
  367. MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
  368. MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
  369. MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
  370. MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
  371. MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
  372. MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
  373. MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
  374. MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
  375. MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
  376. MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
  377. MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
  378. MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
  379. MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
  380. MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
  381. MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
  382. /* McASP function */
  383. MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
  384. MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
  385. MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
  386. MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
  387. MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
  388. MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
  389. MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
  390. MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
  391. MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
  392. MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
  393. MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
  394. MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
  395. MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
  396. MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
  397. MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
  398. MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
  399. MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
  400. MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
  401. MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
  402. MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
  403. MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
  404. MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
  405. MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
  406. /* LCD function */
  407. MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
  408. MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
  409. MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
  410. MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
  411. MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
  412. MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
  413. MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
  414. MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
  415. MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
  416. MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
  417. MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
  418. MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
  419. MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
  420. MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
  421. MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
  422. MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
  423. MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
  424. MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
  425. MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
  426. MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
  427. /* MMC/SD0 function */
  428. MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
  429. MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
  430. MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
  431. MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
  432. MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
  433. MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
  434. /* EMIF2.5/EMIFA function */
  435. MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
  436. MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
  437. MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
  438. MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
  439. MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
  440. MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
  441. MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
  442. MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
  443. MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
  444. MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
  445. MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
  446. MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
  447. MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
  448. MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
  449. MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
  450. MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
  451. MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
  452. MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
  453. MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
  454. MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
  455. MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
  456. MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
  457. MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
  458. MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
  459. MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
  460. MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
  461. MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
  462. MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
  463. MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
  464. MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
  465. MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
  466. MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
  467. MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
  468. MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
  469. MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
  470. MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
  471. MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
  472. MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
  473. MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
  474. MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
  475. MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
  476. MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
  477. MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
  478. MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
  479. MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
  480. MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
  481. MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
  482. MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
  483. /* GPIO function */
  484. MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
  485. MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
  486. MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
  487. MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
  488. MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
  489. MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
  490. #endif
  491. };
  492. const short da850_uart0_pins[] __initdata = {
  493. DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
  494. -1
  495. };
  496. const short da850_uart1_pins[] __initdata = {
  497. DA850_UART1_RXD, DA850_UART1_TXD,
  498. -1
  499. };
  500. const short da850_uart2_pins[] __initdata = {
  501. DA850_UART2_RXD, DA850_UART2_TXD,
  502. -1
  503. };
  504. const short da850_i2c0_pins[] __initdata = {
  505. DA850_I2C0_SDA, DA850_I2C0_SCL,
  506. -1
  507. };
  508. const short da850_i2c1_pins[] __initdata = {
  509. DA850_I2C1_SCL, DA850_I2C1_SDA,
  510. -1
  511. };
  512. const short da850_cpgmac_pins[] __initdata = {
  513. DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
  514. DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
  515. DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
  516. DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
  517. DA850_MDIO_D,
  518. -1
  519. };
  520. const short da850_rmii_pins[] __initdata = {
  521. DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
  522. DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
  523. DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
  524. DA850_MDIO_D,
  525. -1
  526. };
  527. const short da850_mcasp_pins[] __initdata = {
  528. DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
  529. DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
  530. DA850_AXR_11, DA850_AXR_12,
  531. -1
  532. };
  533. const short da850_lcdcntl_pins[] __initdata = {
  534. DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
  535. DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
  536. DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
  537. DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
  538. DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
  539. -1
  540. };
  541. const short da850_mmcsd0_pins[] __initdata = {
  542. DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
  543. DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
  544. DA850_GPIO4_0, DA850_GPIO4_1,
  545. -1
  546. };
  547. const short da850_nand_pins[] __initdata = {
  548. DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
  549. DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
  550. DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
  551. DA850_NEMA_WE, DA850_NEMA_OE,
  552. -1
  553. };
  554. const short da850_nor_pins[] __initdata = {
  555. DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
  556. DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
  557. DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
  558. DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
  559. DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
  560. DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
  561. DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
  562. DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
  563. DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
  564. DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
  565. DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
  566. DA850_EMA_A_22, DA850_EMA_A_23,
  567. -1
  568. };
  569. /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
  570. static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
  571. [IRQ_DA8XX_COMMTX] = 7,
  572. [IRQ_DA8XX_COMMRX] = 7,
  573. [IRQ_DA8XX_NINT] = 7,
  574. [IRQ_DA8XX_EVTOUT0] = 7,
  575. [IRQ_DA8XX_EVTOUT1] = 7,
  576. [IRQ_DA8XX_EVTOUT2] = 7,
  577. [IRQ_DA8XX_EVTOUT3] = 7,
  578. [IRQ_DA8XX_EVTOUT4] = 7,
  579. [IRQ_DA8XX_EVTOUT5] = 7,
  580. [IRQ_DA8XX_EVTOUT6] = 7,
  581. [IRQ_DA8XX_EVTOUT7] = 7,
  582. [IRQ_DA8XX_CCINT0] = 7,
  583. [IRQ_DA8XX_CCERRINT] = 7,
  584. [IRQ_DA8XX_TCERRINT0] = 7,
  585. [IRQ_DA8XX_AEMIFINT] = 7,
  586. [IRQ_DA8XX_I2CINT0] = 7,
  587. [IRQ_DA8XX_MMCSDINT0] = 7,
  588. [IRQ_DA8XX_MMCSDINT1] = 7,
  589. [IRQ_DA8XX_ALLINT0] = 7,
  590. [IRQ_DA8XX_RTC] = 7,
  591. [IRQ_DA8XX_SPINT0] = 7,
  592. [IRQ_DA8XX_TINT12_0] = 7,
  593. [IRQ_DA8XX_TINT34_0] = 7,
  594. [IRQ_DA8XX_TINT12_1] = 7,
  595. [IRQ_DA8XX_TINT34_1] = 7,
  596. [IRQ_DA8XX_UARTINT0] = 7,
  597. [IRQ_DA8XX_KEYMGRINT] = 7,
  598. [IRQ_DA850_MPUADDRERR0] = 7,
  599. [IRQ_DA8XX_CHIPINT0] = 7,
  600. [IRQ_DA8XX_CHIPINT1] = 7,
  601. [IRQ_DA8XX_CHIPINT2] = 7,
  602. [IRQ_DA8XX_CHIPINT3] = 7,
  603. [IRQ_DA8XX_TCERRINT1] = 7,
  604. [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
  605. [IRQ_DA8XX_C0_RX_PULSE] = 7,
  606. [IRQ_DA8XX_C0_TX_PULSE] = 7,
  607. [IRQ_DA8XX_C0_MISC_PULSE] = 7,
  608. [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
  609. [IRQ_DA8XX_C1_RX_PULSE] = 7,
  610. [IRQ_DA8XX_C1_TX_PULSE] = 7,
  611. [IRQ_DA8XX_C1_MISC_PULSE] = 7,
  612. [IRQ_DA8XX_MEMERR] = 7,
  613. [IRQ_DA8XX_GPIO0] = 7,
  614. [IRQ_DA8XX_GPIO1] = 7,
  615. [IRQ_DA8XX_GPIO2] = 7,
  616. [IRQ_DA8XX_GPIO3] = 7,
  617. [IRQ_DA8XX_GPIO4] = 7,
  618. [IRQ_DA8XX_GPIO5] = 7,
  619. [IRQ_DA8XX_GPIO6] = 7,
  620. [IRQ_DA8XX_GPIO7] = 7,
  621. [IRQ_DA8XX_GPIO8] = 7,
  622. [IRQ_DA8XX_I2CINT1] = 7,
  623. [IRQ_DA8XX_LCDINT] = 7,
  624. [IRQ_DA8XX_UARTINT1] = 7,
  625. [IRQ_DA8XX_MCASPINT] = 7,
  626. [IRQ_DA8XX_ALLINT1] = 7,
  627. [IRQ_DA8XX_SPINT1] = 7,
  628. [IRQ_DA8XX_UHPI_INT1] = 7,
  629. [IRQ_DA8XX_USB_INT] = 7,
  630. [IRQ_DA8XX_IRQN] = 7,
  631. [IRQ_DA8XX_RWAKEUP] = 7,
  632. [IRQ_DA8XX_UARTINT2] = 7,
  633. [IRQ_DA8XX_DFTSSINT] = 7,
  634. [IRQ_DA8XX_EHRPWM0] = 7,
  635. [IRQ_DA8XX_EHRPWM0TZ] = 7,
  636. [IRQ_DA8XX_EHRPWM1] = 7,
  637. [IRQ_DA8XX_EHRPWM1TZ] = 7,
  638. [IRQ_DA850_SATAINT] = 7,
  639. [IRQ_DA850_TINTALL_2] = 7,
  640. [IRQ_DA8XX_ECAP0] = 7,
  641. [IRQ_DA8XX_ECAP1] = 7,
  642. [IRQ_DA8XX_ECAP2] = 7,
  643. [IRQ_DA850_MMCSDINT0_1] = 7,
  644. [IRQ_DA850_MMCSDINT1_1] = 7,
  645. [IRQ_DA850_T12CMPINT0_2] = 7,
  646. [IRQ_DA850_T12CMPINT1_2] = 7,
  647. [IRQ_DA850_T12CMPINT2_2] = 7,
  648. [IRQ_DA850_T12CMPINT3_2] = 7,
  649. [IRQ_DA850_T12CMPINT4_2] = 7,
  650. [IRQ_DA850_T12CMPINT5_2] = 7,
  651. [IRQ_DA850_T12CMPINT6_2] = 7,
  652. [IRQ_DA850_T12CMPINT7_2] = 7,
  653. [IRQ_DA850_T12CMPINT0_3] = 7,
  654. [IRQ_DA850_T12CMPINT1_3] = 7,
  655. [IRQ_DA850_T12CMPINT2_3] = 7,
  656. [IRQ_DA850_T12CMPINT3_3] = 7,
  657. [IRQ_DA850_T12CMPINT4_3] = 7,
  658. [IRQ_DA850_T12CMPINT5_3] = 7,
  659. [IRQ_DA850_T12CMPINT6_3] = 7,
  660. [IRQ_DA850_T12CMPINT7_3] = 7,
  661. [IRQ_DA850_RPIINT] = 7,
  662. [IRQ_DA850_VPIFINT] = 7,
  663. [IRQ_DA850_CCINT1] = 7,
  664. [IRQ_DA850_CCERRINT1] = 7,
  665. [IRQ_DA850_TCERRINT2] = 7,
  666. [IRQ_DA850_TINTALL_3] = 7,
  667. [IRQ_DA850_MCBSP0RINT] = 7,
  668. [IRQ_DA850_MCBSP0XINT] = 7,
  669. [IRQ_DA850_MCBSP1RINT] = 7,
  670. [IRQ_DA850_MCBSP1XINT] = 7,
  671. [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
  672. };
  673. static struct map_desc da850_io_desc[] = {
  674. {
  675. .virtual = IO_VIRT,
  676. .pfn = __phys_to_pfn(IO_PHYS),
  677. .length = IO_SIZE,
  678. .type = MT_DEVICE
  679. },
  680. {
  681. .virtual = DA8XX_CP_INTC_VIRT,
  682. .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
  683. .length = DA8XX_CP_INTC_SIZE,
  684. .type = MT_DEVICE
  685. },
  686. {
  687. .virtual = SRAM_VIRT,
  688. .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
  689. .length = SZ_8K,
  690. .type = MT_DEVICE
  691. },
  692. };
  693. static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
  694. /* Contents of JTAG ID register used to identify exact cpu type */
  695. static struct davinci_id da850_ids[] = {
  696. {
  697. .variant = 0x0,
  698. .part_no = 0xb7d1,
  699. .manufacturer = 0x017, /* 0x02f >> 1 */
  700. .cpu_id = DAVINCI_CPU_ID_DA850,
  701. .name = "da850/omap-l138",
  702. },
  703. };
  704. static struct davinci_timer_instance da850_timer_instance[4] = {
  705. {
  706. .base = DA8XX_TIMER64P0_BASE,
  707. .bottom_irq = IRQ_DA8XX_TINT12_0,
  708. .top_irq = IRQ_DA8XX_TINT34_0,
  709. },
  710. {
  711. .base = DA8XX_TIMER64P1_BASE,
  712. .bottom_irq = IRQ_DA8XX_TINT12_1,
  713. .top_irq = IRQ_DA8XX_TINT34_1,
  714. },
  715. {
  716. .base = DA850_TIMER64P2_BASE,
  717. .bottom_irq = IRQ_DA850_TINT12_2,
  718. .top_irq = IRQ_DA850_TINT34_2,
  719. },
  720. {
  721. .base = DA850_TIMER64P3_BASE,
  722. .bottom_irq = IRQ_DA850_TINT12_3,
  723. .top_irq = IRQ_DA850_TINT34_3,
  724. },
  725. };
  726. /*
  727. * T0_BOT: Timer 0, bottom : Used for clock_event
  728. * T0_TOP: Timer 0, top : Used for clocksource
  729. * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
  730. */
  731. static struct davinci_timer_info da850_timer_info = {
  732. .timers = da850_timer_instance,
  733. .clockevent_id = T0_BOT,
  734. .clocksource_id = T0_TOP,
  735. };
  736. static void da850_set_async3_src(int pllnum)
  737. {
  738. struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
  739. struct clk_lookup *c;
  740. unsigned int v;
  741. int ret;
  742. for (c = da850_clks; c->clk; c++) {
  743. clk = c->clk;
  744. if (clk->flags & DA850_CLK_ASYNC3) {
  745. ret = clk_set_parent(clk, newparent);
  746. WARN(ret, "DA850: unable to re-parent clock %s",
  747. clk->name);
  748. }
  749. }
  750. v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
  751. if (pllnum)
  752. v |= CFGCHIP3_ASYNC3_CLKSRC;
  753. else
  754. v &= ~CFGCHIP3_ASYNC3_CLKSRC;
  755. __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
  756. }
  757. #ifdef CONFIG_CPU_FREQ
  758. /*
  759. * Notes:
  760. * According to the TRM, minimum PLLM results in maximum power savings.
  761. * The OPP definitions below should keep the PLLM as low as possible.
  762. *
  763. * The output of the PLLM must be between 400 to 600 MHz.
  764. * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
  765. */
  766. struct da850_opp {
  767. unsigned int freq; /* in KHz */
  768. unsigned int prediv;
  769. unsigned int mult;
  770. unsigned int postdiv;
  771. unsigned int cvdd_min; /* in uV */
  772. unsigned int cvdd_max; /* in uV */
  773. };
  774. static const struct da850_opp da850_opp_300 = {
  775. .freq = 300000,
  776. .prediv = 1,
  777. .mult = 25,
  778. .postdiv = 2,
  779. .cvdd_min = 1140000,
  780. .cvdd_max = 1320000,
  781. };
  782. static const struct da850_opp da850_opp_200 = {
  783. .freq = 200000,
  784. .prediv = 1,
  785. .mult = 25,
  786. .postdiv = 3,
  787. .cvdd_min = 1050000,
  788. .cvdd_max = 1160000,
  789. };
  790. static const struct da850_opp da850_opp_96 = {
  791. .freq = 96000,
  792. .prediv = 1,
  793. .mult = 20,
  794. .postdiv = 5,
  795. .cvdd_min = 950000,
  796. .cvdd_max = 1050000,
  797. };
  798. #define OPP(freq) \
  799. { \
  800. .index = (unsigned int) &da850_opp_##freq, \
  801. .frequency = freq * 1000, \
  802. }
  803. static struct cpufreq_frequency_table da850_freq_table[] = {
  804. OPP(300),
  805. OPP(200),
  806. OPP(96),
  807. {
  808. .index = 0,
  809. .frequency = CPUFREQ_TABLE_END,
  810. },
  811. };
  812. #ifdef CONFIG_REGULATOR
  813. static struct regulator *cvdd;
  814. static int da850_set_voltage(unsigned int index)
  815. {
  816. struct da850_opp *opp;
  817. if (!cvdd)
  818. return -ENODEV;
  819. opp = (struct da850_opp *) da850_freq_table[index].index;
  820. return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
  821. }
  822. static int da850_regulator_init(void)
  823. {
  824. cvdd = regulator_get(NULL, "cvdd");
  825. if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
  826. " voltage scaling unsupported\n")) {
  827. return PTR_ERR(cvdd);
  828. }
  829. return 0;
  830. }
  831. #endif
  832. static struct davinci_cpufreq_config cpufreq_info = {
  833. .freq_table = &da850_freq_table[0],
  834. #ifdef CONFIG_REGULATOR
  835. .init = da850_regulator_init,
  836. .set_voltage = da850_set_voltage,
  837. #endif
  838. };
  839. static struct platform_device da850_cpufreq_device = {
  840. .name = "cpufreq-davinci",
  841. .dev = {
  842. .platform_data = &cpufreq_info,
  843. },
  844. };
  845. int __init da850_register_cpufreq(void)
  846. {
  847. return platform_device_register(&da850_cpufreq_device);
  848. }
  849. static int da850_round_armrate(struct clk *clk, unsigned long rate)
  850. {
  851. int i, ret = 0, diff;
  852. unsigned int best = (unsigned int) -1;
  853. rate /= 1000; /* convert to kHz */
  854. for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
  855. diff = da850_freq_table[i].frequency - rate;
  856. if (diff < 0)
  857. diff = -diff;
  858. if (diff < best) {
  859. best = diff;
  860. ret = da850_freq_table[i].frequency;
  861. }
  862. }
  863. return ret * 1000;
  864. }
  865. static int da850_set_armrate(struct clk *clk, unsigned long index)
  866. {
  867. struct clk *pllclk = &pll0_clk;
  868. return clk_set_rate(pllclk, index);
  869. }
  870. static int da850_set_pll0rate(struct clk *clk, unsigned long index)
  871. {
  872. unsigned int prediv, mult, postdiv;
  873. struct da850_opp *opp;
  874. struct pll_data *pll = clk->pll_data;
  875. int ret;
  876. opp = (struct da850_opp *) da850_freq_table[index].index;
  877. prediv = opp->prediv;
  878. mult = opp->mult;
  879. postdiv = opp->postdiv;
  880. ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
  881. if (WARN_ON(ret))
  882. return ret;
  883. return 0;
  884. }
  885. #else
  886. int __init da850_register_cpufreq(void)
  887. {
  888. return 0;
  889. }
  890. static int da850_set_armrate(struct clk *clk, unsigned long rate)
  891. {
  892. return -EINVAL;
  893. }
  894. static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
  895. {
  896. return -EINVAL;
  897. }
  898. static int da850_round_armrate(struct clk *clk, unsigned long rate)
  899. {
  900. return clk->rate;
  901. }
  902. #endif
  903. int da850_register_pm(struct platform_device *pdev)
  904. {
  905. int ret;
  906. struct davinci_pm_config *pdata = pdev->dev.platform_data;
  907. ret = davinci_cfg_reg(DA850_RTC_ALARM);
  908. if (ret)
  909. return ret;
  910. pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
  911. pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
  912. pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
  913. pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
  914. if (!pdata->cpupll_reg_base)
  915. return -ENOMEM;
  916. pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
  917. if (!pdata->ddrpll_reg_base) {
  918. ret = -ENOMEM;
  919. goto no_ddrpll_mem;
  920. }
  921. pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
  922. if (!pdata->ddrpsc_reg_base) {
  923. ret = -ENOMEM;
  924. goto no_ddrpsc_mem;
  925. }
  926. return platform_device_register(pdev);
  927. no_ddrpsc_mem:
  928. iounmap(pdata->ddrpll_reg_base);
  929. no_ddrpll_mem:
  930. iounmap(pdata->cpupll_reg_base);
  931. return ret;
  932. }
  933. static struct davinci_soc_info davinci_soc_info_da850 = {
  934. .io_desc = da850_io_desc,
  935. .io_desc_num = ARRAY_SIZE(da850_io_desc),
  936. .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
  937. .ids = da850_ids,
  938. .ids_num = ARRAY_SIZE(da850_ids),
  939. .cpu_clks = da850_clks,
  940. .psc_bases = da850_psc_bases,
  941. .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
  942. .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
  943. .pinmux_pins = da850_pins,
  944. .pinmux_pins_num = ARRAY_SIZE(da850_pins),
  945. .intc_base = DA8XX_CP_INTC_BASE,
  946. .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
  947. .intc_irq_prios = da850_default_priorities,
  948. .intc_irq_num = DA850_N_CP_INTC_IRQ,
  949. .timer_info = &da850_timer_info,
  950. .gpio_type = GPIO_TYPE_DAVINCI,
  951. .gpio_base = DA8XX_GPIO_BASE,
  952. .gpio_num = 144,
  953. .gpio_irq = IRQ_DA8XX_GPIO0,
  954. .serial_dev = &da8xx_serial_device,
  955. .emac_pdata = &da8xx_emac_pdata,
  956. .sram_dma = DA8XX_ARM_RAM_BASE,
  957. .sram_len = SZ_8K,
  958. .reset_device = &da8xx_wdt_device,
  959. };
  960. void __init da850_init(void)
  961. {
  962. unsigned int v;
  963. davinci_common_init(&davinci_soc_info_da850);
  964. da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
  965. if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
  966. return;
  967. da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
  968. if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
  969. return;
  970. /*
  971. * Move the clock source of Async3 domain to PLL1 SYSCLK2.
  972. * This helps keeping the peripherals on this domain insulated
  973. * from CPU frequency changes caused by DVFS. The firmware sets
  974. * both PLL0 and PLL1 to the same frequency so, there should not
  975. * be any noticible change even in non-DVFS use cases.
  976. */
  977. da850_set_async3_src(1);
  978. /* Unlock writing to PLL0 registers */
  979. v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
  980. v &= ~CFGCHIP0_PLL_MASTER_LOCK;
  981. __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
  982. /* Unlock writing to PLL1 registers */
  983. v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
  984. v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
  985. __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
  986. }