pl330.h 5.9 KB

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  1. /* linux/include/asm/hardware/pl330.h
  2. *
  3. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  4. * Jaswinder Singh <jassi.brar@samsung.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #ifndef __PL330_CORE_H
  21. #define __PL330_CORE_H
  22. #define PL330_MAX_CHAN 8
  23. #define PL330_MAX_IRQS 32
  24. #define PL330_MAX_PERI 32
  25. enum pl330_srccachectrl {
  26. SCCTRL0 = 0, /* Noncacheable and nonbufferable */
  27. SCCTRL1, /* Bufferable only */
  28. SCCTRL2, /* Cacheable, but do not allocate */
  29. SCCTRL3, /* Cacheable and bufferable, but do not allocate */
  30. SINVALID1,
  31. SINVALID2,
  32. SCCTRL6, /* Cacheable write-through, allocate on reads only */
  33. SCCTRL7, /* Cacheable write-back, allocate on reads only */
  34. };
  35. enum pl330_dstcachectrl {
  36. DCCTRL0 = 0, /* Noncacheable and nonbufferable */
  37. DCCTRL1, /* Bufferable only */
  38. DCCTRL2, /* Cacheable, but do not allocate */
  39. DCCTRL3, /* Cacheable and bufferable, but do not allocate */
  40. DINVALID1 = 8,
  41. DINVALID2,
  42. DCCTRL6, /* Cacheable write-through, allocate on writes only */
  43. DCCTRL7, /* Cacheable write-back, allocate on writes only */
  44. };
  45. /* Populated by the PL330 core driver for DMA API driver's info */
  46. struct pl330_config {
  47. u32 periph_id;
  48. u32 pcell_id;
  49. #define DMAC_MODE_NS (1 << 0)
  50. unsigned int mode;
  51. unsigned int data_bus_width:10; /* In number of bits */
  52. unsigned int data_buf_dep:10;
  53. unsigned int num_chan:4;
  54. unsigned int num_peri:6;
  55. u32 peri_ns;
  56. unsigned int num_events:6;
  57. u32 irq_ns;
  58. };
  59. /* Handle to the DMAC provided to the PL330 core */
  60. struct pl330_info {
  61. /* Owning device */
  62. struct device *dev;
  63. /* Size of MicroCode buffers for each channel. */
  64. unsigned mcbufsz;
  65. /* ioremap'ed address of PL330 registers. */
  66. void __iomem *base;
  67. /* Client can freely use it. */
  68. void *client_data;
  69. /* PL330 core data, Client must not touch it. */
  70. void *pl330_data;
  71. /* Populated by the PL330 core driver during pl330_add */
  72. struct pl330_config pcfg;
  73. /*
  74. * If the DMAC has some reset mechanism, then the
  75. * client may want to provide pointer to the method.
  76. */
  77. void (*dmac_reset)(struct pl330_info *pi);
  78. };
  79. enum pl330_byteswap {
  80. SWAP_NO = 0,
  81. SWAP_2,
  82. SWAP_4,
  83. SWAP_8,
  84. SWAP_16,
  85. };
  86. /**
  87. * Request Configuration.
  88. * The PL330 core does not modify this and uses the last
  89. * working configuration if the request doesn't provide any.
  90. *
  91. * The Client may want to provide this info only for the
  92. * first request and a request with new settings.
  93. */
  94. struct pl330_reqcfg {
  95. /* Address Incrementing */
  96. unsigned dst_inc:1;
  97. unsigned src_inc:1;
  98. /*
  99. * For now, the SRC & DST protection levels
  100. * and burst size/length are assumed same.
  101. */
  102. bool nonsecure;
  103. bool privileged;
  104. bool insnaccess;
  105. unsigned brst_len:5;
  106. unsigned brst_size:3; /* in power of 2 */
  107. enum pl330_dstcachectrl dcctl;
  108. enum pl330_srccachectrl scctl;
  109. enum pl330_byteswap swap;
  110. };
  111. /*
  112. * One cycle of DMAC operation.
  113. * There may be more than one xfer in a request.
  114. */
  115. struct pl330_xfer {
  116. u32 src_addr;
  117. u32 dst_addr;
  118. /* Size to xfer */
  119. u32 bytes;
  120. /*
  121. * Pointer to next xfer in the list.
  122. * The last xfer in the req must point to NULL.
  123. */
  124. struct pl330_xfer *next;
  125. };
  126. /* The xfer callbacks are made with one of these arguments. */
  127. enum pl330_op_err {
  128. /* The all xfers in the request were success. */
  129. PL330_ERR_NONE,
  130. /* If req aborted due to global error. */
  131. PL330_ERR_ABORT,
  132. /* If req failed due to problem with Channel. */
  133. PL330_ERR_FAIL,
  134. };
  135. enum pl330_reqtype {
  136. MEMTOMEM,
  137. MEMTODEV,
  138. DEVTOMEM,
  139. DEVTODEV,
  140. };
  141. /* A request defining Scatter-Gather List ending with NULL xfer. */
  142. struct pl330_req {
  143. enum pl330_reqtype rqtype;
  144. /* Index of peripheral for the xfer. */
  145. unsigned peri:5;
  146. /* Unique token for this xfer, set by the client. */
  147. void *token;
  148. /* Callback to be called after xfer. */
  149. void (*xfer_cb)(void *token, enum pl330_op_err err);
  150. /* If NULL, req will be done at last set parameters. */
  151. struct pl330_reqcfg *cfg;
  152. /* Pointer to first xfer in the request. */
  153. struct pl330_xfer *x;
  154. };
  155. /*
  156. * To know the status of the channel and DMAC, the client
  157. * provides a pointer to this structure. The PL330 core
  158. * fills it with current information.
  159. */
  160. struct pl330_chanstatus {
  161. /*
  162. * If the DMAC engine halted due to some error,
  163. * the client should remove-add DMAC.
  164. */
  165. bool dmac_halted;
  166. /*
  167. * If channel is halted due to some error,
  168. * the client should ABORT/FLUSH and START the channel.
  169. */
  170. bool faulting;
  171. /* Location of last load */
  172. u32 src_addr;
  173. /* Location of last store */
  174. u32 dst_addr;
  175. /*
  176. * Pointer to the currently active req, NULL if channel is
  177. * inactive, even though the requests may be present.
  178. */
  179. struct pl330_req *top_req;
  180. /* Pointer to req waiting second in the queue if any. */
  181. struct pl330_req *wait_req;
  182. };
  183. enum pl330_chan_op {
  184. /* Start the channel */
  185. PL330_OP_START,
  186. /* Abort the active xfer */
  187. PL330_OP_ABORT,
  188. /* Stop xfer and flush queue */
  189. PL330_OP_FLUSH,
  190. };
  191. extern int pl330_add(struct pl330_info *);
  192. extern void pl330_del(struct pl330_info *pi);
  193. extern int pl330_update(const struct pl330_info *pi);
  194. extern void pl330_release_channel(void *ch_id);
  195. extern void *pl330_request_channel(const struct pl330_info *pi);
  196. extern int pl330_chan_status(void *ch_id, struct pl330_chanstatus *pstatus);
  197. extern int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op);
  198. extern int pl330_submit_req(void *ch_id, struct pl330_req *r);
  199. #endif /* __PL330_CORE_H */