main.c 51 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  92. spin_unlock(&common->cc_lock);
  93. }
  94. unlock:
  95. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  96. }
  97. void ath9k_ps_restore(struct ath_softc *sc)
  98. {
  99. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  100. enum ath9k_power_mode mode;
  101. unsigned long flags;
  102. bool reset;
  103. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  104. if (--sc->ps_usecount != 0)
  105. goto unlock;
  106. if (sc->ps_idle) {
  107. ath9k_hw_setrxabort(sc->sc_ah, 1);
  108. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  109. mode = ATH9K_PM_FULL_SLEEP;
  110. } else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK))) {
  115. mode = ATH9K_PM_NETWORK_SLEEP;
  116. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  117. ath9k_btcoex_stop_gen_timer(sc);
  118. } else {
  119. goto unlock;
  120. }
  121. spin_lock(&common->cc_lock);
  122. ath_hw_cycle_counters_update(common);
  123. spin_unlock(&common->cc_lock);
  124. ath9k_hw_setpower(sc->sc_ah, mode);
  125. unlock:
  126. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  127. }
  128. static void __ath_cancel_work(struct ath_softc *sc)
  129. {
  130. cancel_work_sync(&sc->paprd_work);
  131. cancel_work_sync(&sc->hw_check_work);
  132. cancel_delayed_work_sync(&sc->tx_complete_work);
  133. cancel_delayed_work_sync(&sc->hw_pll_work);
  134. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  135. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  136. cancel_work_sync(&sc->mci_work);
  137. #endif
  138. }
  139. static void ath_cancel_work(struct ath_softc *sc)
  140. {
  141. __ath_cancel_work(sc);
  142. cancel_work_sync(&sc->hw_reset_work);
  143. }
  144. static void ath_restart_work(struct ath_softc *sc)
  145. {
  146. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  147. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  148. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  149. AR_SREV_9550(sc->sc_ah))
  150. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  151. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  152. ath_start_rx_poll(sc, 3);
  153. if (!common->disable_ani)
  154. ath_start_ani(common);
  155. }
  156. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. struct ath_common *common = ath9k_hw_common(ah);
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. del_timer_sync(&common->ani.timer);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. if (!ath_drain_all_txq(sc, retry_tx))
  170. ret = false;
  171. if (!flush) {
  172. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  173. ath_rx_tasklet(sc, 1, true);
  174. ath_rx_tasklet(sc, 1, false);
  175. } else {
  176. ath_flushrecv(sc);
  177. }
  178. return ret;
  179. }
  180. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  181. {
  182. struct ath_hw *ah = sc->sc_ah;
  183. struct ath_common *common = ath9k_hw_common(ah);
  184. unsigned long flags;
  185. if (ath_startrecv(sc) != 0) {
  186. ath_err(common, "Unable to restart recv logic\n");
  187. return false;
  188. }
  189. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  190. sc->config.txpowlimit, &sc->curtxpow);
  191. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  192. ath9k_hw_set_interrupts(ah);
  193. ath9k_hw_enable_interrupts(ah);
  194. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  195. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  196. goto work;
  197. ath_set_beacon(sc);
  198. if (ah->opmode == NL80211_IFTYPE_STATION &&
  199. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  200. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  201. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  202. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  203. }
  204. work:
  205. ath_restart_work(sc);
  206. }
  207. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  208. ath_ant_comb_update(sc);
  209. ieee80211_wake_queues(sc->hw);
  210. return true;
  211. }
  212. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  213. bool retry_tx)
  214. {
  215. struct ath_hw *ah = sc->sc_ah;
  216. struct ath_common *common = ath9k_hw_common(ah);
  217. struct ath9k_hw_cal_data *caldata = NULL;
  218. bool fastcc = true;
  219. bool flush = false;
  220. int r;
  221. __ath_cancel_work(sc);
  222. spin_lock_bh(&sc->sc_pcu_lock);
  223. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  224. fastcc = false;
  225. caldata = &sc->caldata;
  226. }
  227. if (!hchan) {
  228. fastcc = false;
  229. flush = true;
  230. hchan = ah->curchan;
  231. }
  232. if (!ath_prepare_reset(sc, retry_tx, flush))
  233. fastcc = false;
  234. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  235. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  236. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  237. if (r) {
  238. ath_err(common,
  239. "Unable to reset channel, reset status %d\n", r);
  240. goto out;
  241. }
  242. if (!ath_complete_reset(sc, true))
  243. r = -EIO;
  244. out:
  245. spin_unlock_bh(&sc->sc_pcu_lock);
  246. return r;
  247. }
  248. /*
  249. * Set/change channels. If the channel is really being changed, it's done
  250. * by reseting the chip. To accomplish this we must first cleanup any pending
  251. * DMA, then restart stuff.
  252. */
  253. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  254. struct ath9k_channel *hchan)
  255. {
  256. int r;
  257. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  258. return -EIO;
  259. r = ath_reset_internal(sc, hchan, false);
  260. return r;
  261. }
  262. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  263. struct ieee80211_vif *vif)
  264. {
  265. struct ath_node *an;
  266. u8 density;
  267. an = (struct ath_node *)sta->drv_priv;
  268. #ifdef CONFIG_ATH9K_DEBUGFS
  269. spin_lock(&sc->nodes_lock);
  270. list_add(&an->list, &sc->nodes);
  271. spin_unlock(&sc->nodes_lock);
  272. #endif
  273. an->sta = sta;
  274. an->vif = vif;
  275. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  276. ath_tx_node_init(sc, an);
  277. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  278. sta->ht_cap.ampdu_factor);
  279. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  280. an->mpdudensity = density;
  281. }
  282. }
  283. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  284. {
  285. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  286. #ifdef CONFIG_ATH9K_DEBUGFS
  287. spin_lock(&sc->nodes_lock);
  288. list_del(&an->list);
  289. spin_unlock(&sc->nodes_lock);
  290. an->sta = NULL;
  291. #endif
  292. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  293. ath_tx_node_cleanup(sc, an);
  294. }
  295. void ath9k_tasklet(unsigned long data)
  296. {
  297. struct ath_softc *sc = (struct ath_softc *)data;
  298. struct ath_hw *ah = sc->sc_ah;
  299. struct ath_common *common = ath9k_hw_common(ah);
  300. unsigned long flags;
  301. u32 status = sc->intrstatus;
  302. u32 rxmask;
  303. ath9k_ps_wakeup(sc);
  304. spin_lock(&sc->sc_pcu_lock);
  305. if ((status & ATH9K_INT_FATAL) ||
  306. (status & ATH9K_INT_BB_WATCHDOG)) {
  307. #ifdef CONFIG_ATH9K_DEBUGFS
  308. enum ath_reset_type type;
  309. if (status & ATH9K_INT_FATAL)
  310. type = RESET_TYPE_FATAL_INT;
  311. else
  312. type = RESET_TYPE_BB_WATCHDOG;
  313. RESET_STAT_INC(sc, type);
  314. #endif
  315. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  316. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  317. goto out;
  318. }
  319. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  320. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  321. /*
  322. * TSF sync does not look correct; remain awake to sync with
  323. * the next Beacon.
  324. */
  325. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  326. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  327. }
  328. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  329. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  330. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  331. ATH9K_INT_RXORN);
  332. else
  333. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  334. if (status & rxmask) {
  335. /* Check for high priority Rx first */
  336. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  337. (status & ATH9K_INT_RXHP))
  338. ath_rx_tasklet(sc, 0, true);
  339. ath_rx_tasklet(sc, 0, false);
  340. }
  341. if (status & ATH9K_INT_TX) {
  342. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  343. ath_tx_edma_tasklet(sc);
  344. else
  345. ath_tx_tasklet(sc);
  346. }
  347. ath9k_btcoex_handle_interrupt(sc, status);
  348. out:
  349. /* re-enable hardware interrupt */
  350. ath9k_hw_enable_interrupts(ah);
  351. spin_unlock(&sc->sc_pcu_lock);
  352. ath9k_ps_restore(sc);
  353. }
  354. irqreturn_t ath_isr(int irq, void *dev)
  355. {
  356. #define SCHED_INTR ( \
  357. ATH9K_INT_FATAL | \
  358. ATH9K_INT_BB_WATCHDOG | \
  359. ATH9K_INT_RXORN | \
  360. ATH9K_INT_RXEOL | \
  361. ATH9K_INT_RX | \
  362. ATH9K_INT_RXLP | \
  363. ATH9K_INT_RXHP | \
  364. ATH9K_INT_TX | \
  365. ATH9K_INT_BMISS | \
  366. ATH9K_INT_CST | \
  367. ATH9K_INT_TSFOOR | \
  368. ATH9K_INT_GENTIMER | \
  369. ATH9K_INT_MCI)
  370. struct ath_softc *sc = dev;
  371. struct ath_hw *ah = sc->sc_ah;
  372. struct ath_common *common = ath9k_hw_common(ah);
  373. enum ath9k_int status;
  374. bool sched = false;
  375. /*
  376. * The hardware is not ready/present, don't
  377. * touch anything. Note this can happen early
  378. * on if the IRQ is shared.
  379. */
  380. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  381. return IRQ_NONE;
  382. /* shared irq, not for us */
  383. if (!ath9k_hw_intrpend(ah))
  384. return IRQ_NONE;
  385. if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  386. return IRQ_HANDLED;
  387. /*
  388. * Figure out the reason(s) for the interrupt. Note
  389. * that the hal returns a pseudo-ISR that may include
  390. * bits we haven't explicitly enabled so we mask the
  391. * value to insure we only process bits we requested.
  392. */
  393. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  394. status &= ah->imask; /* discard unasked-for bits */
  395. /*
  396. * If there are no status bits set, then this interrupt was not
  397. * for me (should have been caught above).
  398. */
  399. if (!status)
  400. return IRQ_NONE;
  401. /* Cache the status */
  402. sc->intrstatus = status;
  403. if (status & SCHED_INTR)
  404. sched = true;
  405. /*
  406. * If a FATAL or RXORN interrupt is received, we have to reset the
  407. * chip immediately.
  408. */
  409. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  410. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  411. goto chip_reset;
  412. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  413. (status & ATH9K_INT_BB_WATCHDOG)) {
  414. spin_lock(&common->cc_lock);
  415. ath_hw_cycle_counters_update(common);
  416. ar9003_hw_bb_watchdog_dbg_info(ah);
  417. spin_unlock(&common->cc_lock);
  418. goto chip_reset;
  419. }
  420. if (status & ATH9K_INT_SWBA)
  421. tasklet_schedule(&sc->bcon_tasklet);
  422. if (status & ATH9K_INT_TXURN)
  423. ath9k_hw_updatetxtriglevel(ah, true);
  424. if (status & ATH9K_INT_RXEOL) {
  425. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  426. ath9k_hw_set_interrupts(ah);
  427. }
  428. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  429. if (status & ATH9K_INT_TIM_TIMER) {
  430. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  431. goto chip_reset;
  432. /* Clear RxAbort bit so that we can
  433. * receive frames */
  434. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  435. spin_lock(&sc->sc_pm_lock);
  436. ath9k_hw_setrxabort(sc->sc_ah, 0);
  437. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  438. spin_unlock(&sc->sc_pm_lock);
  439. }
  440. chip_reset:
  441. ath_debug_stat_interrupt(sc, status);
  442. if (sched) {
  443. /* turn off every interrupt */
  444. ath9k_hw_disable_interrupts(ah);
  445. tasklet_schedule(&sc->intr_tq);
  446. }
  447. return IRQ_HANDLED;
  448. #undef SCHED_INTR
  449. }
  450. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  451. {
  452. int r;
  453. ath9k_ps_wakeup(sc);
  454. r = ath_reset_internal(sc, NULL, retry_tx);
  455. if (retry_tx) {
  456. int i;
  457. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  458. if (ATH_TXQ_SETUP(sc, i)) {
  459. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  460. ath_txq_schedule(sc, &sc->tx.txq[i]);
  461. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  462. }
  463. }
  464. }
  465. ath9k_ps_restore(sc);
  466. return r;
  467. }
  468. void ath_reset_work(struct work_struct *work)
  469. {
  470. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  471. ath_reset(sc, true);
  472. }
  473. /**********************/
  474. /* mac80211 callbacks */
  475. /**********************/
  476. static int ath9k_start(struct ieee80211_hw *hw)
  477. {
  478. struct ath_softc *sc = hw->priv;
  479. struct ath_hw *ah = sc->sc_ah;
  480. struct ath_common *common = ath9k_hw_common(ah);
  481. struct ieee80211_channel *curchan = hw->conf.channel;
  482. struct ath9k_channel *init_channel;
  483. int r;
  484. ath_dbg(common, CONFIG,
  485. "Starting driver with initial channel: %d MHz\n",
  486. curchan->center_freq);
  487. ath9k_ps_wakeup(sc);
  488. mutex_lock(&sc->mutex);
  489. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  490. /* Reset SERDES registers */
  491. ath9k_hw_configpcipowersave(ah, false);
  492. /*
  493. * The basic interface to setting the hardware in a good
  494. * state is ``reset''. On return the hardware is known to
  495. * be powered up and with interrupts disabled. This must
  496. * be followed by initialization of the appropriate bits
  497. * and then setup of the interrupt mask.
  498. */
  499. spin_lock_bh(&sc->sc_pcu_lock);
  500. atomic_set(&ah->intr_ref_cnt, -1);
  501. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  502. if (r) {
  503. ath_err(common,
  504. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  505. r, curchan->center_freq);
  506. spin_unlock_bh(&sc->sc_pcu_lock);
  507. goto mutex_unlock;
  508. }
  509. /* Setup our intr mask. */
  510. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  511. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  512. ATH9K_INT_GLOBAL;
  513. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  514. ah->imask |= ATH9K_INT_RXHP |
  515. ATH9K_INT_RXLP |
  516. ATH9K_INT_BB_WATCHDOG;
  517. else
  518. ah->imask |= ATH9K_INT_RX;
  519. ah->imask |= ATH9K_INT_GTT;
  520. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  521. ah->imask |= ATH9K_INT_CST;
  522. ath_mci_enable(sc);
  523. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  524. sc->sc_ah->is_monitoring = false;
  525. if (!ath_complete_reset(sc, false)) {
  526. r = -EIO;
  527. spin_unlock_bh(&sc->sc_pcu_lock);
  528. goto mutex_unlock;
  529. }
  530. if (ah->led_pin >= 0) {
  531. ath9k_hw_cfg_output(ah, ah->led_pin,
  532. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  533. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  534. }
  535. /*
  536. * Reset key cache to sane defaults (all entries cleared) instead of
  537. * semi-random values after suspend/resume.
  538. */
  539. ath9k_cmn_init_crypto(sc->sc_ah);
  540. spin_unlock_bh(&sc->sc_pcu_lock);
  541. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  542. common->bus_ops->extn_synch_en(common);
  543. mutex_unlock:
  544. mutex_unlock(&sc->mutex);
  545. ath9k_ps_restore(sc);
  546. return r;
  547. }
  548. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  549. {
  550. struct ath_softc *sc = hw->priv;
  551. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  552. struct ath_tx_control txctl;
  553. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  554. unsigned long flags;
  555. if (sc->ps_enabled) {
  556. /*
  557. * mac80211 does not set PM field for normal data frames, so we
  558. * need to update that based on the current PS mode.
  559. */
  560. if (ieee80211_is_data(hdr->frame_control) &&
  561. !ieee80211_is_nullfunc(hdr->frame_control) &&
  562. !ieee80211_has_pm(hdr->frame_control)) {
  563. ath_dbg(common, PS,
  564. "Add PM=1 for a TX frame while in PS mode\n");
  565. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  566. }
  567. }
  568. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  569. /*
  570. * We are using PS-Poll and mac80211 can request TX while in
  571. * power save mode. Need to wake up hardware for the TX to be
  572. * completed and if needed, also for RX of buffered frames.
  573. */
  574. ath9k_ps_wakeup(sc);
  575. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  576. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  577. ath9k_hw_setrxabort(sc->sc_ah, 0);
  578. if (ieee80211_is_pspoll(hdr->frame_control)) {
  579. ath_dbg(common, PS,
  580. "Sending PS-Poll to pick a buffered frame\n");
  581. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  582. } else {
  583. ath_dbg(common, PS, "Wake up to complete TX\n");
  584. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  585. }
  586. /*
  587. * The actual restore operation will happen only after
  588. * the ps_flags bit is cleared. We are just dropping
  589. * the ps_usecount here.
  590. */
  591. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  592. ath9k_ps_restore(sc);
  593. }
  594. /*
  595. * Cannot tx while the hardware is in full sleep, it first needs a full
  596. * chip reset to recover from that
  597. */
  598. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  599. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  600. goto exit;
  601. }
  602. memset(&txctl, 0, sizeof(struct ath_tx_control));
  603. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  604. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  605. if (ath_tx_start(hw, skb, &txctl) != 0) {
  606. ath_dbg(common, XMIT, "TX failed\n");
  607. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  608. goto exit;
  609. }
  610. return;
  611. exit:
  612. dev_kfree_skb_any(skb);
  613. }
  614. static void ath9k_stop(struct ieee80211_hw *hw)
  615. {
  616. struct ath_softc *sc = hw->priv;
  617. struct ath_hw *ah = sc->sc_ah;
  618. struct ath_common *common = ath9k_hw_common(ah);
  619. bool prev_idle;
  620. mutex_lock(&sc->mutex);
  621. ath_cancel_work(sc);
  622. del_timer_sync(&sc->rx_poll_timer);
  623. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  624. ath_dbg(common, ANY, "Device not present\n");
  625. mutex_unlock(&sc->mutex);
  626. return;
  627. }
  628. /* Ensure HW is awake when we try to shut it down. */
  629. ath9k_ps_wakeup(sc);
  630. spin_lock_bh(&sc->sc_pcu_lock);
  631. /* prevent tasklets to enable interrupts once we disable them */
  632. ah->imask &= ~ATH9K_INT_GLOBAL;
  633. /* make sure h/w will not generate any interrupt
  634. * before setting the invalid flag. */
  635. ath9k_hw_disable_interrupts(ah);
  636. spin_unlock_bh(&sc->sc_pcu_lock);
  637. /* we can now sync irq and kill any running tasklets, since we already
  638. * disabled interrupts and not holding a spin lock */
  639. synchronize_irq(sc->irq);
  640. tasklet_kill(&sc->intr_tq);
  641. tasklet_kill(&sc->bcon_tasklet);
  642. prev_idle = sc->ps_idle;
  643. sc->ps_idle = true;
  644. spin_lock_bh(&sc->sc_pcu_lock);
  645. if (ah->led_pin >= 0) {
  646. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  647. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  648. }
  649. ath_prepare_reset(sc, false, true);
  650. if (sc->rx.frag) {
  651. dev_kfree_skb_any(sc->rx.frag);
  652. sc->rx.frag = NULL;
  653. }
  654. if (!ah->curchan)
  655. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  656. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  657. ath9k_hw_phy_disable(ah);
  658. ath9k_hw_configpcipowersave(ah, true);
  659. spin_unlock_bh(&sc->sc_pcu_lock);
  660. ath9k_ps_restore(sc);
  661. set_bit(SC_OP_INVALID, &sc->sc_flags);
  662. sc->ps_idle = prev_idle;
  663. mutex_unlock(&sc->mutex);
  664. ath_dbg(common, CONFIG, "Driver halt\n");
  665. }
  666. bool ath9k_uses_beacons(int type)
  667. {
  668. switch (type) {
  669. case NL80211_IFTYPE_AP:
  670. case NL80211_IFTYPE_ADHOC:
  671. case NL80211_IFTYPE_MESH_POINT:
  672. return true;
  673. default:
  674. return false;
  675. }
  676. }
  677. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  678. struct ieee80211_vif *vif)
  679. {
  680. struct ath_vif *avp = (void *)vif->drv_priv;
  681. ath9k_set_beaconing_status(sc, false);
  682. ath_beacon_return(sc, avp);
  683. ath9k_set_beaconing_status(sc, true);
  684. }
  685. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  686. {
  687. struct ath9k_vif_iter_data *iter_data = data;
  688. int i;
  689. if (iter_data->hw_macaddr)
  690. for (i = 0; i < ETH_ALEN; i++)
  691. iter_data->mask[i] &=
  692. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  693. switch (vif->type) {
  694. case NL80211_IFTYPE_AP:
  695. iter_data->naps++;
  696. break;
  697. case NL80211_IFTYPE_STATION:
  698. iter_data->nstations++;
  699. break;
  700. case NL80211_IFTYPE_ADHOC:
  701. iter_data->nadhocs++;
  702. break;
  703. case NL80211_IFTYPE_MESH_POINT:
  704. iter_data->nmeshes++;
  705. break;
  706. case NL80211_IFTYPE_WDS:
  707. iter_data->nwds++;
  708. break;
  709. default:
  710. break;
  711. }
  712. }
  713. /* Called with sc->mutex held. */
  714. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  715. struct ieee80211_vif *vif,
  716. struct ath9k_vif_iter_data *iter_data)
  717. {
  718. struct ath_softc *sc = hw->priv;
  719. struct ath_hw *ah = sc->sc_ah;
  720. struct ath_common *common = ath9k_hw_common(ah);
  721. /*
  722. * Use the hardware MAC address as reference, the hardware uses it
  723. * together with the BSSID mask when matching addresses.
  724. */
  725. memset(iter_data, 0, sizeof(*iter_data));
  726. iter_data->hw_macaddr = common->macaddr;
  727. memset(&iter_data->mask, 0xff, ETH_ALEN);
  728. if (vif)
  729. ath9k_vif_iter(iter_data, vif->addr, vif);
  730. /* Get list of all active MAC addresses */
  731. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  732. iter_data);
  733. }
  734. /* Called with sc->mutex held. */
  735. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  736. struct ieee80211_vif *vif)
  737. {
  738. struct ath_softc *sc = hw->priv;
  739. struct ath_hw *ah = sc->sc_ah;
  740. struct ath_common *common = ath9k_hw_common(ah);
  741. struct ath9k_vif_iter_data iter_data;
  742. ath9k_calculate_iter_data(hw, vif, &iter_data);
  743. /* Set BSSID mask. */
  744. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  745. ath_hw_setbssidmask(common);
  746. /* Set op-mode & TSF */
  747. if (iter_data.naps > 0) {
  748. ath9k_hw_set_tsfadjust(ah, 1);
  749. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  750. ah->opmode = NL80211_IFTYPE_AP;
  751. } else {
  752. ath9k_hw_set_tsfadjust(ah, 0);
  753. clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  754. if (iter_data.nmeshes)
  755. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  756. else if (iter_data.nwds)
  757. ah->opmode = NL80211_IFTYPE_AP;
  758. else if (iter_data.nadhocs)
  759. ah->opmode = NL80211_IFTYPE_ADHOC;
  760. else
  761. ah->opmode = NL80211_IFTYPE_STATION;
  762. }
  763. /*
  764. * Enable MIB interrupts when there are hardware phy counters.
  765. */
  766. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  767. ah->imask |= ATH9K_INT_TSFOOR;
  768. else
  769. ah->imask &= ~ATH9K_INT_TSFOOR;
  770. ath9k_hw_set_interrupts(ah);
  771. /* Set up ANI */
  772. if (iter_data.naps > 0) {
  773. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  774. if (!common->disable_ani) {
  775. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  776. ath_start_ani(common);
  777. }
  778. } else {
  779. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  780. del_timer_sync(&common->ani.timer);
  781. }
  782. }
  783. /* Called with sc->mutex held, vif counts set up properly. */
  784. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  785. struct ieee80211_vif *vif)
  786. {
  787. struct ath_softc *sc = hw->priv;
  788. ath9k_calculate_summary_state(hw, vif);
  789. if (ath9k_uses_beacons(vif->type)) {
  790. /* Reserve a beacon slot for the vif */
  791. ath9k_set_beaconing_status(sc, false);
  792. ath_beacon_alloc(sc, vif);
  793. ath9k_set_beaconing_status(sc, true);
  794. }
  795. }
  796. static int ath9k_add_interface(struct ieee80211_hw *hw,
  797. struct ieee80211_vif *vif)
  798. {
  799. struct ath_softc *sc = hw->priv;
  800. struct ath_hw *ah = sc->sc_ah;
  801. struct ath_common *common = ath9k_hw_common(ah);
  802. int ret = 0;
  803. ath9k_ps_wakeup(sc);
  804. mutex_lock(&sc->mutex);
  805. switch (vif->type) {
  806. case NL80211_IFTYPE_STATION:
  807. case NL80211_IFTYPE_WDS:
  808. case NL80211_IFTYPE_ADHOC:
  809. case NL80211_IFTYPE_AP:
  810. case NL80211_IFTYPE_MESH_POINT:
  811. break;
  812. default:
  813. ath_err(common, "Interface type %d not yet supported\n",
  814. vif->type);
  815. ret = -EOPNOTSUPP;
  816. goto out;
  817. }
  818. if (ath9k_uses_beacons(vif->type)) {
  819. if (sc->nbcnvifs >= ATH_BCBUF) {
  820. ath_err(common, "Not enough beacon buffers when adding"
  821. " new interface of type: %i\n",
  822. vif->type);
  823. ret = -ENOBUFS;
  824. goto out;
  825. }
  826. }
  827. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  828. sc->nvifs++;
  829. ath9k_do_vif_add_setup(hw, vif);
  830. out:
  831. mutex_unlock(&sc->mutex);
  832. ath9k_ps_restore(sc);
  833. return ret;
  834. }
  835. static int ath9k_change_interface(struct ieee80211_hw *hw,
  836. struct ieee80211_vif *vif,
  837. enum nl80211_iftype new_type,
  838. bool p2p)
  839. {
  840. struct ath_softc *sc = hw->priv;
  841. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  842. int ret = 0;
  843. ath_dbg(common, CONFIG, "Change Interface\n");
  844. mutex_lock(&sc->mutex);
  845. ath9k_ps_wakeup(sc);
  846. if (ath9k_uses_beacons(new_type) &&
  847. !ath9k_uses_beacons(vif->type)) {
  848. if (sc->nbcnvifs >= ATH_BCBUF) {
  849. ath_err(common, "No beacon slot available\n");
  850. ret = -ENOBUFS;
  851. goto out;
  852. }
  853. }
  854. /* Clean up old vif stuff */
  855. if (ath9k_uses_beacons(vif->type))
  856. ath9k_reclaim_beacon(sc, vif);
  857. /* Add new settings */
  858. vif->type = new_type;
  859. vif->p2p = p2p;
  860. ath9k_do_vif_add_setup(hw, vif);
  861. out:
  862. ath9k_ps_restore(sc);
  863. mutex_unlock(&sc->mutex);
  864. return ret;
  865. }
  866. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  867. struct ieee80211_vif *vif)
  868. {
  869. struct ath_softc *sc = hw->priv;
  870. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  871. ath_dbg(common, CONFIG, "Detach Interface\n");
  872. ath9k_ps_wakeup(sc);
  873. mutex_lock(&sc->mutex);
  874. sc->nvifs--;
  875. /* Reclaim beacon resources */
  876. if (ath9k_uses_beacons(vif->type))
  877. ath9k_reclaim_beacon(sc, vif);
  878. ath9k_calculate_summary_state(hw, NULL);
  879. mutex_unlock(&sc->mutex);
  880. ath9k_ps_restore(sc);
  881. }
  882. static void ath9k_enable_ps(struct ath_softc *sc)
  883. {
  884. struct ath_hw *ah = sc->sc_ah;
  885. struct ath_common *common = ath9k_hw_common(ah);
  886. sc->ps_enabled = true;
  887. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  888. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  889. ah->imask |= ATH9K_INT_TIM_TIMER;
  890. ath9k_hw_set_interrupts(ah);
  891. }
  892. ath9k_hw_setrxabort(ah, 1);
  893. }
  894. ath_dbg(common, PS, "PowerSave enabled\n");
  895. }
  896. static void ath9k_disable_ps(struct ath_softc *sc)
  897. {
  898. struct ath_hw *ah = sc->sc_ah;
  899. struct ath_common *common = ath9k_hw_common(ah);
  900. sc->ps_enabled = false;
  901. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  902. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  903. ath9k_hw_setrxabort(ah, 0);
  904. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  905. PS_WAIT_FOR_CAB |
  906. PS_WAIT_FOR_PSPOLL_DATA |
  907. PS_WAIT_FOR_TX_ACK);
  908. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  909. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  910. ath9k_hw_set_interrupts(ah);
  911. }
  912. }
  913. ath_dbg(common, PS, "PowerSave disabled\n");
  914. }
  915. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  916. {
  917. struct ath_softc *sc = hw->priv;
  918. struct ath_hw *ah = sc->sc_ah;
  919. struct ath_common *common = ath9k_hw_common(ah);
  920. struct ieee80211_conf *conf = &hw->conf;
  921. bool reset_channel = false;
  922. ath9k_ps_wakeup(sc);
  923. mutex_lock(&sc->mutex);
  924. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  925. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  926. if (sc->ps_idle) {
  927. ath_cancel_work(sc);
  928. ath9k_stop_btcoex(sc);
  929. } else {
  930. ath9k_start_btcoex(sc);
  931. /*
  932. * The chip needs a reset to properly wake up from
  933. * full sleep
  934. */
  935. reset_channel = ah->chip_fullsleep;
  936. }
  937. }
  938. /*
  939. * We just prepare to enable PS. We have to wait until our AP has
  940. * ACK'd our null data frame to disable RX otherwise we'll ignore
  941. * those ACKs and end up retransmitting the same null data frames.
  942. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  943. */
  944. if (changed & IEEE80211_CONF_CHANGE_PS) {
  945. unsigned long flags;
  946. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  947. if (conf->flags & IEEE80211_CONF_PS)
  948. ath9k_enable_ps(sc);
  949. else
  950. ath9k_disable_ps(sc);
  951. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  952. }
  953. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  954. if (conf->flags & IEEE80211_CONF_MONITOR) {
  955. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  956. sc->sc_ah->is_monitoring = true;
  957. } else {
  958. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  959. sc->sc_ah->is_monitoring = false;
  960. }
  961. }
  962. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  963. struct ieee80211_channel *curchan = hw->conf.channel;
  964. int pos = curchan->hw_value;
  965. int old_pos = -1;
  966. unsigned long flags;
  967. if (ah->curchan)
  968. old_pos = ah->curchan - &ah->channels[0];
  969. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  970. curchan->center_freq, conf->channel_type);
  971. /* update survey stats for the old channel before switching */
  972. spin_lock_irqsave(&common->cc_lock, flags);
  973. ath_update_survey_stats(sc);
  974. spin_unlock_irqrestore(&common->cc_lock, flags);
  975. /*
  976. * Preserve the current channel values, before updating
  977. * the same channel
  978. */
  979. if (ah->curchan && (old_pos == pos))
  980. ath9k_hw_getnf(ah, ah->curchan);
  981. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  982. curchan, conf->channel_type);
  983. /*
  984. * If the operating channel changes, change the survey in-use flags
  985. * along with it.
  986. * Reset the survey data for the new channel, unless we're switching
  987. * back to the operating channel from an off-channel operation.
  988. */
  989. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  990. sc->cur_survey != &sc->survey[pos]) {
  991. if (sc->cur_survey)
  992. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  993. sc->cur_survey = &sc->survey[pos];
  994. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  995. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  996. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  997. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  998. }
  999. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1000. ath_err(common, "Unable to set channel\n");
  1001. mutex_unlock(&sc->mutex);
  1002. ath9k_ps_restore(sc);
  1003. return -EINVAL;
  1004. }
  1005. /*
  1006. * The most recent snapshot of channel->noisefloor for the old
  1007. * channel is only available after the hardware reset. Copy it to
  1008. * the survey stats now.
  1009. */
  1010. if (old_pos >= 0)
  1011. ath_update_survey_nf(sc, old_pos);
  1012. }
  1013. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1014. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1015. sc->config.txpowlimit = 2 * conf->power_level;
  1016. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1017. sc->config.txpowlimit, &sc->curtxpow);
  1018. }
  1019. mutex_unlock(&sc->mutex);
  1020. ath9k_ps_restore(sc);
  1021. return 0;
  1022. }
  1023. #define SUPPORTED_FILTERS \
  1024. (FIF_PROMISC_IN_BSS | \
  1025. FIF_ALLMULTI | \
  1026. FIF_CONTROL | \
  1027. FIF_PSPOLL | \
  1028. FIF_OTHER_BSS | \
  1029. FIF_BCN_PRBRESP_PROMISC | \
  1030. FIF_PROBE_REQ | \
  1031. FIF_FCSFAIL)
  1032. /* FIXME: sc->sc_full_reset ? */
  1033. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1034. unsigned int changed_flags,
  1035. unsigned int *total_flags,
  1036. u64 multicast)
  1037. {
  1038. struct ath_softc *sc = hw->priv;
  1039. u32 rfilt;
  1040. changed_flags &= SUPPORTED_FILTERS;
  1041. *total_flags &= SUPPORTED_FILTERS;
  1042. sc->rx.rxfilter = *total_flags;
  1043. ath9k_ps_wakeup(sc);
  1044. rfilt = ath_calcrxfilter(sc);
  1045. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1046. ath9k_ps_restore(sc);
  1047. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1048. rfilt);
  1049. }
  1050. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1051. struct ieee80211_vif *vif,
  1052. struct ieee80211_sta *sta)
  1053. {
  1054. struct ath_softc *sc = hw->priv;
  1055. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1056. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1057. struct ieee80211_key_conf ps_key = { };
  1058. ath_node_attach(sc, sta, vif);
  1059. if (vif->type != NL80211_IFTYPE_AP &&
  1060. vif->type != NL80211_IFTYPE_AP_VLAN)
  1061. return 0;
  1062. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1063. return 0;
  1064. }
  1065. static void ath9k_del_ps_key(struct ath_softc *sc,
  1066. struct ieee80211_vif *vif,
  1067. struct ieee80211_sta *sta)
  1068. {
  1069. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1070. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1071. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1072. if (!an->ps_key)
  1073. return;
  1074. ath_key_delete(common, &ps_key);
  1075. }
  1076. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1077. struct ieee80211_vif *vif,
  1078. struct ieee80211_sta *sta)
  1079. {
  1080. struct ath_softc *sc = hw->priv;
  1081. ath9k_del_ps_key(sc, vif, sta);
  1082. ath_node_detach(sc, sta);
  1083. return 0;
  1084. }
  1085. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1086. struct ieee80211_vif *vif,
  1087. enum sta_notify_cmd cmd,
  1088. struct ieee80211_sta *sta)
  1089. {
  1090. struct ath_softc *sc = hw->priv;
  1091. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1092. if (!sta->ht_cap.ht_supported)
  1093. return;
  1094. switch (cmd) {
  1095. case STA_NOTIFY_SLEEP:
  1096. an->sleeping = true;
  1097. ath_tx_aggr_sleep(sta, sc, an);
  1098. break;
  1099. case STA_NOTIFY_AWAKE:
  1100. an->sleeping = false;
  1101. ath_tx_aggr_wakeup(sc, an);
  1102. break;
  1103. }
  1104. }
  1105. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1106. struct ieee80211_vif *vif, u16 queue,
  1107. const struct ieee80211_tx_queue_params *params)
  1108. {
  1109. struct ath_softc *sc = hw->priv;
  1110. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1111. struct ath_txq *txq;
  1112. struct ath9k_tx_queue_info qi;
  1113. int ret = 0;
  1114. if (queue >= WME_NUM_AC)
  1115. return 0;
  1116. txq = sc->tx.txq_map[queue];
  1117. ath9k_ps_wakeup(sc);
  1118. mutex_lock(&sc->mutex);
  1119. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1120. qi.tqi_aifs = params->aifs;
  1121. qi.tqi_cwmin = params->cw_min;
  1122. qi.tqi_cwmax = params->cw_max;
  1123. qi.tqi_burstTime = params->txop;
  1124. ath_dbg(common, CONFIG,
  1125. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1126. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1127. params->cw_max, params->txop);
  1128. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1129. if (ret)
  1130. ath_err(common, "TXQ Update failed\n");
  1131. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1132. if (queue == WME_AC_BE && !ret)
  1133. ath_beaconq_config(sc);
  1134. mutex_unlock(&sc->mutex);
  1135. ath9k_ps_restore(sc);
  1136. return ret;
  1137. }
  1138. static int ath9k_set_key(struct ieee80211_hw *hw,
  1139. enum set_key_cmd cmd,
  1140. struct ieee80211_vif *vif,
  1141. struct ieee80211_sta *sta,
  1142. struct ieee80211_key_conf *key)
  1143. {
  1144. struct ath_softc *sc = hw->priv;
  1145. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1146. int ret = 0;
  1147. if (ath9k_modparam_nohwcrypt)
  1148. return -ENOSPC;
  1149. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1150. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1151. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1152. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1153. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1154. /*
  1155. * For now, disable hw crypto for the RSN IBSS group keys. This
  1156. * could be optimized in the future to use a modified key cache
  1157. * design to support per-STA RX GTK, but until that gets
  1158. * implemented, use of software crypto for group addressed
  1159. * frames is a acceptable to allow RSN IBSS to be used.
  1160. */
  1161. return -EOPNOTSUPP;
  1162. }
  1163. mutex_lock(&sc->mutex);
  1164. ath9k_ps_wakeup(sc);
  1165. ath_dbg(common, CONFIG, "Set HW Key\n");
  1166. switch (cmd) {
  1167. case SET_KEY:
  1168. if (sta)
  1169. ath9k_del_ps_key(sc, vif, sta);
  1170. ret = ath_key_config(common, vif, sta, key);
  1171. if (ret >= 0) {
  1172. key->hw_key_idx = ret;
  1173. /* push IV and Michael MIC generation to stack */
  1174. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1175. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1176. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1177. if (sc->sc_ah->sw_mgmt_crypto &&
  1178. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1179. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1180. ret = 0;
  1181. }
  1182. break;
  1183. case DISABLE_KEY:
  1184. ath_key_delete(common, key);
  1185. break;
  1186. default:
  1187. ret = -EINVAL;
  1188. }
  1189. ath9k_ps_restore(sc);
  1190. mutex_unlock(&sc->mutex);
  1191. return ret;
  1192. }
  1193. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1194. {
  1195. struct ath_softc *sc = data;
  1196. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1197. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1198. struct ath_vif *avp = (void *)vif->drv_priv;
  1199. unsigned long flags;
  1200. /*
  1201. * Skip iteration if primary station vif's bss info
  1202. * was not changed
  1203. */
  1204. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1205. return;
  1206. if (bss_conf->assoc) {
  1207. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1208. avp->primary_sta_vif = true;
  1209. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1210. common->curaid = bss_conf->aid;
  1211. ath9k_hw_write_associd(sc->sc_ah);
  1212. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1213. bss_conf->aid, common->curbssid);
  1214. ath_beacon_config(sc, vif);
  1215. /*
  1216. * Request a re-configuration of Beacon related timers
  1217. * on the receipt of the first Beacon frame (i.e.,
  1218. * after time sync with the AP).
  1219. */
  1220. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1221. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1222. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1223. /* Reset rssi stats */
  1224. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1225. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1226. ath_start_rx_poll(sc, 3);
  1227. if (!common->disable_ani) {
  1228. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1229. ath_start_ani(common);
  1230. }
  1231. }
  1232. }
  1233. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1234. {
  1235. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1236. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1237. struct ath_vif *avp = (void *)vif->drv_priv;
  1238. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1239. return;
  1240. /* Reconfigure bss info */
  1241. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1242. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1243. common->curaid, common->curbssid);
  1244. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1245. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1246. avp->primary_sta_vif = false;
  1247. memset(common->curbssid, 0, ETH_ALEN);
  1248. common->curaid = 0;
  1249. }
  1250. ieee80211_iterate_active_interfaces_atomic(
  1251. sc->hw, ath9k_bss_iter, sc);
  1252. /*
  1253. * None of station vifs are associated.
  1254. * Clear bssid & aid
  1255. */
  1256. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1257. ath9k_hw_write_associd(sc->sc_ah);
  1258. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1259. del_timer_sync(&common->ani.timer);
  1260. del_timer_sync(&sc->rx_poll_timer);
  1261. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1262. }
  1263. }
  1264. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1265. struct ieee80211_vif *vif,
  1266. struct ieee80211_bss_conf *bss_conf,
  1267. u32 changed)
  1268. {
  1269. struct ath_softc *sc = hw->priv;
  1270. struct ath_hw *ah = sc->sc_ah;
  1271. struct ath_common *common = ath9k_hw_common(ah);
  1272. struct ath_vif *avp = (void *)vif->drv_priv;
  1273. int slottime;
  1274. ath9k_ps_wakeup(sc);
  1275. mutex_lock(&sc->mutex);
  1276. if (changed & BSS_CHANGED_ASSOC) {
  1277. ath9k_config_bss(sc, vif);
  1278. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1279. common->curbssid, common->curaid);
  1280. }
  1281. if (changed & BSS_CHANGED_IBSS) {
  1282. /* There can be only one vif available */
  1283. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1284. common->curaid = bss_conf->aid;
  1285. ath9k_hw_write_associd(sc->sc_ah);
  1286. if (bss_conf->ibss_joined) {
  1287. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1288. if (!common->disable_ani) {
  1289. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1290. ath_start_ani(common);
  1291. }
  1292. } else {
  1293. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1294. del_timer_sync(&common->ani.timer);
  1295. del_timer_sync(&sc->rx_poll_timer);
  1296. }
  1297. }
  1298. /*
  1299. * In case of AP mode, the HW TSF has to be reset
  1300. * when the beacon interval changes.
  1301. */
  1302. if ((changed & BSS_CHANGED_BEACON_INT) &&
  1303. (vif->type == NL80211_IFTYPE_AP))
  1304. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  1305. /* Configure beaconing (AP, IBSS, MESH) */
  1306. if (ath9k_uses_beacons(vif->type) &&
  1307. ((changed & BSS_CHANGED_BEACON) ||
  1308. (changed & BSS_CHANGED_BEACON_ENABLED) ||
  1309. (changed & BSS_CHANGED_BEACON_INT))) {
  1310. ath9k_set_beaconing_status(sc, false);
  1311. if (bss_conf->enable_beacon)
  1312. ath_beacon_alloc(sc, vif);
  1313. else
  1314. avp->is_bslot_active = false;
  1315. ath_beacon_config(sc, vif);
  1316. ath9k_set_beaconing_status(sc, true);
  1317. }
  1318. if (changed & BSS_CHANGED_ERP_SLOT) {
  1319. if (bss_conf->use_short_slot)
  1320. slottime = 9;
  1321. else
  1322. slottime = 20;
  1323. if (vif->type == NL80211_IFTYPE_AP) {
  1324. /*
  1325. * Defer update, so that connected stations can adjust
  1326. * their settings at the same time.
  1327. * See beacon.c for more details
  1328. */
  1329. sc->beacon.slottime = slottime;
  1330. sc->beacon.updateslot = UPDATE;
  1331. } else {
  1332. ah->slottime = slottime;
  1333. ath9k_hw_init_global_settings(ah);
  1334. }
  1335. }
  1336. mutex_unlock(&sc->mutex);
  1337. ath9k_ps_restore(sc);
  1338. }
  1339. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1340. {
  1341. struct ath_softc *sc = hw->priv;
  1342. u64 tsf;
  1343. mutex_lock(&sc->mutex);
  1344. ath9k_ps_wakeup(sc);
  1345. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1346. ath9k_ps_restore(sc);
  1347. mutex_unlock(&sc->mutex);
  1348. return tsf;
  1349. }
  1350. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1351. struct ieee80211_vif *vif,
  1352. u64 tsf)
  1353. {
  1354. struct ath_softc *sc = hw->priv;
  1355. mutex_lock(&sc->mutex);
  1356. ath9k_ps_wakeup(sc);
  1357. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1358. ath9k_ps_restore(sc);
  1359. mutex_unlock(&sc->mutex);
  1360. }
  1361. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1362. {
  1363. struct ath_softc *sc = hw->priv;
  1364. mutex_lock(&sc->mutex);
  1365. ath9k_ps_wakeup(sc);
  1366. ath9k_hw_reset_tsf(sc->sc_ah);
  1367. ath9k_ps_restore(sc);
  1368. mutex_unlock(&sc->mutex);
  1369. }
  1370. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1371. struct ieee80211_vif *vif,
  1372. enum ieee80211_ampdu_mlme_action action,
  1373. struct ieee80211_sta *sta,
  1374. u16 tid, u16 *ssn, u8 buf_size)
  1375. {
  1376. struct ath_softc *sc = hw->priv;
  1377. int ret = 0;
  1378. local_bh_disable();
  1379. switch (action) {
  1380. case IEEE80211_AMPDU_RX_START:
  1381. break;
  1382. case IEEE80211_AMPDU_RX_STOP:
  1383. break;
  1384. case IEEE80211_AMPDU_TX_START:
  1385. ath9k_ps_wakeup(sc);
  1386. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1387. if (!ret)
  1388. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1389. ath9k_ps_restore(sc);
  1390. break;
  1391. case IEEE80211_AMPDU_TX_STOP:
  1392. ath9k_ps_wakeup(sc);
  1393. ath_tx_aggr_stop(sc, sta, tid);
  1394. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1395. ath9k_ps_restore(sc);
  1396. break;
  1397. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1398. ath9k_ps_wakeup(sc);
  1399. ath_tx_aggr_resume(sc, sta, tid);
  1400. ath9k_ps_restore(sc);
  1401. break;
  1402. default:
  1403. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1404. }
  1405. local_bh_enable();
  1406. return ret;
  1407. }
  1408. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1409. struct survey_info *survey)
  1410. {
  1411. struct ath_softc *sc = hw->priv;
  1412. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1413. struct ieee80211_supported_band *sband;
  1414. struct ieee80211_channel *chan;
  1415. unsigned long flags;
  1416. int pos;
  1417. spin_lock_irqsave(&common->cc_lock, flags);
  1418. if (idx == 0)
  1419. ath_update_survey_stats(sc);
  1420. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1421. if (sband && idx >= sband->n_channels) {
  1422. idx -= sband->n_channels;
  1423. sband = NULL;
  1424. }
  1425. if (!sband)
  1426. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1427. if (!sband || idx >= sband->n_channels) {
  1428. spin_unlock_irqrestore(&common->cc_lock, flags);
  1429. return -ENOENT;
  1430. }
  1431. chan = &sband->channels[idx];
  1432. pos = chan->hw_value;
  1433. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1434. survey->channel = chan;
  1435. spin_unlock_irqrestore(&common->cc_lock, flags);
  1436. return 0;
  1437. }
  1438. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1439. {
  1440. struct ath_softc *sc = hw->priv;
  1441. struct ath_hw *ah = sc->sc_ah;
  1442. mutex_lock(&sc->mutex);
  1443. ah->coverage_class = coverage_class;
  1444. ath9k_ps_wakeup(sc);
  1445. ath9k_hw_init_global_settings(ah);
  1446. ath9k_ps_restore(sc);
  1447. mutex_unlock(&sc->mutex);
  1448. }
  1449. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1450. {
  1451. struct ath_softc *sc = hw->priv;
  1452. struct ath_hw *ah = sc->sc_ah;
  1453. struct ath_common *common = ath9k_hw_common(ah);
  1454. int timeout = 200; /* ms */
  1455. int i, j;
  1456. bool drain_txq;
  1457. mutex_lock(&sc->mutex);
  1458. cancel_delayed_work_sync(&sc->tx_complete_work);
  1459. if (ah->ah_flags & AH_UNPLUGGED) {
  1460. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1461. mutex_unlock(&sc->mutex);
  1462. return;
  1463. }
  1464. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1465. ath_dbg(common, ANY, "Device not present\n");
  1466. mutex_unlock(&sc->mutex);
  1467. return;
  1468. }
  1469. for (j = 0; j < timeout; j++) {
  1470. bool npend = false;
  1471. if (j)
  1472. usleep_range(1000, 2000);
  1473. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1474. if (!ATH_TXQ_SETUP(sc, i))
  1475. continue;
  1476. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1477. if (npend)
  1478. break;
  1479. }
  1480. if (!npend)
  1481. break;
  1482. }
  1483. if (drop) {
  1484. ath9k_ps_wakeup(sc);
  1485. spin_lock_bh(&sc->sc_pcu_lock);
  1486. drain_txq = ath_drain_all_txq(sc, false);
  1487. spin_unlock_bh(&sc->sc_pcu_lock);
  1488. if (!drain_txq)
  1489. ath_reset(sc, false);
  1490. ath9k_ps_restore(sc);
  1491. ieee80211_wake_queues(hw);
  1492. }
  1493. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1494. mutex_unlock(&sc->mutex);
  1495. }
  1496. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1497. {
  1498. struct ath_softc *sc = hw->priv;
  1499. int i;
  1500. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1501. if (!ATH_TXQ_SETUP(sc, i))
  1502. continue;
  1503. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1504. return true;
  1505. }
  1506. return false;
  1507. }
  1508. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1509. {
  1510. struct ath_softc *sc = hw->priv;
  1511. struct ath_hw *ah = sc->sc_ah;
  1512. struct ieee80211_vif *vif;
  1513. struct ath_vif *avp;
  1514. struct ath_buf *bf;
  1515. struct ath_tx_status ts;
  1516. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1517. int status;
  1518. vif = sc->beacon.bslot[0];
  1519. if (!vif)
  1520. return 0;
  1521. avp = (void *)vif->drv_priv;
  1522. if (!avp->is_bslot_active)
  1523. return 0;
  1524. if (!sc->beacon.tx_processed && !edma) {
  1525. tasklet_disable(&sc->bcon_tasklet);
  1526. bf = avp->av_bcbuf;
  1527. if (!bf || !bf->bf_mpdu)
  1528. goto skip;
  1529. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1530. if (status == -EINPROGRESS)
  1531. goto skip;
  1532. sc->beacon.tx_processed = true;
  1533. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1534. skip:
  1535. tasklet_enable(&sc->bcon_tasklet);
  1536. }
  1537. return sc->beacon.tx_last;
  1538. }
  1539. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1540. struct ieee80211_low_level_stats *stats)
  1541. {
  1542. struct ath_softc *sc = hw->priv;
  1543. struct ath_hw *ah = sc->sc_ah;
  1544. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1545. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1546. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1547. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1548. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1549. return 0;
  1550. }
  1551. static u32 fill_chainmask(u32 cap, u32 new)
  1552. {
  1553. u32 filled = 0;
  1554. int i;
  1555. for (i = 0; cap && new; i++, cap >>= 1) {
  1556. if (!(cap & BIT(0)))
  1557. continue;
  1558. if (new & BIT(0))
  1559. filled |= BIT(i);
  1560. new >>= 1;
  1561. }
  1562. return filled;
  1563. }
  1564. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1565. {
  1566. struct ath_softc *sc = hw->priv;
  1567. struct ath_hw *ah = sc->sc_ah;
  1568. if (!rx_ant || !tx_ant)
  1569. return -EINVAL;
  1570. sc->ant_rx = rx_ant;
  1571. sc->ant_tx = tx_ant;
  1572. if (ah->caps.rx_chainmask == 1)
  1573. return 0;
  1574. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1575. if (AR_SREV_9100(ah))
  1576. ah->rxchainmask = 0x7;
  1577. else
  1578. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1579. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1580. ath9k_reload_chainmask_settings(sc);
  1581. return 0;
  1582. }
  1583. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1584. {
  1585. struct ath_softc *sc = hw->priv;
  1586. *tx_ant = sc->ant_tx;
  1587. *rx_ant = sc->ant_rx;
  1588. return 0;
  1589. }
  1590. #ifdef CONFIG_ATH9K_DEBUGFS
  1591. /* Ethtool support for get-stats */
  1592. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1593. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1594. "tx_pkts_nic",
  1595. "tx_bytes_nic",
  1596. "rx_pkts_nic",
  1597. "rx_bytes_nic",
  1598. AMKSTR(d_tx_pkts),
  1599. AMKSTR(d_tx_bytes),
  1600. AMKSTR(d_tx_mpdus_queued),
  1601. AMKSTR(d_tx_mpdus_completed),
  1602. AMKSTR(d_tx_mpdu_xretries),
  1603. AMKSTR(d_tx_aggregates),
  1604. AMKSTR(d_tx_ampdus_queued_hw),
  1605. AMKSTR(d_tx_ampdus_queued_sw),
  1606. AMKSTR(d_tx_ampdus_completed),
  1607. AMKSTR(d_tx_ampdu_retries),
  1608. AMKSTR(d_tx_ampdu_xretries),
  1609. AMKSTR(d_tx_fifo_underrun),
  1610. AMKSTR(d_tx_op_exceeded),
  1611. AMKSTR(d_tx_timer_expiry),
  1612. AMKSTR(d_tx_desc_cfg_err),
  1613. AMKSTR(d_tx_data_underrun),
  1614. AMKSTR(d_tx_delim_underrun),
  1615. "d_rx_decrypt_crc_err",
  1616. "d_rx_phy_err",
  1617. "d_rx_mic_err",
  1618. "d_rx_pre_delim_crc_err",
  1619. "d_rx_post_delim_crc_err",
  1620. "d_rx_decrypt_busy_err",
  1621. "d_rx_phyerr_radar",
  1622. "d_rx_phyerr_ofdm_timing",
  1623. "d_rx_phyerr_cck_timing",
  1624. };
  1625. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1626. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1627. struct ieee80211_vif *vif,
  1628. u32 sset, u8 *data)
  1629. {
  1630. if (sset == ETH_SS_STATS)
  1631. memcpy(data, *ath9k_gstrings_stats,
  1632. sizeof(ath9k_gstrings_stats));
  1633. }
  1634. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1635. struct ieee80211_vif *vif, int sset)
  1636. {
  1637. if (sset == ETH_SS_STATS)
  1638. return ATH9K_SSTATS_LEN;
  1639. return 0;
  1640. }
  1641. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1642. #define AWDATA(elem) \
  1643. do { \
  1644. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1645. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1646. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1647. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1648. } while (0)
  1649. #define AWDATA_RX(elem) \
  1650. do { \
  1651. data[i++] = sc->debug.stats.rxstats.elem; \
  1652. } while (0)
  1653. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1654. struct ieee80211_vif *vif,
  1655. struct ethtool_stats *stats, u64 *data)
  1656. {
  1657. struct ath_softc *sc = hw->priv;
  1658. int i = 0;
  1659. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1660. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1661. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1662. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1663. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1664. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1665. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1666. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1667. AWDATA_RX(rx_pkts_all);
  1668. AWDATA_RX(rx_bytes_all);
  1669. AWDATA(tx_pkts_all);
  1670. AWDATA(tx_bytes_all);
  1671. AWDATA(queued);
  1672. AWDATA(completed);
  1673. AWDATA(xretries);
  1674. AWDATA(a_aggr);
  1675. AWDATA(a_queued_hw);
  1676. AWDATA(a_queued_sw);
  1677. AWDATA(a_completed);
  1678. AWDATA(a_retries);
  1679. AWDATA(a_xretries);
  1680. AWDATA(fifo_underrun);
  1681. AWDATA(xtxop);
  1682. AWDATA(timer_exp);
  1683. AWDATA(desc_cfg_err);
  1684. AWDATA(data_underrun);
  1685. AWDATA(delim_underrun);
  1686. AWDATA_RX(decrypt_crc_err);
  1687. AWDATA_RX(phy_err);
  1688. AWDATA_RX(mic_err);
  1689. AWDATA_RX(pre_delim_crc_err);
  1690. AWDATA_RX(post_delim_crc_err);
  1691. AWDATA_RX(decrypt_busy_err);
  1692. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1693. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1694. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1695. WARN_ON(i != ATH9K_SSTATS_LEN);
  1696. }
  1697. /* End of ethtool get-stats functions */
  1698. #endif
  1699. struct ieee80211_ops ath9k_ops = {
  1700. .tx = ath9k_tx,
  1701. .start = ath9k_start,
  1702. .stop = ath9k_stop,
  1703. .add_interface = ath9k_add_interface,
  1704. .change_interface = ath9k_change_interface,
  1705. .remove_interface = ath9k_remove_interface,
  1706. .config = ath9k_config,
  1707. .configure_filter = ath9k_configure_filter,
  1708. .sta_add = ath9k_sta_add,
  1709. .sta_remove = ath9k_sta_remove,
  1710. .sta_notify = ath9k_sta_notify,
  1711. .conf_tx = ath9k_conf_tx,
  1712. .bss_info_changed = ath9k_bss_info_changed,
  1713. .set_key = ath9k_set_key,
  1714. .get_tsf = ath9k_get_tsf,
  1715. .set_tsf = ath9k_set_tsf,
  1716. .reset_tsf = ath9k_reset_tsf,
  1717. .ampdu_action = ath9k_ampdu_action,
  1718. .get_survey = ath9k_get_survey,
  1719. .rfkill_poll = ath9k_rfkill_poll_state,
  1720. .set_coverage_class = ath9k_set_coverage_class,
  1721. .flush = ath9k_flush,
  1722. .tx_frames_pending = ath9k_tx_frames_pending,
  1723. .tx_last_beacon = ath9k_tx_last_beacon,
  1724. .get_stats = ath9k_get_stats,
  1725. .set_antenna = ath9k_set_antenna,
  1726. .get_antenna = ath9k_get_antenna,
  1727. #ifdef CONFIG_ATH9K_DEBUGFS
  1728. .get_et_sset_count = ath9k_get_et_sset_count,
  1729. .get_et_stats = ath9k_get_et_stats,
  1730. .get_et_strings = ath9k_get_et_strings,
  1731. #endif
  1732. };