i387.h 11 KB

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  1. /*
  2. * Copyright (C) 1994 Linus Torvalds
  3. *
  4. * Pentium III FXSR, SSE support
  5. * General FPU state handling cleanups
  6. * Gareth Hughes <gareth@valinux.com>, May 2000
  7. * x86-64 work by Andi Kleen 2002
  8. */
  9. #ifndef _ASM_X86_I387_H
  10. #define _ASM_X86_I387_H
  11. #ifndef __ASSEMBLY__
  12. #include <linux/sched.h>
  13. #include <linux/kernel_stat.h>
  14. #include <linux/regset.h>
  15. #include <linux/hardirq.h>
  16. #include <asm/asm.h>
  17. #include <asm/processor.h>
  18. #include <asm/sigcontext.h>
  19. #include <asm/user.h>
  20. #include <asm/uaccess.h>
  21. #include <asm/xsave.h>
  22. extern unsigned int sig_xstate_size;
  23. extern void fpu_init(void);
  24. extern void mxcsr_feature_mask_init(void);
  25. extern int init_fpu(struct task_struct *child);
  26. extern asmlinkage void math_state_restore(void);
  27. extern void __math_state_restore(void);
  28. extern void init_thread_xstate(void);
  29. extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
  30. extern user_regset_active_fn fpregs_active, xfpregs_active;
  31. extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
  32. xstateregs_get;
  33. extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
  34. xstateregs_set;
  35. /*
  36. * xstateregs_active == fpregs_active. Please refer to the comment
  37. * at the definition of fpregs_active.
  38. */
  39. #define xstateregs_active fpregs_active
  40. extern struct _fpx_sw_bytes fx_sw_reserved;
  41. #ifdef CONFIG_IA32_EMULATION
  42. extern unsigned int sig_xstate_ia32_size;
  43. extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
  44. struct _fpstate_ia32;
  45. struct _xstate_ia32;
  46. extern int save_i387_xstate_ia32(void __user *buf);
  47. extern int restore_i387_xstate_ia32(void __user *buf);
  48. #endif
  49. #define X87_FSW_ES (1 << 7) /* Exception Summary */
  50. #ifdef CONFIG_X86_64
  51. /* Ignore delayed exceptions from user space */
  52. static inline void tolerant_fwait(void)
  53. {
  54. asm volatile("1: fwait\n"
  55. "2:\n"
  56. _ASM_EXTABLE(1b, 2b));
  57. }
  58. static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
  59. {
  60. int err;
  61. asm volatile("1: rex64/fxrstor (%[fx])\n\t"
  62. "2:\n"
  63. ".section .fixup,\"ax\"\n"
  64. "3: movl $-1,%[err]\n"
  65. " jmp 2b\n"
  66. ".previous\n"
  67. _ASM_EXTABLE(1b, 3b)
  68. : [err] "=r" (err)
  69. #if 0 /* See comment in fxsave() below. */
  70. : [fx] "r" (fx), "m" (*fx), "0" (0));
  71. #else
  72. : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
  73. #endif
  74. return err;
  75. }
  76. /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
  77. is pending. Clear the x87 state here by setting it to fixed
  78. values. The kernel data segment can be sometimes 0 and sometimes
  79. new user value. Both should be ok.
  80. Use the PDA as safe address because it should be already in L1. */
  81. static inline void clear_fpu_state(struct task_struct *tsk)
  82. {
  83. struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
  84. struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
  85. /*
  86. * xsave header may indicate the init state of the FP.
  87. */
  88. if ((task_thread_info(tsk)->status & TS_XSAVE) &&
  89. !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
  90. return;
  91. if (unlikely(fx->swd & X87_FSW_ES))
  92. asm volatile("fnclex");
  93. alternative_input(ASM_NOP8 ASM_NOP2,
  94. " emms\n" /* clear stack tags */
  95. " fildl %%gs:0", /* load to clear state */
  96. X86_FEATURE_FXSAVE_LEAK);
  97. }
  98. static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
  99. {
  100. int err;
  101. asm volatile("1: rex64/fxsave (%[fx])\n\t"
  102. "2:\n"
  103. ".section .fixup,\"ax\"\n"
  104. "3: movl $-1,%[err]\n"
  105. " jmp 2b\n"
  106. ".previous\n"
  107. _ASM_EXTABLE(1b, 3b)
  108. : [err] "=r" (err), "=m" (*fx)
  109. #if 0 /* See comment in fxsave() below. */
  110. : [fx] "r" (fx), "0" (0));
  111. #else
  112. : [fx] "cdaSDb" (fx), "0" (0));
  113. #endif
  114. if (unlikely(err) &&
  115. __clear_user(fx, sizeof(struct i387_fxsave_struct)))
  116. err = -EFAULT;
  117. /* No need to clear here because the caller clears USED_MATH */
  118. return err;
  119. }
  120. static inline void fxsave(struct task_struct *tsk)
  121. {
  122. /* Using "rex64; fxsave %0" is broken because, if the memory operand
  123. uses any extended registers for addressing, a second REX prefix
  124. will be generated (to the assembler, rex64 followed by semicolon
  125. is a separate instruction), and hence the 64-bitness is lost. */
  126. #if 0
  127. /* Using "fxsaveq %0" would be the ideal choice, but is only supported
  128. starting with gas 2.16. */
  129. __asm__ __volatile__("fxsaveq %0"
  130. : "=m" (tsk->thread.xstate->fxsave));
  131. #elif 0
  132. /* Using, as a workaround, the properly prefixed form below isn't
  133. accepted by any binutils version so far released, complaining that
  134. the same type of prefix is used twice if an extended register is
  135. needed for addressing (fix submitted to mainline 2005-11-21). */
  136. __asm__ __volatile__("rex64/fxsave %0"
  137. : "=m" (tsk->thread.xstate->fxsave));
  138. #else
  139. /* This, however, we can work around by forcing the compiler to select
  140. an addressing mode that doesn't require extended registers. */
  141. __asm__ __volatile__("rex64/fxsave (%1)"
  142. : "=m" (tsk->thread.xstate->fxsave)
  143. : "cdaSDb" (&tsk->thread.xstate->fxsave));
  144. #endif
  145. }
  146. static inline void __save_init_fpu(struct task_struct *tsk)
  147. {
  148. if (task_thread_info(tsk)->status & TS_XSAVE)
  149. xsave(tsk);
  150. else
  151. fxsave(tsk);
  152. clear_fpu_state(tsk);
  153. task_thread_info(tsk)->status &= ~TS_USEDFPU;
  154. }
  155. #else /* CONFIG_X86_32 */
  156. #ifdef CONFIG_MATH_EMULATION
  157. extern void finit_task(struct task_struct *tsk);
  158. #else
  159. static inline void finit_task(struct task_struct *tsk)
  160. {
  161. }
  162. #endif
  163. static inline void tolerant_fwait(void)
  164. {
  165. asm volatile("fnclex ; fwait");
  166. }
  167. /* perform fxrstor iff the processor has extended states, otherwise frstor */
  168. static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
  169. {
  170. /*
  171. * The "nop" is needed to make the instructions the same
  172. * length.
  173. */
  174. alternative_input(
  175. "nop ; frstor %1",
  176. "fxrstor %1",
  177. X86_FEATURE_FXSR,
  178. "m" (*fx));
  179. return 0;
  180. }
  181. /* We need a safe address that is cheap to find and that is already
  182. in L1 during context switch. The best choices are unfortunately
  183. different for UP and SMP */
  184. #ifdef CONFIG_SMP
  185. #define safe_address (__per_cpu_offset[0])
  186. #else
  187. #define safe_address (kstat_cpu(0).cpustat.user)
  188. #endif
  189. /*
  190. * These must be called with preempt disabled
  191. */
  192. static inline void __save_init_fpu(struct task_struct *tsk)
  193. {
  194. if (task_thread_info(tsk)->status & TS_XSAVE) {
  195. struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
  196. struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
  197. xsave(tsk);
  198. /*
  199. * xsave header may indicate the init state of the FP.
  200. */
  201. if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
  202. goto end;
  203. if (unlikely(fx->swd & X87_FSW_ES))
  204. asm volatile("fnclex");
  205. /*
  206. * we can do a simple return here or be paranoid :)
  207. */
  208. goto clear_state;
  209. }
  210. /* Use more nops than strictly needed in case the compiler
  211. varies code */
  212. alternative_input(
  213. "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
  214. "fxsave %[fx]\n"
  215. "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
  216. X86_FEATURE_FXSR,
  217. [fx] "m" (tsk->thread.xstate->fxsave),
  218. [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
  219. clear_state:
  220. /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
  221. is pending. Clear the x87 state here by setting it to fixed
  222. values. safe_address is a random variable that should be in L1 */
  223. alternative_input(
  224. GENERIC_NOP8 GENERIC_NOP2,
  225. "emms\n\t" /* clear stack tags */
  226. "fildl %[addr]", /* set F?P to defined value */
  227. X86_FEATURE_FXSAVE_LEAK,
  228. [addr] "m" (safe_address));
  229. end:
  230. task_thread_info(tsk)->status &= ~TS_USEDFPU;
  231. }
  232. #endif /* CONFIG_X86_64 */
  233. static inline int restore_fpu_checking(struct task_struct *tsk)
  234. {
  235. if (task_thread_info(tsk)->status & TS_XSAVE)
  236. return xrstor_checking(&tsk->thread.xstate->xsave);
  237. else
  238. return fxrstor_checking(&tsk->thread.xstate->fxsave);
  239. }
  240. /*
  241. * Signal frame handlers...
  242. */
  243. extern int save_i387_xstate(void __user *buf);
  244. extern int restore_i387_xstate(void __user *buf);
  245. static inline void __unlazy_fpu(struct task_struct *tsk)
  246. {
  247. if (task_thread_info(tsk)->status & TS_USEDFPU) {
  248. __save_init_fpu(tsk);
  249. stts();
  250. } else
  251. tsk->fpu_counter = 0;
  252. }
  253. static inline void __clear_fpu(struct task_struct *tsk)
  254. {
  255. if (task_thread_info(tsk)->status & TS_USEDFPU) {
  256. tolerant_fwait();
  257. task_thread_info(tsk)->status &= ~TS_USEDFPU;
  258. stts();
  259. }
  260. }
  261. static inline void kernel_fpu_begin(void)
  262. {
  263. struct thread_info *me = current_thread_info();
  264. preempt_disable();
  265. if (me->status & TS_USEDFPU)
  266. __save_init_fpu(me->task);
  267. else
  268. clts();
  269. }
  270. static inline void kernel_fpu_end(void)
  271. {
  272. stts();
  273. preempt_enable();
  274. }
  275. static inline bool irq_fpu_usable(void)
  276. {
  277. struct pt_regs *regs;
  278. return !in_interrupt() || !(regs = get_irq_regs()) || \
  279. user_mode(regs) || (read_cr0() & X86_CR0_TS);
  280. }
  281. /*
  282. * Some instructions like VIA's padlock instructions generate a spurious
  283. * DNA fault but don't modify SSE registers. And these instructions
  284. * get used from interrupt context as well. To prevent these kernel instructions
  285. * in interrupt context interacting wrongly with other user/kernel fpu usage, we
  286. * should use them only in the context of irq_ts_save/restore()
  287. */
  288. static inline int irq_ts_save(void)
  289. {
  290. /*
  291. * If in process context and not atomic, we can take a spurious DNA fault.
  292. * Otherwise, doing clts() in process context requires disabling preemption
  293. * or some heavy lifting like kernel_fpu_begin()
  294. */
  295. if (!in_atomic())
  296. return 0;
  297. if (read_cr0() & X86_CR0_TS) {
  298. clts();
  299. return 1;
  300. }
  301. return 0;
  302. }
  303. static inline void irq_ts_restore(int TS_state)
  304. {
  305. if (TS_state)
  306. stts();
  307. }
  308. #ifdef CONFIG_X86_64
  309. static inline void save_init_fpu(struct task_struct *tsk)
  310. {
  311. __save_init_fpu(tsk);
  312. stts();
  313. }
  314. #define unlazy_fpu __unlazy_fpu
  315. #define clear_fpu __clear_fpu
  316. #else /* CONFIG_X86_32 */
  317. /*
  318. * These disable preemption on their own and are safe
  319. */
  320. static inline void save_init_fpu(struct task_struct *tsk)
  321. {
  322. preempt_disable();
  323. __save_init_fpu(tsk);
  324. stts();
  325. preempt_enable();
  326. }
  327. static inline void unlazy_fpu(struct task_struct *tsk)
  328. {
  329. preempt_disable();
  330. __unlazy_fpu(tsk);
  331. preempt_enable();
  332. }
  333. static inline void clear_fpu(struct task_struct *tsk)
  334. {
  335. preempt_disable();
  336. __clear_fpu(tsk);
  337. preempt_enable();
  338. }
  339. #endif /* CONFIG_X86_64 */
  340. /*
  341. * i387 state interaction
  342. */
  343. static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
  344. {
  345. if (cpu_has_fxsr) {
  346. return tsk->thread.xstate->fxsave.cwd;
  347. } else {
  348. return (unsigned short)tsk->thread.xstate->fsave.cwd;
  349. }
  350. }
  351. static inline unsigned short get_fpu_swd(struct task_struct *tsk)
  352. {
  353. if (cpu_has_fxsr) {
  354. return tsk->thread.xstate->fxsave.swd;
  355. } else {
  356. return (unsigned short)tsk->thread.xstate->fsave.swd;
  357. }
  358. }
  359. static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
  360. {
  361. if (cpu_has_xmm) {
  362. return tsk->thread.xstate->fxsave.mxcsr;
  363. } else {
  364. return MXCSR_DEFAULT;
  365. }
  366. }
  367. #endif /* __ASSEMBLY__ */
  368. #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
  369. #define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
  370. #endif /* _ASM_X86_I387_H */