iwl-agn.c 128 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/mac80211.h>
  46. #include <asm/div64.h>
  47. #define DRV_NAME "iwlagn"
  48. #include "iwl-eeprom.h"
  49. #include "iwl-dev.h"
  50. #include "iwl-core.h"
  51. #include "iwl-io.h"
  52. #include "iwl-helpers.h"
  53. #include "iwl-sta.h"
  54. #include "iwl-calib.h"
  55. #include "iwl-agn.h"
  56. /******************************************************************************
  57. *
  58. * module boiler plate
  59. *
  60. ******************************************************************************/
  61. /*
  62. * module name, copyright, version, etc.
  63. */
  64. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  65. #ifdef CONFIG_IWLWIFI_DEBUG
  66. #define VD "d"
  67. #else
  68. #define VD
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /**
  77. * iwl_commit_rxon - commit staging_rxon to hardware
  78. *
  79. * The RXON command in staging_rxon is committed to the hardware and
  80. * the active_rxon structure is updated with the new data. This
  81. * function correctly transitions out of the RXON_ASSOC_MSK state if
  82. * a HW tune is required based on the RXON structure changes.
  83. */
  84. int iwl_commit_rxon(struct iwl_priv *priv)
  85. {
  86. /* cast away the const for active_rxon in this function */
  87. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  88. int ret;
  89. bool new_assoc =
  90. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  91. if (!iwl_is_alive(priv))
  92. return -EBUSY;
  93. /* always get timestamp with Rx frame */
  94. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  95. ret = iwl_check_rxon_cmd(priv);
  96. if (ret) {
  97. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  98. return -EINVAL;
  99. }
  100. /*
  101. * receive commit_rxon request
  102. * abort any previous channel switch if still in process
  103. */
  104. if (priv->switch_rxon.switch_in_progress &&
  105. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  106. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  107. le16_to_cpu(priv->switch_rxon.channel));
  108. iwl_chswitch_done(priv, false);
  109. }
  110. /* If we don't need to send a full RXON, we can use
  111. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  112. * and other flags for the current radio configuration. */
  113. if (!iwl_full_rxon_required(priv)) {
  114. ret = iwl_send_rxon_assoc(priv);
  115. if (ret) {
  116. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  117. return ret;
  118. }
  119. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  120. iwl_print_rx_config_cmd(priv);
  121. return 0;
  122. }
  123. /* If we are currently associated and the new config requires
  124. * an RXON_ASSOC and the new config wants the associated mask enabled,
  125. * we must clear the associated from the active configuration
  126. * before we apply the new config */
  127. if (iwl_is_associated(priv) && new_assoc) {
  128. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  129. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  130. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  131. sizeof(struct iwl_rxon_cmd),
  132. &priv->active_rxon);
  133. /* If the mask clearing failed then we set
  134. * active_rxon back to what it was previously */
  135. if (ret) {
  136. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  137. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  138. return ret;
  139. }
  140. iwl_clear_ucode_stations(priv);
  141. iwl_restore_stations(priv);
  142. ret = iwl_restore_default_wep_keys(priv);
  143. if (ret) {
  144. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  145. return ret;
  146. }
  147. }
  148. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  149. "* with%s RXON_FILTER_ASSOC_MSK\n"
  150. "* channel = %d\n"
  151. "* bssid = %pM\n",
  152. (new_assoc ? "" : "out"),
  153. le16_to_cpu(priv->staging_rxon.channel),
  154. priv->staging_rxon.bssid_addr);
  155. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  156. /* Apply the new configuration
  157. * RXON unassoc clears the station table in uCode so restoration of
  158. * stations is needed after it (the RXON command) completes
  159. */
  160. if (!new_assoc) {
  161. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  162. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  163. if (ret) {
  164. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  165. return ret;
  166. }
  167. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
  168. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  169. iwl_clear_ucode_stations(priv);
  170. iwl_restore_stations(priv);
  171. ret = iwl_restore_default_wep_keys(priv);
  172. if (ret) {
  173. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  174. return ret;
  175. }
  176. }
  177. priv->start_calib = 0;
  178. if (new_assoc) {
  179. /* Apply the new configuration
  180. * RXON assoc doesn't clear the station table in uCode,
  181. */
  182. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  183. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  184. if (ret) {
  185. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  186. return ret;
  187. }
  188. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  189. }
  190. iwl_print_rx_config_cmd(priv);
  191. iwl_init_sensitivity(priv);
  192. /* If we issue a new RXON command which required a tune then we must
  193. * send a new TXPOWER command or we won't be able to Tx any frames */
  194. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  195. if (ret) {
  196. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  197. return ret;
  198. }
  199. return 0;
  200. }
  201. void iwl_update_chain_flags(struct iwl_priv *priv)
  202. {
  203. if (priv->cfg->ops->hcmd->set_rxon_chain)
  204. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  205. iwlcore_commit_rxon(priv);
  206. }
  207. static void iwl_clear_free_frames(struct iwl_priv *priv)
  208. {
  209. struct list_head *element;
  210. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  211. priv->frames_count);
  212. while (!list_empty(&priv->free_frames)) {
  213. element = priv->free_frames.next;
  214. list_del(element);
  215. kfree(list_entry(element, struct iwl_frame, list));
  216. priv->frames_count--;
  217. }
  218. if (priv->frames_count) {
  219. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  220. priv->frames_count);
  221. priv->frames_count = 0;
  222. }
  223. }
  224. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  225. {
  226. struct iwl_frame *frame;
  227. struct list_head *element;
  228. if (list_empty(&priv->free_frames)) {
  229. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  230. if (!frame) {
  231. IWL_ERR(priv, "Could not allocate frame!\n");
  232. return NULL;
  233. }
  234. priv->frames_count++;
  235. return frame;
  236. }
  237. element = priv->free_frames.next;
  238. list_del(element);
  239. return list_entry(element, struct iwl_frame, list);
  240. }
  241. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  242. {
  243. memset(frame, 0, sizeof(*frame));
  244. list_add(&frame->list, &priv->free_frames);
  245. }
  246. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  247. struct ieee80211_hdr *hdr,
  248. int left)
  249. {
  250. if (!priv->ibss_beacon)
  251. return 0;
  252. if (priv->ibss_beacon->len > left)
  253. return 0;
  254. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  255. return priv->ibss_beacon->len;
  256. }
  257. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  258. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  259. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  260. u8 *beacon, u32 frame_size)
  261. {
  262. u16 tim_idx;
  263. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  264. /*
  265. * The index is relative to frame start but we start looking at the
  266. * variable-length part of the beacon.
  267. */
  268. tim_idx = mgmt->u.beacon.variable - beacon;
  269. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  270. while ((tim_idx < (frame_size - 2)) &&
  271. (beacon[tim_idx] != WLAN_EID_TIM))
  272. tim_idx += beacon[tim_idx+1] + 2;
  273. /* If TIM field was found, set variables */
  274. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  275. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  276. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  277. } else
  278. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  279. }
  280. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  281. struct iwl_frame *frame)
  282. {
  283. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  284. u32 frame_size;
  285. u32 rate_flags;
  286. u32 rate;
  287. /*
  288. * We have to set up the TX command, the TX Beacon command, and the
  289. * beacon contents.
  290. */
  291. /* Initialize memory */
  292. tx_beacon_cmd = &frame->u.beacon;
  293. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  294. /* Set up TX beacon contents */
  295. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  296. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  297. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  298. return 0;
  299. /* Set up TX command fields */
  300. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  301. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  302. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  303. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  304. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  305. /* Set up TX beacon command fields */
  306. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  307. frame_size);
  308. /* Set up packet rate and flags */
  309. rate = iwl_rate_get_lowest_plcp(priv);
  310. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
  311. priv->hw_params.valid_tx_ant);
  312. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  313. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  314. rate_flags |= RATE_MCS_CCK_MSK;
  315. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  316. rate_flags);
  317. return sizeof(*tx_beacon_cmd) + frame_size;
  318. }
  319. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  320. {
  321. struct iwl_frame *frame;
  322. unsigned int frame_size;
  323. int rc;
  324. frame = iwl_get_free_frame(priv);
  325. if (!frame) {
  326. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  327. "command.\n");
  328. return -ENOMEM;
  329. }
  330. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  331. if (!frame_size) {
  332. IWL_ERR(priv, "Error configuring the beacon command\n");
  333. iwl_free_frame(priv, frame);
  334. return -EINVAL;
  335. }
  336. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  337. &frame->u.cmd[0]);
  338. iwl_free_frame(priv, frame);
  339. return rc;
  340. }
  341. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  342. {
  343. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  344. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  345. if (sizeof(dma_addr_t) > sizeof(u32))
  346. addr |=
  347. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  348. return addr;
  349. }
  350. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  351. {
  352. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  353. return le16_to_cpu(tb->hi_n_len) >> 4;
  354. }
  355. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  356. dma_addr_t addr, u16 len)
  357. {
  358. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  359. u16 hi_n_len = len << 4;
  360. put_unaligned_le32(addr, &tb->lo);
  361. if (sizeof(dma_addr_t) > sizeof(u32))
  362. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  363. tb->hi_n_len = cpu_to_le16(hi_n_len);
  364. tfd->num_tbs = idx + 1;
  365. }
  366. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  367. {
  368. return tfd->num_tbs & 0x1f;
  369. }
  370. /**
  371. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  372. * @priv - driver private data
  373. * @txq - tx queue
  374. *
  375. * Does NOT advance any TFD circular buffer read/write indexes
  376. * Does NOT free the TFD itself (which is within circular buffer)
  377. */
  378. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  379. {
  380. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  381. struct iwl_tfd *tfd;
  382. struct pci_dev *dev = priv->pci_dev;
  383. int index = txq->q.read_ptr;
  384. int i;
  385. int num_tbs;
  386. tfd = &tfd_tmp[index];
  387. /* Sanity check on number of chunks */
  388. num_tbs = iwl_tfd_get_num_tbs(tfd);
  389. if (num_tbs >= IWL_NUM_OF_TBS) {
  390. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  391. /* @todo issue fatal error, it is quite serious situation */
  392. return;
  393. }
  394. /* Unmap tx_cmd */
  395. if (num_tbs)
  396. pci_unmap_single(dev,
  397. dma_unmap_addr(&txq->meta[index], mapping),
  398. dma_unmap_len(&txq->meta[index], len),
  399. PCI_DMA_BIDIRECTIONAL);
  400. /* Unmap chunks, if any. */
  401. for (i = 1; i < num_tbs; i++)
  402. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  403. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  404. /* free SKB */
  405. if (txq->txb) {
  406. struct sk_buff *skb;
  407. skb = txq->txb[txq->q.read_ptr].skb;
  408. /* can be called from irqs-disabled context */
  409. if (skb) {
  410. dev_kfree_skb_any(skb);
  411. txq->txb[txq->q.read_ptr].skb = NULL;
  412. }
  413. }
  414. }
  415. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  416. struct iwl_tx_queue *txq,
  417. dma_addr_t addr, u16 len,
  418. u8 reset, u8 pad)
  419. {
  420. struct iwl_queue *q;
  421. struct iwl_tfd *tfd, *tfd_tmp;
  422. u32 num_tbs;
  423. q = &txq->q;
  424. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  425. tfd = &tfd_tmp[q->write_ptr];
  426. if (reset)
  427. memset(tfd, 0, sizeof(*tfd));
  428. num_tbs = iwl_tfd_get_num_tbs(tfd);
  429. /* Each TFD can point to a maximum 20 Tx buffers */
  430. if (num_tbs >= IWL_NUM_OF_TBS) {
  431. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  432. IWL_NUM_OF_TBS);
  433. return -EINVAL;
  434. }
  435. BUG_ON(addr & ~DMA_BIT_MASK(36));
  436. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  437. IWL_ERR(priv, "Unaligned address = %llx\n",
  438. (unsigned long long)addr);
  439. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  440. return 0;
  441. }
  442. /*
  443. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  444. * given Tx queue, and enable the DMA channel used for that queue.
  445. *
  446. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  447. * channels supported in hardware.
  448. */
  449. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  450. struct iwl_tx_queue *txq)
  451. {
  452. int txq_id = txq->q.id;
  453. /* Circular buffer (TFD queue in DRAM) physical base address */
  454. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  455. txq->q.dma_addr >> 8);
  456. return 0;
  457. }
  458. /******************************************************************************
  459. *
  460. * Generic RX handler implementations
  461. *
  462. ******************************************************************************/
  463. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  464. struct iwl_rx_mem_buffer *rxb)
  465. {
  466. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  467. struct iwl_alive_resp *palive;
  468. struct delayed_work *pwork;
  469. palive = &pkt->u.alive_frame;
  470. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  471. "0x%01X 0x%01X\n",
  472. palive->is_valid, palive->ver_type,
  473. palive->ver_subtype);
  474. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  475. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  476. memcpy(&priv->card_alive_init,
  477. &pkt->u.alive_frame,
  478. sizeof(struct iwl_init_alive_resp));
  479. pwork = &priv->init_alive_start;
  480. } else {
  481. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  482. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  483. sizeof(struct iwl_alive_resp));
  484. pwork = &priv->alive_start;
  485. }
  486. /* We delay the ALIVE response by 5ms to
  487. * give the HW RF Kill time to activate... */
  488. if (palive->is_valid == UCODE_VALID_OK)
  489. queue_delayed_work(priv->workqueue, pwork,
  490. msecs_to_jiffies(5));
  491. else
  492. IWL_WARN(priv, "uCode did not respond OK.\n");
  493. }
  494. static void iwl_bg_beacon_update(struct work_struct *work)
  495. {
  496. struct iwl_priv *priv =
  497. container_of(work, struct iwl_priv, beacon_update);
  498. struct sk_buff *beacon;
  499. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  500. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  501. if (!beacon) {
  502. IWL_ERR(priv, "update beacon failed\n");
  503. return;
  504. }
  505. mutex_lock(&priv->mutex);
  506. /* new beacon skb is allocated every time; dispose previous.*/
  507. if (priv->ibss_beacon)
  508. dev_kfree_skb(priv->ibss_beacon);
  509. priv->ibss_beacon = beacon;
  510. mutex_unlock(&priv->mutex);
  511. iwl_send_beacon_cmd(priv);
  512. }
  513. /**
  514. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  515. *
  516. * This callback is provided in order to send a statistics request.
  517. *
  518. * This timer function is continually reset to execute within
  519. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  520. * was received. We need to ensure we receive the statistics in order
  521. * to update the temperature used for calibrating the TXPOWER.
  522. */
  523. static void iwl_bg_statistics_periodic(unsigned long data)
  524. {
  525. struct iwl_priv *priv = (struct iwl_priv *)data;
  526. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  527. return;
  528. /* dont send host command if rf-kill is on */
  529. if (!iwl_is_ready_rf(priv))
  530. return;
  531. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  532. }
  533. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  534. u32 start_idx, u32 num_events,
  535. u32 mode)
  536. {
  537. u32 i;
  538. u32 ptr; /* SRAM byte address of log data */
  539. u32 ev, time, data; /* event log data */
  540. unsigned long reg_flags;
  541. if (mode == 0)
  542. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  543. else
  544. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  545. /* Make sure device is powered up for SRAM reads */
  546. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  547. if (iwl_grab_nic_access(priv)) {
  548. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  549. return;
  550. }
  551. /* Set starting address; reads will auto-increment */
  552. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  553. rmb();
  554. /*
  555. * "time" is actually "data" for mode 0 (no timestamp).
  556. * place event id # at far right for easier visual parsing.
  557. */
  558. for (i = 0; i < num_events; i++) {
  559. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  560. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  561. if (mode == 0) {
  562. trace_iwlwifi_dev_ucode_cont_event(priv,
  563. 0, time, ev);
  564. } else {
  565. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  566. trace_iwlwifi_dev_ucode_cont_event(priv,
  567. time, data, ev);
  568. }
  569. }
  570. /* Allow device to power down */
  571. iwl_release_nic_access(priv);
  572. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  573. }
  574. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  575. {
  576. u32 capacity; /* event log capacity in # entries */
  577. u32 base; /* SRAM byte address of event log header */
  578. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  579. u32 num_wraps; /* # times uCode wrapped to top of log */
  580. u32 next_entry; /* index of next entry to be written by uCode */
  581. if (priv->ucode_type == UCODE_INIT)
  582. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  583. else
  584. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  585. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  586. capacity = iwl_read_targ_mem(priv, base);
  587. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  588. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  589. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  590. } else
  591. return;
  592. if (num_wraps == priv->event_log.num_wraps) {
  593. iwl_print_cont_event_trace(priv,
  594. base, priv->event_log.next_entry,
  595. next_entry - priv->event_log.next_entry,
  596. mode);
  597. priv->event_log.non_wraps_count++;
  598. } else {
  599. if ((num_wraps - priv->event_log.num_wraps) > 1)
  600. priv->event_log.wraps_more_count++;
  601. else
  602. priv->event_log.wraps_once_count++;
  603. trace_iwlwifi_dev_ucode_wrap_event(priv,
  604. num_wraps - priv->event_log.num_wraps,
  605. next_entry, priv->event_log.next_entry);
  606. if (next_entry < priv->event_log.next_entry) {
  607. iwl_print_cont_event_trace(priv, base,
  608. priv->event_log.next_entry,
  609. capacity - priv->event_log.next_entry,
  610. mode);
  611. iwl_print_cont_event_trace(priv, base, 0,
  612. next_entry, mode);
  613. } else {
  614. iwl_print_cont_event_trace(priv, base,
  615. next_entry, capacity - next_entry,
  616. mode);
  617. iwl_print_cont_event_trace(priv, base, 0,
  618. next_entry, mode);
  619. }
  620. }
  621. priv->event_log.num_wraps = num_wraps;
  622. priv->event_log.next_entry = next_entry;
  623. }
  624. /**
  625. * iwl_bg_ucode_trace - Timer callback to log ucode event
  626. *
  627. * The timer is continually set to execute every
  628. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  629. * this function is to perform continuous uCode event logging operation
  630. * if enabled
  631. */
  632. static void iwl_bg_ucode_trace(unsigned long data)
  633. {
  634. struct iwl_priv *priv = (struct iwl_priv *)data;
  635. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  636. return;
  637. if (priv->event_log.ucode_trace) {
  638. iwl_continuous_event_trace(priv);
  639. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  640. mod_timer(&priv->ucode_trace,
  641. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  642. }
  643. }
  644. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  645. struct iwl_rx_mem_buffer *rxb)
  646. {
  647. #ifdef CONFIG_IWLWIFI_DEBUG
  648. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  649. struct iwl4965_beacon_notif *beacon =
  650. (struct iwl4965_beacon_notif *)pkt->u.raw;
  651. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  652. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  653. "tsf %d %d rate %d\n",
  654. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  655. beacon->beacon_notify_hdr.failure_frame,
  656. le32_to_cpu(beacon->ibss_mgr_status),
  657. le32_to_cpu(beacon->high_tsf),
  658. le32_to_cpu(beacon->low_tsf), rate);
  659. #endif
  660. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  661. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  662. queue_work(priv->workqueue, &priv->beacon_update);
  663. }
  664. /* Handle notification from uCode that card's power state is changing
  665. * due to software, hardware, or critical temperature RFKILL */
  666. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  667. struct iwl_rx_mem_buffer *rxb)
  668. {
  669. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  670. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  671. unsigned long status = priv->status;
  672. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  673. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  674. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  675. (flags & CT_CARD_DISABLED) ?
  676. "Reached" : "Not reached");
  677. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  678. CT_CARD_DISABLED)) {
  679. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  680. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  681. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  682. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  683. if (!(flags & RXON_CARD_DISABLED)) {
  684. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  685. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  686. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  687. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  688. }
  689. if (flags & CT_CARD_DISABLED)
  690. iwl_tt_enter_ct_kill(priv);
  691. }
  692. if (!(flags & CT_CARD_DISABLED))
  693. iwl_tt_exit_ct_kill(priv);
  694. if (flags & HW_CARD_DISABLED)
  695. set_bit(STATUS_RF_KILL_HW, &priv->status);
  696. else
  697. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  698. if (!(flags & RXON_CARD_DISABLED))
  699. iwl_scan_cancel(priv);
  700. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  701. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  702. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  703. test_bit(STATUS_RF_KILL_HW, &priv->status));
  704. else
  705. wake_up_interruptible(&priv->wait_command_queue);
  706. }
  707. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  708. {
  709. if (src == IWL_PWR_SRC_VAUX) {
  710. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  711. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  712. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  713. ~APMG_PS_CTRL_MSK_PWR_SRC);
  714. } else {
  715. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  716. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  717. ~APMG_PS_CTRL_MSK_PWR_SRC);
  718. }
  719. return 0;
  720. }
  721. static void iwl_bg_tx_flush(struct work_struct *work)
  722. {
  723. struct iwl_priv *priv =
  724. container_of(work, struct iwl_priv, tx_flush);
  725. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  726. return;
  727. /* do nothing if rf-kill is on */
  728. if (!iwl_is_ready_rf(priv))
  729. return;
  730. if (priv->cfg->ops->lib->txfifo_flush) {
  731. IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
  732. iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
  733. }
  734. }
  735. /**
  736. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  737. *
  738. * Setup the RX handlers for each of the reply types sent from the uCode
  739. * to the host.
  740. *
  741. * This function chains into the hardware specific files for them to setup
  742. * any hardware specific handlers as well.
  743. */
  744. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  745. {
  746. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  747. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  748. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  749. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  750. iwl_rx_spectrum_measure_notif;
  751. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  752. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  753. iwl_rx_pm_debug_statistics_notif;
  754. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  755. /*
  756. * The same handler is used for both the REPLY to a discrete
  757. * statistics request from the host as well as for the periodic
  758. * statistics notifications (after received beacons) from the uCode.
  759. */
  760. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  761. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  762. iwl_setup_rx_scan_handlers(priv);
  763. /* status change handler */
  764. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  765. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  766. iwl_rx_missed_beacon_notif;
  767. /* Rx handlers */
  768. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
  769. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
  770. /* block ack */
  771. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
  772. /* Set up hardware specific Rx handlers */
  773. priv->cfg->ops->lib->rx_handler_setup(priv);
  774. }
  775. /**
  776. * iwl_rx_handle - Main entry function for receiving responses from uCode
  777. *
  778. * Uses the priv->rx_handlers callback function array to invoke
  779. * the appropriate handlers, including command responses,
  780. * frame-received notifications, and other notifications.
  781. */
  782. void iwl_rx_handle(struct iwl_priv *priv)
  783. {
  784. struct iwl_rx_mem_buffer *rxb;
  785. struct iwl_rx_packet *pkt;
  786. struct iwl_rx_queue *rxq = &priv->rxq;
  787. u32 r, i;
  788. int reclaim;
  789. unsigned long flags;
  790. u8 fill_rx = 0;
  791. u32 count = 8;
  792. int total_empty;
  793. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  794. * buffer that the driver may process (last buffer filled by ucode). */
  795. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  796. i = rxq->read;
  797. /* Rx interrupt, but nothing sent from uCode */
  798. if (i == r)
  799. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  800. /* calculate total frames need to be restock after handling RX */
  801. total_empty = r - rxq->write_actual;
  802. if (total_empty < 0)
  803. total_empty += RX_QUEUE_SIZE;
  804. if (total_empty > (RX_QUEUE_SIZE / 2))
  805. fill_rx = 1;
  806. while (i != r) {
  807. int len;
  808. rxb = rxq->queue[i];
  809. /* If an RXB doesn't have a Rx queue slot associated with it,
  810. * then a bug has been introduced in the queue refilling
  811. * routines -- catch it here */
  812. BUG_ON(rxb == NULL);
  813. rxq->queue[i] = NULL;
  814. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  815. PAGE_SIZE << priv->hw_params.rx_page_order,
  816. PCI_DMA_FROMDEVICE);
  817. pkt = rxb_addr(rxb);
  818. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  819. len += sizeof(u32); /* account for status word */
  820. trace_iwlwifi_dev_rx(priv, pkt, len);
  821. /* Reclaim a command buffer only if this packet is a response
  822. * to a (driver-originated) command.
  823. * If the packet (e.g. Rx frame) originated from uCode,
  824. * there is no command buffer to reclaim.
  825. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  826. * but apparently a few don't get set; catch them here. */
  827. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  828. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  829. (pkt->hdr.cmd != REPLY_RX) &&
  830. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  831. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  832. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  833. (pkt->hdr.cmd != REPLY_TX);
  834. /* Based on type of command response or notification,
  835. * handle those that need handling via function in
  836. * rx_handlers table. See iwl_setup_rx_handlers() */
  837. if (priv->rx_handlers[pkt->hdr.cmd]) {
  838. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  839. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  840. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  841. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  842. } else {
  843. /* No handling needed */
  844. IWL_DEBUG_RX(priv,
  845. "r %d i %d No handler needed for %s, 0x%02x\n",
  846. r, i, get_cmd_string(pkt->hdr.cmd),
  847. pkt->hdr.cmd);
  848. }
  849. /*
  850. * XXX: After here, we should always check rxb->page
  851. * against NULL before touching it or its virtual
  852. * memory (pkt). Because some rx_handler might have
  853. * already taken or freed the pages.
  854. */
  855. if (reclaim) {
  856. /* Invoke any callbacks, transfer the buffer to caller,
  857. * and fire off the (possibly) blocking iwl_send_cmd()
  858. * as we reclaim the driver command queue */
  859. if (rxb->page)
  860. iwl_tx_cmd_complete(priv, rxb);
  861. else
  862. IWL_WARN(priv, "Claim null rxb?\n");
  863. }
  864. /* Reuse the page if possible. For notification packets and
  865. * SKBs that fail to Rx correctly, add them back into the
  866. * rx_free list for reuse later. */
  867. spin_lock_irqsave(&rxq->lock, flags);
  868. if (rxb->page != NULL) {
  869. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  870. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  871. PCI_DMA_FROMDEVICE);
  872. list_add_tail(&rxb->list, &rxq->rx_free);
  873. rxq->free_count++;
  874. } else
  875. list_add_tail(&rxb->list, &rxq->rx_used);
  876. spin_unlock_irqrestore(&rxq->lock, flags);
  877. i = (i + 1) & RX_QUEUE_MASK;
  878. /* If there are a lot of unused frames,
  879. * restock the Rx queue so ucode wont assert. */
  880. if (fill_rx) {
  881. count++;
  882. if (count >= 8) {
  883. rxq->read = i;
  884. iwlagn_rx_replenish_now(priv);
  885. count = 0;
  886. }
  887. }
  888. }
  889. /* Backtrack one entry */
  890. rxq->read = i;
  891. if (fill_rx)
  892. iwlagn_rx_replenish_now(priv);
  893. else
  894. iwlagn_rx_queue_restock(priv);
  895. }
  896. /* call this function to flush any scheduled tasklet */
  897. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  898. {
  899. /* wait to make sure we flush pending tasklet*/
  900. synchronize_irq(priv->pci_dev->irq);
  901. tasklet_kill(&priv->irq_tasklet);
  902. }
  903. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  904. {
  905. u32 inta, handled = 0;
  906. u32 inta_fh;
  907. unsigned long flags;
  908. u32 i;
  909. #ifdef CONFIG_IWLWIFI_DEBUG
  910. u32 inta_mask;
  911. #endif
  912. spin_lock_irqsave(&priv->lock, flags);
  913. /* Ack/clear/reset pending uCode interrupts.
  914. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  915. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  916. inta = iwl_read32(priv, CSR_INT);
  917. iwl_write32(priv, CSR_INT, inta);
  918. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  919. * Any new interrupts that happen after this, either while we're
  920. * in this tasklet, or later, will show up in next ISR/tasklet. */
  921. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  922. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  923. #ifdef CONFIG_IWLWIFI_DEBUG
  924. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  925. /* just for debug */
  926. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  927. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  928. inta, inta_mask, inta_fh);
  929. }
  930. #endif
  931. spin_unlock_irqrestore(&priv->lock, flags);
  932. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  933. * atomic, make sure that inta covers all the interrupts that
  934. * we've discovered, even if FH interrupt came in just after
  935. * reading CSR_INT. */
  936. if (inta_fh & CSR49_FH_INT_RX_MASK)
  937. inta |= CSR_INT_BIT_FH_RX;
  938. if (inta_fh & CSR49_FH_INT_TX_MASK)
  939. inta |= CSR_INT_BIT_FH_TX;
  940. /* Now service all interrupt bits discovered above. */
  941. if (inta & CSR_INT_BIT_HW_ERR) {
  942. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  943. /* Tell the device to stop sending interrupts */
  944. iwl_disable_interrupts(priv);
  945. priv->isr_stats.hw++;
  946. iwl_irq_handle_error(priv);
  947. handled |= CSR_INT_BIT_HW_ERR;
  948. return;
  949. }
  950. #ifdef CONFIG_IWLWIFI_DEBUG
  951. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  952. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  953. if (inta & CSR_INT_BIT_SCD) {
  954. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  955. "the frame/frames.\n");
  956. priv->isr_stats.sch++;
  957. }
  958. /* Alive notification via Rx interrupt will do the real work */
  959. if (inta & CSR_INT_BIT_ALIVE) {
  960. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  961. priv->isr_stats.alive++;
  962. }
  963. }
  964. #endif
  965. /* Safely ignore these bits for debug checks below */
  966. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  967. /* HW RF KILL switch toggled */
  968. if (inta & CSR_INT_BIT_RF_KILL) {
  969. int hw_rf_kill = 0;
  970. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  971. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  972. hw_rf_kill = 1;
  973. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  974. hw_rf_kill ? "disable radio" : "enable radio");
  975. priv->isr_stats.rfkill++;
  976. /* driver only loads ucode once setting the interface up.
  977. * the driver allows loading the ucode even if the radio
  978. * is killed. Hence update the killswitch state here. The
  979. * rfkill handler will care about restarting if needed.
  980. */
  981. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  982. if (hw_rf_kill)
  983. set_bit(STATUS_RF_KILL_HW, &priv->status);
  984. else
  985. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  986. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  987. }
  988. handled |= CSR_INT_BIT_RF_KILL;
  989. }
  990. /* Chip got too hot and stopped itself */
  991. if (inta & CSR_INT_BIT_CT_KILL) {
  992. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  993. priv->isr_stats.ctkill++;
  994. handled |= CSR_INT_BIT_CT_KILL;
  995. }
  996. /* Error detected by uCode */
  997. if (inta & CSR_INT_BIT_SW_ERR) {
  998. IWL_ERR(priv, "Microcode SW error detected. "
  999. " Restarting 0x%X.\n", inta);
  1000. priv->isr_stats.sw++;
  1001. priv->isr_stats.sw_err = inta;
  1002. iwl_irq_handle_error(priv);
  1003. handled |= CSR_INT_BIT_SW_ERR;
  1004. }
  1005. /*
  1006. * uCode wakes up after power-down sleep.
  1007. * Tell device about any new tx or host commands enqueued,
  1008. * and about any Rx buffers made available while asleep.
  1009. */
  1010. if (inta & CSR_INT_BIT_WAKEUP) {
  1011. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1012. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1013. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1014. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1015. priv->isr_stats.wakeup++;
  1016. handled |= CSR_INT_BIT_WAKEUP;
  1017. }
  1018. /* All uCode command responses, including Tx command responses,
  1019. * Rx "responses" (frame-received notification), and other
  1020. * notifications from uCode come through here*/
  1021. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1022. iwl_rx_handle(priv);
  1023. priv->isr_stats.rx++;
  1024. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1025. }
  1026. /* This "Tx" DMA channel is used only for loading uCode */
  1027. if (inta & CSR_INT_BIT_FH_TX) {
  1028. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1029. priv->isr_stats.tx++;
  1030. handled |= CSR_INT_BIT_FH_TX;
  1031. /* Wake up uCode load routine, now that load is complete */
  1032. priv->ucode_write_complete = 1;
  1033. wake_up_interruptible(&priv->wait_command_queue);
  1034. }
  1035. if (inta & ~handled) {
  1036. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1037. priv->isr_stats.unhandled++;
  1038. }
  1039. if (inta & ~(priv->inta_mask)) {
  1040. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1041. inta & ~priv->inta_mask);
  1042. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1043. }
  1044. /* Re-enable all interrupts */
  1045. /* only Re-enable if diabled by irq */
  1046. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1047. iwl_enable_interrupts(priv);
  1048. #ifdef CONFIG_IWLWIFI_DEBUG
  1049. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1050. inta = iwl_read32(priv, CSR_INT);
  1051. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1052. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1053. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1054. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1055. }
  1056. #endif
  1057. }
  1058. /* tasklet for iwlagn interrupt */
  1059. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1060. {
  1061. u32 inta = 0;
  1062. u32 handled = 0;
  1063. unsigned long flags;
  1064. u32 i;
  1065. #ifdef CONFIG_IWLWIFI_DEBUG
  1066. u32 inta_mask;
  1067. #endif
  1068. spin_lock_irqsave(&priv->lock, flags);
  1069. /* Ack/clear/reset pending uCode interrupts.
  1070. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1071. */
  1072. /* There is a hardware bug in the interrupt mask function that some
  1073. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  1074. * they are disabled in the CSR_INT_MASK register. Furthermore the
  1075. * ICT interrupt handling mechanism has another bug that might cause
  1076. * these unmasked interrupts fail to be detected. We workaround the
  1077. * hardware bugs here by ACKing all the possible interrupts so that
  1078. * interrupt coalescing can still be achieved.
  1079. */
  1080. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  1081. inta = priv->_agn.inta;
  1082. #ifdef CONFIG_IWLWIFI_DEBUG
  1083. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1084. /* just for debug */
  1085. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1086. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1087. inta, inta_mask);
  1088. }
  1089. #endif
  1090. spin_unlock_irqrestore(&priv->lock, flags);
  1091. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1092. priv->_agn.inta = 0;
  1093. /* Now service all interrupt bits discovered above. */
  1094. if (inta & CSR_INT_BIT_HW_ERR) {
  1095. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1096. /* Tell the device to stop sending interrupts */
  1097. iwl_disable_interrupts(priv);
  1098. priv->isr_stats.hw++;
  1099. iwl_irq_handle_error(priv);
  1100. handled |= CSR_INT_BIT_HW_ERR;
  1101. return;
  1102. }
  1103. #ifdef CONFIG_IWLWIFI_DEBUG
  1104. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1105. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1106. if (inta & CSR_INT_BIT_SCD) {
  1107. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1108. "the frame/frames.\n");
  1109. priv->isr_stats.sch++;
  1110. }
  1111. /* Alive notification via Rx interrupt will do the real work */
  1112. if (inta & CSR_INT_BIT_ALIVE) {
  1113. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1114. priv->isr_stats.alive++;
  1115. }
  1116. }
  1117. #endif
  1118. /* Safely ignore these bits for debug checks below */
  1119. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1120. /* HW RF KILL switch toggled */
  1121. if (inta & CSR_INT_BIT_RF_KILL) {
  1122. int hw_rf_kill = 0;
  1123. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1124. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1125. hw_rf_kill = 1;
  1126. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1127. hw_rf_kill ? "disable radio" : "enable radio");
  1128. priv->isr_stats.rfkill++;
  1129. /* driver only loads ucode once setting the interface up.
  1130. * the driver allows loading the ucode even if the radio
  1131. * is killed. Hence update the killswitch state here. The
  1132. * rfkill handler will care about restarting if needed.
  1133. */
  1134. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1135. if (hw_rf_kill)
  1136. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1137. else
  1138. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1139. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1140. }
  1141. handled |= CSR_INT_BIT_RF_KILL;
  1142. }
  1143. /* Chip got too hot and stopped itself */
  1144. if (inta & CSR_INT_BIT_CT_KILL) {
  1145. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1146. priv->isr_stats.ctkill++;
  1147. handled |= CSR_INT_BIT_CT_KILL;
  1148. }
  1149. /* Error detected by uCode */
  1150. if (inta & CSR_INT_BIT_SW_ERR) {
  1151. IWL_ERR(priv, "Microcode SW error detected. "
  1152. " Restarting 0x%X.\n", inta);
  1153. priv->isr_stats.sw++;
  1154. priv->isr_stats.sw_err = inta;
  1155. iwl_irq_handle_error(priv);
  1156. handled |= CSR_INT_BIT_SW_ERR;
  1157. }
  1158. /* uCode wakes up after power-down sleep */
  1159. if (inta & CSR_INT_BIT_WAKEUP) {
  1160. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1161. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1162. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1163. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1164. priv->isr_stats.wakeup++;
  1165. handled |= CSR_INT_BIT_WAKEUP;
  1166. }
  1167. /* All uCode command responses, including Tx command responses,
  1168. * Rx "responses" (frame-received notification), and other
  1169. * notifications from uCode come through here*/
  1170. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1171. CSR_INT_BIT_RX_PERIODIC)) {
  1172. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1173. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1174. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1175. iwl_write32(priv, CSR_FH_INT_STATUS,
  1176. CSR49_FH_INT_RX_MASK);
  1177. }
  1178. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1179. handled |= CSR_INT_BIT_RX_PERIODIC;
  1180. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1181. }
  1182. /* Sending RX interrupt require many steps to be done in the
  1183. * the device:
  1184. * 1- write interrupt to current index in ICT table.
  1185. * 2- dma RX frame.
  1186. * 3- update RX shared data to indicate last write index.
  1187. * 4- send interrupt.
  1188. * This could lead to RX race, driver could receive RX interrupt
  1189. * but the shared data changes does not reflect this;
  1190. * periodic interrupt will detect any dangling Rx activity.
  1191. */
  1192. /* Disable periodic interrupt; we use it as just a one-shot. */
  1193. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1194. CSR_INT_PERIODIC_DIS);
  1195. iwl_rx_handle(priv);
  1196. /*
  1197. * Enable periodic interrupt in 8 msec only if we received
  1198. * real RX interrupt (instead of just periodic int), to catch
  1199. * any dangling Rx interrupt. If it was just the periodic
  1200. * interrupt, there was no dangling Rx activity, and no need
  1201. * to extend the periodic interrupt; one-shot is enough.
  1202. */
  1203. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1204. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1205. CSR_INT_PERIODIC_ENA);
  1206. priv->isr_stats.rx++;
  1207. }
  1208. /* This "Tx" DMA channel is used only for loading uCode */
  1209. if (inta & CSR_INT_BIT_FH_TX) {
  1210. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1211. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1212. priv->isr_stats.tx++;
  1213. handled |= CSR_INT_BIT_FH_TX;
  1214. /* Wake up uCode load routine, now that load is complete */
  1215. priv->ucode_write_complete = 1;
  1216. wake_up_interruptible(&priv->wait_command_queue);
  1217. }
  1218. if (inta & ~handled) {
  1219. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1220. priv->isr_stats.unhandled++;
  1221. }
  1222. if (inta & ~(priv->inta_mask)) {
  1223. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1224. inta & ~priv->inta_mask);
  1225. }
  1226. /* Re-enable all interrupts */
  1227. /* only Re-enable if diabled by irq */
  1228. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1229. iwl_enable_interrupts(priv);
  1230. }
  1231. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  1232. #define ACK_CNT_RATIO (50)
  1233. #define BA_TIMEOUT_CNT (5)
  1234. #define BA_TIMEOUT_MAX (16)
  1235. /**
  1236. * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
  1237. *
  1238. * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
  1239. * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
  1240. * operation state.
  1241. */
  1242. bool iwl_good_ack_health(struct iwl_priv *priv,
  1243. struct iwl_rx_packet *pkt)
  1244. {
  1245. bool rc = true;
  1246. int actual_ack_cnt_delta, expected_ack_cnt_delta;
  1247. int ba_timeout_delta;
  1248. actual_ack_cnt_delta =
  1249. le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  1250. le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
  1251. expected_ack_cnt_delta =
  1252. le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
  1253. le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
  1254. ba_timeout_delta =
  1255. le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
  1256. le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
  1257. if ((priv->_agn.agg_tids_count > 0) &&
  1258. (expected_ack_cnt_delta > 0) &&
  1259. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
  1260. < ACK_CNT_RATIO) &&
  1261. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  1262. IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
  1263. " expected_ack_cnt = %d\n",
  1264. actual_ack_cnt_delta, expected_ack_cnt_delta);
  1265. #ifdef CONFIG_IWLWIFI_DEBUGFS
  1266. /*
  1267. * This is ifdef'ed on DEBUGFS because otherwise the
  1268. * statistics aren't available. If DEBUGFS is set but
  1269. * DEBUG is not, these will just compile out.
  1270. */
  1271. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  1272. priv->_agn.delta_statistics.tx.rx_detected_cnt);
  1273. IWL_DEBUG_RADIO(priv,
  1274. "ack_or_ba_timeout_collision delta = %d\n",
  1275. priv->_agn.delta_statistics.tx.
  1276. ack_or_ba_timeout_collision);
  1277. #endif
  1278. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  1279. ba_timeout_delta);
  1280. if (!actual_ack_cnt_delta &&
  1281. (ba_timeout_delta >= BA_TIMEOUT_MAX))
  1282. rc = false;
  1283. }
  1284. return rc;
  1285. }
  1286. /*****************************************************************************
  1287. *
  1288. * sysfs attributes
  1289. *
  1290. *****************************************************************************/
  1291. #ifdef CONFIG_IWLWIFI_DEBUG
  1292. /*
  1293. * The following adds a new attribute to the sysfs representation
  1294. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1295. * used for controlling the debug level.
  1296. *
  1297. * See the level definitions in iwl for details.
  1298. *
  1299. * The debug_level being managed using sysfs below is a per device debug
  1300. * level that is used instead of the global debug level if it (the per
  1301. * device debug level) is set.
  1302. */
  1303. static ssize_t show_debug_level(struct device *d,
  1304. struct device_attribute *attr, char *buf)
  1305. {
  1306. struct iwl_priv *priv = dev_get_drvdata(d);
  1307. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  1308. }
  1309. static ssize_t store_debug_level(struct device *d,
  1310. struct device_attribute *attr,
  1311. const char *buf, size_t count)
  1312. {
  1313. struct iwl_priv *priv = dev_get_drvdata(d);
  1314. unsigned long val;
  1315. int ret;
  1316. ret = strict_strtoul(buf, 0, &val);
  1317. if (ret)
  1318. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1319. else {
  1320. priv->debug_level = val;
  1321. if (iwl_alloc_traffic_mem(priv))
  1322. IWL_ERR(priv,
  1323. "Not enough memory to generate traffic log\n");
  1324. }
  1325. return strnlen(buf, count);
  1326. }
  1327. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1328. show_debug_level, store_debug_level);
  1329. #endif /* CONFIG_IWLWIFI_DEBUG */
  1330. static ssize_t show_temperature(struct device *d,
  1331. struct device_attribute *attr, char *buf)
  1332. {
  1333. struct iwl_priv *priv = dev_get_drvdata(d);
  1334. if (!iwl_is_alive(priv))
  1335. return -EAGAIN;
  1336. return sprintf(buf, "%d\n", priv->temperature);
  1337. }
  1338. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  1339. static ssize_t show_tx_power(struct device *d,
  1340. struct device_attribute *attr, char *buf)
  1341. {
  1342. struct iwl_priv *priv = dev_get_drvdata(d);
  1343. if (!iwl_is_ready_rf(priv))
  1344. return sprintf(buf, "off\n");
  1345. else
  1346. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  1347. }
  1348. static ssize_t store_tx_power(struct device *d,
  1349. struct device_attribute *attr,
  1350. const char *buf, size_t count)
  1351. {
  1352. struct iwl_priv *priv = dev_get_drvdata(d);
  1353. unsigned long val;
  1354. int ret;
  1355. ret = strict_strtoul(buf, 10, &val);
  1356. if (ret)
  1357. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  1358. else {
  1359. ret = iwl_set_tx_power(priv, val, false);
  1360. if (ret)
  1361. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  1362. ret);
  1363. else
  1364. ret = count;
  1365. }
  1366. return ret;
  1367. }
  1368. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  1369. static struct attribute *iwl_sysfs_entries[] = {
  1370. &dev_attr_temperature.attr,
  1371. &dev_attr_tx_power.attr,
  1372. #ifdef CONFIG_IWLWIFI_DEBUG
  1373. &dev_attr_debug_level.attr,
  1374. #endif
  1375. NULL
  1376. };
  1377. static struct attribute_group iwl_attribute_group = {
  1378. .name = NULL, /* put in device directory */
  1379. .attrs = iwl_sysfs_entries,
  1380. };
  1381. /******************************************************************************
  1382. *
  1383. * uCode download functions
  1384. *
  1385. ******************************************************************************/
  1386. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1387. {
  1388. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1389. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1390. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1391. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1392. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1393. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1394. }
  1395. static void iwl_nic_start(struct iwl_priv *priv)
  1396. {
  1397. /* Remove all resets to allow NIC to operate */
  1398. iwl_write32(priv, CSR_RESET, 0);
  1399. }
  1400. struct iwlagn_ucode_capabilities {
  1401. u32 max_probe_length;
  1402. u32 standard_phy_calibration_size;
  1403. };
  1404. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1405. static int iwl_mac_setup_register(struct iwl_priv *priv,
  1406. struct iwlagn_ucode_capabilities *capa);
  1407. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1408. {
  1409. const char *name_pre = priv->cfg->fw_name_pre;
  1410. if (first)
  1411. priv->fw_index = priv->cfg->ucode_api_max;
  1412. else
  1413. priv->fw_index--;
  1414. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1415. IWL_ERR(priv, "no suitable firmware found!\n");
  1416. return -ENOENT;
  1417. }
  1418. sprintf(priv->firmware_name, "%s%d%s",
  1419. name_pre, priv->fw_index, ".ucode");
  1420. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1421. priv->firmware_name);
  1422. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1423. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1424. iwl_ucode_callback);
  1425. }
  1426. struct iwlagn_firmware_pieces {
  1427. const void *inst, *data, *init, *init_data, *boot;
  1428. size_t inst_size, data_size, init_size, init_data_size, boot_size;
  1429. u32 build;
  1430. u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
  1431. u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
  1432. };
  1433. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  1434. const struct firmware *ucode_raw,
  1435. struct iwlagn_firmware_pieces *pieces)
  1436. {
  1437. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  1438. u32 api_ver, hdr_size;
  1439. const u8 *src;
  1440. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1441. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1442. switch (api_ver) {
  1443. default:
  1444. /*
  1445. * 4965 doesn't revision the firmware file format
  1446. * along with the API version, it always uses v1
  1447. * file format.
  1448. */
  1449. if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
  1450. CSR_HW_REV_TYPE_4965) {
  1451. hdr_size = 28;
  1452. if (ucode_raw->size < hdr_size) {
  1453. IWL_ERR(priv, "File size too small!\n");
  1454. return -EINVAL;
  1455. }
  1456. pieces->build = le32_to_cpu(ucode->u.v2.build);
  1457. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  1458. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  1459. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  1460. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  1461. pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
  1462. src = ucode->u.v2.data;
  1463. break;
  1464. }
  1465. /* fall through for 4965 */
  1466. case 0:
  1467. case 1:
  1468. case 2:
  1469. hdr_size = 24;
  1470. if (ucode_raw->size < hdr_size) {
  1471. IWL_ERR(priv, "File size too small!\n");
  1472. return -EINVAL;
  1473. }
  1474. pieces->build = 0;
  1475. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  1476. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  1477. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  1478. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  1479. pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
  1480. src = ucode->u.v1.data;
  1481. break;
  1482. }
  1483. /* Verify size of file vs. image size info in file's header */
  1484. if (ucode_raw->size != hdr_size + pieces->inst_size +
  1485. pieces->data_size + pieces->init_size +
  1486. pieces->init_data_size + pieces->boot_size) {
  1487. IWL_ERR(priv,
  1488. "uCode file size %d does not match expected size\n",
  1489. (int)ucode_raw->size);
  1490. return -EINVAL;
  1491. }
  1492. pieces->inst = src;
  1493. src += pieces->inst_size;
  1494. pieces->data = src;
  1495. src += pieces->data_size;
  1496. pieces->init = src;
  1497. src += pieces->init_size;
  1498. pieces->init_data = src;
  1499. src += pieces->init_data_size;
  1500. pieces->boot = src;
  1501. src += pieces->boot_size;
  1502. return 0;
  1503. }
  1504. static int iwlagn_wanted_ucode_alternative = 1;
  1505. static int iwlagn_load_firmware(struct iwl_priv *priv,
  1506. const struct firmware *ucode_raw,
  1507. struct iwlagn_firmware_pieces *pieces,
  1508. struct iwlagn_ucode_capabilities *capa)
  1509. {
  1510. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  1511. struct iwl_ucode_tlv *tlv;
  1512. size_t len = ucode_raw->size;
  1513. const u8 *data;
  1514. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  1515. u64 alternatives;
  1516. u32 tlv_len;
  1517. enum iwl_ucode_tlv_type tlv_type;
  1518. const u8 *tlv_data;
  1519. if (len < sizeof(*ucode)) {
  1520. IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
  1521. return -EINVAL;
  1522. }
  1523. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
  1524. IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
  1525. le32_to_cpu(ucode->magic));
  1526. return -EINVAL;
  1527. }
  1528. /*
  1529. * Check which alternatives are present, and "downgrade"
  1530. * when the chosen alternative is not present, warning
  1531. * the user when that happens. Some files may not have
  1532. * any alternatives, so don't warn in that case.
  1533. */
  1534. alternatives = le64_to_cpu(ucode->alternatives);
  1535. tmp = wanted_alternative;
  1536. if (wanted_alternative > 63)
  1537. wanted_alternative = 63;
  1538. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  1539. wanted_alternative--;
  1540. if (wanted_alternative && wanted_alternative != tmp)
  1541. IWL_WARN(priv,
  1542. "uCode alternative %d not available, choosing %d\n",
  1543. tmp, wanted_alternative);
  1544. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1545. pieces->build = le32_to_cpu(ucode->build);
  1546. data = ucode->data;
  1547. len -= sizeof(*ucode);
  1548. while (len >= sizeof(*tlv)) {
  1549. u16 tlv_alt;
  1550. len -= sizeof(*tlv);
  1551. tlv = (void *)data;
  1552. tlv_len = le32_to_cpu(tlv->length);
  1553. tlv_type = le16_to_cpu(tlv->type);
  1554. tlv_alt = le16_to_cpu(tlv->alternative);
  1555. tlv_data = tlv->data;
  1556. if (len < tlv_len) {
  1557. IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
  1558. len, tlv_len);
  1559. return -EINVAL;
  1560. }
  1561. len -= ALIGN(tlv_len, 4);
  1562. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  1563. /*
  1564. * Alternative 0 is always valid.
  1565. *
  1566. * Skip alternative TLVs that are not selected.
  1567. */
  1568. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  1569. continue;
  1570. switch (tlv_type) {
  1571. case IWL_UCODE_TLV_INST:
  1572. pieces->inst = tlv_data;
  1573. pieces->inst_size = tlv_len;
  1574. break;
  1575. case IWL_UCODE_TLV_DATA:
  1576. pieces->data = tlv_data;
  1577. pieces->data_size = tlv_len;
  1578. break;
  1579. case IWL_UCODE_TLV_INIT:
  1580. pieces->init = tlv_data;
  1581. pieces->init_size = tlv_len;
  1582. break;
  1583. case IWL_UCODE_TLV_INIT_DATA:
  1584. pieces->init_data = tlv_data;
  1585. pieces->init_data_size = tlv_len;
  1586. break;
  1587. case IWL_UCODE_TLV_BOOT:
  1588. pieces->boot = tlv_data;
  1589. pieces->boot_size = tlv_len;
  1590. break;
  1591. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1592. if (tlv_len != sizeof(u32))
  1593. goto invalid_tlv_len;
  1594. capa->max_probe_length =
  1595. le32_to_cpup((__le32 *)tlv_data);
  1596. break;
  1597. case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
  1598. if (tlv_len != sizeof(u32))
  1599. goto invalid_tlv_len;
  1600. pieces->init_evtlog_ptr =
  1601. le32_to_cpup((__le32 *)tlv_data);
  1602. break;
  1603. case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
  1604. if (tlv_len != sizeof(u32))
  1605. goto invalid_tlv_len;
  1606. pieces->init_evtlog_size =
  1607. le32_to_cpup((__le32 *)tlv_data);
  1608. break;
  1609. case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
  1610. if (tlv_len != sizeof(u32))
  1611. goto invalid_tlv_len;
  1612. pieces->init_errlog_ptr =
  1613. le32_to_cpup((__le32 *)tlv_data);
  1614. break;
  1615. case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
  1616. if (tlv_len != sizeof(u32))
  1617. goto invalid_tlv_len;
  1618. pieces->inst_evtlog_ptr =
  1619. le32_to_cpup((__le32 *)tlv_data);
  1620. break;
  1621. case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
  1622. if (tlv_len != sizeof(u32))
  1623. goto invalid_tlv_len;
  1624. pieces->inst_evtlog_size =
  1625. le32_to_cpup((__le32 *)tlv_data);
  1626. break;
  1627. case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
  1628. if (tlv_len != sizeof(u32))
  1629. goto invalid_tlv_len;
  1630. pieces->inst_errlog_ptr =
  1631. le32_to_cpup((__le32 *)tlv_data);
  1632. break;
  1633. case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
  1634. if (tlv_len)
  1635. goto invalid_tlv_len;
  1636. priv->enhance_sensitivity_table = true;
  1637. break;
  1638. case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
  1639. if (tlv_len != sizeof(u32))
  1640. goto invalid_tlv_len;
  1641. capa->standard_phy_calibration_size =
  1642. le32_to_cpup((__le32 *)tlv_data);
  1643. break;
  1644. default:
  1645. IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
  1646. break;
  1647. }
  1648. }
  1649. if (len) {
  1650. IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
  1651. iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
  1652. return -EINVAL;
  1653. }
  1654. return 0;
  1655. invalid_tlv_len:
  1656. IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
  1657. iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
  1658. return -EINVAL;
  1659. }
  1660. /**
  1661. * iwl_ucode_callback - callback when firmware was loaded
  1662. *
  1663. * If loaded successfully, copies the firmware into buffers
  1664. * for the card to fetch (via DMA).
  1665. */
  1666. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1667. {
  1668. struct iwl_priv *priv = context;
  1669. struct iwl_ucode_header *ucode;
  1670. int err;
  1671. struct iwlagn_firmware_pieces pieces;
  1672. const unsigned int api_max = priv->cfg->ucode_api_max;
  1673. const unsigned int api_min = priv->cfg->ucode_api_min;
  1674. u32 api_ver;
  1675. char buildstr[25];
  1676. u32 build;
  1677. struct iwlagn_ucode_capabilities ucode_capa = {
  1678. .max_probe_length = 200,
  1679. .standard_phy_calibration_size =
  1680. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
  1681. };
  1682. memset(&pieces, 0, sizeof(pieces));
  1683. if (!ucode_raw) {
  1684. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1685. priv->firmware_name);
  1686. goto try_again;
  1687. }
  1688. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1689. priv->firmware_name, ucode_raw->size);
  1690. /* Make sure that we got at least the API version number */
  1691. if (ucode_raw->size < 4) {
  1692. IWL_ERR(priv, "File size way too small!\n");
  1693. goto try_again;
  1694. }
  1695. /* Data from ucode file: header followed by uCode images */
  1696. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1697. if (ucode->ver)
  1698. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1699. else
  1700. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1701. &ucode_capa);
  1702. if (err)
  1703. goto try_again;
  1704. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1705. build = pieces.build;
  1706. /*
  1707. * api_ver should match the api version forming part of the
  1708. * firmware filename ... but we don't check for that and only rely
  1709. * on the API version read from firmware header from here on forward
  1710. */
  1711. if (api_ver < api_min || api_ver > api_max) {
  1712. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1713. "Driver supports v%u, firmware is v%u.\n",
  1714. api_max, api_ver);
  1715. goto try_again;
  1716. }
  1717. if (api_ver != api_max)
  1718. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1719. "got v%u. New firmware can be obtained "
  1720. "from http://www.intellinuxwireless.org.\n",
  1721. api_max, api_ver);
  1722. if (build)
  1723. sprintf(buildstr, " build %u", build);
  1724. else
  1725. buildstr[0] = '\0';
  1726. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1727. IWL_UCODE_MAJOR(priv->ucode_ver),
  1728. IWL_UCODE_MINOR(priv->ucode_ver),
  1729. IWL_UCODE_API(priv->ucode_ver),
  1730. IWL_UCODE_SERIAL(priv->ucode_ver),
  1731. buildstr);
  1732. snprintf(priv->hw->wiphy->fw_version,
  1733. sizeof(priv->hw->wiphy->fw_version),
  1734. "%u.%u.%u.%u%s",
  1735. IWL_UCODE_MAJOR(priv->ucode_ver),
  1736. IWL_UCODE_MINOR(priv->ucode_ver),
  1737. IWL_UCODE_API(priv->ucode_ver),
  1738. IWL_UCODE_SERIAL(priv->ucode_ver),
  1739. buildstr);
  1740. /*
  1741. * For any of the failures below (before allocating pci memory)
  1742. * we will try to load a version with a smaller API -- maybe the
  1743. * user just got a corrupted version of the latest API.
  1744. */
  1745. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1746. priv->ucode_ver);
  1747. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1748. pieces.inst_size);
  1749. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1750. pieces.data_size);
  1751. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1752. pieces.init_size);
  1753. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1754. pieces.init_data_size);
  1755. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
  1756. pieces.boot_size);
  1757. /* Verify that uCode images will fit in card's SRAM */
  1758. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1759. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1760. pieces.inst_size);
  1761. goto try_again;
  1762. }
  1763. if (pieces.data_size > priv->hw_params.max_data_size) {
  1764. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1765. pieces.data_size);
  1766. goto try_again;
  1767. }
  1768. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1769. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1770. pieces.init_size);
  1771. goto try_again;
  1772. }
  1773. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1774. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1775. pieces.init_data_size);
  1776. goto try_again;
  1777. }
  1778. if (pieces.boot_size > priv->hw_params.max_bsm_size) {
  1779. IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
  1780. pieces.boot_size);
  1781. goto try_again;
  1782. }
  1783. /* Allocate ucode buffers for card's bus-master loading ... */
  1784. /* Runtime instructions and 2 copies of data:
  1785. * 1) unmodified from disk
  1786. * 2) backup cache for save/restore during power-downs */
  1787. priv->ucode_code.len = pieces.inst_size;
  1788. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1789. priv->ucode_data.len = pieces.data_size;
  1790. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1791. priv->ucode_data_backup.len = pieces.data_size;
  1792. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1793. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1794. !priv->ucode_data_backup.v_addr)
  1795. goto err_pci_alloc;
  1796. /* Initialization instructions and data */
  1797. if (pieces.init_size && pieces.init_data_size) {
  1798. priv->ucode_init.len = pieces.init_size;
  1799. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1800. priv->ucode_init_data.len = pieces.init_data_size;
  1801. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1802. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1803. goto err_pci_alloc;
  1804. }
  1805. /* Bootstrap (instructions only, no data) */
  1806. if (pieces.boot_size) {
  1807. priv->ucode_boot.len = pieces.boot_size;
  1808. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1809. if (!priv->ucode_boot.v_addr)
  1810. goto err_pci_alloc;
  1811. }
  1812. /* Now that we can no longer fail, copy information */
  1813. /*
  1814. * The (size - 16) / 12 formula is based on the information recorded
  1815. * for each event, which is of mode 1 (including timestamp) for all
  1816. * new microcodes that include this information.
  1817. */
  1818. priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
  1819. if (pieces.init_evtlog_size)
  1820. priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
  1821. else
  1822. priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
  1823. priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
  1824. priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
  1825. if (pieces.inst_evtlog_size)
  1826. priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
  1827. else
  1828. priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
  1829. priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
  1830. /* Copy images into buffers for card's bus-master reads ... */
  1831. /* Runtime instructions (first block of data in file) */
  1832. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
  1833. pieces.inst_size);
  1834. memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1835. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1836. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1837. /*
  1838. * Runtime data
  1839. * NOTE: Copy into backup buffer will be done in iwl_up()
  1840. */
  1841. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
  1842. pieces.data_size);
  1843. memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
  1844. memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
  1845. /* Initialization instructions */
  1846. if (pieces.init_size) {
  1847. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1848. pieces.init_size);
  1849. memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
  1850. }
  1851. /* Initialization data */
  1852. if (pieces.init_data_size) {
  1853. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1854. pieces.init_data_size);
  1855. memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
  1856. pieces.init_data_size);
  1857. }
  1858. /* Bootstrap instructions */
  1859. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
  1860. pieces.boot_size);
  1861. memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
  1862. /*
  1863. * figure out the offset of chain noise reset and gain commands
  1864. * base on the size of standard phy calibration commands table size
  1865. */
  1866. if (ucode_capa.standard_phy_calibration_size >
  1867. IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
  1868. ucode_capa.standard_phy_calibration_size =
  1869. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
  1870. priv->_agn.phy_calib_chain_noise_reset_cmd =
  1871. ucode_capa.standard_phy_calibration_size;
  1872. priv->_agn.phy_calib_chain_noise_gain_cmd =
  1873. ucode_capa.standard_phy_calibration_size + 1;
  1874. /**************************************************
  1875. * This is still part of probe() in a sense...
  1876. *
  1877. * 9. Setup and register with mac80211 and debugfs
  1878. **************************************************/
  1879. err = iwl_mac_setup_register(priv, &ucode_capa);
  1880. if (err)
  1881. goto out_unbind;
  1882. err = iwl_dbgfs_register(priv, DRV_NAME);
  1883. if (err)
  1884. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1885. err = sysfs_create_group(&priv->pci_dev->dev.kobj,
  1886. &iwl_attribute_group);
  1887. if (err) {
  1888. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  1889. goto out_unbind;
  1890. }
  1891. /* We have our copies now, allow OS release its copies */
  1892. release_firmware(ucode_raw);
  1893. complete(&priv->_agn.firmware_loading_complete);
  1894. return;
  1895. try_again:
  1896. /* try next, if any */
  1897. if (iwl_request_firmware(priv, false))
  1898. goto out_unbind;
  1899. release_firmware(ucode_raw);
  1900. return;
  1901. err_pci_alloc:
  1902. IWL_ERR(priv, "failed to allocate pci memory\n");
  1903. iwl_dealloc_ucode_pci(priv);
  1904. out_unbind:
  1905. complete(&priv->_agn.firmware_loading_complete);
  1906. device_release_driver(&priv->pci_dev->dev);
  1907. release_firmware(ucode_raw);
  1908. }
  1909. static const char *desc_lookup_text[] = {
  1910. "OK",
  1911. "FAIL",
  1912. "BAD_PARAM",
  1913. "BAD_CHECKSUM",
  1914. "NMI_INTERRUPT_WDG",
  1915. "SYSASSERT",
  1916. "FATAL_ERROR",
  1917. "BAD_COMMAND",
  1918. "HW_ERROR_TUNE_LOCK",
  1919. "HW_ERROR_TEMPERATURE",
  1920. "ILLEGAL_CHAN_FREQ",
  1921. "VCC_NOT_STABLE",
  1922. "FH_ERROR",
  1923. "NMI_INTERRUPT_HOST",
  1924. "NMI_INTERRUPT_ACTION_PT",
  1925. "NMI_INTERRUPT_UNKNOWN",
  1926. "UCODE_VERSION_MISMATCH",
  1927. "HW_ERROR_ABS_LOCK",
  1928. "HW_ERROR_CAL_LOCK_FAIL",
  1929. "NMI_INTERRUPT_INST_ACTION_PT",
  1930. "NMI_INTERRUPT_DATA_ACTION_PT",
  1931. "NMI_TRM_HW_ER",
  1932. "NMI_INTERRUPT_TRM",
  1933. "NMI_INTERRUPT_BREAK_POINT"
  1934. "DEBUG_0",
  1935. "DEBUG_1",
  1936. "DEBUG_2",
  1937. "DEBUG_3",
  1938. };
  1939. static struct { char *name; u8 num; } advanced_lookup[] = {
  1940. { "NMI_INTERRUPT_WDG", 0x34 },
  1941. { "SYSASSERT", 0x35 },
  1942. { "UCODE_VERSION_MISMATCH", 0x37 },
  1943. { "BAD_COMMAND", 0x38 },
  1944. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  1945. { "FATAL_ERROR", 0x3D },
  1946. { "NMI_TRM_HW_ERR", 0x46 },
  1947. { "NMI_INTERRUPT_TRM", 0x4C },
  1948. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  1949. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  1950. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  1951. { "NMI_INTERRUPT_HOST", 0x66 },
  1952. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  1953. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  1954. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  1955. { "ADVANCED_SYSASSERT", 0 },
  1956. };
  1957. static const char *desc_lookup(u32 num)
  1958. {
  1959. int i;
  1960. int max = ARRAY_SIZE(desc_lookup_text);
  1961. if (num < max)
  1962. return desc_lookup_text[num];
  1963. max = ARRAY_SIZE(advanced_lookup) - 1;
  1964. for (i = 0; i < max; i++) {
  1965. if (advanced_lookup[i].num == num)
  1966. break;;
  1967. }
  1968. return advanced_lookup[i].name;
  1969. }
  1970. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1971. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1972. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1973. {
  1974. u32 data2, line;
  1975. u32 desc, time, count, base, data1;
  1976. u32 blink1, blink2, ilink1, ilink2;
  1977. u32 pc, hcmd;
  1978. if (priv->ucode_type == UCODE_INIT) {
  1979. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1980. if (!base)
  1981. base = priv->_agn.init_errlog_ptr;
  1982. } else {
  1983. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1984. if (!base)
  1985. base = priv->_agn.inst_errlog_ptr;
  1986. }
  1987. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1988. IWL_ERR(priv,
  1989. "Not valid error log pointer 0x%08X for %s uCode\n",
  1990. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1991. return;
  1992. }
  1993. count = iwl_read_targ_mem(priv, base);
  1994. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1995. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1996. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1997. priv->status, count);
  1998. }
  1999. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  2000. pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
  2001. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  2002. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  2003. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  2004. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  2005. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  2006. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  2007. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  2008. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  2009. hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
  2010. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  2011. blink1, blink2, ilink1, ilink2);
  2012. IWL_ERR(priv, "Desc Time "
  2013. "data1 data2 line\n");
  2014. IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
  2015. desc_lookup(desc), desc, time, data1, data2, line);
  2016. IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
  2017. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  2018. pc, blink1, blink2, ilink1, ilink2, hcmd);
  2019. }
  2020. #define EVENT_START_OFFSET (4 * sizeof(u32))
  2021. /**
  2022. * iwl_print_event_log - Dump error event log to syslog
  2023. *
  2024. */
  2025. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  2026. u32 num_events, u32 mode,
  2027. int pos, char **buf, size_t bufsz)
  2028. {
  2029. u32 i;
  2030. u32 base; /* SRAM byte address of event log header */
  2031. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  2032. u32 ptr; /* SRAM byte address of log data */
  2033. u32 ev, time, data; /* event log data */
  2034. unsigned long reg_flags;
  2035. if (num_events == 0)
  2036. return pos;
  2037. if (priv->ucode_type == UCODE_INIT) {
  2038. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  2039. if (!base)
  2040. base = priv->_agn.init_evtlog_ptr;
  2041. } else {
  2042. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2043. if (!base)
  2044. base = priv->_agn.inst_evtlog_ptr;
  2045. }
  2046. if (mode == 0)
  2047. event_size = 2 * sizeof(u32);
  2048. else
  2049. event_size = 3 * sizeof(u32);
  2050. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  2051. /* Make sure device is powered up for SRAM reads */
  2052. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  2053. iwl_grab_nic_access(priv);
  2054. /* Set starting address; reads will auto-increment */
  2055. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  2056. rmb();
  2057. /* "time" is actually "data" for mode 0 (no timestamp).
  2058. * place event id # at far right for easier visual parsing. */
  2059. for (i = 0; i < num_events; i++) {
  2060. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2061. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2062. if (mode == 0) {
  2063. /* data, ev */
  2064. if (bufsz) {
  2065. pos += scnprintf(*buf + pos, bufsz - pos,
  2066. "EVT_LOG:0x%08x:%04u\n",
  2067. time, ev);
  2068. } else {
  2069. trace_iwlwifi_dev_ucode_event(priv, 0,
  2070. time, ev);
  2071. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  2072. time, ev);
  2073. }
  2074. } else {
  2075. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2076. if (bufsz) {
  2077. pos += scnprintf(*buf + pos, bufsz - pos,
  2078. "EVT_LOGT:%010u:0x%08x:%04u\n",
  2079. time, data, ev);
  2080. } else {
  2081. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  2082. time, data, ev);
  2083. trace_iwlwifi_dev_ucode_event(priv, time,
  2084. data, ev);
  2085. }
  2086. }
  2087. }
  2088. /* Allow device to power down */
  2089. iwl_release_nic_access(priv);
  2090. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  2091. return pos;
  2092. }
  2093. /**
  2094. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  2095. */
  2096. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  2097. u32 num_wraps, u32 next_entry,
  2098. u32 size, u32 mode,
  2099. int pos, char **buf, size_t bufsz)
  2100. {
  2101. /*
  2102. * display the newest DEFAULT_LOG_ENTRIES entries
  2103. * i.e the entries just before the next ont that uCode would fill.
  2104. */
  2105. if (num_wraps) {
  2106. if (next_entry < size) {
  2107. pos = iwl_print_event_log(priv,
  2108. capacity - (size - next_entry),
  2109. size - next_entry, mode,
  2110. pos, buf, bufsz);
  2111. pos = iwl_print_event_log(priv, 0,
  2112. next_entry, mode,
  2113. pos, buf, bufsz);
  2114. } else
  2115. pos = iwl_print_event_log(priv, next_entry - size,
  2116. size, mode, pos, buf, bufsz);
  2117. } else {
  2118. if (next_entry < size) {
  2119. pos = iwl_print_event_log(priv, 0, next_entry,
  2120. mode, pos, buf, bufsz);
  2121. } else {
  2122. pos = iwl_print_event_log(priv, next_entry - size,
  2123. size, mode, pos, buf, bufsz);
  2124. }
  2125. }
  2126. return pos;
  2127. }
  2128. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  2129. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  2130. char **buf, bool display)
  2131. {
  2132. u32 base; /* SRAM byte address of event log header */
  2133. u32 capacity; /* event log capacity in # entries */
  2134. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  2135. u32 num_wraps; /* # times uCode wrapped to top of log */
  2136. u32 next_entry; /* index of next entry to be written by uCode */
  2137. u32 size; /* # entries that we'll print */
  2138. u32 logsize;
  2139. int pos = 0;
  2140. size_t bufsz = 0;
  2141. if (priv->ucode_type == UCODE_INIT) {
  2142. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  2143. logsize = priv->_agn.init_evtlog_size;
  2144. if (!base)
  2145. base = priv->_agn.init_evtlog_ptr;
  2146. } else {
  2147. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2148. logsize = priv->_agn.inst_evtlog_size;
  2149. if (!base)
  2150. base = priv->_agn.inst_evtlog_ptr;
  2151. }
  2152. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  2153. IWL_ERR(priv,
  2154. "Invalid event log pointer 0x%08X for %s uCode\n",
  2155. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  2156. return -EINVAL;
  2157. }
  2158. /* event log header */
  2159. capacity = iwl_read_targ_mem(priv, base);
  2160. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  2161. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  2162. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  2163. if (capacity > logsize) {
  2164. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  2165. capacity, logsize);
  2166. capacity = logsize;
  2167. }
  2168. if (next_entry > logsize) {
  2169. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  2170. next_entry, logsize);
  2171. next_entry = logsize;
  2172. }
  2173. size = num_wraps ? capacity : next_entry;
  2174. /* bail out if nothing in log */
  2175. if (size == 0) {
  2176. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  2177. return pos;
  2178. }
  2179. #ifdef CONFIG_IWLWIFI_DEBUG
  2180. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  2181. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2182. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2183. #else
  2184. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2185. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2186. #endif
  2187. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  2188. size);
  2189. #ifdef CONFIG_IWLWIFI_DEBUG
  2190. if (display) {
  2191. if (full_log)
  2192. bufsz = capacity * 48;
  2193. else
  2194. bufsz = size * 48;
  2195. *buf = kmalloc(bufsz, GFP_KERNEL);
  2196. if (!*buf)
  2197. return -ENOMEM;
  2198. }
  2199. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  2200. /*
  2201. * if uCode has wrapped back to top of log,
  2202. * start at the oldest entry,
  2203. * i.e the next one that uCode would fill.
  2204. */
  2205. if (num_wraps)
  2206. pos = iwl_print_event_log(priv, next_entry,
  2207. capacity - next_entry, mode,
  2208. pos, buf, bufsz);
  2209. /* (then/else) start at top of log */
  2210. pos = iwl_print_event_log(priv, 0,
  2211. next_entry, mode, pos, buf, bufsz);
  2212. } else
  2213. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2214. next_entry, size, mode,
  2215. pos, buf, bufsz);
  2216. #else
  2217. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2218. next_entry, size, mode,
  2219. pos, buf, bufsz);
  2220. #endif
  2221. return pos;
  2222. }
  2223. /**
  2224. * iwl_alive_start - called after REPLY_ALIVE notification received
  2225. * from protocol/runtime uCode (initialization uCode's
  2226. * Alive gets handled by iwl_init_alive_start()).
  2227. */
  2228. static void iwl_alive_start(struct iwl_priv *priv)
  2229. {
  2230. int ret = 0;
  2231. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2232. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2233. /* We had an error bringing up the hardware, so take it
  2234. * all the way back down so we can try again */
  2235. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2236. goto restart;
  2237. }
  2238. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2239. * This is a paranoid check, because we would not have gotten the
  2240. * "runtime" alive if code weren't properly loaded. */
  2241. if (iwl_verify_ucode(priv)) {
  2242. /* Runtime instruction load was bad;
  2243. * take it all the way back down so we can try again */
  2244. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2245. goto restart;
  2246. }
  2247. ret = priv->cfg->ops->lib->alive_notify(priv);
  2248. if (ret) {
  2249. IWL_WARN(priv,
  2250. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  2251. goto restart;
  2252. }
  2253. /* After the ALIVE response, we can send host commands to the uCode */
  2254. set_bit(STATUS_ALIVE, &priv->status);
  2255. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2256. /* Enable timer to monitor the driver queues */
  2257. mod_timer(&priv->monitor_recover,
  2258. jiffies +
  2259. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  2260. }
  2261. if (iwl_is_rfkill(priv))
  2262. return;
  2263. ieee80211_wake_queues(priv->hw);
  2264. priv->active_rate = IWL_RATES_MASK;
  2265. /* Configure Tx antenna selection based on H/W config */
  2266. if (priv->cfg->ops->hcmd->set_tx_ant)
  2267. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  2268. if (iwl_is_associated(priv)) {
  2269. struct iwl_rxon_cmd *active_rxon =
  2270. (struct iwl_rxon_cmd *)&priv->active_rxon;
  2271. /* apply any changes in staging */
  2272. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2273. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2274. } else {
  2275. /* Initialize our rx_config data */
  2276. iwl_connection_init_rx_config(priv, NULL);
  2277. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2278. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2279. }
  2280. /* Configure Bluetooth device coexistence support */
  2281. priv->cfg->ops->hcmd->send_bt_config(priv);
  2282. iwl_reset_run_time_calib(priv);
  2283. /* Configure the adapter for unassociated operation */
  2284. iwlcore_commit_rxon(priv);
  2285. /* At this point, the NIC is initialized and operational */
  2286. iwl_rf_kill_ct_config(priv);
  2287. iwl_leds_init(priv);
  2288. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2289. set_bit(STATUS_READY, &priv->status);
  2290. wake_up_interruptible(&priv->wait_command_queue);
  2291. iwl_power_update_mode(priv, true);
  2292. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  2293. return;
  2294. restart:
  2295. queue_work(priv->workqueue, &priv->restart);
  2296. }
  2297. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  2298. static void __iwl_down(struct iwl_priv *priv)
  2299. {
  2300. unsigned long flags;
  2301. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  2302. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2303. if (!exit_pending)
  2304. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2305. iwl_clear_ucode_stations(priv);
  2306. iwl_dealloc_bcast_station(priv);
  2307. iwl_clear_driver_stations(priv);
  2308. /* Unblock any waiting calls */
  2309. wake_up_interruptible_all(&priv->wait_command_queue);
  2310. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2311. * exiting the module */
  2312. if (!exit_pending)
  2313. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2314. /* stop and reset the on-board processor */
  2315. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2316. /* tell the device to stop sending interrupts */
  2317. spin_lock_irqsave(&priv->lock, flags);
  2318. iwl_disable_interrupts(priv);
  2319. spin_unlock_irqrestore(&priv->lock, flags);
  2320. iwl_synchronize_irq(priv);
  2321. if (priv->mac80211_registered)
  2322. ieee80211_stop_queues(priv->hw);
  2323. /* If we have not previously called iwl_init() then
  2324. * clear all bits but the RF Kill bit and return */
  2325. if (!iwl_is_init(priv)) {
  2326. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2327. STATUS_RF_KILL_HW |
  2328. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2329. STATUS_GEO_CONFIGURED |
  2330. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2331. STATUS_EXIT_PENDING;
  2332. goto exit;
  2333. }
  2334. /* ...otherwise clear out all the status bits but the RF Kill
  2335. * bit and continue taking the NIC down. */
  2336. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2337. STATUS_RF_KILL_HW |
  2338. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2339. STATUS_GEO_CONFIGURED |
  2340. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2341. STATUS_FW_ERROR |
  2342. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2343. STATUS_EXIT_PENDING;
  2344. /* device going down, Stop using ICT table */
  2345. iwl_disable_ict(priv);
  2346. iwlagn_txq_ctx_stop(priv);
  2347. iwlagn_rxq_stop(priv);
  2348. /* Power-down device's busmaster DMA clocks */
  2349. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2350. udelay(5);
  2351. /* Make sure (redundant) we've released our request to stay awake */
  2352. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2353. /* Stop the device, and put it in low power state */
  2354. priv->cfg->ops->lib->apm_ops.stop(priv);
  2355. exit:
  2356. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2357. if (priv->ibss_beacon)
  2358. dev_kfree_skb(priv->ibss_beacon);
  2359. priv->ibss_beacon = NULL;
  2360. /* clear out any free frames */
  2361. iwl_clear_free_frames(priv);
  2362. }
  2363. static void iwl_down(struct iwl_priv *priv)
  2364. {
  2365. mutex_lock(&priv->mutex);
  2366. __iwl_down(priv);
  2367. mutex_unlock(&priv->mutex);
  2368. iwl_cancel_deferred_work(priv);
  2369. }
  2370. #define HW_READY_TIMEOUT (50)
  2371. static int iwl_set_hw_ready(struct iwl_priv *priv)
  2372. {
  2373. int ret = 0;
  2374. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2375. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  2376. /* See if we got it */
  2377. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2378. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2379. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2380. HW_READY_TIMEOUT);
  2381. if (ret != -ETIMEDOUT)
  2382. priv->hw_ready = true;
  2383. else
  2384. priv->hw_ready = false;
  2385. IWL_DEBUG_INFO(priv, "hardware %s\n",
  2386. (priv->hw_ready == 1) ? "ready" : "not ready");
  2387. return ret;
  2388. }
  2389. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  2390. {
  2391. int ret = 0;
  2392. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  2393. ret = iwl_set_hw_ready(priv);
  2394. if (priv->hw_ready)
  2395. return ret;
  2396. /* If HW is not ready, prepare the conditions to check again */
  2397. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2398. CSR_HW_IF_CONFIG_REG_PREPARE);
  2399. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2400. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  2401. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  2402. /* HW should be ready by now, check again. */
  2403. if (ret != -ETIMEDOUT)
  2404. iwl_set_hw_ready(priv);
  2405. return ret;
  2406. }
  2407. #define MAX_HW_RESTARTS 5
  2408. static int __iwl_up(struct iwl_priv *priv)
  2409. {
  2410. int i;
  2411. int ret;
  2412. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2413. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2414. return -EIO;
  2415. }
  2416. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2417. IWL_ERR(priv, "ucode not available for device bringup\n");
  2418. return -EIO;
  2419. }
  2420. ret = iwl_alloc_bcast_station(priv, true);
  2421. if (ret)
  2422. return ret;
  2423. iwl_prepare_card_hw(priv);
  2424. if (!priv->hw_ready) {
  2425. IWL_WARN(priv, "Exit HW not ready\n");
  2426. return -EIO;
  2427. }
  2428. /* If platform's RF_KILL switch is NOT set to KILL */
  2429. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2430. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2431. else
  2432. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2433. if (iwl_is_rfkill(priv)) {
  2434. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  2435. iwl_enable_interrupts(priv);
  2436. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2437. return 0;
  2438. }
  2439. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2440. ret = iwlagn_hw_nic_init(priv);
  2441. if (ret) {
  2442. IWL_ERR(priv, "Unable to init nic\n");
  2443. return ret;
  2444. }
  2445. /* make sure rfkill handshake bits are cleared */
  2446. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2447. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2448. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2449. /* clear (again), then enable host interrupts */
  2450. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2451. iwl_enable_interrupts(priv);
  2452. /* really make sure rfkill handshake bits are cleared */
  2453. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2454. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2455. /* Copy original ucode data image from disk into backup cache.
  2456. * This will be used to initialize the on-board processor's
  2457. * data SRAM for a clean start when the runtime program first loads. */
  2458. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2459. priv->ucode_data.len);
  2460. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2461. /* load bootstrap state machine,
  2462. * load bootstrap program into processor's memory,
  2463. * prepare to load the "initialize" uCode */
  2464. ret = priv->cfg->ops->lib->load_ucode(priv);
  2465. if (ret) {
  2466. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2467. ret);
  2468. continue;
  2469. }
  2470. /* start card; "initialize" will load runtime ucode */
  2471. iwl_nic_start(priv);
  2472. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2473. return 0;
  2474. }
  2475. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2476. __iwl_down(priv);
  2477. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2478. /* tried to restart and config the device for as long as our
  2479. * patience could withstand */
  2480. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2481. return -EIO;
  2482. }
  2483. /*****************************************************************************
  2484. *
  2485. * Workqueue callbacks
  2486. *
  2487. *****************************************************************************/
  2488. static void iwl_bg_init_alive_start(struct work_struct *data)
  2489. {
  2490. struct iwl_priv *priv =
  2491. container_of(data, struct iwl_priv, init_alive_start.work);
  2492. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2493. return;
  2494. mutex_lock(&priv->mutex);
  2495. priv->cfg->ops->lib->init_alive_start(priv);
  2496. mutex_unlock(&priv->mutex);
  2497. }
  2498. static void iwl_bg_alive_start(struct work_struct *data)
  2499. {
  2500. struct iwl_priv *priv =
  2501. container_of(data, struct iwl_priv, alive_start.work);
  2502. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2503. return;
  2504. /* enable dram interrupt */
  2505. iwl_reset_ict(priv);
  2506. mutex_lock(&priv->mutex);
  2507. iwl_alive_start(priv);
  2508. mutex_unlock(&priv->mutex);
  2509. }
  2510. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2511. {
  2512. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2513. run_time_calib_work);
  2514. mutex_lock(&priv->mutex);
  2515. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2516. test_bit(STATUS_SCANNING, &priv->status)) {
  2517. mutex_unlock(&priv->mutex);
  2518. return;
  2519. }
  2520. if (priv->start_calib) {
  2521. if (priv->cfg->bt_statistics) {
  2522. iwl_chain_noise_calibration(priv,
  2523. (void *)&priv->_agn.statistics_bt);
  2524. iwl_sensitivity_calibration(priv,
  2525. (void *)&priv->_agn.statistics_bt);
  2526. } else {
  2527. iwl_chain_noise_calibration(priv,
  2528. (void *)&priv->_agn.statistics);
  2529. iwl_sensitivity_calibration(priv,
  2530. (void *)&priv->_agn.statistics);
  2531. }
  2532. }
  2533. mutex_unlock(&priv->mutex);
  2534. }
  2535. static void iwl_bg_restart(struct work_struct *data)
  2536. {
  2537. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2538. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2539. return;
  2540. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2541. mutex_lock(&priv->mutex);
  2542. priv->vif = NULL;
  2543. priv->is_open = 0;
  2544. mutex_unlock(&priv->mutex);
  2545. iwl_down(priv);
  2546. ieee80211_restart_hw(priv->hw);
  2547. } else {
  2548. iwl_down(priv);
  2549. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2550. return;
  2551. mutex_lock(&priv->mutex);
  2552. __iwl_up(priv);
  2553. mutex_unlock(&priv->mutex);
  2554. }
  2555. }
  2556. static void iwl_bg_rx_replenish(struct work_struct *data)
  2557. {
  2558. struct iwl_priv *priv =
  2559. container_of(data, struct iwl_priv, rx_replenish);
  2560. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2561. return;
  2562. mutex_lock(&priv->mutex);
  2563. iwlagn_rx_replenish(priv);
  2564. mutex_unlock(&priv->mutex);
  2565. }
  2566. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2567. void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2568. {
  2569. struct ieee80211_conf *conf = NULL;
  2570. int ret = 0;
  2571. if (!vif || !priv->is_open)
  2572. return;
  2573. if (vif->type == NL80211_IFTYPE_AP) {
  2574. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2575. return;
  2576. }
  2577. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2578. return;
  2579. iwl_scan_cancel_timeout(priv, 200);
  2580. conf = ieee80211_get_hw_conf(priv->hw);
  2581. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2582. iwlcore_commit_rxon(priv);
  2583. iwl_setup_rxon_timing(priv, vif);
  2584. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2585. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2586. if (ret)
  2587. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2588. "Attempting to continue.\n");
  2589. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2590. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2591. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2592. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2593. priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
  2594. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2595. vif->bss_conf.aid, vif->bss_conf.beacon_int);
  2596. if (vif->bss_conf.use_short_preamble)
  2597. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2598. else
  2599. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2600. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2601. if (vif->bss_conf.use_short_slot)
  2602. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2603. else
  2604. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2605. }
  2606. iwlcore_commit_rxon(priv);
  2607. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2608. vif->bss_conf.aid, priv->active_rxon.bssid_addr);
  2609. switch (vif->type) {
  2610. case NL80211_IFTYPE_STATION:
  2611. break;
  2612. case NL80211_IFTYPE_ADHOC:
  2613. iwl_send_beacon_cmd(priv);
  2614. break;
  2615. default:
  2616. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2617. __func__, vif->type);
  2618. break;
  2619. }
  2620. /* the chain noise calibration will enabled PM upon completion
  2621. * If chain noise has already been run, then we need to enable
  2622. * power management here */
  2623. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2624. iwl_power_update_mode(priv, false);
  2625. /* Enable Rx differential gain and sensitivity calibrations */
  2626. iwl_chain_noise_reset(priv);
  2627. priv->start_calib = 1;
  2628. }
  2629. /*****************************************************************************
  2630. *
  2631. * mac80211 entry point functions
  2632. *
  2633. *****************************************************************************/
  2634. #define UCODE_READY_TIMEOUT (4 * HZ)
  2635. /*
  2636. * Not a mac80211 entry point function, but it fits in with all the
  2637. * other mac80211 functions grouped here.
  2638. */
  2639. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2640. struct iwlagn_ucode_capabilities *capa)
  2641. {
  2642. int ret;
  2643. struct ieee80211_hw *hw = priv->hw;
  2644. hw->rate_control_algorithm = "iwl-agn-rs";
  2645. /* Tell mac80211 our characteristics */
  2646. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2647. IEEE80211_HW_AMPDU_AGGREGATION |
  2648. IEEE80211_HW_SPECTRUM_MGMT;
  2649. if (!priv->cfg->broken_powersave)
  2650. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2651. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2652. if (priv->cfg->sku & IWL_SKU_N)
  2653. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2654. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2655. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2656. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2657. hw->wiphy->interface_modes =
  2658. BIT(NL80211_IFTYPE_STATION) |
  2659. BIT(NL80211_IFTYPE_ADHOC);
  2660. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2661. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2662. /*
  2663. * For now, disable PS by default because it affects
  2664. * RX performance significantly.
  2665. */
  2666. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2667. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2668. /* we create the 802.11 header and a zero-length SSID element */
  2669. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2670. /* Default value; 4 EDCA QOS priorities */
  2671. hw->queues = 4;
  2672. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2673. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2674. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2675. &priv->bands[IEEE80211_BAND_2GHZ];
  2676. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2677. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2678. &priv->bands[IEEE80211_BAND_5GHZ];
  2679. ret = ieee80211_register_hw(priv->hw);
  2680. if (ret) {
  2681. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2682. return ret;
  2683. }
  2684. priv->mac80211_registered = 1;
  2685. return 0;
  2686. }
  2687. static int iwl_mac_start(struct ieee80211_hw *hw)
  2688. {
  2689. struct iwl_priv *priv = hw->priv;
  2690. int ret;
  2691. IWL_DEBUG_MAC80211(priv, "enter\n");
  2692. /* we should be verifying the device is ready to be opened */
  2693. mutex_lock(&priv->mutex);
  2694. ret = __iwl_up(priv);
  2695. mutex_unlock(&priv->mutex);
  2696. if (ret)
  2697. return ret;
  2698. if (iwl_is_rfkill(priv))
  2699. goto out;
  2700. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2701. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2702. * mac80211 will not be run successfully. */
  2703. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2704. test_bit(STATUS_READY, &priv->status),
  2705. UCODE_READY_TIMEOUT);
  2706. if (!ret) {
  2707. if (!test_bit(STATUS_READY, &priv->status)) {
  2708. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2709. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2710. return -ETIMEDOUT;
  2711. }
  2712. }
  2713. iwl_led_start(priv);
  2714. out:
  2715. priv->is_open = 1;
  2716. IWL_DEBUG_MAC80211(priv, "leave\n");
  2717. return 0;
  2718. }
  2719. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2720. {
  2721. struct iwl_priv *priv = hw->priv;
  2722. IWL_DEBUG_MAC80211(priv, "enter\n");
  2723. if (!priv->is_open)
  2724. return;
  2725. priv->is_open = 0;
  2726. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2727. /* stop mac, cancel any scan request and clear
  2728. * RXON_FILTER_ASSOC_MSK BIT
  2729. */
  2730. mutex_lock(&priv->mutex);
  2731. iwl_scan_cancel_timeout(priv, 100);
  2732. mutex_unlock(&priv->mutex);
  2733. }
  2734. iwl_down(priv);
  2735. flush_workqueue(priv->workqueue);
  2736. /* enable interrupts again in order to receive rfkill changes */
  2737. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2738. iwl_enable_interrupts(priv);
  2739. IWL_DEBUG_MAC80211(priv, "leave\n");
  2740. }
  2741. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2742. {
  2743. struct iwl_priv *priv = hw->priv;
  2744. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2745. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2746. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2747. if (iwlagn_tx_skb(priv, skb))
  2748. dev_kfree_skb_any(skb);
  2749. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2750. return NETDEV_TX_OK;
  2751. }
  2752. void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2753. {
  2754. int ret = 0;
  2755. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2756. return;
  2757. /* The following should be done only at AP bring up */
  2758. if (!iwl_is_associated(priv)) {
  2759. /* RXON - unassoc (to set timing command) */
  2760. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2761. iwlcore_commit_rxon(priv);
  2762. /* RXON Timing */
  2763. iwl_setup_rxon_timing(priv, vif);
  2764. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2765. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2766. if (ret)
  2767. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2768. "Attempting to continue.\n");
  2769. /* AP has all antennas */
  2770. priv->chain_noise_data.active_chains =
  2771. priv->hw_params.valid_rx_ant;
  2772. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2773. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2774. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2775. priv->staging_rxon.assoc_id = 0;
  2776. if (vif->bss_conf.use_short_preamble)
  2777. priv->staging_rxon.flags |=
  2778. RXON_FLG_SHORT_PREAMBLE_MSK;
  2779. else
  2780. priv->staging_rxon.flags &=
  2781. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2782. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2783. if (vif->bss_conf.use_short_slot)
  2784. priv->staging_rxon.flags |=
  2785. RXON_FLG_SHORT_SLOT_MSK;
  2786. else
  2787. priv->staging_rxon.flags &=
  2788. ~RXON_FLG_SHORT_SLOT_MSK;
  2789. }
  2790. /* restore RXON assoc */
  2791. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2792. iwlcore_commit_rxon(priv);
  2793. }
  2794. iwl_send_beacon_cmd(priv);
  2795. /* FIXME - we need to add code here to detect a totally new
  2796. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2797. * clear sta table, add BCAST sta... */
  2798. }
  2799. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2800. struct ieee80211_vif *vif,
  2801. struct ieee80211_key_conf *keyconf,
  2802. struct ieee80211_sta *sta,
  2803. u32 iv32, u16 *phase1key)
  2804. {
  2805. struct iwl_priv *priv = hw->priv;
  2806. IWL_DEBUG_MAC80211(priv, "enter\n");
  2807. iwl_update_tkip_key(priv, keyconf, sta,
  2808. iv32, phase1key);
  2809. IWL_DEBUG_MAC80211(priv, "leave\n");
  2810. }
  2811. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2812. struct ieee80211_vif *vif,
  2813. struct ieee80211_sta *sta,
  2814. struct ieee80211_key_conf *key)
  2815. {
  2816. struct iwl_priv *priv = hw->priv;
  2817. int ret;
  2818. u8 sta_id;
  2819. bool is_default_wep_key = false;
  2820. IWL_DEBUG_MAC80211(priv, "enter\n");
  2821. if (priv->cfg->mod_params->sw_crypto) {
  2822. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2823. return -EOPNOTSUPP;
  2824. }
  2825. sta_id = iwl_sta_id_or_broadcast(priv, sta);
  2826. if (sta_id == IWL_INVALID_STATION)
  2827. return -EINVAL;
  2828. mutex_lock(&priv->mutex);
  2829. iwl_scan_cancel_timeout(priv, 100);
  2830. /*
  2831. * If we are getting WEP group key and we didn't receive any key mapping
  2832. * so far, we are in legacy wep mode (group key only), otherwise we are
  2833. * in 1X mode.
  2834. * In legacy wep mode, we use another host command to the uCode.
  2835. */
  2836. if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
  2837. if (cmd == SET_KEY)
  2838. is_default_wep_key = !priv->key_mapping_key;
  2839. else
  2840. is_default_wep_key =
  2841. (key->hw_key_idx == HW_KEY_DEFAULT);
  2842. }
  2843. switch (cmd) {
  2844. case SET_KEY:
  2845. if (is_default_wep_key)
  2846. ret = iwl_set_default_wep_key(priv, key);
  2847. else
  2848. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2849. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2850. break;
  2851. case DISABLE_KEY:
  2852. if (is_default_wep_key)
  2853. ret = iwl_remove_default_wep_key(priv, key);
  2854. else
  2855. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2856. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2857. break;
  2858. default:
  2859. ret = -EINVAL;
  2860. }
  2861. mutex_unlock(&priv->mutex);
  2862. IWL_DEBUG_MAC80211(priv, "leave\n");
  2863. return ret;
  2864. }
  2865. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2866. struct ieee80211_vif *vif,
  2867. enum ieee80211_ampdu_mlme_action action,
  2868. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2869. {
  2870. struct iwl_priv *priv = hw->priv;
  2871. int ret = -EINVAL;
  2872. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2873. sta->addr, tid);
  2874. if (!(priv->cfg->sku & IWL_SKU_N))
  2875. return -EACCES;
  2876. mutex_lock(&priv->mutex);
  2877. switch (action) {
  2878. case IEEE80211_AMPDU_RX_START:
  2879. IWL_DEBUG_HT(priv, "start Rx\n");
  2880. ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2881. break;
  2882. case IEEE80211_AMPDU_RX_STOP:
  2883. IWL_DEBUG_HT(priv, "stop Rx\n");
  2884. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2885. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2886. ret = 0;
  2887. break;
  2888. case IEEE80211_AMPDU_TX_START:
  2889. IWL_DEBUG_HT(priv, "start Tx\n");
  2890. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2891. if (ret == 0) {
  2892. priv->_agn.agg_tids_count++;
  2893. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2894. priv->_agn.agg_tids_count);
  2895. }
  2896. break;
  2897. case IEEE80211_AMPDU_TX_STOP:
  2898. IWL_DEBUG_HT(priv, "stop Tx\n");
  2899. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  2900. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2901. priv->_agn.agg_tids_count--;
  2902. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2903. priv->_agn.agg_tids_count);
  2904. }
  2905. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2906. ret = 0;
  2907. if (priv->cfg->use_rts_for_aggregation) {
  2908. struct iwl_station_priv *sta_priv =
  2909. (void *) sta->drv_priv;
  2910. /*
  2911. * switch off RTS/CTS if it was previously enabled
  2912. */
  2913. sta_priv->lq_sta.lq.general_params.flags &=
  2914. ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2915. iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
  2916. CMD_ASYNC, false);
  2917. }
  2918. break;
  2919. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2920. if (priv->cfg->use_rts_for_aggregation) {
  2921. struct iwl_station_priv *sta_priv =
  2922. (void *) sta->drv_priv;
  2923. /*
  2924. * switch to RTS/CTS if it is the prefer protection
  2925. * method for HT traffic
  2926. */
  2927. sta_priv->lq_sta.lq.general_params.flags |=
  2928. LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2929. iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
  2930. CMD_ASYNC, false);
  2931. }
  2932. ret = 0;
  2933. break;
  2934. }
  2935. mutex_unlock(&priv->mutex);
  2936. return ret;
  2937. }
  2938. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2939. struct ieee80211_vif *vif,
  2940. enum sta_notify_cmd cmd,
  2941. struct ieee80211_sta *sta)
  2942. {
  2943. struct iwl_priv *priv = hw->priv;
  2944. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2945. int sta_id;
  2946. switch (cmd) {
  2947. case STA_NOTIFY_SLEEP:
  2948. WARN_ON(!sta_priv->client);
  2949. sta_priv->asleep = true;
  2950. if (atomic_read(&sta_priv->pending_frames) > 0)
  2951. ieee80211_sta_block_awake(hw, sta, true);
  2952. break;
  2953. case STA_NOTIFY_AWAKE:
  2954. WARN_ON(!sta_priv->client);
  2955. if (!sta_priv->asleep)
  2956. break;
  2957. sta_priv->asleep = false;
  2958. sta_id = iwl_sta_id(sta);
  2959. if (sta_id != IWL_INVALID_STATION)
  2960. iwl_sta_modify_ps_wake(priv, sta_id);
  2961. break;
  2962. default:
  2963. break;
  2964. }
  2965. }
  2966. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2967. struct ieee80211_vif *vif,
  2968. struct ieee80211_sta *sta)
  2969. {
  2970. struct iwl_priv *priv = hw->priv;
  2971. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2972. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2973. int ret;
  2974. u8 sta_id;
  2975. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2976. sta->addr);
  2977. mutex_lock(&priv->mutex);
  2978. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2979. sta->addr);
  2980. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2981. atomic_set(&sta_priv->pending_frames, 0);
  2982. if (vif->type == NL80211_IFTYPE_AP)
  2983. sta_priv->client = true;
  2984. ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
  2985. &sta_id);
  2986. if (ret) {
  2987. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2988. sta->addr, ret);
  2989. /* Should we return success if return code is EEXIST ? */
  2990. mutex_unlock(&priv->mutex);
  2991. return ret;
  2992. }
  2993. sta_priv->common.sta_id = sta_id;
  2994. /* Initialize rate scaling */
  2995. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2996. sta->addr);
  2997. iwl_rs_rate_init(priv, sta, sta_id);
  2998. mutex_unlock(&priv->mutex);
  2999. return 0;
  3000. }
  3001. static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
  3002. struct ieee80211_channel_switch *ch_switch)
  3003. {
  3004. struct iwl_priv *priv = hw->priv;
  3005. const struct iwl_channel_info *ch_info;
  3006. struct ieee80211_conf *conf = &hw->conf;
  3007. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  3008. u16 ch;
  3009. unsigned long flags = 0;
  3010. IWL_DEBUG_MAC80211(priv, "enter\n");
  3011. if (iwl_is_rfkill(priv))
  3012. goto out_exit;
  3013. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  3014. test_bit(STATUS_SCANNING, &priv->status))
  3015. goto out_exit;
  3016. if (!iwl_is_associated(priv))
  3017. goto out_exit;
  3018. /* channel switch in progress */
  3019. if (priv->switch_rxon.switch_in_progress == true)
  3020. goto out_exit;
  3021. mutex_lock(&priv->mutex);
  3022. if (priv->cfg->ops->lib->set_channel_switch) {
  3023. ch = ieee80211_frequency_to_channel(
  3024. ch_switch->channel->center_freq);
  3025. if (le16_to_cpu(priv->active_rxon.channel) != ch) {
  3026. ch_info = iwl_get_channel_info(priv,
  3027. conf->channel->band,
  3028. ch);
  3029. if (!is_channel_valid(ch_info)) {
  3030. IWL_DEBUG_MAC80211(priv, "invalid channel\n");
  3031. goto out;
  3032. }
  3033. spin_lock_irqsave(&priv->lock, flags);
  3034. priv->current_ht_config.smps = conf->smps_mode;
  3035. /* Configure HT40 channels */
  3036. ht_conf->is_ht = conf_is_ht(conf);
  3037. if (ht_conf->is_ht) {
  3038. if (conf_is_ht40_minus(conf)) {
  3039. ht_conf->extension_chan_offset =
  3040. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  3041. ht_conf->is_40mhz = true;
  3042. } else if (conf_is_ht40_plus(conf)) {
  3043. ht_conf->extension_chan_offset =
  3044. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  3045. ht_conf->is_40mhz = true;
  3046. } else {
  3047. ht_conf->extension_chan_offset =
  3048. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  3049. ht_conf->is_40mhz = false;
  3050. }
  3051. } else
  3052. ht_conf->is_40mhz = false;
  3053. /* if we are switching from ht to 2.4 clear flags
  3054. * from any ht related info since 2.4 does not
  3055. * support ht */
  3056. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  3057. priv->staging_rxon.flags = 0;
  3058. iwl_set_rxon_channel(priv, conf->channel);
  3059. iwl_set_rxon_ht(priv, ht_conf);
  3060. iwl_set_flags_for_band(priv, conf->channel->band,
  3061. priv->vif);
  3062. spin_unlock_irqrestore(&priv->lock, flags);
  3063. iwl_set_rate(priv);
  3064. /*
  3065. * at this point, staging_rxon has the
  3066. * configuration for channel switch
  3067. */
  3068. if (priv->cfg->ops->lib->set_channel_switch(priv,
  3069. ch_switch))
  3070. priv->switch_rxon.switch_in_progress = false;
  3071. }
  3072. }
  3073. out:
  3074. mutex_unlock(&priv->mutex);
  3075. out_exit:
  3076. if (!priv->switch_rxon.switch_in_progress)
  3077. ieee80211_chswitch_done(priv->vif, false);
  3078. IWL_DEBUG_MAC80211(priv, "leave\n");
  3079. }
  3080. static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
  3081. {
  3082. struct iwl_priv *priv = hw->priv;
  3083. mutex_lock(&priv->mutex);
  3084. IWL_DEBUG_MAC80211(priv, "enter\n");
  3085. /* do not support "flush" */
  3086. if (!priv->cfg->ops->lib->txfifo_flush)
  3087. goto done;
  3088. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3089. IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
  3090. goto done;
  3091. }
  3092. if (iwl_is_rfkill(priv)) {
  3093. IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
  3094. goto done;
  3095. }
  3096. /*
  3097. * mac80211 will not push any more frames for transmit
  3098. * until the flush is completed
  3099. */
  3100. if (drop) {
  3101. IWL_DEBUG_MAC80211(priv, "send flush command\n");
  3102. if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
  3103. IWL_ERR(priv, "flush request fail\n");
  3104. goto done;
  3105. }
  3106. }
  3107. IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
  3108. iwlagn_wait_tx_queue_empty(priv);
  3109. done:
  3110. mutex_unlock(&priv->mutex);
  3111. IWL_DEBUG_MAC80211(priv, "leave\n");
  3112. }
  3113. /*****************************************************************************
  3114. *
  3115. * driver setup and teardown
  3116. *
  3117. *****************************************************************************/
  3118. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  3119. {
  3120. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3121. init_waitqueue_head(&priv->wait_command_queue);
  3122. INIT_WORK(&priv->restart, iwl_bg_restart);
  3123. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  3124. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  3125. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  3126. INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
  3127. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  3128. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  3129. iwl_setup_scan_deferred_work(priv);
  3130. if (priv->cfg->ops->lib->setup_deferred_work)
  3131. priv->cfg->ops->lib->setup_deferred_work(priv);
  3132. init_timer(&priv->statistics_periodic);
  3133. priv->statistics_periodic.data = (unsigned long)priv;
  3134. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  3135. init_timer(&priv->ucode_trace);
  3136. priv->ucode_trace.data = (unsigned long)priv;
  3137. priv->ucode_trace.function = iwl_bg_ucode_trace;
  3138. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  3139. init_timer(&priv->monitor_recover);
  3140. priv->monitor_recover.data = (unsigned long)priv;
  3141. priv->monitor_recover.function =
  3142. priv->cfg->ops->lib->recover_from_tx_stall;
  3143. }
  3144. if (!priv->cfg->use_isr_legacy)
  3145. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3146. iwl_irq_tasklet, (unsigned long)priv);
  3147. else
  3148. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3149. iwl_irq_tasklet_legacy, (unsigned long)priv);
  3150. }
  3151. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  3152. {
  3153. if (priv->cfg->ops->lib->cancel_deferred_work)
  3154. priv->cfg->ops->lib->cancel_deferred_work(priv);
  3155. cancel_delayed_work_sync(&priv->init_alive_start);
  3156. cancel_delayed_work(&priv->scan_check);
  3157. cancel_work_sync(&priv->start_internal_scan);
  3158. cancel_delayed_work(&priv->alive_start);
  3159. cancel_work_sync(&priv->run_time_calib_work);
  3160. cancel_work_sync(&priv->beacon_update);
  3161. del_timer_sync(&priv->statistics_periodic);
  3162. del_timer_sync(&priv->ucode_trace);
  3163. if (priv->cfg->ops->lib->recover_from_tx_stall)
  3164. del_timer_sync(&priv->monitor_recover);
  3165. }
  3166. static void iwl_init_hw_rates(struct iwl_priv *priv,
  3167. struct ieee80211_rate *rates)
  3168. {
  3169. int i;
  3170. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  3171. rates[i].bitrate = iwl_rates[i].ieee * 5;
  3172. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3173. rates[i].hw_value_short = i;
  3174. rates[i].flags = 0;
  3175. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  3176. /*
  3177. * If CCK != 1M then set short preamble rate flag.
  3178. */
  3179. rates[i].flags |=
  3180. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  3181. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3182. }
  3183. }
  3184. }
  3185. static int iwl_init_drv(struct iwl_priv *priv)
  3186. {
  3187. int ret;
  3188. priv->ibss_beacon = NULL;
  3189. spin_lock_init(&priv->sta_lock);
  3190. spin_lock_init(&priv->hcmd_lock);
  3191. INIT_LIST_HEAD(&priv->free_frames);
  3192. mutex_init(&priv->mutex);
  3193. mutex_init(&priv->sync_cmd_mutex);
  3194. priv->ieee_channels = NULL;
  3195. priv->ieee_rates = NULL;
  3196. priv->band = IEEE80211_BAND_2GHZ;
  3197. priv->iw_mode = NL80211_IFTYPE_STATION;
  3198. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  3199. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3200. priv->_agn.agg_tids_count = 0;
  3201. /* initialize force reset */
  3202. priv->force_reset[IWL_RF_RESET].reset_duration =
  3203. IWL_DELAY_NEXT_FORCE_RF_RESET;
  3204. priv->force_reset[IWL_FW_RESET].reset_duration =
  3205. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  3206. /* Choose which receivers/antennas to use */
  3207. if (priv->cfg->ops->hcmd->set_rxon_chain)
  3208. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  3209. iwl_init_scan_params(priv);
  3210. /* Set the tx_power_user_lmt to the lowest power level
  3211. * this value will get overwritten by channel max power avg
  3212. * from eeprom */
  3213. priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  3214. ret = iwl_init_channel_map(priv);
  3215. if (ret) {
  3216. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3217. goto err;
  3218. }
  3219. ret = iwlcore_init_geos(priv);
  3220. if (ret) {
  3221. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3222. goto err_free_channel_map;
  3223. }
  3224. iwl_init_hw_rates(priv, priv->ieee_rates);
  3225. return 0;
  3226. err_free_channel_map:
  3227. iwl_free_channel_map(priv);
  3228. err:
  3229. return ret;
  3230. }
  3231. static void iwl_uninit_drv(struct iwl_priv *priv)
  3232. {
  3233. iwl_calib_free_results(priv);
  3234. iwlcore_free_geos(priv);
  3235. iwl_free_channel_map(priv);
  3236. kfree(priv->scan_cmd);
  3237. }
  3238. static struct ieee80211_ops iwl_hw_ops = {
  3239. .tx = iwl_mac_tx,
  3240. .start = iwl_mac_start,
  3241. .stop = iwl_mac_stop,
  3242. .add_interface = iwl_mac_add_interface,
  3243. .remove_interface = iwl_mac_remove_interface,
  3244. .config = iwl_mac_config,
  3245. .configure_filter = iwl_configure_filter,
  3246. .set_key = iwl_mac_set_key,
  3247. .update_tkip_key = iwl_mac_update_tkip_key,
  3248. .conf_tx = iwl_mac_conf_tx,
  3249. .reset_tsf = iwl_mac_reset_tsf,
  3250. .bss_info_changed = iwl_bss_info_changed,
  3251. .ampdu_action = iwl_mac_ampdu_action,
  3252. .hw_scan = iwl_mac_hw_scan,
  3253. .sta_notify = iwl_mac_sta_notify,
  3254. .sta_add = iwlagn_mac_sta_add,
  3255. .sta_remove = iwl_mac_sta_remove,
  3256. .channel_switch = iwl_mac_channel_switch,
  3257. .flush = iwl_mac_flush,
  3258. };
  3259. static void iwl_hw_detect(struct iwl_priv *priv)
  3260. {
  3261. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  3262. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  3263. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  3264. }
  3265. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3266. {
  3267. int err = 0;
  3268. struct iwl_priv *priv;
  3269. struct ieee80211_hw *hw;
  3270. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3271. unsigned long flags;
  3272. u16 pci_cmd, num_mac;
  3273. /************************
  3274. * 1. Allocating HW data
  3275. ************************/
  3276. /* Disabling hardware scan means that mac80211 will perform scans
  3277. * "the hard way", rather than using device's scan. */
  3278. if (cfg->mod_params->disable_hw_scan) {
  3279. if (iwl_debug_level & IWL_DL_INFO)
  3280. dev_printk(KERN_DEBUG, &(pdev->dev),
  3281. "Disabling hw_scan\n");
  3282. iwl_hw_ops.hw_scan = NULL;
  3283. }
  3284. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  3285. if (!hw) {
  3286. err = -ENOMEM;
  3287. goto out;
  3288. }
  3289. priv = hw->priv;
  3290. /* At this point both hw and priv are allocated. */
  3291. SET_IEEE80211_DEV(hw, &pdev->dev);
  3292. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3293. priv->cfg = cfg;
  3294. priv->pci_dev = pdev;
  3295. priv->inta_mask = CSR_INI_SET_MASK;
  3296. if (iwl_alloc_traffic_mem(priv))
  3297. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3298. /**************************
  3299. * 2. Initializing PCI bus
  3300. **************************/
  3301. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3302. PCIE_LINK_STATE_CLKPM);
  3303. if (pci_enable_device(pdev)) {
  3304. err = -ENODEV;
  3305. goto out_ieee80211_free_hw;
  3306. }
  3307. pci_set_master(pdev);
  3308. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  3309. if (!err)
  3310. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  3311. if (err) {
  3312. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3313. if (!err)
  3314. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3315. /* both attempts failed: */
  3316. if (err) {
  3317. IWL_WARN(priv, "No suitable DMA available.\n");
  3318. goto out_pci_disable_device;
  3319. }
  3320. }
  3321. err = pci_request_regions(pdev, DRV_NAME);
  3322. if (err)
  3323. goto out_pci_disable_device;
  3324. pci_set_drvdata(pdev, priv);
  3325. /***********************
  3326. * 3. Read REV register
  3327. ***********************/
  3328. priv->hw_base = pci_iomap(pdev, 0, 0);
  3329. if (!priv->hw_base) {
  3330. err = -ENODEV;
  3331. goto out_pci_release_regions;
  3332. }
  3333. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3334. (unsigned long long) pci_resource_len(pdev, 0));
  3335. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3336. /* these spin locks will be used in apm_ops.init and EEPROM access
  3337. * we should init now
  3338. */
  3339. spin_lock_init(&priv->reg_lock);
  3340. spin_lock_init(&priv->lock);
  3341. /*
  3342. * stop and reset the on-board processor just in case it is in a
  3343. * strange state ... like being left stranded by a primary kernel
  3344. * and this is now the kdump kernel trying to start up
  3345. */
  3346. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3347. iwl_hw_detect(priv);
  3348. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3349. priv->cfg->name, priv->hw_rev);
  3350. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3351. * PCI Tx retries from interfering with C3 CPU state */
  3352. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3353. iwl_prepare_card_hw(priv);
  3354. if (!priv->hw_ready) {
  3355. IWL_WARN(priv, "Failed, HW not ready\n");
  3356. goto out_iounmap;
  3357. }
  3358. /*****************
  3359. * 4. Read EEPROM
  3360. *****************/
  3361. /* Read the EEPROM */
  3362. err = iwl_eeprom_init(priv);
  3363. if (err) {
  3364. IWL_ERR(priv, "Unable to init EEPROM\n");
  3365. goto out_iounmap;
  3366. }
  3367. err = iwl_eeprom_check_version(priv);
  3368. if (err)
  3369. goto out_free_eeprom;
  3370. /* extract MAC Address */
  3371. iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
  3372. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
  3373. priv->hw->wiphy->addresses = priv->addresses;
  3374. priv->hw->wiphy->n_addresses = 1;
  3375. num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
  3376. if (num_mac > 1) {
  3377. memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
  3378. ETH_ALEN);
  3379. priv->addresses[1].addr[5]++;
  3380. priv->hw->wiphy->n_addresses++;
  3381. }
  3382. /************************
  3383. * 5. Setup HW constants
  3384. ************************/
  3385. if (iwl_set_hw_params(priv)) {
  3386. IWL_ERR(priv, "failed to set hw parameters\n");
  3387. goto out_free_eeprom;
  3388. }
  3389. /*******************
  3390. * 6. Setup priv
  3391. *******************/
  3392. err = iwl_init_drv(priv);
  3393. if (err)
  3394. goto out_free_eeprom;
  3395. /* At this point both hw and priv are initialized. */
  3396. /********************
  3397. * 7. Setup services
  3398. ********************/
  3399. spin_lock_irqsave(&priv->lock, flags);
  3400. iwl_disable_interrupts(priv);
  3401. spin_unlock_irqrestore(&priv->lock, flags);
  3402. pci_enable_msi(priv->pci_dev);
  3403. iwl_alloc_isr_ict(priv);
  3404. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3405. IRQF_SHARED, DRV_NAME, priv);
  3406. if (err) {
  3407. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3408. goto out_disable_msi;
  3409. }
  3410. iwl_setup_deferred_work(priv);
  3411. iwl_setup_rx_handlers(priv);
  3412. /*********************************************
  3413. * 8. Enable interrupts and read RFKILL state
  3414. *********************************************/
  3415. /* enable interrupts if needed: hw bug w/a */
  3416. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3417. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3418. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3419. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3420. }
  3421. iwl_enable_interrupts(priv);
  3422. /* If platform's RF_KILL switch is NOT set to KILL */
  3423. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3424. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3425. else
  3426. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3427. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3428. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3429. iwl_power_initialize(priv);
  3430. iwl_tt_initialize(priv);
  3431. init_completion(&priv->_agn.firmware_loading_complete);
  3432. err = iwl_request_firmware(priv, true);
  3433. if (err)
  3434. goto out_destroy_workqueue;
  3435. return 0;
  3436. out_destroy_workqueue:
  3437. destroy_workqueue(priv->workqueue);
  3438. priv->workqueue = NULL;
  3439. free_irq(priv->pci_dev->irq, priv);
  3440. iwl_free_isr_ict(priv);
  3441. out_disable_msi:
  3442. pci_disable_msi(priv->pci_dev);
  3443. iwl_uninit_drv(priv);
  3444. out_free_eeprom:
  3445. iwl_eeprom_free(priv);
  3446. out_iounmap:
  3447. pci_iounmap(pdev, priv->hw_base);
  3448. out_pci_release_regions:
  3449. pci_set_drvdata(pdev, NULL);
  3450. pci_release_regions(pdev);
  3451. out_pci_disable_device:
  3452. pci_disable_device(pdev);
  3453. out_ieee80211_free_hw:
  3454. iwl_free_traffic_mem(priv);
  3455. ieee80211_free_hw(priv->hw);
  3456. out:
  3457. return err;
  3458. }
  3459. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3460. {
  3461. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3462. unsigned long flags;
  3463. if (!priv)
  3464. return;
  3465. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3466. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3467. iwl_dbgfs_unregister(priv);
  3468. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3469. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3470. * to be called and iwl_down since we are removing the device
  3471. * we need to set STATUS_EXIT_PENDING bit.
  3472. */
  3473. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3474. if (priv->mac80211_registered) {
  3475. ieee80211_unregister_hw(priv->hw);
  3476. priv->mac80211_registered = 0;
  3477. } else {
  3478. iwl_down(priv);
  3479. }
  3480. /*
  3481. * Make sure device is reset to low power before unloading driver.
  3482. * This may be redundant with iwl_down(), but there are paths to
  3483. * run iwl_down() without calling apm_ops.stop(), and there are
  3484. * paths to avoid running iwl_down() at all before leaving driver.
  3485. * This (inexpensive) call *makes sure* device is reset.
  3486. */
  3487. priv->cfg->ops->lib->apm_ops.stop(priv);
  3488. iwl_tt_exit(priv);
  3489. /* make sure we flush any pending irq or
  3490. * tasklet for the driver
  3491. */
  3492. spin_lock_irqsave(&priv->lock, flags);
  3493. iwl_disable_interrupts(priv);
  3494. spin_unlock_irqrestore(&priv->lock, flags);
  3495. iwl_synchronize_irq(priv);
  3496. iwl_dealloc_ucode_pci(priv);
  3497. if (priv->rxq.bd)
  3498. iwlagn_rx_queue_free(priv, &priv->rxq);
  3499. iwlagn_hw_txq_ctx_free(priv);
  3500. iwl_eeprom_free(priv);
  3501. /*netif_stop_queue(dev); */
  3502. flush_workqueue(priv->workqueue);
  3503. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3504. * priv->workqueue... so we can't take down the workqueue
  3505. * until now... */
  3506. destroy_workqueue(priv->workqueue);
  3507. priv->workqueue = NULL;
  3508. iwl_free_traffic_mem(priv);
  3509. free_irq(priv->pci_dev->irq, priv);
  3510. pci_disable_msi(priv->pci_dev);
  3511. pci_iounmap(pdev, priv->hw_base);
  3512. pci_release_regions(pdev);
  3513. pci_disable_device(pdev);
  3514. pci_set_drvdata(pdev, NULL);
  3515. iwl_uninit_drv(priv);
  3516. iwl_free_isr_ict(priv);
  3517. if (priv->ibss_beacon)
  3518. dev_kfree_skb(priv->ibss_beacon);
  3519. ieee80211_free_hw(priv->hw);
  3520. }
  3521. /*****************************************************************************
  3522. *
  3523. * driver and module entry point
  3524. *
  3525. *****************************************************************************/
  3526. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3527. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3528. #ifdef CONFIG_IWL4965
  3529. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3530. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3531. #endif /* CONFIG_IWL4965 */
  3532. #ifdef CONFIG_IWL5000
  3533. /* 5100 Series WiFi */
  3534. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3535. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3536. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3537. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3538. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3539. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3540. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3541. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3542. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3543. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3544. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3545. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3546. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3547. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3548. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3549. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3550. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3551. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3552. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3553. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3554. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3555. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3556. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3557. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3558. /* 5300 Series WiFi */
  3559. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3560. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3561. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3562. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3563. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3564. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3565. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3566. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3567. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3568. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3569. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3570. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3571. /* 5350 Series WiFi/WiMax */
  3572. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3573. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3574. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3575. /* 5150 Series Wifi/WiMax */
  3576. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3577. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3578. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3579. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3580. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3581. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3582. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3583. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3584. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3585. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3586. /* 6x00 Series */
  3587. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3588. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3589. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3590. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3591. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3592. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3593. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3594. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3595. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3596. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3597. /* 6x00 Series Gen2a */
  3598. {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
  3599. {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
  3600. {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
  3601. {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
  3602. {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
  3603. {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
  3604. {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
  3605. {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
  3606. {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
  3607. {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
  3608. {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
  3609. {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
  3610. {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
  3611. {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
  3612. /* 6x00 Series Gen2b */
  3613. {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
  3614. {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
  3615. {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
  3616. {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
  3617. {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
  3618. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3619. {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
  3620. {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
  3621. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3622. {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
  3623. {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
  3624. {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
  3625. {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
  3626. {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
  3627. {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
  3628. {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
  3629. {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
  3630. {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
  3631. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3632. {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
  3633. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3634. {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
  3635. {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
  3636. {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
  3637. {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
  3638. {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
  3639. {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
  3640. {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
  3641. /* 6x50 WiFi/WiMax Series */
  3642. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3643. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3644. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3645. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3646. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3647. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3648. /* 6x50 WiFi/WiMax Series Gen2 */
  3649. {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
  3650. {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
  3651. {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
  3652. {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
  3653. {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
  3654. {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
  3655. /* 1000 Series WiFi */
  3656. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3657. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3658. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3659. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3660. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3661. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3662. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3663. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3664. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3665. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3666. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3667. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3668. #endif /* CONFIG_IWL5000 */
  3669. {0}
  3670. };
  3671. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3672. static struct pci_driver iwl_driver = {
  3673. .name = DRV_NAME,
  3674. .id_table = iwl_hw_card_ids,
  3675. .probe = iwl_pci_probe,
  3676. .remove = __devexit_p(iwl_pci_remove),
  3677. #ifdef CONFIG_PM
  3678. .suspend = iwl_pci_suspend,
  3679. .resume = iwl_pci_resume,
  3680. #endif
  3681. };
  3682. static int __init iwl_init(void)
  3683. {
  3684. int ret;
  3685. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3686. pr_info(DRV_COPYRIGHT "\n");
  3687. ret = iwlagn_rate_control_register();
  3688. if (ret) {
  3689. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3690. return ret;
  3691. }
  3692. ret = pci_register_driver(&iwl_driver);
  3693. if (ret) {
  3694. pr_err("Unable to initialize PCI module\n");
  3695. goto error_register;
  3696. }
  3697. return ret;
  3698. error_register:
  3699. iwlagn_rate_control_unregister();
  3700. return ret;
  3701. }
  3702. static void __exit iwl_exit(void)
  3703. {
  3704. pci_unregister_driver(&iwl_driver);
  3705. iwlagn_rate_control_unregister();
  3706. }
  3707. module_exit(iwl_exit);
  3708. module_init(iwl_init);
  3709. #ifdef CONFIG_IWLWIFI_DEBUG
  3710. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3711. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3712. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3713. MODULE_PARM_DESC(debug, "debug output mask");
  3714. #endif
  3715. module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
  3716. MODULE_PARM_DESC(swcrypto50,
  3717. "using crypto in software (default 0 [hardware]) (deprecated)");
  3718. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3719. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3720. module_param_named(queues_num50,
  3721. iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3722. MODULE_PARM_DESC(queues_num50,
  3723. "number of hw queues in 50xx series (deprecated)");
  3724. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3725. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3726. module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3727. MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
  3728. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3729. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3730. module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
  3731. int, S_IRUGO);
  3732. MODULE_PARM_DESC(amsdu_size_8K50,
  3733. "enable 8K amsdu size in 50XX series (deprecated)");
  3734. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3735. int, S_IRUGO);
  3736. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3737. module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3738. MODULE_PARM_DESC(fw_restart50,
  3739. "restart firmware in case of error (deprecated)");
  3740. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3741. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3742. module_param_named(
  3743. disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
  3744. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3745. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3746. S_IRUGO);
  3747. MODULE_PARM_DESC(ucode_alternative,
  3748. "specify ucode alternative to use from ucode file");