radeon_legacy_encoders.c 51 KB

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  1. /*
  2. * Copyright 2007-8 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice shall be included in
  13. * all copies or substantial portions of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21. * OTHER DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors: Dave Airlie
  24. * Alex Deucher
  25. */
  26. #include "drmP.h"
  27. #include "drm_crtc_helper.h"
  28. #include "radeon_drm.h"
  29. #include "radeon.h"
  30. #include "atom.h"
  31. #include <linux/backlight.h>
  32. #ifdef CONFIG_PMAC_BACKLIGHT
  33. #include <asm/backlight.h>
  34. #endif
  35. static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  36. {
  37. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  38. struct drm_encoder_helper_funcs *encoder_funcs;
  39. encoder_funcs = encoder->helper_private;
  40. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  41. radeon_encoder->active_device = 0;
  42. }
  43. static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
  44. {
  45. struct drm_device *dev = encoder->dev;
  46. struct radeon_device *rdev = dev->dev_private;
  47. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  48. uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  49. int panel_pwr_delay = 2000;
  50. bool is_mac = false;
  51. uint8_t backlight_level;
  52. DRM_DEBUG_KMS("\n");
  53. lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  54. backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
  55. if (radeon_encoder->enc_priv) {
  56. if (rdev->is_atom_bios) {
  57. struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  58. panel_pwr_delay = lvds->panel_pwr_delay;
  59. if (lvds->bl_dev)
  60. backlight_level = lvds->backlight_level;
  61. } else {
  62. struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  63. panel_pwr_delay = lvds->panel_pwr_delay;
  64. if (lvds->bl_dev)
  65. backlight_level = lvds->backlight_level;
  66. }
  67. }
  68. /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
  69. * Taken from radeonfb.
  70. */
  71. if ((rdev->mode_info.connector_table == CT_IBOOK) ||
  72. (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
  73. (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
  74. (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
  75. is_mac = true;
  76. switch (mode) {
  77. case DRM_MODE_DPMS_ON:
  78. disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  79. disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  80. WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  81. lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  82. lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  83. WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  84. mdelay(1);
  85. lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  86. lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  87. WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  88. lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
  89. RADEON_LVDS_BL_MOD_LEVEL_MASK);
  90. lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
  91. RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
  92. (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
  93. if (is_mac)
  94. lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
  95. mdelay(panel_pwr_delay);
  96. WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  97. break;
  98. case DRM_MODE_DPMS_STANDBY:
  99. case DRM_MODE_DPMS_SUSPEND:
  100. case DRM_MODE_DPMS_OFF:
  101. pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  102. WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  103. lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  104. if (is_mac) {
  105. lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
  106. WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  107. lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
  108. } else {
  109. WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  110. lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
  111. }
  112. mdelay(panel_pwr_delay);
  113. WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  114. WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  115. mdelay(panel_pwr_delay);
  116. break;
  117. }
  118. if (rdev->is_atom_bios)
  119. radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  120. else
  121. radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  122. }
  123. static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  124. {
  125. struct radeon_device *rdev = encoder->dev->dev_private;
  126. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  127. DRM_DEBUG("\n");
  128. if (radeon_encoder->enc_priv) {
  129. if (rdev->is_atom_bios) {
  130. struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  131. lvds->dpms_mode = mode;
  132. } else {
  133. struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  134. lvds->dpms_mode = mode;
  135. }
  136. }
  137. radeon_legacy_lvds_update(encoder, mode);
  138. }
  139. static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
  140. {
  141. struct radeon_device *rdev = encoder->dev->dev_private;
  142. if (rdev->is_atom_bios)
  143. radeon_atom_output_lock(encoder, true);
  144. else
  145. radeon_combios_output_lock(encoder, true);
  146. radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
  147. }
  148. static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
  149. {
  150. struct radeon_device *rdev = encoder->dev->dev_private;
  151. radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
  152. if (rdev->is_atom_bios)
  153. radeon_atom_output_lock(encoder, false);
  154. else
  155. radeon_combios_output_lock(encoder, false);
  156. }
  157. static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
  158. struct drm_display_mode *mode,
  159. struct drm_display_mode *adjusted_mode)
  160. {
  161. struct drm_device *dev = encoder->dev;
  162. struct radeon_device *rdev = dev->dev_private;
  163. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  164. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  165. uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
  166. DRM_DEBUG_KMS("\n");
  167. lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  168. lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
  169. lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
  170. if (rdev->is_atom_bios) {
  171. /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
  172. * need to call that on resume to set up the reg properly.
  173. */
  174. radeon_encoder->pixel_clock = adjusted_mode->clock;
  175. atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
  176. lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  177. } else {
  178. struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
  179. if (lvds) {
  180. DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
  181. lvds_gen_cntl = lvds->lvds_gen_cntl;
  182. lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
  183. (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
  184. lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
  185. (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
  186. } else
  187. lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  188. }
  189. lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  190. lvds_gen_cntl &= ~(RADEON_LVDS_ON |
  191. RADEON_LVDS_BLON |
  192. RADEON_LVDS_EN |
  193. RADEON_LVDS_RST_FM);
  194. if (ASIC_IS_R300(rdev))
  195. lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
  196. if (radeon_crtc->crtc_id == 0) {
  197. if (ASIC_IS_R300(rdev)) {
  198. if (radeon_encoder->rmx_type != RMX_OFF)
  199. lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
  200. } else
  201. lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
  202. } else {
  203. if (ASIC_IS_R300(rdev))
  204. lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
  205. else
  206. lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
  207. }
  208. WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  209. WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  210. WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
  211. if (rdev->family == CHIP_RV410)
  212. WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
  213. if (rdev->is_atom_bios)
  214. radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  215. else
  216. radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  217. }
  218. static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
  219. const struct drm_display_mode *mode,
  220. struct drm_display_mode *adjusted_mode)
  221. {
  222. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  223. /* set the active encoder to connector routing */
  224. radeon_encoder_set_active_device(encoder);
  225. drm_mode_set_crtcinfo(adjusted_mode, 0);
  226. /* get the native mode for LVDS */
  227. if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  228. radeon_panel_mode_fixup(encoder, adjusted_mode);
  229. return true;
  230. }
  231. static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
  232. .dpms = radeon_legacy_lvds_dpms,
  233. .mode_fixup = radeon_legacy_mode_fixup,
  234. .prepare = radeon_legacy_lvds_prepare,
  235. .mode_set = radeon_legacy_lvds_mode_set,
  236. .commit = radeon_legacy_lvds_commit,
  237. .disable = radeon_legacy_encoder_disable,
  238. };
  239. #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
  240. static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
  241. {
  242. struct radeon_backlight_privdata *pdata = bl_get_data(bd);
  243. uint8_t level;
  244. /* Convert brightness to hardware level */
  245. if (bd->props.brightness < 0)
  246. level = 0;
  247. else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
  248. level = RADEON_MAX_BL_LEVEL;
  249. else
  250. level = bd->props.brightness;
  251. if (pdata->negative)
  252. level = RADEON_MAX_BL_LEVEL - level;
  253. return level;
  254. }
  255. void
  256. radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  257. {
  258. struct drm_device *dev = radeon_encoder->base.dev;
  259. struct radeon_device *rdev = dev->dev_private;
  260. int dpms_mode = DRM_MODE_DPMS_ON;
  261. if (radeon_encoder->enc_priv) {
  262. if (rdev->is_atom_bios) {
  263. struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  264. if (lvds->backlight_level > 0)
  265. dpms_mode = lvds->dpms_mode;
  266. else
  267. dpms_mode = DRM_MODE_DPMS_OFF;
  268. lvds->backlight_level = level;
  269. } else {
  270. struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  271. if (lvds->backlight_level > 0)
  272. dpms_mode = lvds->dpms_mode;
  273. else
  274. dpms_mode = DRM_MODE_DPMS_OFF;
  275. lvds->backlight_level = level;
  276. }
  277. }
  278. radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
  279. }
  280. static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
  281. {
  282. struct radeon_backlight_privdata *pdata = bl_get_data(bd);
  283. struct radeon_encoder *radeon_encoder = pdata->encoder;
  284. radeon_legacy_set_backlight_level(radeon_encoder,
  285. radeon_legacy_lvds_level(bd));
  286. return 0;
  287. }
  288. static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
  289. {
  290. struct radeon_backlight_privdata *pdata = bl_get_data(bd);
  291. struct radeon_encoder *radeon_encoder = pdata->encoder;
  292. struct drm_device *dev = radeon_encoder->base.dev;
  293. struct radeon_device *rdev = dev->dev_private;
  294. uint8_t backlight_level;
  295. backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
  296. RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
  297. return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
  298. }
  299. static const struct backlight_ops radeon_backlight_ops = {
  300. .get_brightness = radeon_legacy_backlight_get_brightness,
  301. .update_status = radeon_legacy_backlight_update_status,
  302. };
  303. void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
  304. struct drm_connector *drm_connector)
  305. {
  306. struct drm_device *dev = radeon_encoder->base.dev;
  307. struct radeon_device *rdev = dev->dev_private;
  308. struct backlight_device *bd;
  309. struct backlight_properties props;
  310. struct radeon_backlight_privdata *pdata;
  311. uint8_t backlight_level;
  312. if (!radeon_encoder->enc_priv)
  313. return;
  314. #ifdef CONFIG_PMAC_BACKLIGHT
  315. if (!pmac_has_backlight_type("ati") &&
  316. !pmac_has_backlight_type("mnca"))
  317. return;
  318. #endif
  319. pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
  320. if (!pdata) {
  321. DRM_ERROR("Memory allocation failed\n");
  322. goto error;
  323. }
  324. memset(&props, 0, sizeof(props));
  325. props.max_brightness = RADEON_MAX_BL_LEVEL;
  326. props.type = BACKLIGHT_RAW;
  327. bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
  328. pdata, &radeon_backlight_ops, &props);
  329. if (IS_ERR(bd)) {
  330. DRM_ERROR("Backlight registration failed\n");
  331. goto error;
  332. }
  333. pdata->encoder = radeon_encoder;
  334. backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
  335. RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
  336. /* First, try to detect backlight level sense based on the assumption
  337. * that firmware set it up at full brightness
  338. */
  339. if (backlight_level == 0)
  340. pdata->negative = true;
  341. else if (backlight_level == 0xff)
  342. pdata->negative = false;
  343. else {
  344. /* XXX hack... maybe some day we can figure out in what direction
  345. * backlight should work on a given panel?
  346. */
  347. pdata->negative = (rdev->family != CHIP_RV200 &&
  348. rdev->family != CHIP_RV250 &&
  349. rdev->family != CHIP_RV280 &&
  350. rdev->family != CHIP_RV350);
  351. #ifdef CONFIG_PMAC_BACKLIGHT
  352. pdata->negative = (pdata->negative ||
  353. of_machine_is_compatible("PowerBook4,3") ||
  354. of_machine_is_compatible("PowerBook6,3") ||
  355. of_machine_is_compatible("PowerBook6,5"));
  356. #endif
  357. }
  358. if (rdev->is_atom_bios) {
  359. struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  360. lvds->bl_dev = bd;
  361. } else {
  362. struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  363. lvds->bl_dev = bd;
  364. }
  365. bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
  366. bd->props.power = FB_BLANK_UNBLANK;
  367. backlight_update_status(bd);
  368. DRM_INFO("radeon legacy LVDS backlight initialized\n");
  369. return;
  370. error:
  371. kfree(pdata);
  372. return;
  373. }
  374. static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
  375. {
  376. struct drm_device *dev = radeon_encoder->base.dev;
  377. struct radeon_device *rdev = dev->dev_private;
  378. struct backlight_device *bd = NULL;
  379. if (!radeon_encoder->enc_priv)
  380. return;
  381. if (rdev->is_atom_bios) {
  382. struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  383. bd = lvds->bl_dev;
  384. lvds->bl_dev = NULL;
  385. } else {
  386. struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  387. bd = lvds->bl_dev;
  388. lvds->bl_dev = NULL;
  389. }
  390. if (bd) {
  391. struct radeon_backlight_privdata *pdata;
  392. pdata = bl_get_data(bd);
  393. backlight_device_unregister(bd);
  394. kfree(pdata);
  395. DRM_INFO("radeon legacy LVDS backlight unloaded\n");
  396. }
  397. }
  398. #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
  399. void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
  400. {
  401. }
  402. static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
  403. {
  404. }
  405. #endif
  406. static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
  407. {
  408. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  409. if (radeon_encoder->enc_priv) {
  410. radeon_legacy_backlight_exit(radeon_encoder);
  411. kfree(radeon_encoder->enc_priv);
  412. }
  413. drm_encoder_cleanup(encoder);
  414. kfree(radeon_encoder);
  415. }
  416. static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
  417. .destroy = radeon_lvds_enc_destroy,
  418. };
  419. static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
  420. {
  421. struct drm_device *dev = encoder->dev;
  422. struct radeon_device *rdev = dev->dev_private;
  423. uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  424. uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
  425. uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  426. DRM_DEBUG_KMS("\n");
  427. switch (mode) {
  428. case DRM_MODE_DPMS_ON:
  429. crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
  430. dac_cntl &= ~RADEON_DAC_PDWN;
  431. dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
  432. RADEON_DAC_PDWN_G |
  433. RADEON_DAC_PDWN_B);
  434. break;
  435. case DRM_MODE_DPMS_STANDBY:
  436. case DRM_MODE_DPMS_SUSPEND:
  437. case DRM_MODE_DPMS_OFF:
  438. crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
  439. dac_cntl |= RADEON_DAC_PDWN;
  440. dac_macro_cntl |= (RADEON_DAC_PDWN_R |
  441. RADEON_DAC_PDWN_G |
  442. RADEON_DAC_PDWN_B);
  443. break;
  444. }
  445. WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  446. WREG32(RADEON_DAC_CNTL, dac_cntl);
  447. WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  448. if (rdev->is_atom_bios)
  449. radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  450. else
  451. radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  452. }
  453. static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
  454. {
  455. struct radeon_device *rdev = encoder->dev->dev_private;
  456. if (rdev->is_atom_bios)
  457. radeon_atom_output_lock(encoder, true);
  458. else
  459. radeon_combios_output_lock(encoder, true);
  460. radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
  461. }
  462. static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
  463. {
  464. struct radeon_device *rdev = encoder->dev->dev_private;
  465. radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
  466. if (rdev->is_atom_bios)
  467. radeon_atom_output_lock(encoder, false);
  468. else
  469. radeon_combios_output_lock(encoder, false);
  470. }
  471. static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
  472. struct drm_display_mode *mode,
  473. struct drm_display_mode *adjusted_mode)
  474. {
  475. struct drm_device *dev = encoder->dev;
  476. struct radeon_device *rdev = dev->dev_private;
  477. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  478. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  479. uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
  480. DRM_DEBUG_KMS("\n");
  481. if (radeon_crtc->crtc_id == 0) {
  482. if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
  483. disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
  484. ~(RADEON_DISP_DAC_SOURCE_MASK);
  485. WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  486. } else {
  487. dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
  488. WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  489. }
  490. } else {
  491. if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
  492. disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
  493. ~(RADEON_DISP_DAC_SOURCE_MASK);
  494. disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
  495. WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  496. } else {
  497. dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
  498. WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  499. }
  500. }
  501. dac_cntl = (RADEON_DAC_MASK_ALL |
  502. RADEON_DAC_VGA_ADR_EN |
  503. /* TODO 6-bits */
  504. RADEON_DAC_8BIT_EN);
  505. WREG32_P(RADEON_DAC_CNTL,
  506. dac_cntl,
  507. RADEON_DAC_RANGE_CNTL |
  508. RADEON_DAC_BLANKING);
  509. if (radeon_encoder->enc_priv) {
  510. struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
  511. dac_macro_cntl = p_dac->ps2_pdac_adj;
  512. } else
  513. dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  514. dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
  515. WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  516. if (rdev->is_atom_bios)
  517. radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  518. else
  519. radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  520. }
  521. static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
  522. struct drm_connector *connector)
  523. {
  524. struct drm_device *dev = encoder->dev;
  525. struct radeon_device *rdev = dev->dev_private;
  526. uint32_t vclk_ecp_cntl, crtc_ext_cntl;
  527. uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
  528. enum drm_connector_status found = connector_status_disconnected;
  529. bool color = true;
  530. /* save the regs we need */
  531. vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
  532. crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  533. dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  534. dac_cntl = RREG32(RADEON_DAC_CNTL);
  535. dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  536. tmp = vclk_ecp_cntl &
  537. ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
  538. WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
  539. tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
  540. WREG32(RADEON_CRTC_EXT_CNTL, tmp);
  541. tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
  542. RADEON_DAC_FORCE_DATA_EN;
  543. if (color)
  544. tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
  545. else
  546. tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
  547. if (ASIC_IS_R300(rdev))
  548. tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
  549. else
  550. tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
  551. WREG32(RADEON_DAC_EXT_CNTL, tmp);
  552. tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
  553. tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
  554. WREG32(RADEON_DAC_CNTL, tmp);
  555. tmp &= ~(RADEON_DAC_PDWN_R |
  556. RADEON_DAC_PDWN_G |
  557. RADEON_DAC_PDWN_B);
  558. WREG32(RADEON_DAC_MACRO_CNTL, tmp);
  559. mdelay(2);
  560. if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
  561. found = connector_status_connected;
  562. /* restore the regs we used */
  563. WREG32(RADEON_DAC_CNTL, dac_cntl);
  564. WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  565. WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  566. WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  567. WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
  568. return found;
  569. }
  570. static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
  571. .dpms = radeon_legacy_primary_dac_dpms,
  572. .mode_fixup = radeon_legacy_mode_fixup,
  573. .prepare = radeon_legacy_primary_dac_prepare,
  574. .mode_set = radeon_legacy_primary_dac_mode_set,
  575. .commit = radeon_legacy_primary_dac_commit,
  576. .detect = radeon_legacy_primary_dac_detect,
  577. .disable = radeon_legacy_encoder_disable,
  578. };
  579. static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
  580. .destroy = radeon_enc_destroy,
  581. };
  582. static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
  583. {
  584. struct drm_device *dev = encoder->dev;
  585. struct radeon_device *rdev = dev->dev_private;
  586. uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
  587. DRM_DEBUG_KMS("\n");
  588. switch (mode) {
  589. case DRM_MODE_DPMS_ON:
  590. fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  591. break;
  592. case DRM_MODE_DPMS_STANDBY:
  593. case DRM_MODE_DPMS_SUSPEND:
  594. case DRM_MODE_DPMS_OFF:
  595. fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  596. break;
  597. }
  598. WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
  599. if (rdev->is_atom_bios)
  600. radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  601. else
  602. radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  603. }
  604. static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
  605. {
  606. struct radeon_device *rdev = encoder->dev->dev_private;
  607. if (rdev->is_atom_bios)
  608. radeon_atom_output_lock(encoder, true);
  609. else
  610. radeon_combios_output_lock(encoder, true);
  611. radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
  612. }
  613. static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
  614. {
  615. struct radeon_device *rdev = encoder->dev->dev_private;
  616. radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
  617. if (rdev->is_atom_bios)
  618. radeon_atom_output_lock(encoder, true);
  619. else
  620. radeon_combios_output_lock(encoder, true);
  621. }
  622. static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
  623. struct drm_display_mode *mode,
  624. struct drm_display_mode *adjusted_mode)
  625. {
  626. struct drm_device *dev = encoder->dev;
  627. struct radeon_device *rdev = dev->dev_private;
  628. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  629. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  630. uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
  631. int i;
  632. DRM_DEBUG_KMS("\n");
  633. tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
  634. tmp &= 0xfffff;
  635. if (rdev->family == CHIP_RV280) {
  636. /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
  637. tmp ^= (1 << 22);
  638. tmds_pll_cntl ^= (1 << 22);
  639. }
  640. if (radeon_encoder->enc_priv) {
  641. struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
  642. for (i = 0; i < 4; i++) {
  643. if (tmds->tmds_pll[i].freq == 0)
  644. break;
  645. if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
  646. tmp = tmds->tmds_pll[i].value ;
  647. break;
  648. }
  649. }
  650. }
  651. if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
  652. if (tmp & 0xfff00000)
  653. tmds_pll_cntl = tmp;
  654. else {
  655. tmds_pll_cntl &= 0xfff00000;
  656. tmds_pll_cntl |= tmp;
  657. }
  658. } else
  659. tmds_pll_cntl = tmp;
  660. tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
  661. ~(RADEON_TMDS_TRANSMITTER_PLLRST);
  662. if (rdev->family == CHIP_R200 ||
  663. rdev->family == CHIP_R100 ||
  664. ASIC_IS_R300(rdev))
  665. tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
  666. else /* RV chips got this bit reversed */
  667. tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
  668. fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
  669. (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
  670. RADEON_FP_CRTC_DONT_SHADOW_HEND));
  671. fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  672. fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
  673. RADEON_FP_DFP_SYNC_SEL |
  674. RADEON_FP_CRT_SYNC_SEL |
  675. RADEON_FP_CRTC_LOCK_8DOT |
  676. RADEON_FP_USE_SHADOW_EN |
  677. RADEON_FP_CRTC_USE_SHADOW_VEND |
  678. RADEON_FP_CRT_SYNC_ALT);
  679. if (1) /* FIXME rgbBits == 8 */
  680. fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
  681. else
  682. fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
  683. if (radeon_crtc->crtc_id == 0) {
  684. if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
  685. fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
  686. if (radeon_encoder->rmx_type != RMX_OFF)
  687. fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
  688. else
  689. fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
  690. } else
  691. fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
  692. } else {
  693. if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
  694. fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
  695. fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
  696. } else
  697. fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
  698. }
  699. WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
  700. WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
  701. WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
  702. if (rdev->is_atom_bios)
  703. radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  704. else
  705. radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  706. }
  707. static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
  708. .dpms = radeon_legacy_tmds_int_dpms,
  709. .mode_fixup = radeon_legacy_mode_fixup,
  710. .prepare = radeon_legacy_tmds_int_prepare,
  711. .mode_set = radeon_legacy_tmds_int_mode_set,
  712. .commit = radeon_legacy_tmds_int_commit,
  713. .disable = radeon_legacy_encoder_disable,
  714. };
  715. static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
  716. .destroy = radeon_enc_destroy,
  717. };
  718. static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
  719. {
  720. struct drm_device *dev = encoder->dev;
  721. struct radeon_device *rdev = dev->dev_private;
  722. uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  723. DRM_DEBUG_KMS("\n");
  724. switch (mode) {
  725. case DRM_MODE_DPMS_ON:
  726. fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
  727. fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  728. break;
  729. case DRM_MODE_DPMS_STANDBY:
  730. case DRM_MODE_DPMS_SUSPEND:
  731. case DRM_MODE_DPMS_OFF:
  732. fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
  733. fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  734. break;
  735. }
  736. WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  737. if (rdev->is_atom_bios)
  738. radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  739. else
  740. radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  741. }
  742. static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
  743. {
  744. struct radeon_device *rdev = encoder->dev->dev_private;
  745. if (rdev->is_atom_bios)
  746. radeon_atom_output_lock(encoder, true);
  747. else
  748. radeon_combios_output_lock(encoder, true);
  749. radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
  750. }
  751. static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
  752. {
  753. struct radeon_device *rdev = encoder->dev->dev_private;
  754. radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
  755. if (rdev->is_atom_bios)
  756. radeon_atom_output_lock(encoder, false);
  757. else
  758. radeon_combios_output_lock(encoder, false);
  759. }
  760. static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
  761. struct drm_display_mode *mode,
  762. struct drm_display_mode *adjusted_mode)
  763. {
  764. struct drm_device *dev = encoder->dev;
  765. struct radeon_device *rdev = dev->dev_private;
  766. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  767. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  768. uint32_t fp2_gen_cntl;
  769. DRM_DEBUG_KMS("\n");
  770. if (rdev->is_atom_bios) {
  771. radeon_encoder->pixel_clock = adjusted_mode->clock;
  772. atombios_dvo_setup(encoder, ATOM_ENABLE);
  773. fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  774. } else {
  775. fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  776. if (1) /* FIXME rgbBits == 8 */
  777. fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
  778. else
  779. fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
  780. fp2_gen_cntl &= ~(RADEON_FP2_ON |
  781. RADEON_FP2_DVO_EN |
  782. RADEON_FP2_DVO_RATE_SEL_SDR);
  783. /* XXX: these are oem specific */
  784. if (ASIC_IS_R300(rdev)) {
  785. if ((dev->pdev->device == 0x4850) &&
  786. (dev->pdev->subsystem_vendor == 0x1028) &&
  787. (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
  788. fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
  789. else
  790. fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
  791. /*if (mode->clock > 165000)
  792. fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
  793. }
  794. if (!radeon_combios_external_tmds_setup(encoder))
  795. radeon_external_tmds_setup(encoder);
  796. }
  797. if (radeon_crtc->crtc_id == 0) {
  798. if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
  799. fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
  800. if (radeon_encoder->rmx_type != RMX_OFF)
  801. fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
  802. else
  803. fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
  804. } else
  805. fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
  806. } else {
  807. if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
  808. fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
  809. fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
  810. } else
  811. fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
  812. }
  813. WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  814. if (rdev->is_atom_bios)
  815. radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  816. else
  817. radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  818. }
  819. static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
  820. {
  821. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  822. struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
  823. if (tmds) {
  824. if (tmds->i2c_bus)
  825. radeon_i2c_destroy(tmds->i2c_bus);
  826. }
  827. kfree(radeon_encoder->enc_priv);
  828. drm_encoder_cleanup(encoder);
  829. kfree(radeon_encoder);
  830. }
  831. static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
  832. .dpms = radeon_legacy_tmds_ext_dpms,
  833. .mode_fixup = radeon_legacy_mode_fixup,
  834. .prepare = radeon_legacy_tmds_ext_prepare,
  835. .mode_set = radeon_legacy_tmds_ext_mode_set,
  836. .commit = radeon_legacy_tmds_ext_commit,
  837. .disable = radeon_legacy_encoder_disable,
  838. };
  839. static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
  840. .destroy = radeon_ext_tmds_enc_destroy,
  841. };
  842. static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
  843. {
  844. struct drm_device *dev = encoder->dev;
  845. struct radeon_device *rdev = dev->dev_private;
  846. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  847. uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
  848. uint32_t tv_master_cntl = 0;
  849. bool is_tv;
  850. DRM_DEBUG_KMS("\n");
  851. is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
  852. if (rdev->family == CHIP_R200)
  853. fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  854. else {
  855. if (is_tv)
  856. tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
  857. else
  858. crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  859. tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  860. }
  861. switch (mode) {
  862. case DRM_MODE_DPMS_ON:
  863. if (rdev->family == CHIP_R200) {
  864. fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  865. } else {
  866. if (is_tv)
  867. tv_master_cntl |= RADEON_TV_ON;
  868. else
  869. crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
  870. if (rdev->family == CHIP_R420 ||
  871. rdev->family == CHIP_R423 ||
  872. rdev->family == CHIP_RV410)
  873. tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
  874. R420_TV_DAC_GDACPD |
  875. R420_TV_DAC_BDACPD |
  876. RADEON_TV_DAC_BGSLEEP);
  877. else
  878. tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
  879. RADEON_TV_DAC_GDACPD |
  880. RADEON_TV_DAC_BDACPD |
  881. RADEON_TV_DAC_BGSLEEP);
  882. }
  883. break;
  884. case DRM_MODE_DPMS_STANDBY:
  885. case DRM_MODE_DPMS_SUSPEND:
  886. case DRM_MODE_DPMS_OFF:
  887. if (rdev->family == CHIP_R200)
  888. fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  889. else {
  890. if (is_tv)
  891. tv_master_cntl &= ~RADEON_TV_ON;
  892. else
  893. crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
  894. if (rdev->family == CHIP_R420 ||
  895. rdev->family == CHIP_R423 ||
  896. rdev->family == CHIP_RV410)
  897. tv_dac_cntl |= (R420_TV_DAC_RDACPD |
  898. R420_TV_DAC_GDACPD |
  899. R420_TV_DAC_BDACPD |
  900. RADEON_TV_DAC_BGSLEEP);
  901. else
  902. tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
  903. RADEON_TV_DAC_GDACPD |
  904. RADEON_TV_DAC_BDACPD |
  905. RADEON_TV_DAC_BGSLEEP);
  906. }
  907. break;
  908. }
  909. if (rdev->family == CHIP_R200) {
  910. WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  911. } else {
  912. if (is_tv)
  913. WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
  914. else
  915. WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  916. WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  917. }
  918. if (rdev->is_atom_bios)
  919. radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  920. else
  921. radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  922. }
  923. static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
  924. {
  925. struct radeon_device *rdev = encoder->dev->dev_private;
  926. if (rdev->is_atom_bios)
  927. radeon_atom_output_lock(encoder, true);
  928. else
  929. radeon_combios_output_lock(encoder, true);
  930. radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
  931. }
  932. static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
  933. {
  934. struct radeon_device *rdev = encoder->dev->dev_private;
  935. radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
  936. if (rdev->is_atom_bios)
  937. radeon_atom_output_lock(encoder, true);
  938. else
  939. radeon_combios_output_lock(encoder, true);
  940. }
  941. static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
  942. struct drm_display_mode *mode,
  943. struct drm_display_mode *adjusted_mode)
  944. {
  945. struct drm_device *dev = encoder->dev;
  946. struct radeon_device *rdev = dev->dev_private;
  947. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  948. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  949. struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  950. uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
  951. uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
  952. bool is_tv = false;
  953. DRM_DEBUG_KMS("\n");
  954. is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
  955. if (rdev->family != CHIP_R200) {
  956. tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  957. if (rdev->family == CHIP_R420 ||
  958. rdev->family == CHIP_R423 ||
  959. rdev->family == CHIP_RV410) {
  960. tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
  961. RADEON_TV_DAC_BGADJ_MASK |
  962. R420_TV_DAC_DACADJ_MASK |
  963. R420_TV_DAC_RDACPD |
  964. R420_TV_DAC_GDACPD |
  965. R420_TV_DAC_BDACPD |
  966. R420_TV_DAC_TVENABLE);
  967. } else {
  968. tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
  969. RADEON_TV_DAC_BGADJ_MASK |
  970. RADEON_TV_DAC_DACADJ_MASK |
  971. RADEON_TV_DAC_RDACPD |
  972. RADEON_TV_DAC_GDACPD |
  973. RADEON_TV_DAC_BDACPD);
  974. }
  975. tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
  976. if (is_tv) {
  977. if (tv_dac->tv_std == TV_STD_NTSC ||
  978. tv_dac->tv_std == TV_STD_NTSC_J ||
  979. tv_dac->tv_std == TV_STD_PAL_M ||
  980. tv_dac->tv_std == TV_STD_PAL_60)
  981. tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
  982. else
  983. tv_dac_cntl |= tv_dac->pal_tvdac_adj;
  984. if (tv_dac->tv_std == TV_STD_NTSC ||
  985. tv_dac->tv_std == TV_STD_NTSC_J)
  986. tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
  987. else
  988. tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
  989. } else
  990. tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
  991. tv_dac->ps2_tvdac_adj);
  992. WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  993. }
  994. if (ASIC_IS_R300(rdev)) {
  995. gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
  996. disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
  997. } else if (rdev->family != CHIP_R200)
  998. disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
  999. else if (rdev->family == CHIP_R200)
  1000. fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  1001. if (rdev->family >= CHIP_R200)
  1002. disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
  1003. if (is_tv) {
  1004. uint32_t dac_cntl;
  1005. dac_cntl = RREG32(RADEON_DAC_CNTL);
  1006. dac_cntl &= ~RADEON_DAC_TVO_EN;
  1007. WREG32(RADEON_DAC_CNTL, dac_cntl);
  1008. if (ASIC_IS_R300(rdev))
  1009. gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
  1010. dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
  1011. if (radeon_crtc->crtc_id == 0) {
  1012. if (ASIC_IS_R300(rdev)) {
  1013. disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1014. disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
  1015. RADEON_DISP_TV_SOURCE_CRTC);
  1016. }
  1017. if (rdev->family >= CHIP_R200) {
  1018. disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
  1019. } else {
  1020. disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  1021. }
  1022. } else {
  1023. if (ASIC_IS_R300(rdev)) {
  1024. disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1025. disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
  1026. }
  1027. if (rdev->family >= CHIP_R200) {
  1028. disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
  1029. } else {
  1030. disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
  1031. }
  1032. }
  1033. WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  1034. } else {
  1035. dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
  1036. if (radeon_crtc->crtc_id == 0) {
  1037. if (ASIC_IS_R300(rdev)) {
  1038. disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1039. disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
  1040. } else if (rdev->family == CHIP_R200) {
  1041. fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
  1042. RADEON_FP2_DVO_RATE_SEL_SDR);
  1043. } else
  1044. disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  1045. } else {
  1046. if (ASIC_IS_R300(rdev)) {
  1047. disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1048. disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1049. } else if (rdev->family == CHIP_R200) {
  1050. fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
  1051. RADEON_FP2_DVO_RATE_SEL_SDR);
  1052. fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
  1053. } else
  1054. disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
  1055. }
  1056. WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  1057. }
  1058. if (ASIC_IS_R300(rdev)) {
  1059. WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1060. WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1061. } else if (rdev->family != CHIP_R200)
  1062. WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  1063. else if (rdev->family == CHIP_R200)
  1064. WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  1065. if (rdev->family >= CHIP_R200)
  1066. WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
  1067. if (is_tv)
  1068. radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
  1069. if (rdev->is_atom_bios)
  1070. radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  1071. else
  1072. radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  1073. }
  1074. static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
  1075. struct drm_connector *connector)
  1076. {
  1077. struct drm_device *dev = encoder->dev;
  1078. struct radeon_device *rdev = dev->dev_private;
  1079. uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
  1080. uint32_t disp_output_cntl, gpiopad_a, tmp;
  1081. bool found = false;
  1082. /* save regs needed */
  1083. gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  1084. dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1085. crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1086. dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  1087. tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1088. disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
  1089. WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
  1090. WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
  1091. WREG32(RADEON_CRTC2_GEN_CNTL,
  1092. RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
  1093. tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1094. tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1095. WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
  1096. WREG32(RADEON_DAC_EXT_CNTL,
  1097. RADEON_DAC2_FORCE_BLANK_OFF_EN |
  1098. RADEON_DAC2_FORCE_DATA_EN |
  1099. RADEON_DAC_FORCE_DATA_SEL_RGB |
  1100. (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
  1101. WREG32(RADEON_TV_DAC_CNTL,
  1102. RADEON_TV_DAC_STD_NTSC |
  1103. (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
  1104. (6 << RADEON_TV_DAC_DACADJ_SHIFT));
  1105. RREG32(RADEON_TV_DAC_CNTL);
  1106. mdelay(4);
  1107. WREG32(RADEON_TV_DAC_CNTL,
  1108. RADEON_TV_DAC_NBLANK |
  1109. RADEON_TV_DAC_NHOLD |
  1110. RADEON_TV_MONITOR_DETECT_EN |
  1111. RADEON_TV_DAC_STD_NTSC |
  1112. (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
  1113. (6 << RADEON_TV_DAC_DACADJ_SHIFT));
  1114. RREG32(RADEON_TV_DAC_CNTL);
  1115. mdelay(6);
  1116. tmp = RREG32(RADEON_TV_DAC_CNTL);
  1117. if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
  1118. found = true;
  1119. DRM_DEBUG_KMS("S-video TV connection detected\n");
  1120. } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
  1121. found = true;
  1122. DRM_DEBUG_KMS("Composite TV connection detected\n");
  1123. }
  1124. WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1125. WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  1126. WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1127. WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1128. WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1129. WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1130. return found;
  1131. }
  1132. static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
  1133. struct drm_connector *connector)
  1134. {
  1135. struct drm_device *dev = encoder->dev;
  1136. struct radeon_device *rdev = dev->dev_private;
  1137. uint32_t tv_dac_cntl, dac_cntl2;
  1138. uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
  1139. bool found = false;
  1140. if (ASIC_IS_R300(rdev))
  1141. return r300_legacy_tv_detect(encoder, connector);
  1142. dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1143. tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
  1144. tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1145. config_cntl = RREG32(RADEON_CONFIG_CNTL);
  1146. tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
  1147. tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
  1148. WREG32(RADEON_DAC_CNTL2, tmp);
  1149. tmp = tv_master_cntl | RADEON_TV_ON;
  1150. tmp &= ~(RADEON_TV_ASYNC_RST |
  1151. RADEON_RESTART_PHASE_FIX |
  1152. RADEON_CRT_FIFO_CE_EN |
  1153. RADEON_TV_FIFO_CE_EN |
  1154. RADEON_RE_SYNC_NOW_SEL_MASK);
  1155. tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
  1156. WREG32(RADEON_TV_MASTER_CNTL, tmp);
  1157. tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
  1158. RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
  1159. (8 << RADEON_TV_DAC_BGADJ_SHIFT);
  1160. if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
  1161. tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
  1162. else
  1163. tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
  1164. WREG32(RADEON_TV_DAC_CNTL, tmp);
  1165. tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
  1166. RADEON_RED_MX_FORCE_DAC_DATA |
  1167. RADEON_GRN_MX_FORCE_DAC_DATA |
  1168. RADEON_BLU_MX_FORCE_DAC_DATA |
  1169. (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
  1170. WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
  1171. mdelay(3);
  1172. tmp = RREG32(RADEON_TV_DAC_CNTL);
  1173. if (tmp & RADEON_TV_DAC_GDACDET) {
  1174. found = true;
  1175. DRM_DEBUG_KMS("S-video TV connection detected\n");
  1176. } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
  1177. found = true;
  1178. DRM_DEBUG_KMS("Composite TV connection detected\n");
  1179. }
  1180. WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
  1181. WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1182. WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
  1183. WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1184. return found;
  1185. }
  1186. static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
  1187. struct drm_connector *connector)
  1188. {
  1189. struct drm_device *dev = encoder->dev;
  1190. struct radeon_device *rdev = dev->dev_private;
  1191. uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
  1192. uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
  1193. enum drm_connector_status found = connector_status_disconnected;
  1194. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1195. struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  1196. bool color = true;
  1197. struct drm_crtc *crtc;
  1198. /* find out if crtc2 is in use or if this encoder is using it */
  1199. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1200. struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  1201. if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
  1202. if (encoder->crtc != crtc) {
  1203. return connector_status_disconnected;
  1204. }
  1205. }
  1206. }
  1207. if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
  1208. connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
  1209. connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
  1210. bool tv_detect;
  1211. if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
  1212. return connector_status_disconnected;
  1213. tv_detect = radeon_legacy_tv_detect(encoder, connector);
  1214. if (tv_detect && tv_dac)
  1215. found = connector_status_connected;
  1216. return found;
  1217. }
  1218. /* don't probe if the encoder is being used for something else not CRT related */
  1219. if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
  1220. DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
  1221. return connector_status_disconnected;
  1222. }
  1223. /* save the regs we need */
  1224. pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  1225. gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
  1226. disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
  1227. disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
  1228. crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1229. tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1230. dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  1231. dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1232. tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
  1233. | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
  1234. WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
  1235. if (ASIC_IS_R300(rdev))
  1236. WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
  1237. tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
  1238. tmp |= RADEON_CRTC2_CRT2_ON |
  1239. (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
  1240. WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
  1241. if (ASIC_IS_R300(rdev)) {
  1242. tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1243. tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1244. WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
  1245. } else {
  1246. tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
  1247. WREG32(RADEON_DISP_HW_DEBUG, tmp);
  1248. }
  1249. tmp = RADEON_TV_DAC_NBLANK |
  1250. RADEON_TV_DAC_NHOLD |
  1251. RADEON_TV_MONITOR_DETECT_EN |
  1252. RADEON_TV_DAC_STD_PS2;
  1253. WREG32(RADEON_TV_DAC_CNTL, tmp);
  1254. tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
  1255. RADEON_DAC2_FORCE_DATA_EN;
  1256. if (color)
  1257. tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
  1258. else
  1259. tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
  1260. if (ASIC_IS_R300(rdev))
  1261. tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
  1262. else
  1263. tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
  1264. WREG32(RADEON_DAC_EXT_CNTL, tmp);
  1265. tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
  1266. WREG32(RADEON_DAC_CNTL2, tmp);
  1267. mdelay(10);
  1268. if (ASIC_IS_R300(rdev)) {
  1269. if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
  1270. found = connector_status_connected;
  1271. } else {
  1272. if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
  1273. found = connector_status_connected;
  1274. }
  1275. /* restore regs we used */
  1276. WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1277. WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  1278. WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1279. WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1280. if (ASIC_IS_R300(rdev)) {
  1281. WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1282. WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1283. } else {
  1284. WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  1285. }
  1286. WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  1287. return found;
  1288. }
  1289. static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
  1290. .dpms = radeon_legacy_tv_dac_dpms,
  1291. .mode_fixup = radeon_legacy_mode_fixup,
  1292. .prepare = radeon_legacy_tv_dac_prepare,
  1293. .mode_set = radeon_legacy_tv_dac_mode_set,
  1294. .commit = radeon_legacy_tv_dac_commit,
  1295. .detect = radeon_legacy_tv_dac_detect,
  1296. .disable = radeon_legacy_encoder_disable,
  1297. };
  1298. static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
  1299. .destroy = radeon_enc_destroy,
  1300. };
  1301. static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
  1302. {
  1303. struct drm_device *dev = encoder->base.dev;
  1304. struct radeon_device *rdev = dev->dev_private;
  1305. struct radeon_encoder_int_tmds *tmds = NULL;
  1306. bool ret;
  1307. tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
  1308. if (!tmds)
  1309. return NULL;
  1310. if (rdev->is_atom_bios)
  1311. ret = radeon_atombios_get_tmds_info(encoder, tmds);
  1312. else
  1313. ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
  1314. if (ret == false)
  1315. radeon_legacy_get_tmds_info_from_table(encoder, tmds);
  1316. return tmds;
  1317. }
  1318. static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
  1319. {
  1320. struct drm_device *dev = encoder->base.dev;
  1321. struct radeon_device *rdev = dev->dev_private;
  1322. struct radeon_encoder_ext_tmds *tmds = NULL;
  1323. bool ret;
  1324. if (rdev->is_atom_bios)
  1325. return NULL;
  1326. tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
  1327. if (!tmds)
  1328. return NULL;
  1329. ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
  1330. if (ret == false)
  1331. radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
  1332. return tmds;
  1333. }
  1334. void
  1335. radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
  1336. {
  1337. struct radeon_device *rdev = dev->dev_private;
  1338. struct drm_encoder *encoder;
  1339. struct radeon_encoder *radeon_encoder;
  1340. /* see if we already added it */
  1341. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1342. radeon_encoder = to_radeon_encoder(encoder);
  1343. if (radeon_encoder->encoder_enum == encoder_enum) {
  1344. radeon_encoder->devices |= supported_device;
  1345. return;
  1346. }
  1347. }
  1348. /* add a new one */
  1349. radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
  1350. if (!radeon_encoder)
  1351. return;
  1352. encoder = &radeon_encoder->base;
  1353. if (rdev->flags & RADEON_SINGLE_CRTC)
  1354. encoder->possible_crtcs = 0x1;
  1355. else
  1356. encoder->possible_crtcs = 0x3;
  1357. radeon_encoder->enc_priv = NULL;
  1358. radeon_encoder->encoder_enum = encoder_enum;
  1359. radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  1360. radeon_encoder->devices = supported_device;
  1361. radeon_encoder->rmx_type = RMX_OFF;
  1362. switch (radeon_encoder->encoder_id) {
  1363. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1364. encoder->possible_crtcs = 0x1;
  1365. drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
  1366. drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
  1367. if (rdev->is_atom_bios)
  1368. radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
  1369. else
  1370. radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
  1371. radeon_encoder->rmx_type = RMX_FULL;
  1372. break;
  1373. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1374. drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1375. drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
  1376. radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
  1377. break;
  1378. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1379. drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
  1380. drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
  1381. if (rdev->is_atom_bios)
  1382. radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
  1383. else
  1384. radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
  1385. break;
  1386. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1387. drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
  1388. drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
  1389. if (rdev->is_atom_bios)
  1390. radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
  1391. else
  1392. radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
  1393. break;
  1394. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1395. drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1396. drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
  1397. if (!rdev->is_atom_bios)
  1398. radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
  1399. break;
  1400. }
  1401. }