r8152.c 41 KB

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  1. /*
  2. * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/init.h>
  10. #include <linux/signal.h>
  11. #include <linux/slab.h>
  12. #include <linux/module.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/mii.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/usb.h>
  18. #include <linux/crc32.h>
  19. #include <linux/if_vlan.h>
  20. #include <linux/uaccess.h>
  21. /* Version Information */
  22. #define DRIVER_VERSION "v1.0.0 (2013/05/03)"
  23. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  24. #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
  25. #define MODULENAME "r8152"
  26. #define R8152_PHY_ID 32
  27. #define PLA_IDR 0xc000
  28. #define PLA_RCR 0xc010
  29. #define PLA_RMS 0xc016
  30. #define PLA_RXFIFO_CTRL0 0xc0a0
  31. #define PLA_RXFIFO_CTRL1 0xc0a4
  32. #define PLA_RXFIFO_CTRL2 0xc0a8
  33. #define PLA_FMC 0xc0b4
  34. #define PLA_CFG_WOL 0xc0b6
  35. #define PLA_MAR 0xcd00
  36. #define PAL_BDC_CR 0xd1a0
  37. #define PLA_LEDSEL 0xdd90
  38. #define PLA_LED_FEATURE 0xdd92
  39. #define PLA_PHYAR 0xde00
  40. #define PLA_GPHY_INTR_IMR 0xe022
  41. #define PLA_EEE_CR 0xe040
  42. #define PLA_EEEP_CR 0xe080
  43. #define PLA_MAC_PWR_CTRL 0xe0c0
  44. #define PLA_TCR0 0xe610
  45. #define PLA_TCR1 0xe612
  46. #define PLA_TXFIFO_CTRL 0xe618
  47. #define PLA_RSTTELLY 0xe800
  48. #define PLA_CR 0xe813
  49. #define PLA_CRWECR 0xe81c
  50. #define PLA_CONFIG5 0xe822
  51. #define PLA_PHY_PWR 0xe84c
  52. #define PLA_OOB_CTRL 0xe84f
  53. #define PLA_CPCR 0xe854
  54. #define PLA_MISC_0 0xe858
  55. #define PLA_MISC_1 0xe85a
  56. #define PLA_OCP_GPHY_BASE 0xe86c
  57. #define PLA_TELLYCNT 0xe890
  58. #define PLA_SFF_STS_7 0xe8de
  59. #define PLA_PHYSTATUS 0xe908
  60. #define PLA_BP_BA 0xfc26
  61. #define PLA_BP_0 0xfc28
  62. #define PLA_BP_1 0xfc2a
  63. #define PLA_BP_2 0xfc2c
  64. #define PLA_BP_3 0xfc2e
  65. #define PLA_BP_4 0xfc30
  66. #define PLA_BP_5 0xfc32
  67. #define PLA_BP_6 0xfc34
  68. #define PLA_BP_7 0xfc36
  69. #define USB_DEV_STAT 0xb808
  70. #define USB_USB_CTRL 0xd406
  71. #define USB_PHY_CTRL 0xd408
  72. #define USB_TX_AGG 0xd40a
  73. #define USB_RX_BUF_TH 0xd40c
  74. #define USB_USB_TIMER 0xd428
  75. #define USB_PM_CTRL_STATUS 0xd432
  76. #define USB_TX_DMA 0xd434
  77. #define USB_UPS_CTRL 0xd800
  78. #define USB_BP_BA 0xfc26
  79. #define USB_BP_0 0xfc28
  80. #define USB_BP_1 0xfc2a
  81. #define USB_BP_2 0xfc2c
  82. #define USB_BP_3 0xfc2e
  83. #define USB_BP_4 0xfc30
  84. #define USB_BP_5 0xfc32
  85. #define USB_BP_6 0xfc34
  86. #define USB_BP_7 0xfc36
  87. /* OCP Registers */
  88. #define OCP_ALDPS_CONFIG 0x2010
  89. #define OCP_EEE_CONFIG1 0x2080
  90. #define OCP_EEE_CONFIG2 0x2092
  91. #define OCP_EEE_CONFIG3 0x2094
  92. #define OCP_EEE_AR 0xa41a
  93. #define OCP_EEE_DATA 0xa41c
  94. /* PLA_RCR */
  95. #define RCR_AAP 0x00000001
  96. #define RCR_APM 0x00000002
  97. #define RCR_AM 0x00000004
  98. #define RCR_AB 0x00000008
  99. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  100. /* PLA_RXFIFO_CTRL0 */
  101. #define RXFIFO_THR1_NORMAL 0x00080002
  102. #define RXFIFO_THR1_OOB 0x01800003
  103. /* PLA_RXFIFO_CTRL1 */
  104. #define RXFIFO_THR2_FULL 0x00000060
  105. #define RXFIFO_THR2_HIGH 0x00000038
  106. #define RXFIFO_THR2_OOB 0x0000004a
  107. /* PLA_RXFIFO_CTRL2 */
  108. #define RXFIFO_THR3_FULL 0x00000078
  109. #define RXFIFO_THR3_HIGH 0x00000048
  110. #define RXFIFO_THR3_OOB 0x0000005a
  111. /* PLA_TXFIFO_CTRL */
  112. #define TXFIFO_THR_NORMAL 0x00400008
  113. /* PLA_FMC */
  114. #define FMC_FCR_MCU_EN 0x0001
  115. /* PLA_EEEP_CR */
  116. #define EEEP_CR_EEEP_TX 0x0002
  117. /* PLA_TCR0 */
  118. #define TCR0_TX_EMPTY 0x0800
  119. #define TCR0_AUTO_FIFO 0x0080
  120. /* PLA_TCR1 */
  121. #define VERSION_MASK 0x7cf0
  122. /* PLA_CR */
  123. #define CR_RST 0x10
  124. #define CR_RE 0x08
  125. #define CR_TE 0x04
  126. /* PLA_CRWECR */
  127. #define CRWECR_NORAML 0x00
  128. #define CRWECR_CONFIG 0xc0
  129. /* PLA_OOB_CTRL */
  130. #define NOW_IS_OOB 0x80
  131. #define TXFIFO_EMPTY 0x20
  132. #define RXFIFO_EMPTY 0x10
  133. #define LINK_LIST_READY 0x02
  134. #define DIS_MCU_CLROOB 0x01
  135. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  136. /* PLA_MISC_1 */
  137. #define RXDY_GATED_EN 0x0008
  138. /* PLA_SFF_STS_7 */
  139. #define RE_INIT_LL 0x8000
  140. #define MCU_BORW_EN 0x4000
  141. /* PLA_CPCR */
  142. #define CPCR_RX_VLAN 0x0040
  143. /* PLA_CFG_WOL */
  144. #define MAGIC_EN 0x0001
  145. /* PAL_BDC_CR */
  146. #define ALDPS_PROXY_MODE 0x0001
  147. /* PLA_CONFIG5 */
  148. #define LAN_WAKE_EN 0x0002
  149. /* PLA_LED_FEATURE */
  150. #define LED_MODE_MASK 0x0700
  151. /* PLA_PHY_PWR */
  152. #define TX_10M_IDLE_EN 0x0080
  153. #define PFM_PWM_SWITCH 0x0040
  154. /* PLA_MAC_PWR_CTRL */
  155. #define D3_CLK_GATED_EN 0x00004000
  156. #define MCU_CLK_RATIO 0x07010f07
  157. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  158. /* PLA_GPHY_INTR_IMR */
  159. #define GPHY_STS_MSK 0x0001
  160. #define SPEED_DOWN_MSK 0x0002
  161. #define SPDWN_RXDV_MSK 0x0004
  162. #define SPDWN_LINKCHG_MSK 0x0008
  163. /* PLA_PHYAR */
  164. #define PHYAR_FLAG 0x80000000
  165. /* PLA_EEE_CR */
  166. #define EEE_RX_EN 0x0001
  167. #define EEE_TX_EN 0x0002
  168. /* USB_DEV_STAT */
  169. #define STAT_SPEED_MASK 0x0006
  170. #define STAT_SPEED_HIGH 0x0000
  171. #define STAT_SPEED_FULL 0x0001
  172. /* USB_TX_AGG */
  173. #define TX_AGG_MAX_THRESHOLD 0x03
  174. /* USB_RX_BUF_TH */
  175. #define RX_BUF_THR 0x7a120180
  176. /* USB_TX_DMA */
  177. #define TEST_MODE_DISABLE 0x00000001
  178. #define TX_SIZE_ADJUST1 0x00000100
  179. /* USB_UPS_CTRL */
  180. #define POWER_CUT 0x0100
  181. /* USB_PM_CTRL_STATUS */
  182. #define RWSUME_INDICATE 0x0001
  183. /* USB_USB_CTRL */
  184. #define RX_AGG_DISABLE 0x0010
  185. /* OCP_ALDPS_CONFIG */
  186. #define ENPWRSAVE 0x8000
  187. #define ENPDNPS 0x0200
  188. #define LINKENA 0x0100
  189. #define DIS_SDSAVE 0x0010
  190. /* OCP_EEE_CONFIG1 */
  191. #define RG_TXLPI_MSK_HFDUP 0x8000
  192. #define RG_MATCLR_EN 0x4000
  193. #define EEE_10_CAP 0x2000
  194. #define EEE_NWAY_EN 0x1000
  195. #define TX_QUIET_EN 0x0200
  196. #define RX_QUIET_EN 0x0100
  197. #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
  198. #define RG_RXLPI_MSK_HFDUP 0x0008
  199. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  200. /* OCP_EEE_CONFIG2 */
  201. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  202. #define RG_DACQUIET_EN 0x0400
  203. #define RG_LDVQUIET_EN 0x0200
  204. #define RG_CKRSEL 0x0020
  205. #define RG_EEEPRG_EN 0x0010
  206. /* OCP_EEE_CONFIG3 */
  207. #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
  208. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  209. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  210. /* OCP_EEE_AR */
  211. /* bit[15:14] function */
  212. #define FUN_ADDR 0x0000
  213. #define FUN_DATA 0x4000
  214. /* bit[4:0] device addr */
  215. #define DEVICE_ADDR 0x0007
  216. /* OCP_EEE_DATA */
  217. #define EEE_ADDR 0x003C
  218. #define EEE_DATA 0x0002
  219. enum rtl_register_content {
  220. _100bps = 0x08,
  221. _10bps = 0x04,
  222. LINK_STATUS = 0x02,
  223. FULL_DUP = 0x01,
  224. };
  225. #define RTL8152_REQT_READ 0xc0
  226. #define RTL8152_REQT_WRITE 0x40
  227. #define RTL8152_REQ_GET_REGS 0x05
  228. #define RTL8152_REQ_SET_REGS 0x05
  229. #define BYTE_EN_DWORD 0xff
  230. #define BYTE_EN_WORD 0x33
  231. #define BYTE_EN_BYTE 0x11
  232. #define BYTE_EN_SIX_BYTES 0x3f
  233. #define BYTE_EN_START_MASK 0x0f
  234. #define BYTE_EN_END_MASK 0xf0
  235. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  236. #define RTL8152_TX_TIMEOUT (HZ)
  237. /* rtl8152 flags */
  238. enum rtl8152_flags {
  239. RTL8152_UNPLUG = 0,
  240. RX_URB_FAIL,
  241. RTL8152_SET_RX_MODE,
  242. WORK_ENABLE
  243. };
  244. /* Define these values to match your device */
  245. #define VENDOR_ID_REALTEK 0x0bda
  246. #define PRODUCT_ID_RTL8152 0x8152
  247. #define MCU_TYPE_PLA 0x0100
  248. #define MCU_TYPE_USB 0x0000
  249. struct rx_desc {
  250. u32 opts1;
  251. #define RX_LEN_MASK 0x7fff
  252. u32 opts2;
  253. u32 opts3;
  254. u32 opts4;
  255. u32 opts5;
  256. u32 opts6;
  257. };
  258. struct tx_desc {
  259. u32 opts1;
  260. #define TX_FS (1 << 31) /* First segment of a packet */
  261. #define TX_LS (1 << 30) /* Final segment of a packet */
  262. #define TX_LEN_MASK 0xffff
  263. u32 opts2;
  264. };
  265. struct r8152 {
  266. unsigned long flags;
  267. struct usb_device *udev;
  268. struct tasklet_struct tl;
  269. struct net_device *netdev;
  270. struct urb *rx_urb, *tx_urb;
  271. struct sk_buff *tx_skb, *rx_skb;
  272. struct delayed_work schedule;
  273. struct mii_if_info mii;
  274. u32 msg_enable;
  275. u16 ocp_base;
  276. u8 version;
  277. u8 speed;
  278. };
  279. enum rtl_version {
  280. RTL_VER_UNKNOWN = 0,
  281. RTL_VER_01,
  282. RTL_VER_02
  283. };
  284. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  285. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  286. */
  287. static const int multicast_filter_limit = 32;
  288. static
  289. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  290. {
  291. return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  292. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  293. value, index, data, size, 500);
  294. }
  295. static
  296. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  297. {
  298. return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  299. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  300. value, index, data, size, 500);
  301. }
  302. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  303. void *data, u16 type)
  304. {
  305. u16 limit = 64;
  306. int ret = 0;
  307. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  308. return -ENODEV;
  309. /* both size and indix must be 4 bytes align */
  310. if ((size & 3) || !size || (index & 3) || !data)
  311. return -EPERM;
  312. if ((u32)index + (u32)size > 0xffff)
  313. return -EPERM;
  314. while (size) {
  315. if (size > limit) {
  316. ret = get_registers(tp, index, type, limit, data);
  317. if (ret < 0)
  318. break;
  319. index += limit;
  320. data += limit;
  321. size -= limit;
  322. } else {
  323. ret = get_registers(tp, index, type, size, data);
  324. if (ret < 0)
  325. break;
  326. index += size;
  327. data += size;
  328. size = 0;
  329. break;
  330. }
  331. }
  332. return ret;
  333. }
  334. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  335. u16 size, void *data, u16 type)
  336. {
  337. int ret;
  338. u16 byteen_start, byteen_end, byen;
  339. u16 limit = 512;
  340. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  341. return -ENODEV;
  342. /* both size and indix must be 4 bytes align */
  343. if ((size & 3) || !size || (index & 3) || !data)
  344. return -EPERM;
  345. if ((u32)index + (u32)size > 0xffff)
  346. return -EPERM;
  347. byteen_start = byteen & BYTE_EN_START_MASK;
  348. byteen_end = byteen & BYTE_EN_END_MASK;
  349. byen = byteen_start | (byteen_start << 4);
  350. ret = set_registers(tp, index, type | byen, 4, data);
  351. if (ret < 0)
  352. goto error1;
  353. index += 4;
  354. data += 4;
  355. size -= 4;
  356. if (size) {
  357. size -= 4;
  358. while (size) {
  359. if (size > limit) {
  360. ret = set_registers(tp, index,
  361. type | BYTE_EN_DWORD,
  362. limit, data);
  363. if (ret < 0)
  364. goto error1;
  365. index += limit;
  366. data += limit;
  367. size -= limit;
  368. } else {
  369. ret = set_registers(tp, index,
  370. type | BYTE_EN_DWORD,
  371. size, data);
  372. if (ret < 0)
  373. goto error1;
  374. index += size;
  375. data += size;
  376. size = 0;
  377. break;
  378. }
  379. }
  380. byen = byteen_end | (byteen_end >> 4);
  381. ret = set_registers(tp, index, type | byen, 4, data);
  382. if (ret < 0)
  383. goto error1;
  384. }
  385. error1:
  386. return ret;
  387. }
  388. static inline
  389. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  390. {
  391. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  392. }
  393. static inline
  394. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  395. {
  396. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  397. }
  398. static inline
  399. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  400. {
  401. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  402. }
  403. static inline
  404. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  405. {
  406. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  407. }
  408. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  409. {
  410. u32 data;
  411. if (type == MCU_TYPE_PLA)
  412. pla_ocp_read(tp, index, sizeof(data), &data);
  413. else
  414. usb_ocp_read(tp, index, sizeof(data), &data);
  415. return __le32_to_cpu(data);
  416. }
  417. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  418. {
  419. if (type == MCU_TYPE_PLA)
  420. pla_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(data), &data);
  421. else
  422. usb_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(data), &data);
  423. }
  424. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  425. {
  426. u32 data;
  427. u8 shift = index & 2;
  428. index &= ~3;
  429. if (type == MCU_TYPE_PLA)
  430. pla_ocp_read(tp, index, sizeof(data), &data);
  431. else
  432. usb_ocp_read(tp, index, sizeof(data), &data);
  433. data = __le32_to_cpu(data);
  434. data >>= (shift * 8);
  435. data &= 0xffff;
  436. return (u16)data;
  437. }
  438. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  439. {
  440. u32 tmp, mask = 0xffff;
  441. u16 byen = BYTE_EN_WORD;
  442. u8 shift = index & 2;
  443. data &= mask;
  444. if (index & 2) {
  445. byen <<= shift;
  446. mask <<= (shift * 8);
  447. data <<= (shift * 8);
  448. index &= ~3;
  449. }
  450. if (type == MCU_TYPE_PLA)
  451. pla_ocp_read(tp, index, sizeof(tmp), &tmp);
  452. else
  453. usb_ocp_read(tp, index, sizeof(tmp), &tmp);
  454. tmp = __le32_to_cpu(tmp) & ~mask;
  455. tmp |= data;
  456. tmp = __cpu_to_le32(tmp);
  457. if (type == MCU_TYPE_PLA)
  458. pla_ocp_write(tp, index, byen, sizeof(tmp), &tmp);
  459. else
  460. usb_ocp_write(tp, index, byen, sizeof(tmp), &tmp);
  461. }
  462. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  463. {
  464. u32 data;
  465. u8 shift = index & 3;
  466. index &= ~3;
  467. if (type == MCU_TYPE_PLA)
  468. pla_ocp_read(tp, index, sizeof(data), &data);
  469. else
  470. usb_ocp_read(tp, index, sizeof(data), &data);
  471. data = __le32_to_cpu(data);
  472. data >>= (shift * 8);
  473. data &= 0xff;
  474. return (u8)data;
  475. }
  476. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  477. {
  478. u32 tmp, mask = 0xff;
  479. u16 byen = BYTE_EN_BYTE;
  480. u8 shift = index & 3;
  481. data &= mask;
  482. if (index & 3) {
  483. byen <<= shift;
  484. mask <<= (shift * 8);
  485. data <<= (shift * 8);
  486. index &= ~3;
  487. }
  488. if (type == MCU_TYPE_PLA)
  489. pla_ocp_read(tp, index, sizeof(tmp), &tmp);
  490. else
  491. usb_ocp_read(tp, index, sizeof(tmp), &tmp);
  492. tmp = __le32_to_cpu(tmp) & ~mask;
  493. tmp |= data;
  494. tmp = __cpu_to_le32(tmp);
  495. if (type == MCU_TYPE_PLA)
  496. pla_ocp_write(tp, index, byen, sizeof(tmp), &tmp);
  497. else
  498. usb_ocp_write(tp, index, byen, sizeof(tmp), &tmp);
  499. }
  500. static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  501. {
  502. u32 ocp_data;
  503. int i;
  504. ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
  505. (value & 0xffff);
  506. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  507. for (i = 20; i > 0; i--) {
  508. udelay(25);
  509. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  510. if (!(ocp_data & PHYAR_FLAG))
  511. break;
  512. }
  513. udelay(20);
  514. }
  515. static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  516. {
  517. u32 ocp_data;
  518. int i;
  519. ocp_data = (reg_addr & 0x1f) << 16;
  520. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  521. for (i = 20; i > 0; i--) {
  522. udelay(25);
  523. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  524. if (ocp_data & PHYAR_FLAG)
  525. break;
  526. }
  527. udelay(20);
  528. if (!(ocp_data & PHYAR_FLAG))
  529. return -EAGAIN;
  530. return (u16)(ocp_data & 0xffff);
  531. }
  532. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  533. {
  534. struct r8152 *tp = netdev_priv(netdev);
  535. if (phy_id != R8152_PHY_ID)
  536. return -EINVAL;
  537. return r8152_mdio_read(tp, reg);
  538. }
  539. static
  540. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  541. {
  542. struct r8152 *tp = netdev_priv(netdev);
  543. if (phy_id != R8152_PHY_ID)
  544. return;
  545. r8152_mdio_write(tp, reg, val);
  546. }
  547. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  548. {
  549. u16 ocp_base, ocp_index;
  550. ocp_base = addr & 0xf000;
  551. if (ocp_base != tp->ocp_base) {
  552. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  553. tp->ocp_base = ocp_base;
  554. }
  555. ocp_index = (addr & 0x0fff) | 0xb000;
  556. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  557. }
  558. static inline void set_ethernet_addr(struct r8152 *tp)
  559. {
  560. struct net_device *dev = tp->netdev;
  561. u8 *node_id;
  562. node_id = kmalloc(sizeof(u8) * 8, GFP_KERNEL);
  563. if (!node_id) {
  564. netif_err(tp, probe, dev, "out of memory");
  565. return;
  566. }
  567. if (pla_ocp_read(tp, PLA_IDR, sizeof(u8) * 8, node_id) < 0)
  568. netif_notice(tp, probe, dev, "inet addr fail\n");
  569. else {
  570. memcpy(dev->dev_addr, node_id, dev->addr_len);
  571. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  572. }
  573. kfree(node_id);
  574. }
  575. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  576. {
  577. struct r8152 *tp = netdev_priv(netdev);
  578. struct sockaddr *addr = p;
  579. if (!is_valid_ether_addr(addr->sa_data))
  580. return -EADDRNOTAVAIL;
  581. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  582. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  583. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  584. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  585. return 0;
  586. }
  587. static int alloc_all_urbs(struct r8152 *tp)
  588. {
  589. tp->rx_urb = usb_alloc_urb(0, GFP_KERNEL);
  590. if (!tp->rx_urb)
  591. return 0;
  592. tp->tx_urb = usb_alloc_urb(0, GFP_KERNEL);
  593. if (!tp->tx_urb) {
  594. usb_free_urb(tp->rx_urb);
  595. return 0;
  596. }
  597. return 1;
  598. }
  599. static void free_all_urbs(struct r8152 *tp)
  600. {
  601. usb_free_urb(tp->rx_urb);
  602. usb_free_urb(tp->tx_urb);
  603. }
  604. static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
  605. {
  606. return &dev->stats;
  607. }
  608. static void read_bulk_callback(struct urb *urb)
  609. {
  610. struct r8152 *tp;
  611. unsigned pkt_len;
  612. struct sk_buff *skb;
  613. struct net_device *netdev;
  614. struct net_device_stats *stats;
  615. int status = urb->status;
  616. int result;
  617. struct rx_desc *rx_desc;
  618. tp = urb->context;
  619. if (!tp)
  620. return;
  621. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  622. return;
  623. netdev = tp->netdev;
  624. if (!netif_device_present(netdev))
  625. return;
  626. stats = rtl8152_get_stats(netdev);
  627. switch (status) {
  628. case 0:
  629. break;
  630. case -ESHUTDOWN:
  631. set_bit(RTL8152_UNPLUG, &tp->flags);
  632. netif_device_detach(tp->netdev);
  633. case -ENOENT:
  634. return; /* the urb is in unlink state */
  635. case -ETIME:
  636. pr_warn_ratelimited("may be reset is needed?..\n");
  637. goto goon;
  638. default:
  639. pr_warn_ratelimited("Rx status %d\n", status);
  640. goto goon;
  641. }
  642. /* protect against short packets (tell me why we got some?!?) */
  643. if (urb->actual_length < sizeof(*rx_desc))
  644. goto goon;
  645. rx_desc = (struct rx_desc *)urb->transfer_buffer;
  646. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  647. if (urb->actual_length < sizeof(struct rx_desc) + pkt_len)
  648. goto goon;
  649. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  650. if (!skb)
  651. goto goon;
  652. memcpy(skb->data, tp->rx_skb->data + sizeof(struct rx_desc), pkt_len);
  653. skb_put(skb, pkt_len);
  654. skb->protocol = eth_type_trans(skb, netdev);
  655. netif_rx(skb);
  656. stats->rx_packets++;
  657. stats->rx_bytes += pkt_len;
  658. goon:
  659. usb_fill_bulk_urb(tp->rx_urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  660. tp->rx_skb->data, RTL8152_RMS + sizeof(struct rx_desc),
  661. (usb_complete_t)read_bulk_callback, tp);
  662. result = usb_submit_urb(tp->rx_urb, GFP_ATOMIC);
  663. if (result == -ENODEV) {
  664. netif_device_detach(tp->netdev);
  665. } else if (result) {
  666. set_bit(RX_URB_FAIL, &tp->flags);
  667. goto resched;
  668. } else {
  669. clear_bit(RX_URB_FAIL, &tp->flags);
  670. }
  671. return;
  672. resched:
  673. tasklet_schedule(&tp->tl);
  674. }
  675. static void rx_fixup(unsigned long data)
  676. {
  677. struct r8152 *tp;
  678. int status;
  679. tp = (struct r8152 *)data;
  680. if (!test_bit(WORK_ENABLE, &tp->flags))
  681. return;
  682. status = usb_submit_urb(tp->rx_urb, GFP_ATOMIC);
  683. if (status == -ENODEV) {
  684. netif_device_detach(tp->netdev);
  685. } else if (status) {
  686. set_bit(RX_URB_FAIL, &tp->flags);
  687. goto tlsched;
  688. } else {
  689. clear_bit(RX_URB_FAIL, &tp->flags);
  690. }
  691. return;
  692. tlsched:
  693. tasklet_schedule(&tp->tl);
  694. }
  695. static void write_bulk_callback(struct urb *urb)
  696. {
  697. struct r8152 *tp;
  698. int status = urb->status;
  699. tp = urb->context;
  700. if (!tp)
  701. return;
  702. dev_kfree_skb_irq(tp->tx_skb);
  703. if (!netif_device_present(tp->netdev))
  704. return;
  705. if (status)
  706. dev_info(&urb->dev->dev, "%s: Tx status %d\n",
  707. tp->netdev->name, status);
  708. tp->netdev->trans_start = jiffies;
  709. netif_wake_queue(tp->netdev);
  710. }
  711. static void rtl8152_tx_timeout(struct net_device *netdev)
  712. {
  713. struct r8152 *tp = netdev_priv(netdev);
  714. struct net_device_stats *stats = rtl8152_get_stats(netdev);
  715. netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
  716. usb_unlink_urb(tp->tx_urb);
  717. stats->tx_errors++;
  718. }
  719. static void rtl8152_set_rx_mode(struct net_device *netdev)
  720. {
  721. struct r8152 *tp = netdev_priv(netdev);
  722. if (tp->speed & LINK_STATUS)
  723. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  724. }
  725. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  726. {
  727. struct r8152 *tp = netdev_priv(netdev);
  728. u32 tmp, *mc_filter; /* Multicast hash filter */
  729. u32 ocp_data;
  730. mc_filter = kmalloc(sizeof(u32) * 2, GFP_KERNEL);
  731. if (!mc_filter) {
  732. netif_err(tp, link, netdev, "out of memory");
  733. return;
  734. }
  735. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  736. netif_stop_queue(netdev);
  737. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  738. ocp_data &= ~RCR_ACPT_ALL;
  739. ocp_data |= RCR_AB | RCR_APM;
  740. if (netdev->flags & IFF_PROMISC) {
  741. /* Unconditionally log net taps. */
  742. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  743. ocp_data |= RCR_AM | RCR_AAP;
  744. mc_filter[1] = mc_filter[0] = 0xffffffff;
  745. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  746. (netdev->flags & IFF_ALLMULTI)) {
  747. /* Too many to filter perfectly -- accept all multicasts. */
  748. ocp_data |= RCR_AM;
  749. mc_filter[1] = mc_filter[0] = 0xffffffff;
  750. } else {
  751. struct netdev_hw_addr *ha;
  752. mc_filter[1] = mc_filter[0] = 0;
  753. netdev_for_each_mc_addr(ha, netdev) {
  754. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  755. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  756. ocp_data |= RCR_AM;
  757. }
  758. }
  759. tmp = mc_filter[0];
  760. mc_filter[0] = __cpu_to_le32(swab32(mc_filter[1]));
  761. mc_filter[1] = __cpu_to_le32(swab32(tmp));
  762. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(u32) * 2, mc_filter);
  763. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  764. netif_wake_queue(netdev);
  765. kfree(mc_filter);
  766. }
  767. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  768. struct net_device *netdev)
  769. {
  770. struct r8152 *tp = netdev_priv(netdev);
  771. struct net_device_stats *stats = rtl8152_get_stats(netdev);
  772. struct tx_desc *tx_desc;
  773. unsigned int len;
  774. int res;
  775. netif_stop_queue(netdev);
  776. len = skb->len;
  777. if (skb_header_cloned(skb) || skb_headroom(skb) < sizeof(*tx_desc)) {
  778. struct sk_buff *tx_skb;
  779. tx_skb = skb_copy_expand(skb, sizeof(*tx_desc), 0, GFP_ATOMIC);
  780. dev_kfree_skb_any(skb);
  781. if (!tx_skb) {
  782. stats->tx_dropped++;
  783. netif_wake_queue(netdev);
  784. return NETDEV_TX_OK;
  785. }
  786. skb = tx_skb;
  787. }
  788. tx_desc = (struct tx_desc *)skb_push(skb, sizeof(*tx_desc));
  789. memset(tx_desc, 0, sizeof(*tx_desc));
  790. tx_desc->opts1 = cpu_to_le32((len & TX_LEN_MASK) | TX_FS | TX_LS);
  791. tp->tx_skb = skb;
  792. skb_tx_timestamp(skb);
  793. usb_fill_bulk_urb(tp->tx_urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  794. skb->data, skb->len,
  795. (usb_complete_t)write_bulk_callback, tp);
  796. res = usb_submit_urb(tp->tx_urb, GFP_ATOMIC);
  797. if (res) {
  798. /* Can we get/handle EPIPE here? */
  799. if (res == -ENODEV) {
  800. netif_device_detach(tp->netdev);
  801. } else {
  802. netif_warn(tp, tx_err, netdev,
  803. "failed tx_urb %d\n", res);
  804. stats->tx_errors++;
  805. netif_start_queue(netdev);
  806. }
  807. } else {
  808. stats->tx_packets++;
  809. stats->tx_bytes += skb->len;
  810. }
  811. return NETDEV_TX_OK;
  812. }
  813. static void r8152b_reset_packet_filter(struct r8152 *tp)
  814. {
  815. u32 ocp_data;
  816. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  817. ocp_data &= ~FMC_FCR_MCU_EN;
  818. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  819. ocp_data |= FMC_FCR_MCU_EN;
  820. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  821. }
  822. static void rtl8152_nic_reset(struct r8152 *tp)
  823. {
  824. int i;
  825. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  826. for (i = 0; i < 1000; i++) {
  827. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  828. break;
  829. udelay(100);
  830. }
  831. }
  832. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  833. {
  834. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  835. }
  836. static int rtl8152_enable(struct r8152 *tp)
  837. {
  838. u32 ocp_data;
  839. u8 speed;
  840. speed = rtl8152_get_speed(tp);
  841. if (speed & _100bps) {
  842. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  843. ocp_data &= ~EEEP_CR_EEEP_TX;
  844. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  845. } else {
  846. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  847. ocp_data |= EEEP_CR_EEEP_TX;
  848. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  849. }
  850. r8152b_reset_packet_filter(tp);
  851. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  852. ocp_data |= CR_RE | CR_TE;
  853. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  854. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  855. ocp_data &= ~RXDY_GATED_EN;
  856. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  857. usb_fill_bulk_urb(tp->rx_urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  858. tp->rx_skb->data, RTL8152_RMS + sizeof(struct rx_desc),
  859. (usb_complete_t)read_bulk_callback, tp);
  860. return usb_submit_urb(tp->rx_urb, GFP_KERNEL);
  861. }
  862. static void rtl8152_disable(struct r8152 *tp)
  863. {
  864. u32 ocp_data;
  865. int i;
  866. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  867. ocp_data &= ~RCR_ACPT_ALL;
  868. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  869. usb_kill_urb(tp->tx_urb);
  870. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  871. ocp_data |= RXDY_GATED_EN;
  872. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  873. for (i = 0; i < 1000; i++) {
  874. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  875. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  876. break;
  877. mdelay(1);
  878. }
  879. for (i = 0; i < 1000; i++) {
  880. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  881. break;
  882. mdelay(1);
  883. }
  884. usb_kill_urb(tp->rx_urb);
  885. rtl8152_nic_reset(tp);
  886. }
  887. static void r8152b_exit_oob(struct r8152 *tp)
  888. {
  889. u32 ocp_data;
  890. int i;
  891. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  892. ocp_data &= ~RCR_ACPT_ALL;
  893. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  894. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  895. ocp_data |= RXDY_GATED_EN;
  896. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  897. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  898. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  899. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  900. ocp_data &= ~NOW_IS_OOB;
  901. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  902. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  903. ocp_data &= ~MCU_BORW_EN;
  904. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  905. for (i = 0; i < 1000; i++) {
  906. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  907. if (ocp_data & LINK_LIST_READY)
  908. break;
  909. mdelay(1);
  910. }
  911. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  912. ocp_data |= RE_INIT_LL;
  913. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  914. for (i = 0; i < 1000; i++) {
  915. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  916. if (ocp_data & LINK_LIST_READY)
  917. break;
  918. mdelay(1);
  919. }
  920. rtl8152_nic_reset(tp);
  921. /* rx share fifo credit full threshold */
  922. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  923. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
  924. ocp_data &= STAT_SPEED_MASK;
  925. if (ocp_data == STAT_SPEED_FULL) {
  926. /* rx share fifo credit near full threshold */
  927. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  928. RXFIFO_THR2_FULL);
  929. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  930. RXFIFO_THR3_FULL);
  931. } else {
  932. /* rx share fifo credit near full threshold */
  933. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  934. RXFIFO_THR2_HIGH);
  935. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  936. RXFIFO_THR3_HIGH);
  937. }
  938. /* TX share fifo free credit full threshold */
  939. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  940. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  941. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
  942. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  943. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  944. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  945. ocp_data &= ~CPCR_RX_VLAN;
  946. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  947. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  948. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  949. ocp_data |= TCR0_AUTO_FIFO;
  950. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  951. }
  952. static void r8152b_enter_oob(struct r8152 *tp)
  953. {
  954. u32 ocp_data;
  955. int i;
  956. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  957. ocp_data &= ~NOW_IS_OOB;
  958. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  959. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  960. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  961. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  962. rtl8152_disable(tp);
  963. for (i = 0; i < 1000; i++) {
  964. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  965. if (ocp_data & LINK_LIST_READY)
  966. break;
  967. mdelay(1);
  968. }
  969. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  970. ocp_data |= RE_INIT_LL;
  971. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  972. for (i = 0; i < 1000; i++) {
  973. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  974. if (ocp_data & LINK_LIST_READY)
  975. break;
  976. mdelay(1);
  977. }
  978. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  979. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  980. ocp_data |= MAGIC_EN;
  981. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  982. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  983. ocp_data |= CPCR_RX_VLAN;
  984. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  985. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  986. ocp_data |= ALDPS_PROXY_MODE;
  987. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  988. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  989. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  990. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  991. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
  992. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  993. ocp_data &= ~RXDY_GATED_EN;
  994. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  995. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  996. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  997. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  998. }
  999. static void r8152b_disable_aldps(struct r8152 *tp)
  1000. {
  1001. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1002. msleep(20);
  1003. }
  1004. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1005. {
  1006. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1007. LINKENA | DIS_SDSAVE);
  1008. }
  1009. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  1010. {
  1011. u16 bmcr, anar;
  1012. int ret = 0;
  1013. cancel_delayed_work_sync(&tp->schedule);
  1014. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1015. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1016. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1017. if (autoneg == AUTONEG_DISABLE) {
  1018. if (speed == SPEED_10) {
  1019. bmcr = 0;
  1020. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1021. } else if (speed == SPEED_100) {
  1022. bmcr = BMCR_SPEED100;
  1023. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1024. } else {
  1025. ret = -EINVAL;
  1026. goto out;
  1027. }
  1028. if (duplex == DUPLEX_FULL)
  1029. bmcr |= BMCR_FULLDPLX;
  1030. } else {
  1031. if (speed == SPEED_10) {
  1032. if (duplex == DUPLEX_FULL)
  1033. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1034. else
  1035. anar |= ADVERTISE_10HALF;
  1036. } else if (speed == SPEED_100) {
  1037. if (duplex == DUPLEX_FULL) {
  1038. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1039. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1040. } else {
  1041. anar |= ADVERTISE_10HALF;
  1042. anar |= ADVERTISE_100HALF;
  1043. }
  1044. } else {
  1045. ret = -EINVAL;
  1046. goto out;
  1047. }
  1048. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1049. }
  1050. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1051. r8152_mdio_write(tp, MII_BMCR, bmcr);
  1052. out:
  1053. schedule_delayed_work(&tp->schedule, 5 * HZ);
  1054. return ret;
  1055. }
  1056. static void rtl8152_down(struct r8152 *tp)
  1057. {
  1058. u32 ocp_data;
  1059. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1060. ocp_data &= ~POWER_CUT;
  1061. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1062. r8152b_disable_aldps(tp);
  1063. r8152b_enter_oob(tp);
  1064. r8152b_enable_aldps(tp);
  1065. }
  1066. static void set_carrier(struct r8152 *tp)
  1067. {
  1068. struct net_device *netdev = tp->netdev;
  1069. u8 speed;
  1070. speed = rtl8152_get_speed(tp);
  1071. if (speed & LINK_STATUS) {
  1072. if (!(tp->speed & LINK_STATUS)) {
  1073. rtl8152_enable(tp);
  1074. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1075. netif_carrier_on(netdev);
  1076. }
  1077. } else {
  1078. if (tp->speed & LINK_STATUS) {
  1079. netif_carrier_off(netdev);
  1080. rtl8152_disable(tp);
  1081. }
  1082. }
  1083. tp->speed = speed;
  1084. }
  1085. static void rtl_work_func_t(struct work_struct *work)
  1086. {
  1087. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  1088. if (!test_bit(WORK_ENABLE, &tp->flags))
  1089. goto out1;
  1090. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1091. goto out1;
  1092. set_carrier(tp);
  1093. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  1094. _rtl8152_set_rx_mode(tp->netdev);
  1095. schedule_delayed_work(&tp->schedule, HZ);
  1096. out1:
  1097. return;
  1098. }
  1099. static int rtl8152_open(struct net_device *netdev)
  1100. {
  1101. struct r8152 *tp = netdev_priv(netdev);
  1102. int res = 0;
  1103. tp->speed = rtl8152_get_speed(tp);
  1104. if (tp->speed & LINK_STATUS) {
  1105. res = rtl8152_enable(tp);
  1106. if (res) {
  1107. if (res == -ENODEV)
  1108. netif_device_detach(tp->netdev);
  1109. netif_err(tp, ifup, netdev,
  1110. "rtl8152_open failed: %d\n", res);
  1111. return res;
  1112. }
  1113. netif_carrier_on(netdev);
  1114. } else {
  1115. netif_stop_queue(netdev);
  1116. netif_carrier_off(netdev);
  1117. }
  1118. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1119. netif_start_queue(netdev);
  1120. set_bit(WORK_ENABLE, &tp->flags);
  1121. schedule_delayed_work(&tp->schedule, 0);
  1122. return res;
  1123. }
  1124. static int rtl8152_close(struct net_device *netdev)
  1125. {
  1126. struct r8152 *tp = netdev_priv(netdev);
  1127. int res = 0;
  1128. clear_bit(WORK_ENABLE, &tp->flags);
  1129. cancel_delayed_work_sync(&tp->schedule);
  1130. netif_stop_queue(netdev);
  1131. rtl8152_disable(tp);
  1132. return res;
  1133. }
  1134. static void rtl_clear_bp(struct r8152 *tp)
  1135. {
  1136. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
  1137. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
  1138. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
  1139. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
  1140. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
  1141. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
  1142. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
  1143. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
  1144. mdelay(3);
  1145. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
  1146. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
  1147. }
  1148. static void r8152b_enable_eee(struct r8152 *tp)
  1149. {
  1150. u32 ocp_data;
  1151. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  1152. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  1153. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  1154. ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
  1155. EEE_10_CAP | EEE_NWAY_EN |
  1156. TX_QUIET_EN | RX_QUIET_EN |
  1157. SDRISETIME | RG_RXLPI_MSK_HFDUP |
  1158. SDFALLTIME);
  1159. ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
  1160. RG_LDVQUIET_EN | RG_CKRSEL |
  1161. RG_EEEPRG_EN);
  1162. ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
  1163. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
  1164. ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
  1165. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
  1166. ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
  1167. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  1168. }
  1169. static void r8152b_enable_fc(struct r8152 *tp)
  1170. {
  1171. u16 anar;
  1172. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1173. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1174. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1175. }
  1176. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1177. {
  1178. r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
  1179. r8152b_disable_aldps(tp);
  1180. }
  1181. static void r8152b_init(struct r8152 *tp)
  1182. {
  1183. u32 ocp_data;
  1184. int i;
  1185. rtl_clear_bp(tp);
  1186. if (tp->version == RTL_VER_01) {
  1187. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  1188. ocp_data &= ~LED_MODE_MASK;
  1189. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  1190. }
  1191. r8152b_hw_phy_cfg(tp);
  1192. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1193. ocp_data &= ~POWER_CUT;
  1194. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1195. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1196. ocp_data &= ~RWSUME_INDICATE;
  1197. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1198. r8152b_exit_oob(tp);
  1199. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  1200. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  1201. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  1202. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  1203. ocp_data &= ~MCU_CLK_RATIO_MASK;
  1204. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  1205. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  1206. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  1207. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  1208. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  1209. r8152b_enable_eee(tp);
  1210. r8152b_enable_aldps(tp);
  1211. r8152b_enable_fc(tp);
  1212. r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
  1213. BMCR_ANRESTART);
  1214. for (i = 0; i < 100; i++) {
  1215. udelay(100);
  1216. if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
  1217. break;
  1218. }
  1219. /* disable rx aggregation */
  1220. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1221. ocp_data |= RX_AGG_DISABLE;
  1222. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1223. }
  1224. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  1225. {
  1226. struct r8152 *tp = usb_get_intfdata(intf);
  1227. netif_device_detach(tp->netdev);
  1228. if (netif_running(tp->netdev)) {
  1229. clear_bit(WORK_ENABLE, &tp->flags);
  1230. cancel_delayed_work_sync(&tp->schedule);
  1231. }
  1232. rtl8152_down(tp);
  1233. return 0;
  1234. }
  1235. static int rtl8152_resume(struct usb_interface *intf)
  1236. {
  1237. struct r8152 *tp = usb_get_intfdata(intf);
  1238. r8152b_init(tp);
  1239. netif_device_attach(tp->netdev);
  1240. if (netif_running(tp->netdev)) {
  1241. rtl8152_enable(tp);
  1242. set_bit(WORK_ENABLE, &tp->flags);
  1243. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1244. schedule_delayed_work(&tp->schedule, 0);
  1245. }
  1246. return 0;
  1247. }
  1248. static void rtl8152_get_drvinfo(struct net_device *netdev,
  1249. struct ethtool_drvinfo *info)
  1250. {
  1251. struct r8152 *tp = netdev_priv(netdev);
  1252. strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
  1253. strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
  1254. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  1255. }
  1256. static
  1257. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  1258. {
  1259. struct r8152 *tp = netdev_priv(netdev);
  1260. if (!tp->mii.mdio_read)
  1261. return -EOPNOTSUPP;
  1262. return mii_ethtool_gset(&tp->mii, cmd);
  1263. }
  1264. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1265. {
  1266. struct r8152 *tp = netdev_priv(dev);
  1267. return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  1268. }
  1269. static struct ethtool_ops ops = {
  1270. .get_drvinfo = rtl8152_get_drvinfo,
  1271. .get_settings = rtl8152_get_settings,
  1272. .set_settings = rtl8152_set_settings,
  1273. .get_link = ethtool_op_get_link,
  1274. };
  1275. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  1276. {
  1277. struct r8152 *tp = netdev_priv(netdev);
  1278. struct mii_ioctl_data *data = if_mii(rq);
  1279. int res = 0;
  1280. switch (cmd) {
  1281. case SIOCGMIIPHY:
  1282. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  1283. break;
  1284. case SIOCGMIIREG:
  1285. data->val_out = r8152_mdio_read(tp, data->reg_num);
  1286. break;
  1287. case SIOCSMIIREG:
  1288. if (!capable(CAP_NET_ADMIN)) {
  1289. res = -EPERM;
  1290. break;
  1291. }
  1292. r8152_mdio_write(tp, data->reg_num, data->val_in);
  1293. break;
  1294. default:
  1295. res = -EOPNOTSUPP;
  1296. }
  1297. return res;
  1298. }
  1299. static const struct net_device_ops rtl8152_netdev_ops = {
  1300. .ndo_open = rtl8152_open,
  1301. .ndo_stop = rtl8152_close,
  1302. .ndo_do_ioctl = rtl8152_ioctl,
  1303. .ndo_start_xmit = rtl8152_start_xmit,
  1304. .ndo_tx_timeout = rtl8152_tx_timeout,
  1305. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  1306. .ndo_set_mac_address = rtl8152_set_mac_address,
  1307. .ndo_change_mtu = eth_change_mtu,
  1308. .ndo_validate_addr = eth_validate_addr,
  1309. };
  1310. static void r8152b_get_version(struct r8152 *tp)
  1311. {
  1312. u32 ocp_data;
  1313. u16 version;
  1314. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  1315. version = (u16)(ocp_data & VERSION_MASK);
  1316. switch (version) {
  1317. case 0x4c00:
  1318. tp->version = RTL_VER_01;
  1319. break;
  1320. case 0x4c10:
  1321. tp->version = RTL_VER_02;
  1322. break;
  1323. default:
  1324. netif_info(tp, probe, tp->netdev,
  1325. "Unknown version 0x%04x\n", version);
  1326. break;
  1327. }
  1328. }
  1329. static int rtl8152_probe(struct usb_interface *intf,
  1330. const struct usb_device_id *id)
  1331. {
  1332. struct usb_device *udev = interface_to_usbdev(intf);
  1333. struct r8152 *tp;
  1334. struct net_device *netdev;
  1335. if (udev->actconfig->desc.bConfigurationValue != 1) {
  1336. usb_driver_set_configuration(udev, 1);
  1337. return -ENODEV;
  1338. }
  1339. netdev = alloc_etherdev(sizeof(struct r8152));
  1340. if (!netdev) {
  1341. dev_err(&intf->dev, "Out of memory");
  1342. return -ENOMEM;
  1343. }
  1344. tp = netdev_priv(netdev);
  1345. tp->msg_enable = 0x7FFF;
  1346. tasklet_init(&tp->tl, rx_fixup, (unsigned long)tp);
  1347. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  1348. tp->udev = udev;
  1349. tp->netdev = netdev;
  1350. netdev->netdev_ops = &rtl8152_netdev_ops;
  1351. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  1352. netdev->features &= ~NETIF_F_IP_CSUM;
  1353. SET_ETHTOOL_OPS(netdev, &ops);
  1354. tp->speed = 0;
  1355. tp->mii.dev = netdev;
  1356. tp->mii.mdio_read = read_mii_word;
  1357. tp->mii.mdio_write = write_mii_word;
  1358. tp->mii.phy_id_mask = 0x3f;
  1359. tp->mii.reg_num_mask = 0x1f;
  1360. tp->mii.phy_id = R8152_PHY_ID;
  1361. tp->mii.supports_gmii = 0;
  1362. r8152b_get_version(tp);
  1363. r8152b_init(tp);
  1364. set_ethernet_addr(tp);
  1365. if (!alloc_all_urbs(tp)) {
  1366. netif_err(tp, probe, netdev, "out of memory");
  1367. goto out;
  1368. }
  1369. tp->rx_skb = netdev_alloc_skb(netdev,
  1370. RTL8152_RMS + sizeof(struct rx_desc));
  1371. if (!tp->rx_skb)
  1372. goto out1;
  1373. usb_set_intfdata(intf, tp);
  1374. SET_NETDEV_DEV(netdev, &intf->dev);
  1375. if (register_netdev(netdev) != 0) {
  1376. netif_err(tp, probe, netdev, "couldn't register the device");
  1377. goto out2;
  1378. }
  1379. netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
  1380. return 0;
  1381. out2:
  1382. usb_set_intfdata(intf, NULL);
  1383. dev_kfree_skb(tp->rx_skb);
  1384. out1:
  1385. free_all_urbs(tp);
  1386. out:
  1387. free_netdev(netdev);
  1388. return -EIO;
  1389. }
  1390. static void rtl8152_unload(struct r8152 *tp)
  1391. {
  1392. u32 ocp_data;
  1393. if (tp->version != RTL_VER_01) {
  1394. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1395. ocp_data |= POWER_CUT;
  1396. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1397. }
  1398. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1399. ocp_data &= ~RWSUME_INDICATE;
  1400. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1401. }
  1402. static void rtl8152_disconnect(struct usb_interface *intf)
  1403. {
  1404. struct r8152 *tp = usb_get_intfdata(intf);
  1405. usb_set_intfdata(intf, NULL);
  1406. if (tp) {
  1407. set_bit(RTL8152_UNPLUG, &tp->flags);
  1408. tasklet_kill(&tp->tl);
  1409. unregister_netdev(tp->netdev);
  1410. rtl8152_unload(tp);
  1411. free_all_urbs(tp);
  1412. if (tp->rx_skb)
  1413. dev_kfree_skb(tp->rx_skb);
  1414. free_netdev(tp->netdev);
  1415. }
  1416. }
  1417. /* table of devices that work with this driver */
  1418. static struct usb_device_id rtl8152_table[] = {
  1419. {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
  1420. {}
  1421. };
  1422. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  1423. static struct usb_driver rtl8152_driver = {
  1424. .name = MODULENAME,
  1425. .probe = rtl8152_probe,
  1426. .disconnect = rtl8152_disconnect,
  1427. .id_table = rtl8152_table,
  1428. .suspend = rtl8152_suspend,
  1429. .resume = rtl8152_resume
  1430. };
  1431. module_usb_driver(rtl8152_driver);
  1432. MODULE_AUTHOR(DRIVER_AUTHOR);
  1433. MODULE_DESCRIPTION(DRIVER_DESC);
  1434. MODULE_LICENSE("GPL");