pci.c 21 KB

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  1. /*
  2. * Sonics Silicon Backplane PCI-Hostbus related functions.
  3. *
  4. * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
  5. * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  7. * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  8. * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. *
  10. * Derived from the Broadcom 4400 device driver.
  11. * Copyright (C) 2002 David S. Miller (davem@redhat.com)
  12. * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  13. * Copyright (C) 2006 Broadcom Corporation.
  14. *
  15. * Licensed under the GNU/GPL. See COPYING for details.
  16. */
  17. #include <linux/ssb/ssb.h>
  18. #include <linux/ssb/ssb_regs.h>
  19. #include <linux/pci.h>
  20. #include <linux/delay.h>
  21. #include "ssb_private.h"
  22. /* Define the following to 1 to enable a printk on each coreswitch. */
  23. #define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
  24. /* Lowlevel coreswitching */
  25. int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
  26. {
  27. int err;
  28. int attempts = 0;
  29. u32 cur_core;
  30. while (1) {
  31. err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
  32. (coreidx * SSB_CORE_SIZE)
  33. + SSB_ENUM_BASE);
  34. if (err)
  35. goto error;
  36. err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
  37. &cur_core);
  38. if (err)
  39. goto error;
  40. cur_core = (cur_core - SSB_ENUM_BASE)
  41. / SSB_CORE_SIZE;
  42. if (cur_core == coreidx)
  43. break;
  44. if (attempts++ > SSB_BAR0_MAX_RETRIES)
  45. goto error;
  46. udelay(10);
  47. }
  48. return 0;
  49. error:
  50. ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
  51. return -ENODEV;
  52. }
  53. int ssb_pci_switch_core(struct ssb_bus *bus,
  54. struct ssb_device *dev)
  55. {
  56. int err;
  57. unsigned long flags;
  58. #if SSB_VERBOSE_PCICORESWITCH_DEBUG
  59. ssb_printk(KERN_INFO PFX
  60. "Switching to %s core, index %d\n",
  61. ssb_core_name(dev->id.coreid),
  62. dev->core_index);
  63. #endif
  64. spin_lock_irqsave(&bus->bar_lock, flags);
  65. err = ssb_pci_switch_coreidx(bus, dev->core_index);
  66. if (!err)
  67. bus->mapped_device = dev;
  68. spin_unlock_irqrestore(&bus->bar_lock, flags);
  69. return err;
  70. }
  71. /* Enable/disable the on board crystal oscillator and/or PLL. */
  72. int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
  73. {
  74. int err;
  75. u32 in, out, outenable;
  76. u16 pci_status;
  77. if (bus->bustype != SSB_BUSTYPE_PCI)
  78. return 0;
  79. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
  80. if (err)
  81. goto err_pci;
  82. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
  83. if (err)
  84. goto err_pci;
  85. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
  86. if (err)
  87. goto err_pci;
  88. outenable |= what;
  89. if (turn_on) {
  90. /* Avoid glitching the clock if GPRS is already using it.
  91. * We can't actually read the state of the PLLPD so we infer it
  92. * by the value of XTAL_PU which *is* readable via gpioin.
  93. */
  94. if (!(in & SSB_GPIO_XTAL)) {
  95. if (what & SSB_GPIO_XTAL) {
  96. /* Turn the crystal on */
  97. out |= SSB_GPIO_XTAL;
  98. if (what & SSB_GPIO_PLL)
  99. out |= SSB_GPIO_PLL;
  100. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  101. if (err)
  102. goto err_pci;
  103. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
  104. outenable);
  105. if (err)
  106. goto err_pci;
  107. msleep(1);
  108. }
  109. if (what & SSB_GPIO_PLL) {
  110. /* Turn the PLL on */
  111. out &= ~SSB_GPIO_PLL;
  112. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  113. if (err)
  114. goto err_pci;
  115. msleep(5);
  116. }
  117. }
  118. err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
  119. if (err)
  120. goto err_pci;
  121. pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
  122. err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
  123. if (err)
  124. goto err_pci;
  125. } else {
  126. if (what & SSB_GPIO_XTAL) {
  127. /* Turn the crystal off */
  128. out &= ~SSB_GPIO_XTAL;
  129. }
  130. if (what & SSB_GPIO_PLL) {
  131. /* Turn the PLL off */
  132. out |= SSB_GPIO_PLL;
  133. }
  134. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  135. if (err)
  136. goto err_pci;
  137. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
  138. if (err)
  139. goto err_pci;
  140. }
  141. out:
  142. return err;
  143. err_pci:
  144. printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
  145. err = -EBUSY;
  146. goto out;
  147. }
  148. /* Get the word-offset for a SSB_SPROM_XXX define. */
  149. #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
  150. /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
  151. #define SPEX(_outvar, _offset, _mask, _shift) \
  152. out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
  153. static inline u8 ssb_crc8(u8 crc, u8 data)
  154. {
  155. /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
  156. static const u8 t[] = {
  157. 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
  158. 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
  159. 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
  160. 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
  161. 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
  162. 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
  163. 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
  164. 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
  165. 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
  166. 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
  167. 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
  168. 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
  169. 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
  170. 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
  171. 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
  172. 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
  173. 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
  174. 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
  175. 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
  176. 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
  177. 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
  178. 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
  179. 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
  180. 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
  181. 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
  182. 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
  183. 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
  184. 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
  185. 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
  186. 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
  187. 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
  188. 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
  189. };
  190. return t[crc ^ data];
  191. }
  192. static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
  193. {
  194. int word;
  195. u8 crc = 0xFF;
  196. for (word = 0; word < size - 1; word++) {
  197. crc = ssb_crc8(crc, sprom[word] & 0x00FF);
  198. crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
  199. }
  200. crc = ssb_crc8(crc, sprom[size - 1] & 0x00FF);
  201. crc ^= 0xFF;
  202. return crc;
  203. }
  204. static int sprom_check_crc(const u16 *sprom, size_t size)
  205. {
  206. u8 crc;
  207. u8 expected_crc;
  208. u16 tmp;
  209. crc = ssb_sprom_crc(sprom, size);
  210. tmp = sprom[size - 1] & SSB_SPROM_REVISION_CRC;
  211. expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
  212. if (crc != expected_crc)
  213. return -EPROTO;
  214. return 0;
  215. }
  216. static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
  217. {
  218. int i;
  219. for (i = 0; i < bus->sprom_size; i++)
  220. sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
  221. return 0;
  222. }
  223. static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
  224. {
  225. struct pci_dev *pdev = bus->host_pci;
  226. int i, err;
  227. u32 spromctl;
  228. u16 size = bus->sprom_size;
  229. ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
  230. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  231. if (err)
  232. goto err_ctlreg;
  233. spromctl |= SSB_SPROMCTL_WE;
  234. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  235. if (err)
  236. goto err_ctlreg;
  237. ssb_printk(KERN_NOTICE PFX "[ 0%%");
  238. msleep(500);
  239. for (i = 0; i < size; i++) {
  240. if (i == size / 4)
  241. ssb_printk("25%%");
  242. else if (i == size / 2)
  243. ssb_printk("50%%");
  244. else if (i == (size * 3) / 4)
  245. ssb_printk("75%%");
  246. else if (i % 2)
  247. ssb_printk(".");
  248. writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
  249. mmiowb();
  250. msleep(20);
  251. }
  252. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  253. if (err)
  254. goto err_ctlreg;
  255. spromctl &= ~SSB_SPROMCTL_WE;
  256. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  257. if (err)
  258. goto err_ctlreg;
  259. msleep(500);
  260. ssb_printk("100%% ]\n");
  261. ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
  262. return 0;
  263. err_ctlreg:
  264. ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
  265. return err;
  266. }
  267. static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
  268. u16 mask, u16 shift)
  269. {
  270. u16 v;
  271. u8 gain;
  272. v = in[SPOFF(SSB_SPROM1_AGAIN)];
  273. gain = (v & mask) >> shift;
  274. if (gain == 0xFF)
  275. gain = 2; /* If unset use 2dBm */
  276. if (sprom_revision == 1) {
  277. /* Convert to Q5.2 */
  278. gain <<= 2;
  279. } else {
  280. /* Q5.2 Fractional part is stored in 0xC0 */
  281. gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
  282. }
  283. return (s8)gain;
  284. }
  285. static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
  286. {
  287. int i;
  288. u16 v;
  289. s8 gain;
  290. u16 loc[3];
  291. if (out->revision == 3) { /* rev 3 moved MAC */
  292. loc[0] = SSB_SPROM3_IL0MAC;
  293. loc[1] = SSB_SPROM3_ET0MAC;
  294. loc[2] = SSB_SPROM3_ET1MAC;
  295. } else {
  296. loc[0] = SSB_SPROM1_IL0MAC;
  297. loc[1] = SSB_SPROM1_ET0MAC;
  298. loc[2] = SSB_SPROM1_ET1MAC;
  299. }
  300. for (i = 0; i < 3; i++) {
  301. v = in[SPOFF(loc[0]) + i];
  302. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  303. }
  304. for (i = 0; i < 3; i++) {
  305. v = in[SPOFF(loc[1]) + i];
  306. *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
  307. }
  308. for (i = 0; i < 3; i++) {
  309. v = in[SPOFF(loc[2]) + i];
  310. *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
  311. }
  312. SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
  313. SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
  314. SSB_SPROM1_ETHPHY_ET1A_SHIFT);
  315. SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
  316. SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
  317. SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
  318. SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
  319. SSB_SPROM1_BINF_CCODE_SHIFT);
  320. SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
  321. SSB_SPROM1_BINF_ANTA_SHIFT);
  322. SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
  323. SSB_SPROM1_BINF_ANTBG_SHIFT);
  324. SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
  325. SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
  326. SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
  327. SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
  328. SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
  329. SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
  330. SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
  331. SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
  332. SSB_SPROM1_GPIOA_P1_SHIFT);
  333. SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
  334. SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
  335. SSB_SPROM1_GPIOB_P3_SHIFT);
  336. SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
  337. SSB_SPROM1_MAXPWR_A_SHIFT);
  338. SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
  339. SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
  340. SSB_SPROM1_ITSSI_A_SHIFT);
  341. SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
  342. SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
  343. if (out->revision >= 2)
  344. SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  345. /* Extract the antenna gain values. */
  346. gain = r123_extract_antgain(out->revision, in,
  347. SSB_SPROM1_AGAIN_BG,
  348. SSB_SPROM1_AGAIN_BG_SHIFT);
  349. out->antenna_gain.ghz24.a0 = gain;
  350. out->antenna_gain.ghz24.a1 = gain;
  351. out->antenna_gain.ghz24.a2 = gain;
  352. out->antenna_gain.ghz24.a3 = gain;
  353. gain = r123_extract_antgain(out->revision, in,
  354. SSB_SPROM1_AGAIN_A,
  355. SSB_SPROM1_AGAIN_A_SHIFT);
  356. out->antenna_gain.ghz5.a0 = gain;
  357. out->antenna_gain.ghz5.a1 = gain;
  358. out->antenna_gain.ghz5.a2 = gain;
  359. out->antenna_gain.ghz5.a3 = gain;
  360. }
  361. static void sprom_extract_r4(struct ssb_sprom *out, const u16 *in)
  362. {
  363. int i;
  364. u16 v;
  365. /* extract the equivalent of the r1 variables */
  366. for (i = 0; i < 3; i++) {
  367. v = in[SPOFF(SSB_SPROM4_IL0MAC) + i];
  368. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  369. }
  370. for (i = 0; i < 3; i++) {
  371. v = in[SPOFF(SSB_SPROM4_ET0MAC) + i];
  372. *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
  373. }
  374. for (i = 0; i < 3; i++) {
  375. v = in[SPOFF(SSB_SPROM4_ET1MAC) + i];
  376. *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
  377. }
  378. SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
  379. SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
  380. SSB_SPROM4_ETHPHY_ET1A_SHIFT);
  381. SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
  382. SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
  383. SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
  384. SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
  385. SSB_SPROM4_ANTAVAIL_A_SHIFT);
  386. SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
  387. SSB_SPROM4_ANTAVAIL_BG_SHIFT);
  388. SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
  389. SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
  390. SSB_SPROM4_ITSSI_BG_SHIFT);
  391. SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
  392. SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
  393. SSB_SPROM4_ITSSI_A_SHIFT);
  394. SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
  395. SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
  396. SSB_SPROM4_GPIOA_P1_SHIFT);
  397. SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
  398. SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
  399. SSB_SPROM4_GPIOB_P3_SHIFT);
  400. /* Extract the antenna gain values. */
  401. SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
  402. SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
  403. SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
  404. SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
  405. SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
  406. SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
  407. SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
  408. SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
  409. memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
  410. sizeof(out->antenna_gain.ghz5));
  411. /* TODO - get remaining rev 4 stuff needed */
  412. }
  413. static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
  414. const u16 *in, u16 size)
  415. {
  416. memset(out, 0, sizeof(*out));
  417. out->revision = in[size - 1] & 0x00FF;
  418. ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
  419. if ((bus->chip_id & 0xFF00) == 0x4400) {
  420. /* Workaround: The BCM44XX chip has a stupid revision
  421. * number stored in the SPROM.
  422. * Always extract r1. */
  423. out->revision = 1;
  424. sprom_extract_r123(out, in);
  425. } else if (bus->chip_id == 0x4321) {
  426. /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
  427. out->revision = 4;
  428. sprom_extract_r4(out, in);
  429. } else {
  430. if (out->revision == 0)
  431. goto unsupported;
  432. if (out->revision >= 1 && out->revision <= 3) {
  433. sprom_extract_r123(out, in);
  434. }
  435. if (out->revision == 4)
  436. sprom_extract_r4(out, in);
  437. if (out->revision >= 5)
  438. goto unsupported;
  439. }
  440. if (out->boardflags_lo == 0xFFFF)
  441. out->boardflags_lo = 0; /* per specs */
  442. if (out->boardflags_hi == 0xFFFF)
  443. out->boardflags_hi = 0; /* per specs */
  444. return 0;
  445. unsupported:
  446. ssb_printk(KERN_WARNING PFX "Unsupported SPROM revision %d "
  447. "detected. Will extract v1\n", out->revision);
  448. sprom_extract_r123(out, in);
  449. return 0;
  450. }
  451. static int ssb_pci_sprom_get(struct ssb_bus *bus,
  452. struct ssb_sprom *sprom)
  453. {
  454. int err = -ENOMEM;
  455. u16 *buf;
  456. buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
  457. if (!buf)
  458. goto out;
  459. bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
  460. sprom_do_read(bus, buf);
  461. err = sprom_check_crc(buf, bus->sprom_size);
  462. if (err) {
  463. /* try for a 440 byte SPROM - revision 4 and higher */
  464. kfree(buf);
  465. buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
  466. GFP_KERNEL);
  467. if (!buf)
  468. goto out;
  469. bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
  470. sprom_do_read(bus, buf);
  471. err = sprom_check_crc(buf, bus->sprom_size);
  472. if (err)
  473. ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
  474. " SPROM CRC (corrupt SPROM)\n");
  475. }
  476. err = sprom_extract(bus, sprom, buf, bus->sprom_size);
  477. kfree(buf);
  478. out:
  479. return err;
  480. }
  481. static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
  482. struct ssb_boardinfo *bi)
  483. {
  484. pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
  485. &bi->vendor);
  486. pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
  487. &bi->type);
  488. pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
  489. &bi->rev);
  490. }
  491. int ssb_pci_get_invariants(struct ssb_bus *bus,
  492. struct ssb_init_invariants *iv)
  493. {
  494. int err;
  495. err = ssb_pci_sprom_get(bus, &iv->sprom);
  496. if (err)
  497. goto out;
  498. ssb_pci_get_boardinfo(bus, &iv->boardinfo);
  499. out:
  500. return err;
  501. }
  502. #ifdef CONFIG_SSB_DEBUG
  503. static int ssb_pci_assert_buspower(struct ssb_bus *bus)
  504. {
  505. if (likely(bus->powered_up))
  506. return 0;
  507. printk(KERN_ERR PFX "FATAL ERROR: Bus powered down "
  508. "while accessing PCI MMIO space\n");
  509. if (bus->power_warn_count <= 10) {
  510. bus->power_warn_count++;
  511. dump_stack();
  512. }
  513. return -ENODEV;
  514. }
  515. #else /* DEBUG */
  516. static inline int ssb_pci_assert_buspower(struct ssb_bus *bus)
  517. {
  518. return 0;
  519. }
  520. #endif /* DEBUG */
  521. static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
  522. {
  523. struct ssb_bus *bus = dev->bus;
  524. if (unlikely(ssb_pci_assert_buspower(bus)))
  525. return 0xFF;
  526. if (unlikely(bus->mapped_device != dev)) {
  527. if (unlikely(ssb_pci_switch_core(bus, dev)))
  528. return 0xFF;
  529. }
  530. return ioread8(bus->mmio + offset);
  531. }
  532. static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
  533. {
  534. struct ssb_bus *bus = dev->bus;
  535. if (unlikely(ssb_pci_assert_buspower(bus)))
  536. return 0xFFFF;
  537. if (unlikely(bus->mapped_device != dev)) {
  538. if (unlikely(ssb_pci_switch_core(bus, dev)))
  539. return 0xFFFF;
  540. }
  541. return ioread16(bus->mmio + offset);
  542. }
  543. static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
  544. {
  545. struct ssb_bus *bus = dev->bus;
  546. if (unlikely(ssb_pci_assert_buspower(bus)))
  547. return 0xFFFFFFFF;
  548. if (unlikely(bus->mapped_device != dev)) {
  549. if (unlikely(ssb_pci_switch_core(bus, dev)))
  550. return 0xFFFFFFFF;
  551. }
  552. return ioread32(bus->mmio + offset);
  553. }
  554. #ifdef CONFIG_SSB_BLOCKIO
  555. static void ssb_pci_block_read(struct ssb_device *dev, void *buffer,
  556. size_t count, u16 offset, u8 reg_width)
  557. {
  558. struct ssb_bus *bus = dev->bus;
  559. void __iomem *addr = bus->mmio + offset;
  560. if (unlikely(ssb_pci_assert_buspower(bus)))
  561. goto error;
  562. if (unlikely(bus->mapped_device != dev)) {
  563. if (unlikely(ssb_pci_switch_core(bus, dev)))
  564. goto error;
  565. }
  566. switch (reg_width) {
  567. case sizeof(u8):
  568. ioread8_rep(addr, buffer, count);
  569. break;
  570. case sizeof(u16):
  571. SSB_WARN_ON(count & 1);
  572. ioread16_rep(addr, buffer, count >> 1);
  573. break;
  574. case sizeof(u32):
  575. SSB_WARN_ON(count & 3);
  576. ioread32_rep(addr, buffer, count >> 2);
  577. break;
  578. default:
  579. SSB_WARN_ON(1);
  580. }
  581. return;
  582. error:
  583. memset(buffer, 0xFF, count);
  584. }
  585. #endif /* CONFIG_SSB_BLOCKIO */
  586. static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
  587. {
  588. struct ssb_bus *bus = dev->bus;
  589. if (unlikely(ssb_pci_assert_buspower(bus)))
  590. return;
  591. if (unlikely(bus->mapped_device != dev)) {
  592. if (unlikely(ssb_pci_switch_core(bus, dev)))
  593. return;
  594. }
  595. iowrite8(value, bus->mmio + offset);
  596. }
  597. static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
  598. {
  599. struct ssb_bus *bus = dev->bus;
  600. if (unlikely(ssb_pci_assert_buspower(bus)))
  601. return;
  602. if (unlikely(bus->mapped_device != dev)) {
  603. if (unlikely(ssb_pci_switch_core(bus, dev)))
  604. return;
  605. }
  606. iowrite16(value, bus->mmio + offset);
  607. }
  608. static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
  609. {
  610. struct ssb_bus *bus = dev->bus;
  611. if (unlikely(ssb_pci_assert_buspower(bus)))
  612. return;
  613. if (unlikely(bus->mapped_device != dev)) {
  614. if (unlikely(ssb_pci_switch_core(bus, dev)))
  615. return;
  616. }
  617. iowrite32(value, bus->mmio + offset);
  618. }
  619. #ifdef CONFIG_SSB_BLOCKIO
  620. static void ssb_pci_block_write(struct ssb_device *dev, const void *buffer,
  621. size_t count, u16 offset, u8 reg_width)
  622. {
  623. struct ssb_bus *bus = dev->bus;
  624. void __iomem *addr = bus->mmio + offset;
  625. if (unlikely(ssb_pci_assert_buspower(bus)))
  626. return;
  627. if (unlikely(bus->mapped_device != dev)) {
  628. if (unlikely(ssb_pci_switch_core(bus, dev)))
  629. return;
  630. }
  631. switch (reg_width) {
  632. case sizeof(u8):
  633. iowrite8_rep(addr, buffer, count);
  634. break;
  635. case sizeof(u16):
  636. SSB_WARN_ON(count & 1);
  637. iowrite16_rep(addr, buffer, count >> 1);
  638. break;
  639. case sizeof(u32):
  640. SSB_WARN_ON(count & 3);
  641. iowrite32_rep(addr, buffer, count >> 2);
  642. break;
  643. default:
  644. SSB_WARN_ON(1);
  645. }
  646. }
  647. #endif /* CONFIG_SSB_BLOCKIO */
  648. /* Not "static", as it's used in main.c */
  649. const struct ssb_bus_ops ssb_pci_ops = {
  650. .read8 = ssb_pci_read8,
  651. .read16 = ssb_pci_read16,
  652. .read32 = ssb_pci_read32,
  653. .write8 = ssb_pci_write8,
  654. .write16 = ssb_pci_write16,
  655. .write32 = ssb_pci_write32,
  656. #ifdef CONFIG_SSB_BLOCKIO
  657. .block_read = ssb_pci_block_read,
  658. .block_write = ssb_pci_block_write,
  659. #endif
  660. };
  661. static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
  662. struct device_attribute *attr,
  663. char *buf)
  664. {
  665. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  666. struct ssb_bus *bus;
  667. bus = ssb_pci_dev_to_bus(pdev);
  668. if (!bus)
  669. return -ENODEV;
  670. return ssb_attr_sprom_show(bus, buf, sprom_do_read);
  671. }
  672. static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
  673. struct device_attribute *attr,
  674. const char *buf, size_t count)
  675. {
  676. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  677. struct ssb_bus *bus;
  678. bus = ssb_pci_dev_to_bus(pdev);
  679. if (!bus)
  680. return -ENODEV;
  681. return ssb_attr_sprom_store(bus, buf, count,
  682. sprom_check_crc, sprom_do_write);
  683. }
  684. static DEVICE_ATTR(ssb_sprom, 0600,
  685. ssb_pci_attr_sprom_show,
  686. ssb_pci_attr_sprom_store);
  687. void ssb_pci_exit(struct ssb_bus *bus)
  688. {
  689. struct pci_dev *pdev;
  690. if (bus->bustype != SSB_BUSTYPE_PCI)
  691. return;
  692. pdev = bus->host_pci;
  693. device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
  694. }
  695. int ssb_pci_init(struct ssb_bus *bus)
  696. {
  697. struct pci_dev *pdev;
  698. int err;
  699. if (bus->bustype != SSB_BUSTYPE_PCI)
  700. return 0;
  701. pdev = bus->host_pci;
  702. mutex_init(&bus->sprom_mutex);
  703. err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
  704. if (err)
  705. goto out;
  706. out:
  707. return err;
  708. }