mthca_main.c 37 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/module.h>
  35. #include <linux/init.h>
  36. #include <linux/errno.h>
  37. #include <linux/pci.h>
  38. #include <linux/interrupt.h>
  39. #include "mthca_dev.h"
  40. #include "mthca_config_reg.h"
  41. #include "mthca_cmd.h"
  42. #include "mthca_profile.h"
  43. #include "mthca_memfree.h"
  44. #include "mthca_wqe.h"
  45. MODULE_AUTHOR("Roland Dreier");
  46. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  47. MODULE_LICENSE("Dual BSD/GPL");
  48. MODULE_VERSION(DRV_VERSION);
  49. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  50. int mthca_debug_level = 0;
  51. module_param_named(debug_level, mthca_debug_level, int, 0644);
  52. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  53. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  54. #ifdef CONFIG_PCI_MSI
  55. static int msi_x = 1;
  56. module_param(msi_x, int, 0444);
  57. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #endif /* CONFIG_PCI_MSI */
  61. static int tune_pci = 0;
  62. module_param(tune_pci, int, 0444);
  63. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  64. DEFINE_MUTEX(mthca_device_mutex);
  65. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  66. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  67. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  68. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  69. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  70. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  71. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  72. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  73. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  74. static struct mthca_profile hca_profile = {
  75. .num_qp = MTHCA_DEFAULT_NUM_QP,
  76. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  77. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  78. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  79. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  80. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  81. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  82. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  83. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  84. };
  85. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  86. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  87. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  88. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  89. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  90. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  91. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  92. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  93. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  94. MODULE_PARM_DESC(num_mpt,
  95. "maximum number of memory protection table entries per HCA");
  96. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  97. MODULE_PARM_DESC(num_mtt,
  98. "maximum number of memory translation table segments per HCA");
  99. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  100. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  101. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  102. MODULE_PARM_DESC(fmr_reserved_mtts,
  103. "number of memory translation table segments reserved for FMR");
  104. static char mthca_version[] __devinitdata =
  105. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  106. DRV_VERSION " (" DRV_RELDATE ")\n";
  107. static int mthca_tune_pci(struct mthca_dev *mdev)
  108. {
  109. if (!tune_pci)
  110. return 0;
  111. /* First try to max out Read Byte Count */
  112. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
  113. if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
  114. mthca_err(mdev, "Couldn't set PCI-X max read count, "
  115. "aborting.\n");
  116. return -ENODEV;
  117. }
  118. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  119. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  120. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) {
  121. if (pcie_set_readrq(mdev->pdev, 4096)) {
  122. mthca_err(mdev, "Couldn't write PCI Express read request, "
  123. "aborting.\n");
  124. return -ENODEV;
  125. }
  126. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  127. mthca_info(mdev, "No PCI Express capability, "
  128. "not setting Max Read Request Size.\n");
  129. return 0;
  130. }
  131. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  132. {
  133. int err;
  134. u8 status;
  135. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  136. if (err) {
  137. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  138. return err;
  139. }
  140. if (status) {
  141. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  142. "aborting.\n", status);
  143. return -EINVAL;
  144. }
  145. if (dev_lim->min_page_sz > PAGE_SIZE) {
  146. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  147. "kernel PAGE_SIZE of %ld, aborting.\n",
  148. dev_lim->min_page_sz, PAGE_SIZE);
  149. return -ENODEV;
  150. }
  151. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  152. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  153. "aborting.\n",
  154. dev_lim->num_ports, MTHCA_MAX_PORTS);
  155. return -ENODEV;
  156. }
  157. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  158. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  159. "PCI resource 2 size of 0x%llx, aborting.\n",
  160. dev_lim->uar_size,
  161. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  162. return -ENODEV;
  163. }
  164. mdev->limits.num_ports = dev_lim->num_ports;
  165. mdev->limits.vl_cap = dev_lim->max_vl;
  166. mdev->limits.mtu_cap = dev_lim->max_mtu;
  167. mdev->limits.gid_table_len = dev_lim->max_gids;
  168. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  169. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  170. /*
  171. * Need to allow for worst case send WQE overhead and check
  172. * whether max_desc_sz imposes a lower limit than max_sg; UD
  173. * send has the biggest overhead.
  174. */
  175. mdev->limits.max_sg = min_t(int, dev_lim->max_sg,
  176. (dev_lim->max_desc_sz -
  177. sizeof (struct mthca_next_seg) -
  178. (mthca_is_memfree(mdev) ?
  179. sizeof (struct mthca_arbel_ud_seg) :
  180. sizeof (struct mthca_tavor_ud_seg))) /
  181. sizeof (struct mthca_data_seg));
  182. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  183. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  184. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  185. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  186. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  187. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  188. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  189. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  190. /*
  191. * Subtract 1 from the limit because we need to allocate a
  192. * spare CQE so the HCA HW can tell the difference between an
  193. * empty CQ and a full CQ.
  194. */
  195. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  196. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  197. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  198. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  199. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  200. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  201. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  202. mdev->limits.port_width_cap = dev_lim->max_port_width;
  203. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  204. mdev->limits.flags = dev_lim->flags;
  205. /*
  206. * For old FW that doesn't return static rate support, use a
  207. * value of 0x3 (only static rate values of 0 or 1 are handled),
  208. * except on Sinai, where even old FW can handle static rate
  209. * values of 2 and 3.
  210. */
  211. if (dev_lim->stat_rate_support)
  212. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  213. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  214. mdev->limits.stat_rate_support = 0xf;
  215. else
  216. mdev->limits.stat_rate_support = 0x3;
  217. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  218. May be doable since hardware supports it for SRQ.
  219. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  220. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  221. supported by driver. */
  222. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  223. IB_DEVICE_PORT_ACTIVE_EVENT |
  224. IB_DEVICE_SYS_IMAGE_GUID |
  225. IB_DEVICE_RC_RNR_NAK_GEN;
  226. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  227. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  228. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  229. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  230. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  231. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  232. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  233. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  234. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  235. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  236. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  237. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  238. if (mthca_is_memfree(mdev))
  239. if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
  240. mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  241. return 0;
  242. }
  243. static int mthca_init_tavor(struct mthca_dev *mdev)
  244. {
  245. s64 size;
  246. u8 status;
  247. int err;
  248. struct mthca_dev_lim dev_lim;
  249. struct mthca_profile profile;
  250. struct mthca_init_hca_param init_hca;
  251. err = mthca_SYS_EN(mdev, &status);
  252. if (err) {
  253. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  254. return err;
  255. }
  256. if (status) {
  257. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  258. "aborting.\n", status);
  259. return -EINVAL;
  260. }
  261. err = mthca_QUERY_FW(mdev, &status);
  262. if (err) {
  263. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  264. goto err_disable;
  265. }
  266. if (status) {
  267. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  268. "aborting.\n", status);
  269. err = -EINVAL;
  270. goto err_disable;
  271. }
  272. err = mthca_QUERY_DDR(mdev, &status);
  273. if (err) {
  274. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  275. goto err_disable;
  276. }
  277. if (status) {
  278. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  279. "aborting.\n", status);
  280. err = -EINVAL;
  281. goto err_disable;
  282. }
  283. err = mthca_dev_lim(mdev, &dev_lim);
  284. if (err) {
  285. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  286. goto err_disable;
  287. }
  288. profile = hca_profile;
  289. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  290. profile.uarc_size = 0;
  291. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  292. profile.num_srq = dev_lim.max_srqs;
  293. size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  294. if (size < 0) {
  295. err = size;
  296. goto err_disable;
  297. }
  298. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  299. if (err) {
  300. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  301. goto err_disable;
  302. }
  303. if (status) {
  304. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  305. "aborting.\n", status);
  306. err = -EINVAL;
  307. goto err_disable;
  308. }
  309. return 0;
  310. err_disable:
  311. mthca_SYS_DIS(mdev, &status);
  312. return err;
  313. }
  314. static int mthca_load_fw(struct mthca_dev *mdev)
  315. {
  316. u8 status;
  317. int err;
  318. /* FIXME: use HCA-attached memory for FW if present */
  319. mdev->fw.arbel.fw_icm =
  320. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  321. GFP_HIGHUSER | __GFP_NOWARN, 0);
  322. if (!mdev->fw.arbel.fw_icm) {
  323. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  324. return -ENOMEM;
  325. }
  326. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  327. if (err) {
  328. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  329. goto err_free;
  330. }
  331. if (status) {
  332. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  333. err = -EINVAL;
  334. goto err_free;
  335. }
  336. err = mthca_RUN_FW(mdev, &status);
  337. if (err) {
  338. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  339. goto err_unmap_fa;
  340. }
  341. if (status) {
  342. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  343. err = -EINVAL;
  344. goto err_unmap_fa;
  345. }
  346. return 0;
  347. err_unmap_fa:
  348. mthca_UNMAP_FA(mdev, &status);
  349. err_free:
  350. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  351. return err;
  352. }
  353. static int mthca_init_icm(struct mthca_dev *mdev,
  354. struct mthca_dev_lim *dev_lim,
  355. struct mthca_init_hca_param *init_hca,
  356. u64 icm_size)
  357. {
  358. u64 aux_pages;
  359. u8 status;
  360. int err;
  361. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  362. if (err) {
  363. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  364. return err;
  365. }
  366. if (status) {
  367. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  368. "aborting.\n", status);
  369. return -EINVAL;
  370. }
  371. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  372. (unsigned long long) icm_size >> 10,
  373. (unsigned long long) aux_pages << 2);
  374. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  375. GFP_HIGHUSER | __GFP_NOWARN, 0);
  376. if (!mdev->fw.arbel.aux_icm) {
  377. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  378. return -ENOMEM;
  379. }
  380. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  381. if (err) {
  382. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  383. goto err_free_aux;
  384. }
  385. if (status) {
  386. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  387. err = -EINVAL;
  388. goto err_free_aux;
  389. }
  390. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  391. if (err) {
  392. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  393. goto err_unmap_aux;
  394. }
  395. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  396. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * MTHCA_MTT_SEG_SIZE,
  397. dma_get_cache_alignment()) / MTHCA_MTT_SEG_SIZE;
  398. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  399. MTHCA_MTT_SEG_SIZE,
  400. mdev->limits.num_mtt_segs,
  401. mdev->limits.reserved_mtts,
  402. 1, 0);
  403. if (!mdev->mr_table.mtt_table) {
  404. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  405. err = -ENOMEM;
  406. goto err_unmap_eq;
  407. }
  408. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  409. dev_lim->mpt_entry_sz,
  410. mdev->limits.num_mpts,
  411. mdev->limits.reserved_mrws,
  412. 1, 1);
  413. if (!mdev->mr_table.mpt_table) {
  414. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  415. err = -ENOMEM;
  416. goto err_unmap_mtt;
  417. }
  418. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  419. dev_lim->qpc_entry_sz,
  420. mdev->limits.num_qps,
  421. mdev->limits.reserved_qps,
  422. 0, 0);
  423. if (!mdev->qp_table.qp_table) {
  424. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  425. err = -ENOMEM;
  426. goto err_unmap_mpt;
  427. }
  428. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  429. dev_lim->eqpc_entry_sz,
  430. mdev->limits.num_qps,
  431. mdev->limits.reserved_qps,
  432. 0, 0);
  433. if (!mdev->qp_table.eqp_table) {
  434. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  435. err = -ENOMEM;
  436. goto err_unmap_qp;
  437. }
  438. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  439. MTHCA_RDB_ENTRY_SIZE,
  440. mdev->limits.num_qps <<
  441. mdev->qp_table.rdb_shift, 0,
  442. 0, 0);
  443. if (!mdev->qp_table.rdb_table) {
  444. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  445. err = -ENOMEM;
  446. goto err_unmap_eqp;
  447. }
  448. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  449. dev_lim->cqc_entry_sz,
  450. mdev->limits.num_cqs,
  451. mdev->limits.reserved_cqs,
  452. 0, 0);
  453. if (!mdev->cq_table.table) {
  454. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  455. err = -ENOMEM;
  456. goto err_unmap_rdb;
  457. }
  458. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  459. mdev->srq_table.table =
  460. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  461. dev_lim->srq_entry_sz,
  462. mdev->limits.num_srqs,
  463. mdev->limits.reserved_srqs,
  464. 0, 0);
  465. if (!mdev->srq_table.table) {
  466. mthca_err(mdev, "Failed to map SRQ context memory, "
  467. "aborting.\n");
  468. err = -ENOMEM;
  469. goto err_unmap_cq;
  470. }
  471. }
  472. /*
  473. * It's not strictly required, but for simplicity just map the
  474. * whole multicast group table now. The table isn't very big
  475. * and it's a lot easier than trying to track ref counts.
  476. */
  477. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  478. MTHCA_MGM_ENTRY_SIZE,
  479. mdev->limits.num_mgms +
  480. mdev->limits.num_amgms,
  481. mdev->limits.num_mgms +
  482. mdev->limits.num_amgms,
  483. 0, 0);
  484. if (!mdev->mcg_table.table) {
  485. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  486. err = -ENOMEM;
  487. goto err_unmap_srq;
  488. }
  489. return 0;
  490. err_unmap_srq:
  491. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  492. mthca_free_icm_table(mdev, mdev->srq_table.table);
  493. err_unmap_cq:
  494. mthca_free_icm_table(mdev, mdev->cq_table.table);
  495. err_unmap_rdb:
  496. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  497. err_unmap_eqp:
  498. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  499. err_unmap_qp:
  500. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  501. err_unmap_mpt:
  502. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  503. err_unmap_mtt:
  504. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  505. err_unmap_eq:
  506. mthca_unmap_eq_icm(mdev);
  507. err_unmap_aux:
  508. mthca_UNMAP_ICM_AUX(mdev, &status);
  509. err_free_aux:
  510. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  511. return err;
  512. }
  513. static void mthca_free_icms(struct mthca_dev *mdev)
  514. {
  515. u8 status;
  516. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  517. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  518. mthca_free_icm_table(mdev, mdev->srq_table.table);
  519. mthca_free_icm_table(mdev, mdev->cq_table.table);
  520. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  521. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  522. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  523. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  524. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  525. mthca_unmap_eq_icm(mdev);
  526. mthca_UNMAP_ICM_AUX(mdev, &status);
  527. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  528. }
  529. static int mthca_init_arbel(struct mthca_dev *mdev)
  530. {
  531. struct mthca_dev_lim dev_lim;
  532. struct mthca_profile profile;
  533. struct mthca_init_hca_param init_hca;
  534. s64 icm_size;
  535. u8 status;
  536. int err;
  537. err = mthca_QUERY_FW(mdev, &status);
  538. if (err) {
  539. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  540. return err;
  541. }
  542. if (status) {
  543. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  544. "aborting.\n", status);
  545. return -EINVAL;
  546. }
  547. err = mthca_ENABLE_LAM(mdev, &status);
  548. if (err) {
  549. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  550. return err;
  551. }
  552. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  553. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  554. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  555. } else if (status) {
  556. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  557. "aborting.\n", status);
  558. return -EINVAL;
  559. }
  560. err = mthca_load_fw(mdev);
  561. if (err) {
  562. mthca_err(mdev, "Failed to start FW, aborting.\n");
  563. goto err_disable;
  564. }
  565. err = mthca_dev_lim(mdev, &dev_lim);
  566. if (err) {
  567. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  568. goto err_stop_fw;
  569. }
  570. profile = hca_profile;
  571. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  572. profile.num_udav = 0;
  573. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  574. profile.num_srq = dev_lim.max_srqs;
  575. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  576. if (icm_size < 0) {
  577. err = icm_size;
  578. goto err_stop_fw;
  579. }
  580. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  581. if (err)
  582. goto err_stop_fw;
  583. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  584. if (err) {
  585. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  586. goto err_free_icm;
  587. }
  588. if (status) {
  589. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  590. "aborting.\n", status);
  591. err = -EINVAL;
  592. goto err_free_icm;
  593. }
  594. return 0;
  595. err_free_icm:
  596. mthca_free_icms(mdev);
  597. err_stop_fw:
  598. mthca_UNMAP_FA(mdev, &status);
  599. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  600. err_disable:
  601. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  602. mthca_DISABLE_LAM(mdev, &status);
  603. return err;
  604. }
  605. static void mthca_close_hca(struct mthca_dev *mdev)
  606. {
  607. u8 status;
  608. mthca_CLOSE_HCA(mdev, 0, &status);
  609. if (mthca_is_memfree(mdev)) {
  610. mthca_free_icms(mdev);
  611. mthca_UNMAP_FA(mdev, &status);
  612. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  613. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  614. mthca_DISABLE_LAM(mdev, &status);
  615. } else
  616. mthca_SYS_DIS(mdev, &status);
  617. }
  618. static int mthca_init_hca(struct mthca_dev *mdev)
  619. {
  620. u8 status;
  621. int err;
  622. struct mthca_adapter adapter;
  623. if (mthca_is_memfree(mdev))
  624. err = mthca_init_arbel(mdev);
  625. else
  626. err = mthca_init_tavor(mdev);
  627. if (err)
  628. return err;
  629. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  630. if (err) {
  631. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  632. goto err_close;
  633. }
  634. if (status) {
  635. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  636. "aborting.\n", status);
  637. err = -EINVAL;
  638. goto err_close;
  639. }
  640. mdev->eq_table.inta_pin = adapter.inta_pin;
  641. if (!mthca_is_memfree(mdev))
  642. mdev->rev_id = adapter.revision_id;
  643. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  644. return 0;
  645. err_close:
  646. mthca_close_hca(mdev);
  647. return err;
  648. }
  649. static int mthca_setup_hca(struct mthca_dev *dev)
  650. {
  651. int err;
  652. u8 status;
  653. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  654. err = mthca_init_uar_table(dev);
  655. if (err) {
  656. mthca_err(dev, "Failed to initialize "
  657. "user access region table, aborting.\n");
  658. return err;
  659. }
  660. err = mthca_uar_alloc(dev, &dev->driver_uar);
  661. if (err) {
  662. mthca_err(dev, "Failed to allocate driver access region, "
  663. "aborting.\n");
  664. goto err_uar_table_free;
  665. }
  666. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  667. if (!dev->kar) {
  668. mthca_err(dev, "Couldn't map kernel access region, "
  669. "aborting.\n");
  670. err = -ENOMEM;
  671. goto err_uar_free;
  672. }
  673. err = mthca_init_pd_table(dev);
  674. if (err) {
  675. mthca_err(dev, "Failed to initialize "
  676. "protection domain table, aborting.\n");
  677. goto err_kar_unmap;
  678. }
  679. err = mthca_init_mr_table(dev);
  680. if (err) {
  681. mthca_err(dev, "Failed to initialize "
  682. "memory region table, aborting.\n");
  683. goto err_pd_table_free;
  684. }
  685. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  686. if (err) {
  687. mthca_err(dev, "Failed to create driver PD, "
  688. "aborting.\n");
  689. goto err_mr_table_free;
  690. }
  691. err = mthca_init_eq_table(dev);
  692. if (err) {
  693. mthca_err(dev, "Failed to initialize "
  694. "event queue table, aborting.\n");
  695. goto err_pd_free;
  696. }
  697. err = mthca_cmd_use_events(dev);
  698. if (err) {
  699. mthca_err(dev, "Failed to switch to event-driven "
  700. "firmware commands, aborting.\n");
  701. goto err_eq_table_free;
  702. }
  703. err = mthca_NOP(dev, &status);
  704. if (err || status) {
  705. if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
  706. mthca_warn(dev, "NOP command failed to generate interrupt "
  707. "(IRQ %d).\n",
  708. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
  709. mthca_warn(dev, "Trying again with MSI-X disabled.\n");
  710. } else {
  711. mthca_err(dev, "NOP command failed to generate interrupt "
  712. "(IRQ %d), aborting.\n",
  713. dev->pdev->irq);
  714. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  715. }
  716. goto err_cmd_poll;
  717. }
  718. mthca_dbg(dev, "NOP command IRQ test passed\n");
  719. err = mthca_init_cq_table(dev);
  720. if (err) {
  721. mthca_err(dev, "Failed to initialize "
  722. "completion queue table, aborting.\n");
  723. goto err_cmd_poll;
  724. }
  725. err = mthca_init_srq_table(dev);
  726. if (err) {
  727. mthca_err(dev, "Failed to initialize "
  728. "shared receive queue table, aborting.\n");
  729. goto err_cq_table_free;
  730. }
  731. err = mthca_init_qp_table(dev);
  732. if (err) {
  733. mthca_err(dev, "Failed to initialize "
  734. "queue pair table, aborting.\n");
  735. goto err_srq_table_free;
  736. }
  737. err = mthca_init_av_table(dev);
  738. if (err) {
  739. mthca_err(dev, "Failed to initialize "
  740. "address vector table, aborting.\n");
  741. goto err_qp_table_free;
  742. }
  743. err = mthca_init_mcg_table(dev);
  744. if (err) {
  745. mthca_err(dev, "Failed to initialize "
  746. "multicast group table, aborting.\n");
  747. goto err_av_table_free;
  748. }
  749. return 0;
  750. err_av_table_free:
  751. mthca_cleanup_av_table(dev);
  752. err_qp_table_free:
  753. mthca_cleanup_qp_table(dev);
  754. err_srq_table_free:
  755. mthca_cleanup_srq_table(dev);
  756. err_cq_table_free:
  757. mthca_cleanup_cq_table(dev);
  758. err_cmd_poll:
  759. mthca_cmd_use_polling(dev);
  760. err_eq_table_free:
  761. mthca_cleanup_eq_table(dev);
  762. err_pd_free:
  763. mthca_pd_free(dev, &dev->driver_pd);
  764. err_mr_table_free:
  765. mthca_cleanup_mr_table(dev);
  766. err_pd_table_free:
  767. mthca_cleanup_pd_table(dev);
  768. err_kar_unmap:
  769. iounmap(dev->kar);
  770. err_uar_free:
  771. mthca_uar_free(dev, &dev->driver_uar);
  772. err_uar_table_free:
  773. mthca_cleanup_uar_table(dev);
  774. return err;
  775. }
  776. static int mthca_request_regions(struct pci_dev *pdev, int ddr_hidden)
  777. {
  778. int err;
  779. /*
  780. * We can't just use pci_request_regions() because the MSI-X
  781. * table is right in the middle of the first BAR. If we did
  782. * pci_request_region and grab all of the first BAR, then
  783. * setting up MSI-X would fail, since the PCI core wants to do
  784. * request_mem_region on the MSI-X vector table.
  785. *
  786. * So just request what we need right now, and request any
  787. * other regions we need when setting up EQs.
  788. */
  789. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  790. MTHCA_HCR_SIZE, DRV_NAME))
  791. return -EBUSY;
  792. err = pci_request_region(pdev, 2, DRV_NAME);
  793. if (err)
  794. goto err_bar2_failed;
  795. if (!ddr_hidden) {
  796. err = pci_request_region(pdev, 4, DRV_NAME);
  797. if (err)
  798. goto err_bar4_failed;
  799. }
  800. return 0;
  801. err_bar4_failed:
  802. pci_release_region(pdev, 2);
  803. err_bar2_failed:
  804. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  805. MTHCA_HCR_SIZE);
  806. return err;
  807. }
  808. static void mthca_release_regions(struct pci_dev *pdev,
  809. int ddr_hidden)
  810. {
  811. if (!ddr_hidden)
  812. pci_release_region(pdev, 4);
  813. pci_release_region(pdev, 2);
  814. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  815. MTHCA_HCR_SIZE);
  816. }
  817. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  818. {
  819. struct msix_entry entries[3];
  820. int err;
  821. entries[0].entry = 0;
  822. entries[1].entry = 1;
  823. entries[2].entry = 2;
  824. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  825. if (err) {
  826. if (err > 0)
  827. mthca_info(mdev, "Only %d MSI-X vectors available, "
  828. "not using MSI-X\n", err);
  829. return err;
  830. }
  831. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  832. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  833. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  834. return 0;
  835. }
  836. /* Types of supported HCA */
  837. enum {
  838. TAVOR, /* MT23108 */
  839. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  840. ARBEL_NATIVE, /* MT25208 with extended features */
  841. SINAI /* MT25204 */
  842. };
  843. #define MTHCA_FW_VER(major, minor, subminor) \
  844. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  845. static struct {
  846. u64 latest_fw;
  847. u32 flags;
  848. } mthca_hca_table[] = {
  849. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  850. .flags = 0 },
  851. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  852. .flags = MTHCA_FLAG_PCIE },
  853. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
  854. .flags = MTHCA_FLAG_MEMFREE |
  855. MTHCA_FLAG_PCIE },
  856. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  857. .flags = MTHCA_FLAG_MEMFREE |
  858. MTHCA_FLAG_PCIE |
  859. MTHCA_FLAG_SINAI_OPT }
  860. };
  861. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  862. {
  863. int ddr_hidden = 0;
  864. int err;
  865. struct mthca_dev *mdev;
  866. printk(KERN_INFO PFX "Initializing %s\n",
  867. pci_name(pdev));
  868. err = pci_enable_device(pdev);
  869. if (err) {
  870. dev_err(&pdev->dev, "Cannot enable PCI device, "
  871. "aborting.\n");
  872. return err;
  873. }
  874. /*
  875. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  876. * be present)
  877. */
  878. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  879. pci_resource_len(pdev, 0) != 1 << 20) {
  880. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  881. err = -ENODEV;
  882. goto err_disable_pdev;
  883. }
  884. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  885. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  886. err = -ENODEV;
  887. goto err_disable_pdev;
  888. }
  889. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  890. ddr_hidden = 1;
  891. err = mthca_request_regions(pdev, ddr_hidden);
  892. if (err) {
  893. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  894. "aborting.\n");
  895. goto err_disable_pdev;
  896. }
  897. pci_set_master(pdev);
  898. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  899. if (err) {
  900. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  901. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  902. if (err) {
  903. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  904. goto err_free_res;
  905. }
  906. }
  907. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  908. if (err) {
  909. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  910. "consistent PCI DMA mask.\n");
  911. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  912. if (err) {
  913. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  914. "aborting.\n");
  915. goto err_free_res;
  916. }
  917. }
  918. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  919. if (!mdev) {
  920. dev_err(&pdev->dev, "Device struct alloc failed, "
  921. "aborting.\n");
  922. err = -ENOMEM;
  923. goto err_free_res;
  924. }
  925. mdev->pdev = pdev;
  926. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  927. if (ddr_hidden)
  928. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  929. /*
  930. * Now reset the HCA before we touch the PCI capabilities or
  931. * attempt a firmware command, since a boot ROM may have left
  932. * the HCA in an undefined state.
  933. */
  934. err = mthca_reset(mdev);
  935. if (err) {
  936. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  937. goto err_free_dev;
  938. }
  939. if (mthca_cmd_init(mdev)) {
  940. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  941. goto err_free_dev;
  942. }
  943. err = mthca_tune_pci(mdev);
  944. if (err)
  945. goto err_cmd;
  946. err = mthca_init_hca(mdev);
  947. if (err)
  948. goto err_cmd;
  949. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  950. mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
  951. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  952. (int) (mdev->fw_ver & 0xffff),
  953. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  954. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  955. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  956. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  957. }
  958. if (msi_x && !mthca_enable_msi_x(mdev))
  959. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  960. err = mthca_setup_hca(mdev);
  961. if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
  962. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  963. pci_disable_msix(pdev);
  964. mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
  965. err = mthca_setup_hca(mdev);
  966. }
  967. if (err)
  968. goto err_close;
  969. err = mthca_register_device(mdev);
  970. if (err)
  971. goto err_cleanup;
  972. err = mthca_create_agents(mdev);
  973. if (err)
  974. goto err_unregister;
  975. pci_set_drvdata(pdev, mdev);
  976. mdev->hca_type = hca_type;
  977. return 0;
  978. err_unregister:
  979. mthca_unregister_device(mdev);
  980. err_cleanup:
  981. mthca_cleanup_mcg_table(mdev);
  982. mthca_cleanup_av_table(mdev);
  983. mthca_cleanup_qp_table(mdev);
  984. mthca_cleanup_srq_table(mdev);
  985. mthca_cleanup_cq_table(mdev);
  986. mthca_cmd_use_polling(mdev);
  987. mthca_cleanup_eq_table(mdev);
  988. mthca_pd_free(mdev, &mdev->driver_pd);
  989. mthca_cleanup_mr_table(mdev);
  990. mthca_cleanup_pd_table(mdev);
  991. mthca_cleanup_uar_table(mdev);
  992. err_close:
  993. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  994. pci_disable_msix(pdev);
  995. mthca_close_hca(mdev);
  996. err_cmd:
  997. mthca_cmd_cleanup(mdev);
  998. err_free_dev:
  999. ib_dealloc_device(&mdev->ib_dev);
  1000. err_free_res:
  1001. mthca_release_regions(pdev, ddr_hidden);
  1002. err_disable_pdev:
  1003. pci_disable_device(pdev);
  1004. pci_set_drvdata(pdev, NULL);
  1005. return err;
  1006. }
  1007. static void __mthca_remove_one(struct pci_dev *pdev)
  1008. {
  1009. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  1010. u8 status;
  1011. int p;
  1012. if (mdev) {
  1013. mthca_free_agents(mdev);
  1014. mthca_unregister_device(mdev);
  1015. for (p = 1; p <= mdev->limits.num_ports; ++p)
  1016. mthca_CLOSE_IB(mdev, p, &status);
  1017. mthca_cleanup_mcg_table(mdev);
  1018. mthca_cleanup_av_table(mdev);
  1019. mthca_cleanup_qp_table(mdev);
  1020. mthca_cleanup_srq_table(mdev);
  1021. mthca_cleanup_cq_table(mdev);
  1022. mthca_cmd_use_polling(mdev);
  1023. mthca_cleanup_eq_table(mdev);
  1024. mthca_pd_free(mdev, &mdev->driver_pd);
  1025. mthca_cleanup_mr_table(mdev);
  1026. mthca_cleanup_pd_table(mdev);
  1027. iounmap(mdev->kar);
  1028. mthca_uar_free(mdev, &mdev->driver_uar);
  1029. mthca_cleanup_uar_table(mdev);
  1030. mthca_close_hca(mdev);
  1031. mthca_cmd_cleanup(mdev);
  1032. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1033. pci_disable_msix(pdev);
  1034. ib_dealloc_device(&mdev->ib_dev);
  1035. mthca_release_regions(pdev, mdev->mthca_flags &
  1036. MTHCA_FLAG_DDR_HIDDEN);
  1037. pci_disable_device(pdev);
  1038. pci_set_drvdata(pdev, NULL);
  1039. }
  1040. }
  1041. int __mthca_restart_one(struct pci_dev *pdev)
  1042. {
  1043. struct mthca_dev *mdev;
  1044. int hca_type;
  1045. mdev = pci_get_drvdata(pdev);
  1046. if (!mdev)
  1047. return -ENODEV;
  1048. hca_type = mdev->hca_type;
  1049. __mthca_remove_one(pdev);
  1050. return __mthca_init_one(pdev, hca_type);
  1051. }
  1052. static int __devinit mthca_init_one(struct pci_dev *pdev,
  1053. const struct pci_device_id *id)
  1054. {
  1055. static int mthca_version_printed = 0;
  1056. int ret;
  1057. mutex_lock(&mthca_device_mutex);
  1058. if (!mthca_version_printed) {
  1059. printk(KERN_INFO "%s", mthca_version);
  1060. ++mthca_version_printed;
  1061. }
  1062. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  1063. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  1064. pci_name(pdev), id->driver_data);
  1065. mutex_unlock(&mthca_device_mutex);
  1066. return -ENODEV;
  1067. }
  1068. ret = __mthca_init_one(pdev, id->driver_data);
  1069. mutex_unlock(&mthca_device_mutex);
  1070. return ret;
  1071. }
  1072. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  1073. {
  1074. mutex_lock(&mthca_device_mutex);
  1075. __mthca_remove_one(pdev);
  1076. mutex_unlock(&mthca_device_mutex);
  1077. }
  1078. static struct pci_device_id mthca_pci_table[] = {
  1079. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1080. .driver_data = TAVOR },
  1081. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1082. .driver_data = TAVOR },
  1083. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1084. .driver_data = ARBEL_COMPAT },
  1085. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1086. .driver_data = ARBEL_COMPAT },
  1087. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1088. .driver_data = ARBEL_NATIVE },
  1089. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1090. .driver_data = ARBEL_NATIVE },
  1091. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1092. .driver_data = SINAI },
  1093. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1094. .driver_data = SINAI },
  1095. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1096. .driver_data = SINAI },
  1097. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1098. .driver_data = SINAI },
  1099. { 0, }
  1100. };
  1101. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1102. static struct pci_driver mthca_driver = {
  1103. .name = DRV_NAME,
  1104. .id_table = mthca_pci_table,
  1105. .probe = mthca_init_one,
  1106. .remove = __devexit_p(mthca_remove_one)
  1107. };
  1108. static void __init __mthca_check_profile_val(const char *name, int *pval,
  1109. int pval_default)
  1110. {
  1111. /* value must be positive and power of 2 */
  1112. int old_pval = *pval;
  1113. if (old_pval <= 0)
  1114. *pval = pval_default;
  1115. else
  1116. *pval = roundup_pow_of_two(old_pval);
  1117. if (old_pval != *pval) {
  1118. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  1119. old_pval, name);
  1120. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1121. }
  1122. }
  1123. #define mthca_check_profile_val(name, default) \
  1124. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1125. static void __init mthca_validate_profile(void)
  1126. {
  1127. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1128. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1129. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1130. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1131. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1132. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1133. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1134. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1135. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1136. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1137. hca_profile.fmr_reserved_mtts);
  1138. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1139. hca_profile.num_mtt);
  1140. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1141. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1142. hca_profile.fmr_reserved_mtts);
  1143. }
  1144. }
  1145. static int __init mthca_init(void)
  1146. {
  1147. int ret;
  1148. mthca_validate_profile();
  1149. ret = mthca_catas_init();
  1150. if (ret)
  1151. return ret;
  1152. ret = pci_register_driver(&mthca_driver);
  1153. if (ret < 0) {
  1154. mthca_catas_cleanup();
  1155. return ret;
  1156. }
  1157. return 0;
  1158. }
  1159. static void __exit mthca_cleanup(void)
  1160. {
  1161. pci_unregister_driver(&mthca_driver);
  1162. mthca_catas_cleanup();
  1163. }
  1164. module_init(mthca_init);
  1165. module_exit(mthca_cleanup);