fpu-internal.h 13 KB

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  1. /*
  2. * Copyright (C) 1994 Linus Torvalds
  3. *
  4. * Pentium III FXSR, SSE support
  5. * General FPU state handling cleanups
  6. * Gareth Hughes <gareth@valinux.com>, May 2000
  7. * x86-64 work by Andi Kleen 2002
  8. */
  9. #ifndef _FPU_INTERNAL_H
  10. #define _FPU_INTERNAL_H
  11. #include <linux/kernel_stat.h>
  12. #include <linux/regset.h>
  13. #include <linux/compat.h>
  14. #include <linux/slab.h>
  15. #include <asm/asm.h>
  16. #include <asm/cpufeature.h>
  17. #include <asm/processor.h>
  18. #include <asm/sigcontext.h>
  19. #include <asm/user.h>
  20. #include <asm/uaccess.h>
  21. #include <asm/xsave.h>
  22. #ifdef CONFIG_X86_64
  23. # include <asm/sigcontext32.h>
  24. # include <asm/user32.h>
  25. int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
  26. compat_sigset_t *set, struct pt_regs *regs);
  27. int ia32_setup_frame(int sig, struct k_sigaction *ka,
  28. compat_sigset_t *set, struct pt_regs *regs);
  29. #else
  30. # define user_i387_ia32_struct user_i387_struct
  31. # define user32_fxsr_struct user_fxsr_struct
  32. # define ia32_setup_frame __setup_frame
  33. # define ia32_setup_rt_frame __setup_rt_frame
  34. #endif
  35. extern unsigned int mxcsr_feature_mask;
  36. extern void fpu_init(void);
  37. DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
  38. extern void convert_from_fxsr(struct user_i387_ia32_struct *env,
  39. struct task_struct *tsk);
  40. extern void convert_to_fxsr(struct task_struct *tsk,
  41. const struct user_i387_ia32_struct *env);
  42. extern user_regset_active_fn fpregs_active, xfpregs_active;
  43. extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
  44. xstateregs_get;
  45. extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
  46. xstateregs_set;
  47. /*
  48. * xstateregs_active == fpregs_active. Please refer to the comment
  49. * at the definition of fpregs_active.
  50. */
  51. #define xstateregs_active fpregs_active
  52. #ifdef CONFIG_MATH_EMULATION
  53. # define HAVE_HWFP (boot_cpu_data.hard_math)
  54. extern void finit_soft_fpu(struct i387_soft_struct *soft);
  55. #else
  56. # define HAVE_HWFP 1
  57. static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
  58. #endif
  59. static inline int is_ia32_compat_frame(void)
  60. {
  61. return config_enabled(CONFIG_IA32_EMULATION) &&
  62. test_thread_flag(TIF_IA32);
  63. }
  64. static inline int is_ia32_frame(void)
  65. {
  66. return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame();
  67. }
  68. static inline int is_x32_frame(void)
  69. {
  70. return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32);
  71. }
  72. #define X87_FSW_ES (1 << 7) /* Exception Summary */
  73. static __always_inline __pure bool use_xsaveopt(void)
  74. {
  75. return static_cpu_has(X86_FEATURE_XSAVEOPT);
  76. }
  77. static __always_inline __pure bool use_xsave(void)
  78. {
  79. return static_cpu_has(X86_FEATURE_XSAVE);
  80. }
  81. static __always_inline __pure bool use_fxsr(void)
  82. {
  83. return static_cpu_has(X86_FEATURE_FXSR);
  84. }
  85. extern void __sanitize_i387_state(struct task_struct *);
  86. static inline void sanitize_i387_state(struct task_struct *tsk)
  87. {
  88. if (!use_xsaveopt())
  89. return;
  90. __sanitize_i387_state(tsk);
  91. }
  92. #define check_insn(insn, output, input...) \
  93. ({ \
  94. int err; \
  95. asm volatile("1:" #insn "\n\t" \
  96. "2:\n" \
  97. ".section .fixup,\"ax\"\n" \
  98. "3: movl $-1,%[err]\n" \
  99. " jmp 2b\n" \
  100. ".previous\n" \
  101. _ASM_EXTABLE(1b, 3b) \
  102. : [err] "=r" (err), output \
  103. : "0"(0), input); \
  104. err; \
  105. })
  106. static inline int fsave_user(struct i387_fsave_struct __user *fx)
  107. {
  108. return check_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
  109. }
  110. static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
  111. {
  112. if (config_enabled(CONFIG_X86_32))
  113. return check_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
  114. else if (config_enabled(CONFIG_AS_FXSAVEQ))
  115. return check_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
  116. /* See comment in fpu_fxsave() below. */
  117. return check_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
  118. }
  119. static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
  120. {
  121. if (config_enabled(CONFIG_X86_32))
  122. return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
  123. else if (config_enabled(CONFIG_AS_FXSAVEQ))
  124. return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
  125. /* See comment in fpu_fxsave() below. */
  126. return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
  127. "m" (*fx));
  128. }
  129. static inline int frstor_checking(struct i387_fsave_struct *fx)
  130. {
  131. return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
  132. }
  133. static inline void fpu_fxsave(struct fpu *fpu)
  134. {
  135. if (config_enabled(CONFIG_X86_32))
  136. asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave));
  137. else if (config_enabled(CONFIG_AS_FXSAVEQ))
  138. asm volatile("fxsaveq %0" : "=m" (fpu->state->fxsave));
  139. else {
  140. /* Using "rex64; fxsave %0" is broken because, if the memory
  141. * operand uses any extended registers for addressing, a second
  142. * REX prefix will be generated (to the assembler, rex64
  143. * followed by semicolon is a separate instruction), and hence
  144. * the 64-bitness is lost.
  145. *
  146. * Using "fxsaveq %0" would be the ideal choice, but is only
  147. * supported starting with gas 2.16.
  148. *
  149. * Using, as a workaround, the properly prefixed form below
  150. * isn't accepted by any binutils version so far released,
  151. * complaining that the same type of prefix is used twice if
  152. * an extended register is needed for addressing (fix submitted
  153. * to mainline 2005-11-21).
  154. *
  155. * asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave));
  156. *
  157. * This, however, we can work around by forcing the compiler to
  158. * select an addressing mode that doesn't require extended
  159. * registers.
  160. */
  161. asm volatile( "rex64/fxsave (%[fx])"
  162. : "=m" (fpu->state->fxsave)
  163. : [fx] "R" (&fpu->state->fxsave));
  164. }
  165. }
  166. /*
  167. * These must be called with preempt disabled. Returns
  168. * 'true' if the FPU state is still intact.
  169. */
  170. static inline int fpu_save_init(struct fpu *fpu)
  171. {
  172. if (use_xsave()) {
  173. fpu_xsave(fpu);
  174. /*
  175. * xsave header may indicate the init state of the FP.
  176. */
  177. if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
  178. return 1;
  179. } else if (use_fxsr()) {
  180. fpu_fxsave(fpu);
  181. } else {
  182. asm volatile("fnsave %[fx]; fwait"
  183. : [fx] "=m" (fpu->state->fsave));
  184. return 0;
  185. }
  186. /*
  187. * If exceptions are pending, we need to clear them so
  188. * that we don't randomly get exceptions later.
  189. *
  190. * FIXME! Is this perhaps only true for the old-style
  191. * irq13 case? Maybe we could leave the x87 state
  192. * intact otherwise?
  193. */
  194. if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
  195. asm volatile("fnclex");
  196. return 0;
  197. }
  198. return 1;
  199. }
  200. static inline int __save_init_fpu(struct task_struct *tsk)
  201. {
  202. return fpu_save_init(&tsk->thread.fpu);
  203. }
  204. static inline int fpu_restore_checking(struct fpu *fpu)
  205. {
  206. if (use_xsave())
  207. return fpu_xrstor_checking(&fpu->state->xsave);
  208. else if (use_fxsr())
  209. return fxrstor_checking(&fpu->state->fxsave);
  210. else
  211. return frstor_checking(&fpu->state->fsave);
  212. }
  213. static inline int restore_fpu_checking(struct task_struct *tsk)
  214. {
  215. /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
  216. is pending. Clear the x87 state here by setting it to fixed
  217. values. "m" is a random variable that should be in L1 */
  218. alternative_input(
  219. ASM_NOP8 ASM_NOP2,
  220. "emms\n\t" /* clear stack tags */
  221. "fildl %P[addr]", /* set F?P to defined value */
  222. X86_FEATURE_FXSAVE_LEAK,
  223. [addr] "m" (tsk->thread.fpu.has_fpu));
  224. return fpu_restore_checking(&tsk->thread.fpu);
  225. }
  226. /*
  227. * Software FPU state helpers. Careful: these need to
  228. * be preemption protection *and* they need to be
  229. * properly paired with the CR0.TS changes!
  230. */
  231. static inline int __thread_has_fpu(struct task_struct *tsk)
  232. {
  233. return tsk->thread.fpu.has_fpu;
  234. }
  235. /* Must be paired with an 'stts' after! */
  236. static inline void __thread_clear_has_fpu(struct task_struct *tsk)
  237. {
  238. tsk->thread.fpu.has_fpu = 0;
  239. this_cpu_write(fpu_owner_task, NULL);
  240. }
  241. /* Must be paired with a 'clts' before! */
  242. static inline void __thread_set_has_fpu(struct task_struct *tsk)
  243. {
  244. tsk->thread.fpu.has_fpu = 1;
  245. this_cpu_write(fpu_owner_task, tsk);
  246. }
  247. /*
  248. * Encapsulate the CR0.TS handling together with the
  249. * software flag.
  250. *
  251. * These generally need preemption protection to work,
  252. * do try to avoid using these on their own.
  253. */
  254. static inline void __thread_fpu_end(struct task_struct *tsk)
  255. {
  256. __thread_clear_has_fpu(tsk);
  257. stts();
  258. }
  259. static inline void __thread_fpu_begin(struct task_struct *tsk)
  260. {
  261. clts();
  262. __thread_set_has_fpu(tsk);
  263. }
  264. /*
  265. * FPU state switching for scheduling.
  266. *
  267. * This is a two-stage process:
  268. *
  269. * - switch_fpu_prepare() saves the old state and
  270. * sets the new state of the CR0.TS bit. This is
  271. * done within the context of the old process.
  272. *
  273. * - switch_fpu_finish() restores the new state as
  274. * necessary.
  275. */
  276. typedef struct { int preload; } fpu_switch_t;
  277. /*
  278. * FIXME! We could do a totally lazy restore, but we need to
  279. * add a per-cpu "this was the task that last touched the FPU
  280. * on this CPU" variable, and the task needs to have a "I last
  281. * touched the FPU on this CPU" and check them.
  282. *
  283. * We don't do that yet, so "fpu_lazy_restore()" always returns
  284. * false, but some day..
  285. */
  286. static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
  287. {
  288. return new == this_cpu_read_stable(fpu_owner_task) &&
  289. cpu == new->thread.fpu.last_cpu;
  290. }
  291. static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
  292. {
  293. fpu_switch_t fpu;
  294. fpu.preload = tsk_used_math(new) && new->fpu_counter > 5;
  295. if (__thread_has_fpu(old)) {
  296. if (!__save_init_fpu(old))
  297. cpu = ~0;
  298. old->thread.fpu.last_cpu = cpu;
  299. old->thread.fpu.has_fpu = 0; /* But leave fpu_owner_task! */
  300. /* Don't change CR0.TS if we just switch! */
  301. if (fpu.preload) {
  302. new->fpu_counter++;
  303. __thread_set_has_fpu(new);
  304. prefetch(new->thread.fpu.state);
  305. } else
  306. stts();
  307. } else {
  308. old->fpu_counter = 0;
  309. old->thread.fpu.last_cpu = ~0;
  310. if (fpu.preload) {
  311. new->fpu_counter++;
  312. if (fpu_lazy_restore(new, cpu))
  313. fpu.preload = 0;
  314. else
  315. prefetch(new->thread.fpu.state);
  316. __thread_fpu_begin(new);
  317. }
  318. }
  319. return fpu;
  320. }
  321. /*
  322. * By the time this gets called, we've already cleared CR0.TS and
  323. * given the process the FPU if we are going to preload the FPU
  324. * state - all we need to do is to conditionally restore the register
  325. * state itself.
  326. */
  327. static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
  328. {
  329. if (fpu.preload) {
  330. if (unlikely(restore_fpu_checking(new)))
  331. __thread_fpu_end(new);
  332. }
  333. }
  334. /*
  335. * Signal frame handlers...
  336. */
  337. extern int save_xstate_sig(void __user *buf, void __user *fx, int size);
  338. extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size);
  339. static inline int xstate_sigframe_size(void)
  340. {
  341. return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size;
  342. }
  343. static inline int restore_xstate_sig(void __user *buf, int ia32_frame)
  344. {
  345. void __user *buf_fx = buf;
  346. int size = xstate_sigframe_size();
  347. if (ia32_frame && use_fxsr()) {
  348. buf_fx = buf + sizeof(struct i387_fsave_struct);
  349. size += sizeof(struct i387_fsave_struct);
  350. }
  351. return __restore_xstate_sig(buf, buf_fx, size);
  352. }
  353. static inline void __drop_fpu(struct task_struct *tsk)
  354. {
  355. if (__thread_has_fpu(tsk)) {
  356. /* Ignore delayed exceptions from user space */
  357. asm volatile("1: fwait\n"
  358. "2:\n"
  359. _ASM_EXTABLE(1b, 2b));
  360. __thread_fpu_end(tsk);
  361. }
  362. }
  363. /*
  364. * Need to be preemption-safe.
  365. *
  366. * NOTE! user_fpu_begin() must be used only immediately before restoring
  367. * it. This function does not do any save/restore on their own.
  368. */
  369. static inline void user_fpu_begin(void)
  370. {
  371. preempt_disable();
  372. if (!user_has_fpu())
  373. __thread_fpu_begin(current);
  374. preempt_enable();
  375. }
  376. /*
  377. * These disable preemption on their own and are safe
  378. */
  379. static inline void save_init_fpu(struct task_struct *tsk)
  380. {
  381. WARN_ON_ONCE(!__thread_has_fpu(tsk));
  382. preempt_disable();
  383. __save_init_fpu(tsk);
  384. __thread_fpu_end(tsk);
  385. preempt_enable();
  386. }
  387. static inline void drop_fpu(struct task_struct *tsk)
  388. {
  389. /*
  390. * Forget coprocessor state..
  391. */
  392. tsk->fpu_counter = 0;
  393. preempt_disable();
  394. __drop_fpu(tsk);
  395. preempt_enable();
  396. clear_used_math();
  397. }
  398. /*
  399. * i387 state interaction
  400. */
  401. static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
  402. {
  403. if (cpu_has_fxsr) {
  404. return tsk->thread.fpu.state->fxsave.cwd;
  405. } else {
  406. return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
  407. }
  408. }
  409. static inline unsigned short get_fpu_swd(struct task_struct *tsk)
  410. {
  411. if (cpu_has_fxsr) {
  412. return tsk->thread.fpu.state->fxsave.swd;
  413. } else {
  414. return (unsigned short)tsk->thread.fpu.state->fsave.swd;
  415. }
  416. }
  417. static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
  418. {
  419. if (cpu_has_xmm) {
  420. return tsk->thread.fpu.state->fxsave.mxcsr;
  421. } else {
  422. return MXCSR_DEFAULT;
  423. }
  424. }
  425. static bool fpu_allocated(struct fpu *fpu)
  426. {
  427. return fpu->state != NULL;
  428. }
  429. static inline int fpu_alloc(struct fpu *fpu)
  430. {
  431. if (fpu_allocated(fpu))
  432. return 0;
  433. fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
  434. if (!fpu->state)
  435. return -ENOMEM;
  436. WARN_ON((unsigned long)fpu->state & 15);
  437. return 0;
  438. }
  439. static inline void fpu_free(struct fpu *fpu)
  440. {
  441. if (fpu->state) {
  442. kmem_cache_free(task_xstate_cachep, fpu->state);
  443. fpu->state = NULL;
  444. }
  445. }
  446. static inline void fpu_copy(struct fpu *dst, struct fpu *src)
  447. {
  448. memcpy(dst->state, src->state, xstate_size);
  449. }
  450. extern void fpu_finit(struct fpu *fpu);
  451. static inline unsigned long
  452. alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx,
  453. unsigned long *size)
  454. {
  455. unsigned long frame_size = xstate_sigframe_size();
  456. *buf_fx = sp = round_down(sp - frame_size, 64);
  457. if (ia32_frame && use_fxsr()) {
  458. frame_size += sizeof(struct i387_fsave_struct);
  459. sp -= sizeof(struct i387_fsave_struct);
  460. }
  461. *size = frame_size;
  462. return sp;
  463. }
  464. #endif