twl4030.c 59 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /* codec private data */
  117. struct twl4030_priv {
  118. unsigned int bypass_state;
  119. unsigned int codec_powered;
  120. unsigned int codec_muted;
  121. struct snd_pcm_substream *master_substream;
  122. struct snd_pcm_substream *slave_substream;
  123. unsigned int configured;
  124. unsigned int rate;
  125. unsigned int sample_bits;
  126. unsigned int channels;
  127. };
  128. /*
  129. * read twl4030 register cache
  130. */
  131. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  132. unsigned int reg)
  133. {
  134. u8 *cache = codec->reg_cache;
  135. if (reg >= TWL4030_CACHEREGNUM)
  136. return -EIO;
  137. return cache[reg];
  138. }
  139. /*
  140. * write twl4030 register cache
  141. */
  142. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  143. u8 reg, u8 value)
  144. {
  145. u8 *cache = codec->reg_cache;
  146. if (reg >= TWL4030_CACHEREGNUM)
  147. return;
  148. cache[reg] = value;
  149. }
  150. /*
  151. * write to the twl4030 register space
  152. */
  153. static int twl4030_write(struct snd_soc_codec *codec,
  154. unsigned int reg, unsigned int value)
  155. {
  156. twl4030_write_reg_cache(codec, reg, value);
  157. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  158. }
  159. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  160. {
  161. struct twl4030_priv *twl4030 = codec->private_data;
  162. u8 mode;
  163. if (enable == twl4030->codec_powered)
  164. return;
  165. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  166. if (enable)
  167. mode |= TWL4030_CODECPDZ;
  168. else
  169. mode &= ~TWL4030_CODECPDZ;
  170. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  171. twl4030->codec_powered = enable;
  172. /* REVISIT: this delay is present in TI sample drivers */
  173. /* but there seems to be no TRM requirement for it */
  174. udelay(10);
  175. }
  176. static void twl4030_init_chip(struct snd_soc_codec *codec)
  177. {
  178. int i;
  179. /* clear CODECPDZ prior to setting register defaults */
  180. twl4030_codec_enable(codec, 0);
  181. /* set all audio section registers to reasonable defaults */
  182. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  183. twl4030_write(codec, i, twl4030_reg[i]);
  184. }
  185. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  186. {
  187. struct twl4030_priv *twl4030 = codec->private_data;
  188. u8 reg_val;
  189. if (mute == twl4030->codec_muted)
  190. return;
  191. if (mute) {
  192. /* Bypass the reg_cache and mute the volumes
  193. * Headset mute is done in it's own event handler
  194. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  195. */
  196. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  197. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  198. reg_val & (~TWL4030_EAR_GAIN),
  199. TWL4030_REG_EAR_CTL);
  200. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  201. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  202. reg_val & (~TWL4030_PREDL_GAIN),
  203. TWL4030_REG_PREDL_CTL);
  204. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  205. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  206. reg_val & (~TWL4030_PREDR_GAIN),
  207. TWL4030_REG_PREDL_CTL);
  208. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  209. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  210. reg_val & (~TWL4030_PRECKL_GAIN),
  211. TWL4030_REG_PRECKL_CTL);
  212. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  213. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  214. reg_val & (~TWL4030_PRECKL_GAIN),
  215. TWL4030_REG_PRECKR_CTL);
  216. /* Disable PLL */
  217. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  218. reg_val &= ~TWL4030_APLL_EN;
  219. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  220. } else {
  221. /* Restore the volumes
  222. * Headset mute is done in it's own event handler
  223. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  224. */
  225. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  226. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  227. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  228. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  229. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  230. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  231. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  232. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  233. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  234. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  235. /* Enable PLL */
  236. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  237. reg_val |= TWL4030_APLL_EN;
  238. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  239. }
  240. twl4030->codec_muted = mute;
  241. }
  242. static void twl4030_power_up(struct snd_soc_codec *codec)
  243. {
  244. struct twl4030_priv *twl4030 = codec->private_data;
  245. u8 anamicl, regmisc1, byte;
  246. int i = 0;
  247. if (twl4030->codec_powered)
  248. return;
  249. /* set CODECPDZ to turn on codec */
  250. twl4030_codec_enable(codec, 1);
  251. /* initiate offset cancellation */
  252. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  253. twl4030_write(codec, TWL4030_REG_ANAMICL,
  254. anamicl | TWL4030_CNCL_OFFSET_START);
  255. /* wait for offset cancellation to complete */
  256. do {
  257. /* this takes a little while, so don't slam i2c */
  258. udelay(2000);
  259. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  260. TWL4030_REG_ANAMICL);
  261. } while ((i++ < 100) &&
  262. ((byte & TWL4030_CNCL_OFFSET_START) ==
  263. TWL4030_CNCL_OFFSET_START));
  264. /* Make sure that the reg_cache has the same value as the HW */
  265. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  266. /* anti-pop when changing analog gain */
  267. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  268. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  269. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  270. /* toggle CODECPDZ as per TRM */
  271. twl4030_codec_enable(codec, 0);
  272. twl4030_codec_enable(codec, 1);
  273. }
  274. /*
  275. * Unconditional power down
  276. */
  277. static void twl4030_power_down(struct snd_soc_codec *codec)
  278. {
  279. /* power down */
  280. twl4030_codec_enable(codec, 0);
  281. }
  282. /* Earpiece */
  283. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  284. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  285. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  286. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  287. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  288. };
  289. /* PreDrive Left */
  290. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  291. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  292. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  293. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  294. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  295. };
  296. /* PreDrive Right */
  297. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  298. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  299. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  300. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  301. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  302. };
  303. /* Headset Left */
  304. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  305. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  306. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  307. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  308. };
  309. /* Headset Right */
  310. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  311. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  312. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  313. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  314. };
  315. /* Carkit Left */
  316. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  317. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  318. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  319. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  320. };
  321. /* Carkit Right */
  322. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  323. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  324. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  325. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  326. };
  327. /* Handsfree Left */
  328. static const char *twl4030_handsfreel_texts[] =
  329. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  330. static const struct soc_enum twl4030_handsfreel_enum =
  331. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  332. ARRAY_SIZE(twl4030_handsfreel_texts),
  333. twl4030_handsfreel_texts);
  334. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  335. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  336. /* Handsfree Right */
  337. static const char *twl4030_handsfreer_texts[] =
  338. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  339. static const struct soc_enum twl4030_handsfreer_enum =
  340. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  341. ARRAY_SIZE(twl4030_handsfreer_texts),
  342. twl4030_handsfreer_texts);
  343. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  344. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  345. /* Vibra */
  346. /* Vibra audio path selection */
  347. static const char *twl4030_vibra_texts[] =
  348. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  349. static const struct soc_enum twl4030_vibra_enum =
  350. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  351. ARRAY_SIZE(twl4030_vibra_texts),
  352. twl4030_vibra_texts);
  353. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  354. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  355. /* Vibra path selection: local vibrator (PWM) or audio driven */
  356. static const char *twl4030_vibrapath_texts[] =
  357. {"Local vibrator", "Audio"};
  358. static const struct soc_enum twl4030_vibrapath_enum =
  359. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  360. ARRAY_SIZE(twl4030_vibrapath_texts),
  361. twl4030_vibrapath_texts);
  362. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  363. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  364. /* Left analog microphone selection */
  365. static const char *twl4030_analoglmic_texts[] =
  366. {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
  367. static const unsigned int twl4030_analoglmic_values[] =
  368. {0x0, 0x1, 0x2, 0x4, 0x8};
  369. static const struct soc_enum twl4030_analoglmic_enum =
  370. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
  371. ARRAY_SIZE(twl4030_analoglmic_texts),
  372. twl4030_analoglmic_texts,
  373. twl4030_analoglmic_values);
  374. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  375. SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
  376. /* Right analog microphone selection */
  377. static const char *twl4030_analogrmic_texts[] =
  378. {"Off", "Sub mic", "AUXR"};
  379. static const unsigned int twl4030_analogrmic_values[] =
  380. {0x0, 0x1, 0x4};
  381. static const struct soc_enum twl4030_analogrmic_enum =
  382. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
  383. ARRAY_SIZE(twl4030_analogrmic_texts),
  384. twl4030_analogrmic_texts,
  385. twl4030_analogrmic_values);
  386. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  387. SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
  388. /* TX1 L/R Analog/Digital microphone selection */
  389. static const char *twl4030_micpathtx1_texts[] =
  390. {"Analog", "Digimic0"};
  391. static const struct soc_enum twl4030_micpathtx1_enum =
  392. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  393. ARRAY_SIZE(twl4030_micpathtx1_texts),
  394. twl4030_micpathtx1_texts);
  395. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  396. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  397. /* TX2 L/R Analog/Digital microphone selection */
  398. static const char *twl4030_micpathtx2_texts[] =
  399. {"Analog", "Digimic1"};
  400. static const struct soc_enum twl4030_micpathtx2_enum =
  401. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  402. ARRAY_SIZE(twl4030_micpathtx2_texts),
  403. twl4030_micpathtx2_texts);
  404. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  405. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  406. /* Analog bypass for AudioR1 */
  407. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  408. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  409. /* Analog bypass for AudioL1 */
  410. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  411. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  412. /* Analog bypass for AudioR2 */
  413. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  414. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  415. /* Analog bypass for AudioL2 */
  416. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  417. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  418. /* Analog bypass for Voice */
  419. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  420. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  421. /* Digital bypass gain, 0 mutes the bypass */
  422. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  423. TLV_DB_RANGE_HEAD(2),
  424. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  425. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  426. };
  427. /* Digital bypass left (TX1L -> RX2L) */
  428. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  429. SOC_DAPM_SINGLE_TLV("Volume",
  430. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  431. twl4030_dapm_dbypass_tlv);
  432. /* Digital bypass right (TX1R -> RX2R) */
  433. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  434. SOC_DAPM_SINGLE_TLV("Volume",
  435. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  436. twl4030_dapm_dbypass_tlv);
  437. /*
  438. * Voice Sidetone GAIN volume control:
  439. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  440. */
  441. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  442. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  443. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  444. SOC_DAPM_SINGLE_TLV("Volume",
  445. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  446. twl4030_dapm_dbypassv_tlv);
  447. static int micpath_event(struct snd_soc_dapm_widget *w,
  448. struct snd_kcontrol *kcontrol, int event)
  449. {
  450. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  451. unsigned char adcmicsel, micbias_ctl;
  452. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  453. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  454. /* Prepare the bits for the given TX path:
  455. * shift_l == 0: TX1 microphone path
  456. * shift_l == 2: TX2 microphone path */
  457. if (e->shift_l) {
  458. /* TX2 microphone path */
  459. if (adcmicsel & TWL4030_TX2IN_SEL)
  460. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  461. else
  462. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  463. } else {
  464. /* TX1 microphone path */
  465. if (adcmicsel & TWL4030_TX1IN_SEL)
  466. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  467. else
  468. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  469. }
  470. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  471. return 0;
  472. }
  473. static int handsfree_event(struct snd_soc_dapm_widget *w,
  474. struct snd_kcontrol *kcontrol, int event)
  475. {
  476. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  477. unsigned char hs_ctl;
  478. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  479. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  480. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  481. twl4030_write(w->codec, e->reg, hs_ctl);
  482. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  483. twl4030_write(w->codec, e->reg, hs_ctl);
  484. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  485. twl4030_write(w->codec, e->reg, hs_ctl);
  486. } else {
  487. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  488. | TWL4030_HF_CTL_HB_EN);
  489. twl4030_write(w->codec, e->reg, hs_ctl);
  490. }
  491. return 0;
  492. }
  493. static int headsetl_event(struct snd_soc_dapm_widget *w,
  494. struct snd_kcontrol *kcontrol, int event)
  495. {
  496. unsigned char hs_gain, hs_pop;
  497. /* Save the current volume */
  498. hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
  499. hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
  500. switch (event) {
  501. case SND_SOC_DAPM_POST_PMU:
  502. /* Do the anti-pop/bias ramp enable according to the TRM */
  503. hs_pop |= TWL4030_VMID_EN;
  504. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  505. /* Is this needed? Can we just use whatever gain here? */
  506. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
  507. (hs_gain & (~0x0f)) | 0x0a);
  508. hs_pop |= TWL4030_RAMP_EN;
  509. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  510. /* Restore the original volume */
  511. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  512. break;
  513. case SND_SOC_DAPM_POST_PMD:
  514. /* Do the anti-pop/bias ramp disable according to the TRM */
  515. hs_pop &= ~TWL4030_RAMP_EN;
  516. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  517. /* Bypass the reg_cache to mute the headset */
  518. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  519. hs_gain & (~0x0f),
  520. TWL4030_REG_HS_GAIN_SET);
  521. hs_pop &= ~TWL4030_VMID_EN;
  522. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  523. break;
  524. }
  525. return 0;
  526. }
  527. static int bypass_event(struct snd_soc_dapm_widget *w,
  528. struct snd_kcontrol *kcontrol, int event)
  529. {
  530. struct soc_mixer_control *m =
  531. (struct soc_mixer_control *)w->kcontrols->private_value;
  532. struct twl4030_priv *twl4030 = w->codec->private_data;
  533. unsigned char reg, misc;
  534. reg = twl4030_read_reg_cache(w->codec, m->reg);
  535. if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  536. /* Analog bypass */
  537. if (reg & (1 << m->shift))
  538. twl4030->bypass_state |=
  539. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  540. else
  541. twl4030->bypass_state &=
  542. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  543. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  544. /* Analog voice bypass */
  545. if (reg & (1 << m->shift))
  546. twl4030->bypass_state |= (1 << 4);
  547. else
  548. twl4030->bypass_state &= ~(1 << 4);
  549. } else if (m->reg == TWL4030_REG_VSTPGA) {
  550. /* Voice digital bypass */
  551. if (reg)
  552. twl4030->bypass_state |= (1 << 5);
  553. else
  554. twl4030->bypass_state &= ~(1 << 5);
  555. } else {
  556. /* Digital bypass */
  557. if (reg & (0x7 << m->shift))
  558. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  559. else
  560. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  561. }
  562. /* Enable master analog loopback mode if any analog switch is enabled*/
  563. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  564. if (twl4030->bypass_state & 0x1F)
  565. misc |= TWL4030_FMLOOP_EN;
  566. else
  567. misc &= ~TWL4030_FMLOOP_EN;
  568. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  569. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  570. if (twl4030->bypass_state)
  571. twl4030_codec_mute(w->codec, 0);
  572. else
  573. twl4030_codec_mute(w->codec, 1);
  574. }
  575. return 0;
  576. }
  577. /*
  578. * Some of the gain controls in TWL (mostly those which are associated with
  579. * the outputs) are implemented in an interesting way:
  580. * 0x0 : Power down (mute)
  581. * 0x1 : 6dB
  582. * 0x2 : 0 dB
  583. * 0x3 : -6 dB
  584. * Inverting not going to help with these.
  585. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  586. */
  587. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  588. xinvert, tlv_array) \
  589. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  590. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  591. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  592. .tlv.p = (tlv_array), \
  593. .info = snd_soc_info_volsw, \
  594. .get = snd_soc_get_volsw_twl4030, \
  595. .put = snd_soc_put_volsw_twl4030, \
  596. .private_value = (unsigned long)&(struct soc_mixer_control) \
  597. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  598. .max = xmax, .invert = xinvert} }
  599. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  600. xinvert, tlv_array) \
  601. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  602. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  603. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  604. .tlv.p = (tlv_array), \
  605. .info = snd_soc_info_volsw_2r, \
  606. .get = snd_soc_get_volsw_r2_twl4030,\
  607. .put = snd_soc_put_volsw_r2_twl4030, \
  608. .private_value = (unsigned long)&(struct soc_mixer_control) \
  609. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  610. .rshift = xshift, .max = xmax, .invert = xinvert} }
  611. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  612. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  613. xinvert, tlv_array)
  614. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  615. struct snd_ctl_elem_value *ucontrol)
  616. {
  617. struct soc_mixer_control *mc =
  618. (struct soc_mixer_control *)kcontrol->private_value;
  619. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  620. unsigned int reg = mc->reg;
  621. unsigned int shift = mc->shift;
  622. unsigned int rshift = mc->rshift;
  623. int max = mc->max;
  624. int mask = (1 << fls(max)) - 1;
  625. ucontrol->value.integer.value[0] =
  626. (snd_soc_read(codec, reg) >> shift) & mask;
  627. if (ucontrol->value.integer.value[0])
  628. ucontrol->value.integer.value[0] =
  629. max + 1 - ucontrol->value.integer.value[0];
  630. if (shift != rshift) {
  631. ucontrol->value.integer.value[1] =
  632. (snd_soc_read(codec, reg) >> rshift) & mask;
  633. if (ucontrol->value.integer.value[1])
  634. ucontrol->value.integer.value[1] =
  635. max + 1 - ucontrol->value.integer.value[1];
  636. }
  637. return 0;
  638. }
  639. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  640. struct snd_ctl_elem_value *ucontrol)
  641. {
  642. struct soc_mixer_control *mc =
  643. (struct soc_mixer_control *)kcontrol->private_value;
  644. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  645. unsigned int reg = mc->reg;
  646. unsigned int shift = mc->shift;
  647. unsigned int rshift = mc->rshift;
  648. int max = mc->max;
  649. int mask = (1 << fls(max)) - 1;
  650. unsigned short val, val2, val_mask;
  651. val = (ucontrol->value.integer.value[0] & mask);
  652. val_mask = mask << shift;
  653. if (val)
  654. val = max + 1 - val;
  655. val = val << shift;
  656. if (shift != rshift) {
  657. val2 = (ucontrol->value.integer.value[1] & mask);
  658. val_mask |= mask << rshift;
  659. if (val2)
  660. val2 = max + 1 - val2;
  661. val |= val2 << rshift;
  662. }
  663. return snd_soc_update_bits(codec, reg, val_mask, val);
  664. }
  665. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  666. struct snd_ctl_elem_value *ucontrol)
  667. {
  668. struct soc_mixer_control *mc =
  669. (struct soc_mixer_control *)kcontrol->private_value;
  670. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  671. unsigned int reg = mc->reg;
  672. unsigned int reg2 = mc->rreg;
  673. unsigned int shift = mc->shift;
  674. int max = mc->max;
  675. int mask = (1<<fls(max))-1;
  676. ucontrol->value.integer.value[0] =
  677. (snd_soc_read(codec, reg) >> shift) & mask;
  678. ucontrol->value.integer.value[1] =
  679. (snd_soc_read(codec, reg2) >> shift) & mask;
  680. if (ucontrol->value.integer.value[0])
  681. ucontrol->value.integer.value[0] =
  682. max + 1 - ucontrol->value.integer.value[0];
  683. if (ucontrol->value.integer.value[1])
  684. ucontrol->value.integer.value[1] =
  685. max + 1 - ucontrol->value.integer.value[1];
  686. return 0;
  687. }
  688. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  689. struct snd_ctl_elem_value *ucontrol)
  690. {
  691. struct soc_mixer_control *mc =
  692. (struct soc_mixer_control *)kcontrol->private_value;
  693. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  694. unsigned int reg = mc->reg;
  695. unsigned int reg2 = mc->rreg;
  696. unsigned int shift = mc->shift;
  697. int max = mc->max;
  698. int mask = (1 << fls(max)) - 1;
  699. int err;
  700. unsigned short val, val2, val_mask;
  701. val_mask = mask << shift;
  702. val = (ucontrol->value.integer.value[0] & mask);
  703. val2 = (ucontrol->value.integer.value[1] & mask);
  704. if (val)
  705. val = max + 1 - val;
  706. if (val2)
  707. val2 = max + 1 - val2;
  708. val = val << shift;
  709. val2 = val2 << shift;
  710. err = snd_soc_update_bits(codec, reg, val_mask, val);
  711. if (err < 0)
  712. return err;
  713. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  714. return err;
  715. }
  716. /*
  717. * FGAIN volume control:
  718. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  719. */
  720. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  721. /*
  722. * CGAIN volume control:
  723. * 0 dB to 12 dB in 6 dB steps
  724. * value 2 and 3 means 12 dB
  725. */
  726. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  727. /*
  728. * Voice Downlink GAIN volume control:
  729. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  730. */
  731. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  732. /*
  733. * Analog playback gain
  734. * -24 dB to 12 dB in 2 dB steps
  735. */
  736. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  737. /*
  738. * Gain controls tied to outputs
  739. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  740. */
  741. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  742. /*
  743. * Gain control for earpiece amplifier
  744. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  745. */
  746. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  747. /*
  748. * Capture gain after the ADCs
  749. * from 0 dB to 31 dB in 1 dB steps
  750. */
  751. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  752. /*
  753. * Gain control for input amplifiers
  754. * 0 dB to 30 dB in 6 dB steps
  755. */
  756. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  757. static const char *twl4030_rampdelay_texts[] = {
  758. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  759. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  760. "3495/2581/1748 ms"
  761. };
  762. static const struct soc_enum twl4030_rampdelay_enum =
  763. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  764. ARRAY_SIZE(twl4030_rampdelay_texts),
  765. twl4030_rampdelay_texts);
  766. /* Vibra H-bridge direction mode */
  767. static const char *twl4030_vibradirmode_texts[] = {
  768. "Vibra H-bridge direction", "Audio data MSB",
  769. };
  770. static const struct soc_enum twl4030_vibradirmode_enum =
  771. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  772. ARRAY_SIZE(twl4030_vibradirmode_texts),
  773. twl4030_vibradirmode_texts);
  774. /* Vibra H-bridge direction */
  775. static const char *twl4030_vibradir_texts[] = {
  776. "Positive polarity", "Negative polarity",
  777. };
  778. static const struct soc_enum twl4030_vibradir_enum =
  779. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  780. ARRAY_SIZE(twl4030_vibradir_texts),
  781. twl4030_vibradir_texts);
  782. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  783. /* Common playback gain controls */
  784. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  785. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  786. 0, 0x3f, 0, digital_fine_tlv),
  787. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  788. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  789. 0, 0x3f, 0, digital_fine_tlv),
  790. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  791. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  792. 6, 0x2, 0, digital_coarse_tlv),
  793. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  794. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  795. 6, 0x2, 0, digital_coarse_tlv),
  796. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  797. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  798. 3, 0x12, 1, analog_tlv),
  799. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  800. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  801. 3, 0x12, 1, analog_tlv),
  802. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  803. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  804. 1, 1, 0),
  805. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  806. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  807. 1, 1, 0),
  808. /* Common voice downlink gain controls */
  809. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  810. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  811. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  812. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  813. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  814. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  815. /* Separate output gain controls */
  816. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  817. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  818. 4, 3, 0, output_tvl),
  819. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  820. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  821. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  822. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  823. 4, 3, 0, output_tvl),
  824. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  825. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  826. /* Common capture gain controls */
  827. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  828. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  829. 0, 0x1f, 0, digital_capture_tlv),
  830. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  831. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  832. 0, 0x1f, 0, digital_capture_tlv),
  833. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  834. 0, 3, 5, 0, input_gain_tlv),
  835. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  836. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  837. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  838. };
  839. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  840. /* Left channel inputs */
  841. SND_SOC_DAPM_INPUT("MAINMIC"),
  842. SND_SOC_DAPM_INPUT("HSMIC"),
  843. SND_SOC_DAPM_INPUT("AUXL"),
  844. SND_SOC_DAPM_INPUT("CARKITMIC"),
  845. /* Right channel inputs */
  846. SND_SOC_DAPM_INPUT("SUBMIC"),
  847. SND_SOC_DAPM_INPUT("AUXR"),
  848. /* Digital microphones (Stereo) */
  849. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  850. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  851. /* Outputs */
  852. SND_SOC_DAPM_OUTPUT("OUTL"),
  853. SND_SOC_DAPM_OUTPUT("OUTR"),
  854. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  855. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  856. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  857. SND_SOC_DAPM_OUTPUT("HSOL"),
  858. SND_SOC_DAPM_OUTPUT("HSOR"),
  859. SND_SOC_DAPM_OUTPUT("CARKITL"),
  860. SND_SOC_DAPM_OUTPUT("CARKITR"),
  861. SND_SOC_DAPM_OUTPUT("HFL"),
  862. SND_SOC_DAPM_OUTPUT("HFR"),
  863. SND_SOC_DAPM_OUTPUT("VIBRA"),
  864. /* DACs */
  865. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  866. SND_SOC_NOPM, 0, 0),
  867. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  868. SND_SOC_NOPM, 0, 0),
  869. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  870. SND_SOC_NOPM, 0, 0),
  871. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  872. SND_SOC_NOPM, 0, 0),
  873. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  874. SND_SOC_NOPM, 0, 0),
  875. /* Analog PGAs */
  876. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  877. 0, 0, NULL, 0),
  878. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  879. 0, 0, NULL, 0),
  880. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  881. 0, 0, NULL, 0),
  882. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  883. 0, 0, NULL, 0),
  884. SND_SOC_DAPM_PGA("VDL_APGA", TWL4030_REG_VDL_APGA_CTL,
  885. 0, 0, NULL, 0),
  886. /* Analog bypasses */
  887. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  888. &twl4030_dapm_abypassr1_control, bypass_event,
  889. SND_SOC_DAPM_POST_REG),
  890. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  891. &twl4030_dapm_abypassl1_control,
  892. bypass_event, SND_SOC_DAPM_POST_REG),
  893. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  894. &twl4030_dapm_abypassr2_control,
  895. bypass_event, SND_SOC_DAPM_POST_REG),
  896. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  897. &twl4030_dapm_abypassl2_control,
  898. bypass_event, SND_SOC_DAPM_POST_REG),
  899. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  900. &twl4030_dapm_abypassv_control,
  901. bypass_event, SND_SOC_DAPM_POST_REG),
  902. /* Digital bypasses */
  903. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  904. &twl4030_dapm_dbypassl_control, bypass_event,
  905. SND_SOC_DAPM_POST_REG),
  906. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  907. &twl4030_dapm_dbypassr_control, bypass_event,
  908. SND_SOC_DAPM_POST_REG),
  909. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  910. &twl4030_dapm_dbypassv_control, bypass_event,
  911. SND_SOC_DAPM_POST_REG),
  912. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  913. 0, 0, NULL, 0),
  914. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  915. 1, 0, NULL, 0),
  916. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  917. 2, 0, NULL, 0),
  918. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  919. 3, 0, NULL, 0),
  920. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", TWL4030_REG_AVDAC_CTL,
  921. 4, 0, NULL, 0),
  922. /* Output MIXER controls */
  923. /* Earpiece */
  924. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  925. &twl4030_dapm_earpiece_controls[0],
  926. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  927. /* PreDrivL/R */
  928. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  929. &twl4030_dapm_predrivel_controls[0],
  930. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  931. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  932. &twl4030_dapm_predriver_controls[0],
  933. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  934. /* HeadsetL/R */
  935. SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  936. &twl4030_dapm_hsol_controls[0],
  937. ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
  938. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  939. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  940. &twl4030_dapm_hsor_controls[0],
  941. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  942. /* CarkitL/R */
  943. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  944. &twl4030_dapm_carkitl_controls[0],
  945. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  946. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  947. &twl4030_dapm_carkitr_controls[0],
  948. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  949. /* Output MUX controls */
  950. /* HandsfreeL/R */
  951. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  952. &twl4030_dapm_handsfreel_control, handsfree_event,
  953. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  954. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  955. &twl4030_dapm_handsfreer_control, handsfree_event,
  956. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  957. /* Vibra */
  958. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  959. &twl4030_dapm_vibra_control),
  960. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  961. &twl4030_dapm_vibrapath_control),
  962. /* Introducing four virtual ADC, since TWL4030 have four channel for
  963. capture */
  964. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  965. SND_SOC_NOPM, 0, 0),
  966. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  967. SND_SOC_NOPM, 0, 0),
  968. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  969. SND_SOC_NOPM, 0, 0),
  970. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  971. SND_SOC_NOPM, 0, 0),
  972. /* Analog/Digital mic path selection.
  973. TX1 Left/Right: either analog Left/Right or Digimic0
  974. TX2 Left/Right: either analog Left/Right or Digimic1 */
  975. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  976. &twl4030_dapm_micpathtx1_control, micpath_event,
  977. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  978. SND_SOC_DAPM_POST_REG),
  979. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  980. &twl4030_dapm_micpathtx2_control, micpath_event,
  981. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  982. SND_SOC_DAPM_POST_REG),
  983. /* Analog input muxes with switch for the capture amplifiers */
  984. SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
  985. TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
  986. SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
  987. TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
  988. SND_SOC_DAPM_PGA("ADC Physical Left",
  989. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  990. SND_SOC_DAPM_PGA("ADC Physical Right",
  991. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  992. SND_SOC_DAPM_PGA("Digimic0 Enable",
  993. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  994. SND_SOC_DAPM_PGA("Digimic1 Enable",
  995. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  996. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  997. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  998. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  999. };
  1000. static const struct snd_soc_dapm_route intercon[] = {
  1001. {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
  1002. {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
  1003. {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
  1004. {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
  1005. {"Analog Voice Playback Mixer", NULL, "DAC Voice"},
  1006. {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
  1007. {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
  1008. {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
  1009. {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
  1010. {"VDL_APGA", NULL, "Analog Voice Playback Mixer"},
  1011. /* Internal playback routings */
  1012. /* Earpiece */
  1013. {"Earpiece Mixer", "Voice", "VDL_APGA"},
  1014. {"Earpiece Mixer", "AudioL1", "ARXL1_APGA"},
  1015. {"Earpiece Mixer", "AudioL2", "ARXL2_APGA"},
  1016. {"Earpiece Mixer", "AudioR1", "ARXR1_APGA"},
  1017. /* PreDrivL */
  1018. {"PredriveL Mixer", "Voice", "VDL_APGA"},
  1019. {"PredriveL Mixer", "AudioL1", "ARXL1_APGA"},
  1020. {"PredriveL Mixer", "AudioL2", "ARXL2_APGA"},
  1021. {"PredriveL Mixer", "AudioR2", "ARXR2_APGA"},
  1022. /* PreDrivR */
  1023. {"PredriveR Mixer", "Voice", "VDL_APGA"},
  1024. {"PredriveR Mixer", "AudioR1", "ARXR1_APGA"},
  1025. {"PredriveR Mixer", "AudioR2", "ARXR2_APGA"},
  1026. {"PredriveR Mixer", "AudioL2", "ARXL2_APGA"},
  1027. /* HeadsetL */
  1028. {"HeadsetL Mixer", "Voice", "VDL_APGA"},
  1029. {"HeadsetL Mixer", "AudioL1", "ARXL1_APGA"},
  1030. {"HeadsetL Mixer", "AudioL2", "ARXL2_APGA"},
  1031. /* HeadsetR */
  1032. {"HeadsetR Mixer", "Voice", "VDL_APGA"},
  1033. {"HeadsetR Mixer", "AudioR1", "ARXR1_APGA"},
  1034. {"HeadsetR Mixer", "AudioR2", "ARXR2_APGA"},
  1035. /* CarkitL */
  1036. {"CarkitL Mixer", "Voice", "VDL_APGA"},
  1037. {"CarkitL Mixer", "AudioL1", "ARXL1_APGA"},
  1038. {"CarkitL Mixer", "AudioL2", "ARXL2_APGA"},
  1039. /* CarkitR */
  1040. {"CarkitR Mixer", "Voice", "VDL_APGA"},
  1041. {"CarkitR Mixer", "AudioR1", "ARXR1_APGA"},
  1042. {"CarkitR Mixer", "AudioR2", "ARXR2_APGA"},
  1043. /* HandsfreeL */
  1044. {"HandsfreeL Mux", "Voice", "VDL_APGA"},
  1045. {"HandsfreeL Mux", "AudioL1", "ARXL1_APGA"},
  1046. {"HandsfreeL Mux", "AudioL2", "ARXL2_APGA"},
  1047. {"HandsfreeL Mux", "AudioR2", "ARXR2_APGA"},
  1048. /* HandsfreeR */
  1049. {"HandsfreeR Mux", "Voice", "VDL_APGA"},
  1050. {"HandsfreeR Mux", "AudioR1", "ARXR1_APGA"},
  1051. {"HandsfreeR Mux", "AudioR2", "ARXR2_APGA"},
  1052. {"HandsfreeR Mux", "AudioL2", "ARXL2_APGA"},
  1053. /* Vibra */
  1054. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1055. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1056. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1057. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1058. /* outputs */
  1059. {"OUTL", NULL, "ARXL2_APGA"},
  1060. {"OUTR", NULL, "ARXR2_APGA"},
  1061. {"EARPIECE", NULL, "Earpiece Mixer"},
  1062. {"PREDRIVEL", NULL, "PredriveL Mixer"},
  1063. {"PREDRIVER", NULL, "PredriveR Mixer"},
  1064. {"HSOL", NULL, "HeadsetL Mixer"},
  1065. {"HSOR", NULL, "HeadsetR Mixer"},
  1066. {"CARKITL", NULL, "CarkitL Mixer"},
  1067. {"CARKITR", NULL, "CarkitR Mixer"},
  1068. {"HFL", NULL, "HandsfreeL Mux"},
  1069. {"HFR", NULL, "HandsfreeR Mux"},
  1070. {"Vibra Route", "Audio", "Vibra Mux"},
  1071. {"VIBRA", NULL, "Vibra Route"},
  1072. /* Capture path */
  1073. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  1074. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  1075. {"Analog Left Capture Route", "AUXL", "AUXL"},
  1076. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  1077. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  1078. {"Analog Right Capture Route", "AUXR", "AUXR"},
  1079. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  1080. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  1081. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1082. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1083. /* TX1 Left capture path */
  1084. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1085. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1086. /* TX1 Right capture path */
  1087. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1088. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1089. /* TX2 Left capture path */
  1090. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1091. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1092. /* TX2 Right capture path */
  1093. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1094. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1095. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1096. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1097. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1098. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1099. /* Analog bypass routes */
  1100. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1101. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1102. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1103. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1104. {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
  1105. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1106. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1107. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1108. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1109. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1110. /* Digital bypass routes */
  1111. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1112. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1113. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1114. {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1115. {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1116. {"Analog Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1117. };
  1118. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1119. {
  1120. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1121. ARRAY_SIZE(twl4030_dapm_widgets));
  1122. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1123. snd_soc_dapm_new_widgets(codec);
  1124. return 0;
  1125. }
  1126. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1127. enum snd_soc_bias_level level)
  1128. {
  1129. struct twl4030_priv *twl4030 = codec->private_data;
  1130. switch (level) {
  1131. case SND_SOC_BIAS_ON:
  1132. twl4030_codec_mute(codec, 0);
  1133. break;
  1134. case SND_SOC_BIAS_PREPARE:
  1135. twl4030_power_up(codec);
  1136. if (twl4030->bypass_state)
  1137. twl4030_codec_mute(codec, 0);
  1138. else
  1139. twl4030_codec_mute(codec, 1);
  1140. break;
  1141. case SND_SOC_BIAS_STANDBY:
  1142. twl4030_power_up(codec);
  1143. if (twl4030->bypass_state)
  1144. twl4030_codec_mute(codec, 0);
  1145. else
  1146. twl4030_codec_mute(codec, 1);
  1147. break;
  1148. case SND_SOC_BIAS_OFF:
  1149. twl4030_power_down(codec);
  1150. break;
  1151. }
  1152. codec->bias_level = level;
  1153. return 0;
  1154. }
  1155. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1156. struct snd_pcm_substream *mst_substream)
  1157. {
  1158. struct snd_pcm_substream *slv_substream;
  1159. /* Pick the stream, which need to be constrained */
  1160. if (mst_substream == twl4030->master_substream)
  1161. slv_substream = twl4030->slave_substream;
  1162. else if (mst_substream == twl4030->slave_substream)
  1163. slv_substream = twl4030->master_substream;
  1164. else /* This should not happen.. */
  1165. return;
  1166. /* Set the constraints according to the already configured stream */
  1167. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1168. SNDRV_PCM_HW_PARAM_RATE,
  1169. twl4030->rate,
  1170. twl4030->rate);
  1171. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1172. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1173. twl4030->sample_bits,
  1174. twl4030->sample_bits);
  1175. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1176. SNDRV_PCM_HW_PARAM_CHANNELS,
  1177. twl4030->channels,
  1178. twl4030->channels);
  1179. }
  1180. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1181. * capture has to be enabled/disabled. */
  1182. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1183. int enable)
  1184. {
  1185. u8 reg, mask;
  1186. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1187. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1188. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1189. else
  1190. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1191. if (enable)
  1192. reg |= mask;
  1193. else
  1194. reg &= ~mask;
  1195. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1196. }
  1197. static int twl4030_startup(struct snd_pcm_substream *substream,
  1198. struct snd_soc_dai *dai)
  1199. {
  1200. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1201. struct snd_soc_device *socdev = rtd->socdev;
  1202. struct snd_soc_codec *codec = socdev->card->codec;
  1203. struct twl4030_priv *twl4030 = codec->private_data;
  1204. if (twl4030->master_substream) {
  1205. twl4030->slave_substream = substream;
  1206. /* The DAI has one configuration for playback and capture, so
  1207. * if the DAI has been already configured then constrain this
  1208. * substream to match it. */
  1209. if (twl4030->configured)
  1210. twl4030_constraints(twl4030, twl4030->master_substream);
  1211. } else {
  1212. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1213. TWL4030_OPTION_1)) {
  1214. /* In option2 4 channel is not supported, set the
  1215. * constraint for the first stream for channels, the
  1216. * second stream will 'inherit' this cosntraint */
  1217. snd_pcm_hw_constraint_minmax(substream->runtime,
  1218. SNDRV_PCM_HW_PARAM_CHANNELS,
  1219. 2, 2);
  1220. }
  1221. twl4030->master_substream = substream;
  1222. }
  1223. return 0;
  1224. }
  1225. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1226. struct snd_soc_dai *dai)
  1227. {
  1228. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1229. struct snd_soc_device *socdev = rtd->socdev;
  1230. struct snd_soc_codec *codec = socdev->card->codec;
  1231. struct twl4030_priv *twl4030 = codec->private_data;
  1232. if (twl4030->master_substream == substream)
  1233. twl4030->master_substream = twl4030->slave_substream;
  1234. twl4030->slave_substream = NULL;
  1235. /* If all streams are closed, or the remaining stream has not yet
  1236. * been configured than set the DAI as not configured. */
  1237. if (!twl4030->master_substream)
  1238. twl4030->configured = 0;
  1239. else if (!twl4030->master_substream->runtime->channels)
  1240. twl4030->configured = 0;
  1241. /* If the closing substream had 4 channel, do the necessary cleanup */
  1242. if (substream->runtime->channels == 4)
  1243. twl4030_tdm_enable(codec, substream->stream, 0);
  1244. }
  1245. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1246. struct snd_pcm_hw_params *params,
  1247. struct snd_soc_dai *dai)
  1248. {
  1249. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1250. struct snd_soc_device *socdev = rtd->socdev;
  1251. struct snd_soc_codec *codec = socdev->card->codec;
  1252. struct twl4030_priv *twl4030 = codec->private_data;
  1253. u8 mode, old_mode, format, old_format;
  1254. /* If the substream has 4 channel, do the necessary setup */
  1255. if (params_channels(params) == 4) {
  1256. /* Safety check: are we in the correct operating mode? */
  1257. if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1258. TWL4030_OPTION_1))
  1259. twl4030_tdm_enable(codec, substream->stream, 1);
  1260. else
  1261. return -EINVAL;
  1262. }
  1263. if (twl4030->configured)
  1264. /* Ignoring hw_params for already configured DAI */
  1265. return 0;
  1266. /* bit rate */
  1267. old_mode = twl4030_read_reg_cache(codec,
  1268. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1269. mode = old_mode & ~TWL4030_APLL_RATE;
  1270. switch (params_rate(params)) {
  1271. case 8000:
  1272. mode |= TWL4030_APLL_RATE_8000;
  1273. break;
  1274. case 11025:
  1275. mode |= TWL4030_APLL_RATE_11025;
  1276. break;
  1277. case 12000:
  1278. mode |= TWL4030_APLL_RATE_12000;
  1279. break;
  1280. case 16000:
  1281. mode |= TWL4030_APLL_RATE_16000;
  1282. break;
  1283. case 22050:
  1284. mode |= TWL4030_APLL_RATE_22050;
  1285. break;
  1286. case 24000:
  1287. mode |= TWL4030_APLL_RATE_24000;
  1288. break;
  1289. case 32000:
  1290. mode |= TWL4030_APLL_RATE_32000;
  1291. break;
  1292. case 44100:
  1293. mode |= TWL4030_APLL_RATE_44100;
  1294. break;
  1295. case 48000:
  1296. mode |= TWL4030_APLL_RATE_48000;
  1297. break;
  1298. case 96000:
  1299. mode |= TWL4030_APLL_RATE_96000;
  1300. break;
  1301. default:
  1302. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1303. params_rate(params));
  1304. return -EINVAL;
  1305. }
  1306. if (mode != old_mode) {
  1307. /* change rate and set CODECPDZ */
  1308. twl4030_codec_enable(codec, 0);
  1309. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1310. twl4030_codec_enable(codec, 1);
  1311. }
  1312. /* sample size */
  1313. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1314. format = old_format;
  1315. format &= ~TWL4030_DATA_WIDTH;
  1316. switch (params_format(params)) {
  1317. case SNDRV_PCM_FORMAT_S16_LE:
  1318. format |= TWL4030_DATA_WIDTH_16S_16W;
  1319. break;
  1320. case SNDRV_PCM_FORMAT_S24_LE:
  1321. format |= TWL4030_DATA_WIDTH_32S_24W;
  1322. break;
  1323. default:
  1324. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1325. params_format(params));
  1326. return -EINVAL;
  1327. }
  1328. if (format != old_format) {
  1329. /* clear CODECPDZ before changing format (codec requirement) */
  1330. twl4030_codec_enable(codec, 0);
  1331. /* change format */
  1332. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1333. /* set CODECPDZ afterwards */
  1334. twl4030_codec_enable(codec, 1);
  1335. }
  1336. /* Store the important parameters for the DAI configuration and set
  1337. * the DAI as configured */
  1338. twl4030->configured = 1;
  1339. twl4030->rate = params_rate(params);
  1340. twl4030->sample_bits = hw_param_interval(params,
  1341. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1342. twl4030->channels = params_channels(params);
  1343. /* If both playback and capture streams are open, and one of them
  1344. * is setting the hw parameters right now (since we are here), set
  1345. * constraints to the other stream to match the current one. */
  1346. if (twl4030->slave_substream)
  1347. twl4030_constraints(twl4030, substream);
  1348. return 0;
  1349. }
  1350. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1351. int clk_id, unsigned int freq, int dir)
  1352. {
  1353. struct snd_soc_codec *codec = codec_dai->codec;
  1354. u8 infreq;
  1355. switch (freq) {
  1356. case 19200000:
  1357. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1358. break;
  1359. case 26000000:
  1360. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1361. break;
  1362. case 38400000:
  1363. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1364. break;
  1365. default:
  1366. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1367. freq);
  1368. return -EINVAL;
  1369. }
  1370. infreq |= TWL4030_APLL_EN;
  1371. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1372. return 0;
  1373. }
  1374. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1375. unsigned int fmt)
  1376. {
  1377. struct snd_soc_codec *codec = codec_dai->codec;
  1378. u8 old_format, format;
  1379. /* get format */
  1380. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1381. format = old_format;
  1382. /* set master/slave audio interface */
  1383. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1384. case SND_SOC_DAIFMT_CBM_CFM:
  1385. format &= ~(TWL4030_AIF_SLAVE_EN);
  1386. format &= ~(TWL4030_CLK256FS_EN);
  1387. break;
  1388. case SND_SOC_DAIFMT_CBS_CFS:
  1389. format |= TWL4030_AIF_SLAVE_EN;
  1390. format |= TWL4030_CLK256FS_EN;
  1391. break;
  1392. default:
  1393. return -EINVAL;
  1394. }
  1395. /* interface format */
  1396. format &= ~TWL4030_AIF_FORMAT;
  1397. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1398. case SND_SOC_DAIFMT_I2S:
  1399. format |= TWL4030_AIF_FORMAT_CODEC;
  1400. break;
  1401. case SND_SOC_DAIFMT_DSP_A:
  1402. format |= TWL4030_AIF_FORMAT_TDM;
  1403. break;
  1404. default:
  1405. return -EINVAL;
  1406. }
  1407. if (format != old_format) {
  1408. /* clear CODECPDZ before changing format (codec requirement) */
  1409. twl4030_codec_enable(codec, 0);
  1410. /* change format */
  1411. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1412. /* set CODECPDZ afterwards */
  1413. twl4030_codec_enable(codec, 1);
  1414. }
  1415. return 0;
  1416. }
  1417. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1418. struct snd_soc_dai *dai)
  1419. {
  1420. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1421. struct snd_soc_device *socdev = rtd->socdev;
  1422. struct snd_soc_codec *codec = socdev->card->codec;
  1423. u8 infreq;
  1424. u8 mode;
  1425. /* If the system master clock is not 26MHz, the voice PCM interface is
  1426. * not avilable.
  1427. */
  1428. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1429. & TWL4030_APLL_INFREQ;
  1430. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1431. printk(KERN_ERR "TWL4030 voice startup: "
  1432. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1433. return -EINVAL;
  1434. }
  1435. /* If the codec mode is not option2, the voice PCM interface is not
  1436. * avilable.
  1437. */
  1438. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1439. & TWL4030_OPT_MODE;
  1440. if (mode != TWL4030_OPTION_2) {
  1441. printk(KERN_ERR "TWL4030 voice startup: "
  1442. "the codec mode is not option2\n");
  1443. return -EINVAL;
  1444. }
  1445. return 0;
  1446. }
  1447. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1448. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1449. {
  1450. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1451. struct snd_soc_device *socdev = rtd->socdev;
  1452. struct snd_soc_codec *codec = socdev->card->codec;
  1453. u8 old_mode, mode;
  1454. /* bit rate */
  1455. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1456. & ~(TWL4030_CODECPDZ);
  1457. mode = old_mode;
  1458. switch (params_rate(params)) {
  1459. case 8000:
  1460. mode &= ~(TWL4030_SEL_16K);
  1461. break;
  1462. case 16000:
  1463. mode |= TWL4030_SEL_16K;
  1464. break;
  1465. default:
  1466. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1467. params_rate(params));
  1468. return -EINVAL;
  1469. }
  1470. if (mode != old_mode) {
  1471. /* change rate and set CODECPDZ */
  1472. twl4030_codec_enable(codec, 0);
  1473. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1474. twl4030_codec_enable(codec, 1);
  1475. }
  1476. return 0;
  1477. }
  1478. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1479. int clk_id, unsigned int freq, int dir)
  1480. {
  1481. struct snd_soc_codec *codec = codec_dai->codec;
  1482. u8 infreq;
  1483. switch (freq) {
  1484. case 26000000:
  1485. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1486. break;
  1487. default:
  1488. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1489. freq);
  1490. return -EINVAL;
  1491. }
  1492. infreq |= TWL4030_APLL_EN;
  1493. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1494. return 0;
  1495. }
  1496. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1497. unsigned int fmt)
  1498. {
  1499. struct snd_soc_codec *codec = codec_dai->codec;
  1500. u8 old_format, format;
  1501. /* get format */
  1502. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1503. format = old_format;
  1504. /* set master/slave audio interface */
  1505. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1506. case SND_SOC_DAIFMT_CBS_CFM:
  1507. format &= ~(TWL4030_VIF_SLAVE_EN);
  1508. break;
  1509. case SND_SOC_DAIFMT_CBS_CFS:
  1510. format |= TWL4030_VIF_SLAVE_EN;
  1511. break;
  1512. default:
  1513. return -EINVAL;
  1514. }
  1515. /* clock inversion */
  1516. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1517. case SND_SOC_DAIFMT_IB_NF:
  1518. format &= ~(TWL4030_VIF_FORMAT);
  1519. break;
  1520. case SND_SOC_DAIFMT_NB_IF:
  1521. format |= TWL4030_VIF_FORMAT;
  1522. break;
  1523. default:
  1524. return -EINVAL;
  1525. }
  1526. if (format != old_format) {
  1527. /* change format and set CODECPDZ */
  1528. twl4030_codec_enable(codec, 0);
  1529. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1530. twl4030_codec_enable(codec, 1);
  1531. }
  1532. return 0;
  1533. }
  1534. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1535. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1536. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1537. .startup = twl4030_startup,
  1538. .shutdown = twl4030_shutdown,
  1539. .hw_params = twl4030_hw_params,
  1540. .set_sysclk = twl4030_set_dai_sysclk,
  1541. .set_fmt = twl4030_set_dai_fmt,
  1542. };
  1543. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1544. .startup = twl4030_voice_startup,
  1545. .hw_params = twl4030_voice_hw_params,
  1546. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1547. .set_fmt = twl4030_voice_set_dai_fmt,
  1548. };
  1549. struct snd_soc_dai twl4030_dai[] = {
  1550. {
  1551. .name = "twl4030",
  1552. .playback = {
  1553. .stream_name = "Playback",
  1554. .channels_min = 2,
  1555. .channels_max = 4,
  1556. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1557. .formats = TWL4030_FORMATS,},
  1558. .capture = {
  1559. .stream_name = "Capture",
  1560. .channels_min = 2,
  1561. .channels_max = 4,
  1562. .rates = TWL4030_RATES,
  1563. .formats = TWL4030_FORMATS,},
  1564. .ops = &twl4030_dai_ops,
  1565. },
  1566. {
  1567. .name = "twl4030 Voice",
  1568. .playback = {
  1569. .stream_name = "Playback",
  1570. .channels_min = 1,
  1571. .channels_max = 1,
  1572. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1573. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1574. .capture = {
  1575. .stream_name = "Capture",
  1576. .channels_min = 1,
  1577. .channels_max = 2,
  1578. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1579. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1580. .ops = &twl4030_dai_voice_ops,
  1581. },
  1582. };
  1583. EXPORT_SYMBOL_GPL(twl4030_dai);
  1584. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1585. {
  1586. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1587. struct snd_soc_codec *codec = socdev->card->codec;
  1588. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1589. return 0;
  1590. }
  1591. static int twl4030_resume(struct platform_device *pdev)
  1592. {
  1593. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1594. struct snd_soc_codec *codec = socdev->card->codec;
  1595. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1596. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1597. return 0;
  1598. }
  1599. /*
  1600. * initialize the driver
  1601. * register the mixer and dsp interfaces with the kernel
  1602. */
  1603. static int twl4030_init(struct snd_soc_device *socdev)
  1604. {
  1605. struct snd_soc_codec *codec = socdev->card->codec;
  1606. int ret = 0;
  1607. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1608. codec->name = "twl4030";
  1609. codec->owner = THIS_MODULE;
  1610. codec->read = twl4030_read_reg_cache;
  1611. codec->write = twl4030_write;
  1612. codec->set_bias_level = twl4030_set_bias_level;
  1613. codec->dai = twl4030_dai;
  1614. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1615. codec->reg_cache_size = sizeof(twl4030_reg);
  1616. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1617. GFP_KERNEL);
  1618. if (codec->reg_cache == NULL)
  1619. return -ENOMEM;
  1620. /* register pcms */
  1621. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1622. if (ret < 0) {
  1623. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1624. goto pcm_err;
  1625. }
  1626. twl4030_init_chip(codec);
  1627. /* power on device */
  1628. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1629. snd_soc_add_controls(codec, twl4030_snd_controls,
  1630. ARRAY_SIZE(twl4030_snd_controls));
  1631. twl4030_add_widgets(codec);
  1632. ret = snd_soc_init_card(socdev);
  1633. if (ret < 0) {
  1634. printk(KERN_ERR "twl4030: failed to register card\n");
  1635. goto card_err;
  1636. }
  1637. return ret;
  1638. card_err:
  1639. snd_soc_free_pcms(socdev);
  1640. snd_soc_dapm_free(socdev);
  1641. pcm_err:
  1642. kfree(codec->reg_cache);
  1643. return ret;
  1644. }
  1645. static struct snd_soc_device *twl4030_socdev;
  1646. static int twl4030_probe(struct platform_device *pdev)
  1647. {
  1648. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1649. struct snd_soc_codec *codec;
  1650. struct twl4030_priv *twl4030;
  1651. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1652. if (codec == NULL)
  1653. return -ENOMEM;
  1654. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1655. if (twl4030 == NULL) {
  1656. kfree(codec);
  1657. return -ENOMEM;
  1658. }
  1659. codec->private_data = twl4030;
  1660. socdev->card->codec = codec;
  1661. mutex_init(&codec->mutex);
  1662. INIT_LIST_HEAD(&codec->dapm_widgets);
  1663. INIT_LIST_HEAD(&codec->dapm_paths);
  1664. twl4030_socdev = socdev;
  1665. twl4030_init(socdev);
  1666. return 0;
  1667. }
  1668. static int twl4030_remove(struct platform_device *pdev)
  1669. {
  1670. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1671. struct snd_soc_codec *codec = socdev->card->codec;
  1672. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1673. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1674. snd_soc_free_pcms(socdev);
  1675. snd_soc_dapm_free(socdev);
  1676. kfree(codec->private_data);
  1677. kfree(codec);
  1678. return 0;
  1679. }
  1680. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1681. .probe = twl4030_probe,
  1682. .remove = twl4030_remove,
  1683. .suspend = twl4030_suspend,
  1684. .resume = twl4030_resume,
  1685. };
  1686. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1687. static int __init twl4030_modinit(void)
  1688. {
  1689. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1690. }
  1691. module_init(twl4030_modinit);
  1692. static void __exit twl4030_exit(void)
  1693. {
  1694. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1695. }
  1696. module_exit(twl4030_exit);
  1697. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1698. MODULE_AUTHOR("Steve Sakoman");
  1699. MODULE_LICENSE("GPL");