intel_panel.c 21 KB

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  1. /*
  2. * Copyright © 2006-2010 Intel Corporation
  3. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Dave Airlie <airlied@linux.ie>
  27. * Jesse Barnes <jesse.barnes@intel.com>
  28. * Chris Wilson <chris@chris-wilson.co.uk>
  29. */
  30. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31. #include <linux/moduleparam.h>
  32. #include "intel_drv.h"
  33. #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
  34. void
  35. intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  36. struct drm_display_mode *adjusted_mode)
  37. {
  38. drm_mode_copy(adjusted_mode, fixed_mode);
  39. drm_mode_set_crtcinfo(adjusted_mode, 0);
  40. }
  41. /* adjusted_mode has been preset to be the panel's fixed mode */
  42. void
  43. intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
  44. struct intel_crtc_config *pipe_config,
  45. int fitting_mode)
  46. {
  47. struct drm_display_mode *adjusted_mode;
  48. int x, y, width, height;
  49. adjusted_mode = &pipe_config->adjusted_mode;
  50. x = y = width = height = 0;
  51. /* Native modes don't need fitting */
  52. if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
  53. adjusted_mode->vdisplay == pipe_config->pipe_src_h)
  54. goto done;
  55. switch (fitting_mode) {
  56. case DRM_MODE_SCALE_CENTER:
  57. width = pipe_config->pipe_src_w;
  58. height = pipe_config->pipe_src_h;
  59. x = (adjusted_mode->hdisplay - width + 1)/2;
  60. y = (adjusted_mode->vdisplay - height + 1)/2;
  61. break;
  62. case DRM_MODE_SCALE_ASPECT:
  63. /* Scale but preserve the aspect ratio */
  64. {
  65. u32 scaled_width = adjusted_mode->hdisplay * pipe_config->pipe_src_h;
  66. u32 scaled_height = pipe_config->pipe_src_w * adjusted_mode->vdisplay;
  67. if (scaled_width > scaled_height) { /* pillar */
  68. width = scaled_height / pipe_config->pipe_src_h;
  69. if (width & 1)
  70. width++;
  71. x = (adjusted_mode->hdisplay - width + 1) / 2;
  72. y = 0;
  73. height = adjusted_mode->vdisplay;
  74. } else if (scaled_width < scaled_height) { /* letter */
  75. height = scaled_width / pipe_config->pipe_src_w;
  76. if (height & 1)
  77. height++;
  78. y = (adjusted_mode->vdisplay - height + 1) / 2;
  79. x = 0;
  80. width = adjusted_mode->hdisplay;
  81. } else {
  82. x = y = 0;
  83. width = adjusted_mode->hdisplay;
  84. height = adjusted_mode->vdisplay;
  85. }
  86. }
  87. break;
  88. case DRM_MODE_SCALE_FULLSCREEN:
  89. x = y = 0;
  90. width = adjusted_mode->hdisplay;
  91. height = adjusted_mode->vdisplay;
  92. break;
  93. default:
  94. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  95. return;
  96. }
  97. done:
  98. pipe_config->pch_pfit.pos = (x << 16) | y;
  99. pipe_config->pch_pfit.size = (width << 16) | height;
  100. }
  101. static void
  102. centre_horizontally(struct drm_display_mode *mode,
  103. int width)
  104. {
  105. u32 border, sync_pos, blank_width, sync_width;
  106. /* keep the hsync and hblank widths constant */
  107. sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
  108. blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
  109. sync_pos = (blank_width - sync_width + 1) / 2;
  110. border = (mode->hdisplay - width + 1) / 2;
  111. border += border & 1; /* make the border even */
  112. mode->crtc_hdisplay = width;
  113. mode->crtc_hblank_start = width + border;
  114. mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
  115. mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
  116. mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
  117. }
  118. static void
  119. centre_vertically(struct drm_display_mode *mode,
  120. int height)
  121. {
  122. u32 border, sync_pos, blank_width, sync_width;
  123. /* keep the vsync and vblank widths constant */
  124. sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
  125. blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
  126. sync_pos = (blank_width - sync_width + 1) / 2;
  127. border = (mode->vdisplay - height + 1) / 2;
  128. mode->crtc_vdisplay = height;
  129. mode->crtc_vblank_start = height + border;
  130. mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
  131. mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
  132. mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
  133. }
  134. static inline u32 panel_fitter_scaling(u32 source, u32 target)
  135. {
  136. /*
  137. * Floating point operation is not supported. So the FACTOR
  138. * is defined, which can avoid the floating point computation
  139. * when calculating the panel ratio.
  140. */
  141. #define ACCURACY 12
  142. #define FACTOR (1 << ACCURACY)
  143. u32 ratio = source * FACTOR / target;
  144. return (FACTOR * ratio + FACTOR/2) / FACTOR;
  145. }
  146. void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
  147. struct intel_crtc_config *pipe_config,
  148. int fitting_mode)
  149. {
  150. struct drm_device *dev = intel_crtc->base.dev;
  151. u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
  152. struct drm_display_mode *adjusted_mode;
  153. adjusted_mode = &pipe_config->adjusted_mode;
  154. /* Native modes don't need fitting */
  155. if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
  156. adjusted_mode->vdisplay == pipe_config->pipe_src_h)
  157. goto out;
  158. switch (fitting_mode) {
  159. case DRM_MODE_SCALE_CENTER:
  160. /*
  161. * For centered modes, we have to calculate border widths &
  162. * heights and modify the values programmed into the CRTC.
  163. */
  164. centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
  165. centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
  166. border = LVDS_BORDER_ENABLE;
  167. break;
  168. case DRM_MODE_SCALE_ASPECT:
  169. /* Scale but preserve the aspect ratio */
  170. if (INTEL_INFO(dev)->gen >= 4) {
  171. u32 scaled_width = adjusted_mode->hdisplay *
  172. pipe_config->pipe_src_h;
  173. u32 scaled_height = pipe_config->pipe_src_w *
  174. adjusted_mode->vdisplay;
  175. /* 965+ is easy, it does everything in hw */
  176. if (scaled_width > scaled_height)
  177. pfit_control |= PFIT_ENABLE |
  178. PFIT_SCALING_PILLAR;
  179. else if (scaled_width < scaled_height)
  180. pfit_control |= PFIT_ENABLE |
  181. PFIT_SCALING_LETTER;
  182. else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
  183. pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
  184. } else {
  185. u32 scaled_width = adjusted_mode->hdisplay *
  186. pipe_config->pipe_src_h;
  187. u32 scaled_height = pipe_config->pipe_src_w *
  188. adjusted_mode->vdisplay;
  189. /*
  190. * For earlier chips we have to calculate the scaling
  191. * ratio by hand and program it into the
  192. * PFIT_PGM_RATIO register
  193. */
  194. if (scaled_width > scaled_height) { /* pillar */
  195. centre_horizontally(adjusted_mode,
  196. scaled_height /
  197. pipe_config->pipe_src_h);
  198. border = LVDS_BORDER_ENABLE;
  199. if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
  200. u32 bits = panel_fitter_scaling(pipe_config->pipe_src_h, adjusted_mode->vdisplay);
  201. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  202. bits << PFIT_VERT_SCALE_SHIFT);
  203. pfit_control |= (PFIT_ENABLE |
  204. VERT_INTERP_BILINEAR |
  205. HORIZ_INTERP_BILINEAR);
  206. }
  207. } else if (scaled_width < scaled_height) { /* letter */
  208. centre_vertically(adjusted_mode,
  209. scaled_width /
  210. pipe_config->pipe_src_w);
  211. border = LVDS_BORDER_ENABLE;
  212. if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
  213. u32 bits = panel_fitter_scaling(pipe_config->pipe_src_w, adjusted_mode->hdisplay);
  214. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  215. bits << PFIT_VERT_SCALE_SHIFT);
  216. pfit_control |= (PFIT_ENABLE |
  217. VERT_INTERP_BILINEAR |
  218. HORIZ_INTERP_BILINEAR);
  219. }
  220. } else {
  221. /* Aspects match, Let hw scale both directions */
  222. pfit_control |= (PFIT_ENABLE |
  223. VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
  224. VERT_INTERP_BILINEAR |
  225. HORIZ_INTERP_BILINEAR);
  226. }
  227. }
  228. break;
  229. case DRM_MODE_SCALE_FULLSCREEN:
  230. /*
  231. * Full scaling, even if it changes the aspect ratio.
  232. * Fortunately this is all done for us in hw.
  233. */
  234. if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
  235. pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
  236. pfit_control |= PFIT_ENABLE;
  237. if (INTEL_INFO(dev)->gen >= 4)
  238. pfit_control |= PFIT_SCALING_AUTO;
  239. else
  240. pfit_control |= (VERT_AUTO_SCALE |
  241. VERT_INTERP_BILINEAR |
  242. HORIZ_AUTO_SCALE |
  243. HORIZ_INTERP_BILINEAR);
  244. }
  245. break;
  246. default:
  247. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  248. return;
  249. }
  250. /* 965+ wants fuzzy fitting */
  251. /* FIXME: handle multiple panels by failing gracefully */
  252. if (INTEL_INFO(dev)->gen >= 4)
  253. pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
  254. PFIT_FILTER_FUZZY);
  255. out:
  256. if ((pfit_control & PFIT_ENABLE) == 0) {
  257. pfit_control = 0;
  258. pfit_pgm_ratios = 0;
  259. }
  260. /* Make sure pre-965 set dither correctly for 18bpp panels. */
  261. if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
  262. pfit_control |= PANEL_8TO6_DITHER_ENABLE;
  263. pipe_config->gmch_pfit.control = pfit_control;
  264. pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
  265. pipe_config->gmch_pfit.lvds_border_bits = border;
  266. }
  267. static int is_backlight_combination_mode(struct drm_device *dev)
  268. {
  269. struct drm_i915_private *dev_priv = dev->dev_private;
  270. if (INTEL_INFO(dev)->gen >= 4)
  271. return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
  272. if (IS_GEN2(dev))
  273. return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
  274. return 0;
  275. }
  276. /* XXX: query mode clock or hardware clock and program max PWM appropriately
  277. * when it's 0.
  278. */
  279. static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
  280. {
  281. struct drm_i915_private *dev_priv = dev->dev_private;
  282. u32 val;
  283. WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
  284. /* Restore the CTL value if it lost, e.g. GPU reset */
  285. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  286. val = I915_READ(BLC_PWM_PCH_CTL2);
  287. if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
  288. dev_priv->regfile.saveBLC_PWM_CTL2 = val;
  289. } else if (val == 0) {
  290. val = dev_priv->regfile.saveBLC_PWM_CTL2;
  291. I915_WRITE(BLC_PWM_PCH_CTL2, val);
  292. }
  293. } else {
  294. val = I915_READ(BLC_PWM_CTL);
  295. if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
  296. dev_priv->regfile.saveBLC_PWM_CTL = val;
  297. if (INTEL_INFO(dev)->gen >= 4)
  298. dev_priv->regfile.saveBLC_PWM_CTL2 =
  299. I915_READ(BLC_PWM_CTL2);
  300. } else if (val == 0) {
  301. val = dev_priv->regfile.saveBLC_PWM_CTL;
  302. I915_WRITE(BLC_PWM_CTL, val);
  303. if (INTEL_INFO(dev)->gen >= 4)
  304. I915_WRITE(BLC_PWM_CTL2,
  305. dev_priv->regfile.saveBLC_PWM_CTL2);
  306. }
  307. }
  308. return val;
  309. }
  310. static u32 intel_panel_get_max_backlight(struct drm_device *dev)
  311. {
  312. u32 max;
  313. max = i915_read_blc_pwm_ctl(dev);
  314. if (HAS_PCH_SPLIT(dev)) {
  315. max >>= 16;
  316. } else {
  317. if (INTEL_INFO(dev)->gen < 4)
  318. max >>= 17;
  319. else
  320. max >>= 16;
  321. if (is_backlight_combination_mode(dev))
  322. max *= 0xff;
  323. }
  324. DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
  325. return max;
  326. }
  327. static int i915_panel_invert_brightness;
  328. MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
  329. "(-1 force normal, 0 machine defaults, 1 force inversion), please "
  330. "report PCI device ID, subsystem vendor and subsystem device ID "
  331. "to dri-devel@lists.freedesktop.org, if your machine needs it. "
  332. "It will then be included in an upcoming module version.");
  333. module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
  334. static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
  335. {
  336. struct drm_i915_private *dev_priv = dev->dev_private;
  337. if (i915_panel_invert_brightness < 0)
  338. return val;
  339. if (i915_panel_invert_brightness > 0 ||
  340. dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
  341. u32 max = intel_panel_get_max_backlight(dev);
  342. if (max)
  343. return max - val;
  344. }
  345. return val;
  346. }
  347. static u32 intel_panel_get_backlight(struct drm_device *dev)
  348. {
  349. struct drm_i915_private *dev_priv = dev->dev_private;
  350. u32 val;
  351. unsigned long flags;
  352. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  353. if (HAS_PCH_SPLIT(dev)) {
  354. val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  355. } else {
  356. val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  357. if (INTEL_INFO(dev)->gen < 4)
  358. val >>= 1;
  359. if (is_backlight_combination_mode(dev)) {
  360. u8 lbpc;
  361. pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
  362. val *= lbpc;
  363. }
  364. }
  365. val = intel_panel_compute_brightness(dev, val);
  366. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  367. DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
  368. return val;
  369. }
  370. static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
  371. {
  372. struct drm_i915_private *dev_priv = dev->dev_private;
  373. u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  374. I915_WRITE(BLC_PWM_CPU_CTL, val | level);
  375. }
  376. static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
  377. {
  378. struct drm_i915_private *dev_priv = dev->dev_private;
  379. u32 tmp;
  380. DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
  381. level = intel_panel_compute_brightness(dev, level);
  382. if (HAS_PCH_SPLIT(dev))
  383. return intel_pch_panel_set_backlight(dev, level);
  384. if (is_backlight_combination_mode(dev)) {
  385. u32 max = intel_panel_get_max_backlight(dev);
  386. u8 lbpc;
  387. /* we're screwed, but keep behaviour backwards compatible */
  388. if (!max)
  389. max = 1;
  390. lbpc = level * 0xfe / max + 1;
  391. level /= lbpc;
  392. pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
  393. }
  394. tmp = I915_READ(BLC_PWM_CTL);
  395. if (INTEL_INFO(dev)->gen < 4)
  396. level <<= 1;
  397. tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
  398. I915_WRITE(BLC_PWM_CTL, tmp | level);
  399. }
  400. /* set backlight brightness to level in range [0..max] */
  401. void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
  402. {
  403. struct drm_i915_private *dev_priv = dev->dev_private;
  404. u32 freq;
  405. unsigned long flags;
  406. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  407. freq = intel_panel_get_max_backlight(dev);
  408. if (!freq) {
  409. /* we are screwed, bail out */
  410. goto out;
  411. }
  412. /* scale to hardware, but be careful to not overflow */
  413. if (freq < max)
  414. level = level * freq / max;
  415. else
  416. level = freq / max * level;
  417. dev_priv->backlight.level = level;
  418. if (dev_priv->backlight.device)
  419. dev_priv->backlight.device->props.brightness = level;
  420. if (dev_priv->backlight.enabled)
  421. intel_panel_actually_set_backlight(dev, level);
  422. out:
  423. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  424. }
  425. void intel_panel_disable_backlight(struct drm_device *dev)
  426. {
  427. struct drm_i915_private *dev_priv = dev->dev_private;
  428. unsigned long flags;
  429. /*
  430. * Do not disable backlight on the vgaswitcheroo path. When switching
  431. * away from i915, the other client may depend on i915 to handle the
  432. * backlight. This will leave the backlight on unnecessarily when
  433. * another client is not activated.
  434. */
  435. if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
  436. DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
  437. return;
  438. }
  439. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  440. dev_priv->backlight.enabled = false;
  441. intel_panel_actually_set_backlight(dev, 0);
  442. if (INTEL_INFO(dev)->gen >= 4) {
  443. uint32_t reg, tmp;
  444. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  445. I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
  446. if (HAS_PCH_SPLIT(dev)) {
  447. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  448. tmp &= ~BLM_PCH_PWM_ENABLE;
  449. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  450. }
  451. }
  452. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  453. }
  454. void intel_panel_enable_backlight(struct drm_device *dev,
  455. enum pipe pipe)
  456. {
  457. struct drm_i915_private *dev_priv = dev->dev_private;
  458. enum transcoder cpu_transcoder =
  459. intel_pipe_to_cpu_transcoder(dev_priv, pipe);
  460. unsigned long flags;
  461. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  462. if (dev_priv->backlight.level == 0) {
  463. dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
  464. if (dev_priv->backlight.device)
  465. dev_priv->backlight.device->props.brightness =
  466. dev_priv->backlight.level;
  467. }
  468. if (INTEL_INFO(dev)->gen >= 4) {
  469. uint32_t reg, tmp;
  470. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  471. tmp = I915_READ(reg);
  472. /* Note that this can also get called through dpms changes. And
  473. * we don't track the backlight dpms state, hence check whether
  474. * we have to do anything first. */
  475. if (tmp & BLM_PWM_ENABLE)
  476. goto set_level;
  477. if (INTEL_INFO(dev)->num_pipes == 3)
  478. tmp &= ~BLM_PIPE_SELECT_IVB;
  479. else
  480. tmp &= ~BLM_PIPE_SELECT;
  481. if (cpu_transcoder == TRANSCODER_EDP)
  482. tmp |= BLM_TRANSCODER_EDP;
  483. else
  484. tmp |= BLM_PIPE(cpu_transcoder);
  485. tmp &= ~BLM_PWM_ENABLE;
  486. I915_WRITE(reg, tmp);
  487. POSTING_READ(reg);
  488. I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
  489. if (HAS_PCH_SPLIT(dev) &&
  490. !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
  491. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  492. tmp |= BLM_PCH_PWM_ENABLE;
  493. tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
  494. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  495. }
  496. }
  497. set_level:
  498. /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
  499. * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
  500. * registers are set.
  501. */
  502. dev_priv->backlight.enabled = true;
  503. intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
  504. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  505. }
  506. static void intel_panel_init_backlight(struct drm_device *dev)
  507. {
  508. struct drm_i915_private *dev_priv = dev->dev_private;
  509. dev_priv->backlight.level = intel_panel_get_backlight(dev);
  510. dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
  511. }
  512. enum drm_connector_status
  513. intel_panel_detect(struct drm_device *dev)
  514. {
  515. struct drm_i915_private *dev_priv = dev->dev_private;
  516. /* Assume that the BIOS does not lie through the OpRegion... */
  517. if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
  518. return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
  519. connector_status_connected :
  520. connector_status_disconnected;
  521. }
  522. switch (i915_panel_ignore_lid) {
  523. case -2:
  524. return connector_status_connected;
  525. case -1:
  526. return connector_status_disconnected;
  527. default:
  528. return connector_status_unknown;
  529. }
  530. }
  531. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  532. static int intel_panel_update_status(struct backlight_device *bd)
  533. {
  534. struct drm_device *dev = bl_get_data(bd);
  535. intel_panel_set_backlight(dev, bd->props.brightness,
  536. bd->props.max_brightness);
  537. return 0;
  538. }
  539. static int intel_panel_get_brightness(struct backlight_device *bd)
  540. {
  541. struct drm_device *dev = bl_get_data(bd);
  542. return intel_panel_get_backlight(dev);
  543. }
  544. static const struct backlight_ops intel_panel_bl_ops = {
  545. .update_status = intel_panel_update_status,
  546. .get_brightness = intel_panel_get_brightness,
  547. };
  548. int intel_panel_setup_backlight(struct drm_connector *connector)
  549. {
  550. struct drm_device *dev = connector->dev;
  551. struct drm_i915_private *dev_priv = dev->dev_private;
  552. struct backlight_properties props;
  553. unsigned long flags;
  554. intel_panel_init_backlight(dev);
  555. if (WARN_ON(dev_priv->backlight.device))
  556. return -ENODEV;
  557. memset(&props, 0, sizeof(props));
  558. props.type = BACKLIGHT_RAW;
  559. props.brightness = dev_priv->backlight.level;
  560. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  561. props.max_brightness = intel_panel_get_max_backlight(dev);
  562. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  563. if (props.max_brightness == 0) {
  564. DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
  565. return -ENODEV;
  566. }
  567. dev_priv->backlight.device =
  568. backlight_device_register("intel_backlight",
  569. &connector->kdev, dev,
  570. &intel_panel_bl_ops, &props);
  571. if (IS_ERR(dev_priv->backlight.device)) {
  572. DRM_ERROR("Failed to register backlight: %ld\n",
  573. PTR_ERR(dev_priv->backlight.device));
  574. dev_priv->backlight.device = NULL;
  575. return -ENODEV;
  576. }
  577. return 0;
  578. }
  579. void intel_panel_destroy_backlight(struct drm_device *dev)
  580. {
  581. struct drm_i915_private *dev_priv = dev->dev_private;
  582. if (dev_priv->backlight.device) {
  583. backlight_device_unregister(dev_priv->backlight.device);
  584. dev_priv->backlight.device = NULL;
  585. }
  586. }
  587. #else
  588. int intel_panel_setup_backlight(struct drm_connector *connector)
  589. {
  590. intel_panel_init_backlight(connector->dev);
  591. return 0;
  592. }
  593. void intel_panel_destroy_backlight(struct drm_device *dev)
  594. {
  595. return;
  596. }
  597. #endif
  598. int intel_panel_init(struct intel_panel *panel,
  599. struct drm_display_mode *fixed_mode)
  600. {
  601. panel->fixed_mode = fixed_mode;
  602. return 0;
  603. }
  604. void intel_panel_fini(struct intel_panel *panel)
  605. {
  606. struct intel_connector *intel_connector =
  607. container_of(panel, struct intel_connector, panel);
  608. if (panel->fixed_mode)
  609. drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
  610. }