intel_pm.c 152 KB

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  1. /*
  2. * Copyright © 2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eugeni Dodonov <eugeni.dodonov@intel.com>
  25. *
  26. */
  27. #include <linux/cpufreq.h>
  28. #include "i915_drv.h"
  29. #include "intel_drv.h"
  30. #include "../../../platform/x86/intel_ips.h"
  31. #include <linux/module.h>
  32. #include <drm/i915_powerwell.h>
  33. /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  34. * framebuffer contents in-memory, aiming at reducing the required bandwidth
  35. * during in-memory transfers and, therefore, reduce the power packet.
  36. *
  37. * The benefits of FBC are mostly visible with solid backgrounds and
  38. * variation-less patterns.
  39. *
  40. * FBC-related functionality can be enabled by the means of the
  41. * i915.i915_enable_fbc parameter
  42. */
  43. static bool intel_crtc_active(struct drm_crtc *crtc)
  44. {
  45. /* Be paranoid as we can arrive here with only partial
  46. * state retrieved from the hardware during setup.
  47. */
  48. return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
  49. }
  50. static void i8xx_disable_fbc(struct drm_device *dev)
  51. {
  52. struct drm_i915_private *dev_priv = dev->dev_private;
  53. u32 fbc_ctl;
  54. /* Disable compression */
  55. fbc_ctl = I915_READ(FBC_CONTROL);
  56. if ((fbc_ctl & FBC_CTL_EN) == 0)
  57. return;
  58. fbc_ctl &= ~FBC_CTL_EN;
  59. I915_WRITE(FBC_CONTROL, fbc_ctl);
  60. /* Wait for compressing bit to clear */
  61. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  62. DRM_DEBUG_KMS("FBC idle timed out\n");
  63. return;
  64. }
  65. DRM_DEBUG_KMS("disabled FBC\n");
  66. }
  67. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  68. {
  69. struct drm_device *dev = crtc->dev;
  70. struct drm_i915_private *dev_priv = dev->dev_private;
  71. struct drm_framebuffer *fb = crtc->fb;
  72. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  73. struct drm_i915_gem_object *obj = intel_fb->obj;
  74. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  75. int cfb_pitch;
  76. int plane, i;
  77. u32 fbc_ctl, fbc_ctl2;
  78. cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
  79. if (fb->pitches[0] < cfb_pitch)
  80. cfb_pitch = fb->pitches[0];
  81. /* FBC_CTL wants 64B units */
  82. cfb_pitch = (cfb_pitch / 64) - 1;
  83. plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  84. /* Clear old tags */
  85. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  86. I915_WRITE(FBC_TAG + (i * 4), 0);
  87. /* Set it up... */
  88. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  89. fbc_ctl2 |= plane;
  90. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  91. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  92. /* enable it... */
  93. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  94. if (IS_I945GM(dev))
  95. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  96. fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  97. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  98. fbc_ctl |= obj->fence_reg;
  99. I915_WRITE(FBC_CONTROL, fbc_ctl);
  100. DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
  101. cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
  102. }
  103. static bool i8xx_fbc_enabled(struct drm_device *dev)
  104. {
  105. struct drm_i915_private *dev_priv = dev->dev_private;
  106. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  107. }
  108. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  109. {
  110. struct drm_device *dev = crtc->dev;
  111. struct drm_i915_private *dev_priv = dev->dev_private;
  112. struct drm_framebuffer *fb = crtc->fb;
  113. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  114. struct drm_i915_gem_object *obj = intel_fb->obj;
  115. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  116. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  117. unsigned long stall_watermark = 200;
  118. u32 dpfc_ctl;
  119. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  120. dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
  121. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  122. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  123. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  124. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  125. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  126. /* enable it... */
  127. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  128. DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
  129. }
  130. static void g4x_disable_fbc(struct drm_device *dev)
  131. {
  132. struct drm_i915_private *dev_priv = dev->dev_private;
  133. u32 dpfc_ctl;
  134. /* Disable compression */
  135. dpfc_ctl = I915_READ(DPFC_CONTROL);
  136. if (dpfc_ctl & DPFC_CTL_EN) {
  137. dpfc_ctl &= ~DPFC_CTL_EN;
  138. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  139. DRM_DEBUG_KMS("disabled FBC\n");
  140. }
  141. }
  142. static bool g4x_fbc_enabled(struct drm_device *dev)
  143. {
  144. struct drm_i915_private *dev_priv = dev->dev_private;
  145. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  146. }
  147. static void sandybridge_blit_fbc_update(struct drm_device *dev)
  148. {
  149. struct drm_i915_private *dev_priv = dev->dev_private;
  150. u32 blt_ecoskpd;
  151. /* Make sure blitter notifies FBC of writes */
  152. gen6_gt_force_wake_get(dev_priv);
  153. blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  154. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  155. GEN6_BLITTER_LOCK_SHIFT;
  156. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  157. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  158. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  159. blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  160. GEN6_BLITTER_LOCK_SHIFT);
  161. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  162. POSTING_READ(GEN6_BLITTER_ECOSKPD);
  163. gen6_gt_force_wake_put(dev_priv);
  164. }
  165. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  166. {
  167. struct drm_device *dev = crtc->dev;
  168. struct drm_i915_private *dev_priv = dev->dev_private;
  169. struct drm_framebuffer *fb = crtc->fb;
  170. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  171. struct drm_i915_gem_object *obj = intel_fb->obj;
  172. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  173. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  174. unsigned long stall_watermark = 200;
  175. u32 dpfc_ctl;
  176. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  177. dpfc_ctl &= DPFC_RESERVED;
  178. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  179. /* Set persistent mode for front-buffer rendering, ala X. */
  180. dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
  181. dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
  182. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  183. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  184. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  185. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  186. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  187. I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
  188. /* enable it... */
  189. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  190. if (IS_GEN6(dev)) {
  191. I915_WRITE(SNB_DPFC_CTL_SA,
  192. SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  193. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  194. sandybridge_blit_fbc_update(dev);
  195. }
  196. DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
  197. }
  198. static void ironlake_disable_fbc(struct drm_device *dev)
  199. {
  200. struct drm_i915_private *dev_priv = dev->dev_private;
  201. u32 dpfc_ctl;
  202. /* Disable compression */
  203. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  204. if (dpfc_ctl & DPFC_CTL_EN) {
  205. dpfc_ctl &= ~DPFC_CTL_EN;
  206. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  207. if (IS_IVYBRIDGE(dev))
  208. /* WaFbcDisableDpfcClockGating:ivb */
  209. I915_WRITE(ILK_DSPCLK_GATE_D,
  210. I915_READ(ILK_DSPCLK_GATE_D) &
  211. ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
  212. if (IS_HASWELL(dev))
  213. /* WaFbcDisableDpfcClockGating:hsw */
  214. I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
  215. I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
  216. ~HSW_DPFC_GATING_DISABLE);
  217. DRM_DEBUG_KMS("disabled FBC\n");
  218. }
  219. }
  220. static bool ironlake_fbc_enabled(struct drm_device *dev)
  221. {
  222. struct drm_i915_private *dev_priv = dev->dev_private;
  223. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  224. }
  225. static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  226. {
  227. struct drm_device *dev = crtc->dev;
  228. struct drm_i915_private *dev_priv = dev->dev_private;
  229. struct drm_framebuffer *fb = crtc->fb;
  230. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  231. struct drm_i915_gem_object *obj = intel_fb->obj;
  232. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  233. I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
  234. I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
  235. IVB_DPFC_CTL_FENCE_EN |
  236. intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
  237. if (IS_IVYBRIDGE(dev)) {
  238. /* WaFbcAsynchFlipDisableFbcQueue:ivb */
  239. I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
  240. /* WaFbcDisableDpfcClockGating:ivb */
  241. I915_WRITE(ILK_DSPCLK_GATE_D,
  242. I915_READ(ILK_DSPCLK_GATE_D) |
  243. ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
  244. } else {
  245. /* WaFbcAsynchFlipDisableFbcQueue:hsw */
  246. I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
  247. HSW_BYPASS_FBC_QUEUE);
  248. /* WaFbcDisableDpfcClockGating:hsw */
  249. I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
  250. I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
  251. HSW_DPFC_GATING_DISABLE);
  252. }
  253. I915_WRITE(SNB_DPFC_CTL_SA,
  254. SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  255. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  256. sandybridge_blit_fbc_update(dev);
  257. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  258. }
  259. bool intel_fbc_enabled(struct drm_device *dev)
  260. {
  261. struct drm_i915_private *dev_priv = dev->dev_private;
  262. if (!dev_priv->display.fbc_enabled)
  263. return false;
  264. return dev_priv->display.fbc_enabled(dev);
  265. }
  266. static void intel_fbc_work_fn(struct work_struct *__work)
  267. {
  268. struct intel_fbc_work *work =
  269. container_of(to_delayed_work(__work),
  270. struct intel_fbc_work, work);
  271. struct drm_device *dev = work->crtc->dev;
  272. struct drm_i915_private *dev_priv = dev->dev_private;
  273. mutex_lock(&dev->struct_mutex);
  274. if (work == dev_priv->fbc.fbc_work) {
  275. /* Double check that we haven't switched fb without cancelling
  276. * the prior work.
  277. */
  278. if (work->crtc->fb == work->fb) {
  279. dev_priv->display.enable_fbc(work->crtc,
  280. work->interval);
  281. dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
  282. dev_priv->fbc.fb_id = work->crtc->fb->base.id;
  283. dev_priv->fbc.y = work->crtc->y;
  284. }
  285. dev_priv->fbc.fbc_work = NULL;
  286. }
  287. mutex_unlock(&dev->struct_mutex);
  288. kfree(work);
  289. }
  290. static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
  291. {
  292. if (dev_priv->fbc.fbc_work == NULL)
  293. return;
  294. DRM_DEBUG_KMS("cancelling pending FBC enable\n");
  295. /* Synchronisation is provided by struct_mutex and checking of
  296. * dev_priv->fbc.fbc_work, so we can perform the cancellation
  297. * entirely asynchronously.
  298. */
  299. if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
  300. /* tasklet was killed before being run, clean up */
  301. kfree(dev_priv->fbc.fbc_work);
  302. /* Mark the work as no longer wanted so that if it does
  303. * wake-up (because the work was already running and waiting
  304. * for our mutex), it will discover that is no longer
  305. * necessary to run.
  306. */
  307. dev_priv->fbc.fbc_work = NULL;
  308. }
  309. static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  310. {
  311. struct intel_fbc_work *work;
  312. struct drm_device *dev = crtc->dev;
  313. struct drm_i915_private *dev_priv = dev->dev_private;
  314. if (!dev_priv->display.enable_fbc)
  315. return;
  316. intel_cancel_fbc_work(dev_priv);
  317. work = kzalloc(sizeof *work, GFP_KERNEL);
  318. if (work == NULL) {
  319. DRM_ERROR("Failed to allocate FBC work structure\n");
  320. dev_priv->display.enable_fbc(crtc, interval);
  321. return;
  322. }
  323. work->crtc = crtc;
  324. work->fb = crtc->fb;
  325. work->interval = interval;
  326. INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
  327. dev_priv->fbc.fbc_work = work;
  328. /* Delay the actual enabling to let pageflipping cease and the
  329. * display to settle before starting the compression. Note that
  330. * this delay also serves a second purpose: it allows for a
  331. * vblank to pass after disabling the FBC before we attempt
  332. * to modify the control registers.
  333. *
  334. * A more complicated solution would involve tracking vblanks
  335. * following the termination of the page-flipping sequence
  336. * and indeed performing the enable as a co-routine and not
  337. * waiting synchronously upon the vblank.
  338. *
  339. * WaFbcWaitForVBlankBeforeEnable:ilk,snb
  340. */
  341. schedule_delayed_work(&work->work, msecs_to_jiffies(50));
  342. }
  343. void intel_disable_fbc(struct drm_device *dev)
  344. {
  345. struct drm_i915_private *dev_priv = dev->dev_private;
  346. intel_cancel_fbc_work(dev_priv);
  347. if (!dev_priv->display.disable_fbc)
  348. return;
  349. dev_priv->display.disable_fbc(dev);
  350. dev_priv->fbc.plane = -1;
  351. }
  352. static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
  353. enum no_fbc_reason reason)
  354. {
  355. if (dev_priv->fbc.no_fbc_reason == reason)
  356. return false;
  357. dev_priv->fbc.no_fbc_reason = reason;
  358. return true;
  359. }
  360. /**
  361. * intel_update_fbc - enable/disable FBC as needed
  362. * @dev: the drm_device
  363. *
  364. * Set up the framebuffer compression hardware at mode set time. We
  365. * enable it if possible:
  366. * - plane A only (on pre-965)
  367. * - no pixel mulitply/line duplication
  368. * - no alpha buffer discard
  369. * - no dual wide
  370. * - framebuffer <= max_hdisplay in width, max_vdisplay in height
  371. *
  372. * We can't assume that any compression will take place (worst case),
  373. * so the compressed buffer has to be the same size as the uncompressed
  374. * one. It also must reside (along with the line length buffer) in
  375. * stolen memory.
  376. *
  377. * We need to enable/disable FBC on a global basis.
  378. */
  379. void intel_update_fbc(struct drm_device *dev)
  380. {
  381. struct drm_i915_private *dev_priv = dev->dev_private;
  382. struct drm_crtc *crtc = NULL, *tmp_crtc;
  383. struct intel_crtc *intel_crtc;
  384. struct drm_framebuffer *fb;
  385. struct intel_framebuffer *intel_fb;
  386. struct drm_i915_gem_object *obj;
  387. unsigned int max_hdisplay, max_vdisplay;
  388. if (!I915_HAS_FBC(dev)) {
  389. set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
  390. return;
  391. }
  392. if (!i915_powersave) {
  393. if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
  394. DRM_DEBUG_KMS("fbc disabled per module param\n");
  395. return;
  396. }
  397. /*
  398. * If FBC is already on, we just have to verify that we can
  399. * keep it that way...
  400. * Need to disable if:
  401. * - more than one pipe is active
  402. * - changing FBC params (stride, fence, mode)
  403. * - new fb is too large to fit in compressed buffer
  404. * - going to an unsupported config (interlace, pixel multiply, etc.)
  405. */
  406. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  407. if (intel_crtc_active(tmp_crtc) &&
  408. !to_intel_crtc(tmp_crtc)->primary_disabled) {
  409. if (crtc) {
  410. if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
  411. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  412. goto out_disable;
  413. }
  414. crtc = tmp_crtc;
  415. }
  416. }
  417. if (!crtc || crtc->fb == NULL) {
  418. if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
  419. DRM_DEBUG_KMS("no output, disabling\n");
  420. goto out_disable;
  421. }
  422. intel_crtc = to_intel_crtc(crtc);
  423. fb = crtc->fb;
  424. intel_fb = to_intel_framebuffer(fb);
  425. obj = intel_fb->obj;
  426. if (i915_enable_fbc < 0 &&
  427. INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
  428. if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
  429. DRM_DEBUG_KMS("disabled per chip default\n");
  430. goto out_disable;
  431. }
  432. if (!i915_enable_fbc) {
  433. if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
  434. DRM_DEBUG_KMS("fbc disabled per module param\n");
  435. goto out_disable;
  436. }
  437. if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  438. (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  439. if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
  440. DRM_DEBUG_KMS("mode incompatible with compression, "
  441. "disabling\n");
  442. goto out_disable;
  443. }
  444. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  445. max_hdisplay = 4096;
  446. max_vdisplay = 2048;
  447. } else {
  448. max_hdisplay = 2048;
  449. max_vdisplay = 1536;
  450. }
  451. if ((crtc->mode.hdisplay > max_hdisplay) ||
  452. (crtc->mode.vdisplay > max_vdisplay)) {
  453. if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
  454. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  455. goto out_disable;
  456. }
  457. if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
  458. intel_crtc->plane != 0) {
  459. if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
  460. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  461. goto out_disable;
  462. }
  463. /* The use of a CPU fence is mandatory in order to detect writes
  464. * by the CPU to the scanout and trigger updates to the FBC.
  465. */
  466. if (obj->tiling_mode != I915_TILING_X ||
  467. obj->fence_reg == I915_FENCE_REG_NONE) {
  468. if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
  469. DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
  470. goto out_disable;
  471. }
  472. /* If the kernel debugger is active, always disable compression */
  473. if (in_dbg_master())
  474. goto out_disable;
  475. if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
  476. if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
  477. DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
  478. goto out_disable;
  479. }
  480. /* If the scanout has not changed, don't modify the FBC settings.
  481. * Note that we make the fundamental assumption that the fb->obj
  482. * cannot be unpinned (and have its GTT offset and fence revoked)
  483. * without first being decoupled from the scanout and FBC disabled.
  484. */
  485. if (dev_priv->fbc.plane == intel_crtc->plane &&
  486. dev_priv->fbc.fb_id == fb->base.id &&
  487. dev_priv->fbc.y == crtc->y)
  488. return;
  489. if (intel_fbc_enabled(dev)) {
  490. /* We update FBC along two paths, after changing fb/crtc
  491. * configuration (modeswitching) and after page-flipping
  492. * finishes. For the latter, we know that not only did
  493. * we disable the FBC at the start of the page-flip
  494. * sequence, but also more than one vblank has passed.
  495. *
  496. * For the former case of modeswitching, it is possible
  497. * to switch between two FBC valid configurations
  498. * instantaneously so we do need to disable the FBC
  499. * before we can modify its control registers. We also
  500. * have to wait for the next vblank for that to take
  501. * effect. However, since we delay enabling FBC we can
  502. * assume that a vblank has passed since disabling and
  503. * that we can safely alter the registers in the deferred
  504. * callback.
  505. *
  506. * In the scenario that we go from a valid to invalid
  507. * and then back to valid FBC configuration we have
  508. * no strict enforcement that a vblank occurred since
  509. * disabling the FBC. However, along all current pipe
  510. * disabling paths we do need to wait for a vblank at
  511. * some point. And we wait before enabling FBC anyway.
  512. */
  513. DRM_DEBUG_KMS("disabling active FBC for update\n");
  514. intel_disable_fbc(dev);
  515. }
  516. intel_enable_fbc(crtc, 500);
  517. dev_priv->fbc.no_fbc_reason = FBC_OK;
  518. return;
  519. out_disable:
  520. /* Multiple disables should be harmless */
  521. if (intel_fbc_enabled(dev)) {
  522. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  523. intel_disable_fbc(dev);
  524. }
  525. i915_gem_stolen_cleanup_compression(dev);
  526. }
  527. static void i915_pineview_get_mem_freq(struct drm_device *dev)
  528. {
  529. drm_i915_private_t *dev_priv = dev->dev_private;
  530. u32 tmp;
  531. tmp = I915_READ(CLKCFG);
  532. switch (tmp & CLKCFG_FSB_MASK) {
  533. case CLKCFG_FSB_533:
  534. dev_priv->fsb_freq = 533; /* 133*4 */
  535. break;
  536. case CLKCFG_FSB_800:
  537. dev_priv->fsb_freq = 800; /* 200*4 */
  538. break;
  539. case CLKCFG_FSB_667:
  540. dev_priv->fsb_freq = 667; /* 167*4 */
  541. break;
  542. case CLKCFG_FSB_400:
  543. dev_priv->fsb_freq = 400; /* 100*4 */
  544. break;
  545. }
  546. switch (tmp & CLKCFG_MEM_MASK) {
  547. case CLKCFG_MEM_533:
  548. dev_priv->mem_freq = 533;
  549. break;
  550. case CLKCFG_MEM_667:
  551. dev_priv->mem_freq = 667;
  552. break;
  553. case CLKCFG_MEM_800:
  554. dev_priv->mem_freq = 800;
  555. break;
  556. }
  557. /* detect pineview DDR3 setting */
  558. tmp = I915_READ(CSHRDDR3CTL);
  559. dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
  560. }
  561. static void i915_ironlake_get_mem_freq(struct drm_device *dev)
  562. {
  563. drm_i915_private_t *dev_priv = dev->dev_private;
  564. u16 ddrpll, csipll;
  565. ddrpll = I915_READ16(DDRMPLL1);
  566. csipll = I915_READ16(CSIPLL0);
  567. switch (ddrpll & 0xff) {
  568. case 0xc:
  569. dev_priv->mem_freq = 800;
  570. break;
  571. case 0x10:
  572. dev_priv->mem_freq = 1066;
  573. break;
  574. case 0x14:
  575. dev_priv->mem_freq = 1333;
  576. break;
  577. case 0x18:
  578. dev_priv->mem_freq = 1600;
  579. break;
  580. default:
  581. DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
  582. ddrpll & 0xff);
  583. dev_priv->mem_freq = 0;
  584. break;
  585. }
  586. dev_priv->ips.r_t = dev_priv->mem_freq;
  587. switch (csipll & 0x3ff) {
  588. case 0x00c:
  589. dev_priv->fsb_freq = 3200;
  590. break;
  591. case 0x00e:
  592. dev_priv->fsb_freq = 3733;
  593. break;
  594. case 0x010:
  595. dev_priv->fsb_freq = 4266;
  596. break;
  597. case 0x012:
  598. dev_priv->fsb_freq = 4800;
  599. break;
  600. case 0x014:
  601. dev_priv->fsb_freq = 5333;
  602. break;
  603. case 0x016:
  604. dev_priv->fsb_freq = 5866;
  605. break;
  606. case 0x018:
  607. dev_priv->fsb_freq = 6400;
  608. break;
  609. default:
  610. DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
  611. csipll & 0x3ff);
  612. dev_priv->fsb_freq = 0;
  613. break;
  614. }
  615. if (dev_priv->fsb_freq == 3200) {
  616. dev_priv->ips.c_m = 0;
  617. } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
  618. dev_priv->ips.c_m = 1;
  619. } else {
  620. dev_priv->ips.c_m = 2;
  621. }
  622. }
  623. static const struct cxsr_latency cxsr_latency_table[] = {
  624. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  625. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  626. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  627. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  628. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  629. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  630. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  631. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  632. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  633. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  634. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  635. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  636. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  637. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  638. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  639. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  640. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  641. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  642. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  643. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  644. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  645. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  646. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  647. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  648. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  649. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  650. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  651. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  652. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  653. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  654. };
  655. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  656. int is_ddr3,
  657. int fsb,
  658. int mem)
  659. {
  660. const struct cxsr_latency *latency;
  661. int i;
  662. if (fsb == 0 || mem == 0)
  663. return NULL;
  664. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  665. latency = &cxsr_latency_table[i];
  666. if (is_desktop == latency->is_desktop &&
  667. is_ddr3 == latency->is_ddr3 &&
  668. fsb == latency->fsb_freq && mem == latency->mem_freq)
  669. return latency;
  670. }
  671. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  672. return NULL;
  673. }
  674. static void pineview_disable_cxsr(struct drm_device *dev)
  675. {
  676. struct drm_i915_private *dev_priv = dev->dev_private;
  677. /* deactivate cxsr */
  678. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  679. }
  680. /*
  681. * Latency for FIFO fetches is dependent on several factors:
  682. * - memory configuration (speed, channels)
  683. * - chipset
  684. * - current MCH state
  685. * It can be fairly high in some situations, so here we assume a fairly
  686. * pessimal value. It's a tradeoff between extra memory fetches (if we
  687. * set this value too high, the FIFO will fetch frequently to stay full)
  688. * and power consumption (set it too low to save power and we might see
  689. * FIFO underruns and display "flicker").
  690. *
  691. * A value of 5us seems to be a good balance; safe for very low end
  692. * platforms but not overly aggressive on lower latency configs.
  693. */
  694. static const int latency_ns = 5000;
  695. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  696. {
  697. struct drm_i915_private *dev_priv = dev->dev_private;
  698. uint32_t dsparb = I915_READ(DSPARB);
  699. int size;
  700. size = dsparb & 0x7f;
  701. if (plane)
  702. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  703. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  704. plane ? "B" : "A", size);
  705. return size;
  706. }
  707. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  708. {
  709. struct drm_i915_private *dev_priv = dev->dev_private;
  710. uint32_t dsparb = I915_READ(DSPARB);
  711. int size;
  712. size = dsparb & 0x1ff;
  713. if (plane)
  714. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  715. size >>= 1; /* Convert to cachelines */
  716. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  717. plane ? "B" : "A", size);
  718. return size;
  719. }
  720. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  721. {
  722. struct drm_i915_private *dev_priv = dev->dev_private;
  723. uint32_t dsparb = I915_READ(DSPARB);
  724. int size;
  725. size = dsparb & 0x7f;
  726. size >>= 2; /* Convert to cachelines */
  727. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  728. plane ? "B" : "A",
  729. size);
  730. return size;
  731. }
  732. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  733. {
  734. struct drm_i915_private *dev_priv = dev->dev_private;
  735. uint32_t dsparb = I915_READ(DSPARB);
  736. int size;
  737. size = dsparb & 0x7f;
  738. size >>= 1; /* Convert to cachelines */
  739. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  740. plane ? "B" : "A", size);
  741. return size;
  742. }
  743. /* Pineview has different values for various configs */
  744. static const struct intel_watermark_params pineview_display_wm = {
  745. PINEVIEW_DISPLAY_FIFO,
  746. PINEVIEW_MAX_WM,
  747. PINEVIEW_DFT_WM,
  748. PINEVIEW_GUARD_WM,
  749. PINEVIEW_FIFO_LINE_SIZE
  750. };
  751. static const struct intel_watermark_params pineview_display_hplloff_wm = {
  752. PINEVIEW_DISPLAY_FIFO,
  753. PINEVIEW_MAX_WM,
  754. PINEVIEW_DFT_HPLLOFF_WM,
  755. PINEVIEW_GUARD_WM,
  756. PINEVIEW_FIFO_LINE_SIZE
  757. };
  758. static const struct intel_watermark_params pineview_cursor_wm = {
  759. PINEVIEW_CURSOR_FIFO,
  760. PINEVIEW_CURSOR_MAX_WM,
  761. PINEVIEW_CURSOR_DFT_WM,
  762. PINEVIEW_CURSOR_GUARD_WM,
  763. PINEVIEW_FIFO_LINE_SIZE,
  764. };
  765. static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
  766. PINEVIEW_CURSOR_FIFO,
  767. PINEVIEW_CURSOR_MAX_WM,
  768. PINEVIEW_CURSOR_DFT_WM,
  769. PINEVIEW_CURSOR_GUARD_WM,
  770. PINEVIEW_FIFO_LINE_SIZE
  771. };
  772. static const struct intel_watermark_params g4x_wm_info = {
  773. G4X_FIFO_SIZE,
  774. G4X_MAX_WM,
  775. G4X_MAX_WM,
  776. 2,
  777. G4X_FIFO_LINE_SIZE,
  778. };
  779. static const struct intel_watermark_params g4x_cursor_wm_info = {
  780. I965_CURSOR_FIFO,
  781. I965_CURSOR_MAX_WM,
  782. I965_CURSOR_DFT_WM,
  783. 2,
  784. G4X_FIFO_LINE_SIZE,
  785. };
  786. static const struct intel_watermark_params valleyview_wm_info = {
  787. VALLEYVIEW_FIFO_SIZE,
  788. VALLEYVIEW_MAX_WM,
  789. VALLEYVIEW_MAX_WM,
  790. 2,
  791. G4X_FIFO_LINE_SIZE,
  792. };
  793. static const struct intel_watermark_params valleyview_cursor_wm_info = {
  794. I965_CURSOR_FIFO,
  795. VALLEYVIEW_CURSOR_MAX_WM,
  796. I965_CURSOR_DFT_WM,
  797. 2,
  798. G4X_FIFO_LINE_SIZE,
  799. };
  800. static const struct intel_watermark_params i965_cursor_wm_info = {
  801. I965_CURSOR_FIFO,
  802. I965_CURSOR_MAX_WM,
  803. I965_CURSOR_DFT_WM,
  804. 2,
  805. I915_FIFO_LINE_SIZE,
  806. };
  807. static const struct intel_watermark_params i945_wm_info = {
  808. I945_FIFO_SIZE,
  809. I915_MAX_WM,
  810. 1,
  811. 2,
  812. I915_FIFO_LINE_SIZE
  813. };
  814. static const struct intel_watermark_params i915_wm_info = {
  815. I915_FIFO_SIZE,
  816. I915_MAX_WM,
  817. 1,
  818. 2,
  819. I915_FIFO_LINE_SIZE
  820. };
  821. static const struct intel_watermark_params i855_wm_info = {
  822. I855GM_FIFO_SIZE,
  823. I915_MAX_WM,
  824. 1,
  825. 2,
  826. I830_FIFO_LINE_SIZE
  827. };
  828. static const struct intel_watermark_params i830_wm_info = {
  829. I830_FIFO_SIZE,
  830. I915_MAX_WM,
  831. 1,
  832. 2,
  833. I830_FIFO_LINE_SIZE
  834. };
  835. static const struct intel_watermark_params ironlake_display_wm_info = {
  836. ILK_DISPLAY_FIFO,
  837. ILK_DISPLAY_MAXWM,
  838. ILK_DISPLAY_DFTWM,
  839. 2,
  840. ILK_FIFO_LINE_SIZE
  841. };
  842. static const struct intel_watermark_params ironlake_cursor_wm_info = {
  843. ILK_CURSOR_FIFO,
  844. ILK_CURSOR_MAXWM,
  845. ILK_CURSOR_DFTWM,
  846. 2,
  847. ILK_FIFO_LINE_SIZE
  848. };
  849. static const struct intel_watermark_params ironlake_display_srwm_info = {
  850. ILK_DISPLAY_SR_FIFO,
  851. ILK_DISPLAY_MAX_SRWM,
  852. ILK_DISPLAY_DFT_SRWM,
  853. 2,
  854. ILK_FIFO_LINE_SIZE
  855. };
  856. static const struct intel_watermark_params ironlake_cursor_srwm_info = {
  857. ILK_CURSOR_SR_FIFO,
  858. ILK_CURSOR_MAX_SRWM,
  859. ILK_CURSOR_DFT_SRWM,
  860. 2,
  861. ILK_FIFO_LINE_SIZE
  862. };
  863. static const struct intel_watermark_params sandybridge_display_wm_info = {
  864. SNB_DISPLAY_FIFO,
  865. SNB_DISPLAY_MAXWM,
  866. SNB_DISPLAY_DFTWM,
  867. 2,
  868. SNB_FIFO_LINE_SIZE
  869. };
  870. static const struct intel_watermark_params sandybridge_cursor_wm_info = {
  871. SNB_CURSOR_FIFO,
  872. SNB_CURSOR_MAXWM,
  873. SNB_CURSOR_DFTWM,
  874. 2,
  875. SNB_FIFO_LINE_SIZE
  876. };
  877. static const struct intel_watermark_params sandybridge_display_srwm_info = {
  878. SNB_DISPLAY_SR_FIFO,
  879. SNB_DISPLAY_MAX_SRWM,
  880. SNB_DISPLAY_DFT_SRWM,
  881. 2,
  882. SNB_FIFO_LINE_SIZE
  883. };
  884. static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
  885. SNB_CURSOR_SR_FIFO,
  886. SNB_CURSOR_MAX_SRWM,
  887. SNB_CURSOR_DFT_SRWM,
  888. 2,
  889. SNB_FIFO_LINE_SIZE
  890. };
  891. /**
  892. * intel_calculate_wm - calculate watermark level
  893. * @clock_in_khz: pixel clock
  894. * @wm: chip FIFO params
  895. * @pixel_size: display pixel size
  896. * @latency_ns: memory latency for the platform
  897. *
  898. * Calculate the watermark level (the level at which the display plane will
  899. * start fetching from memory again). Each chip has a different display
  900. * FIFO size and allocation, so the caller needs to figure that out and pass
  901. * in the correct intel_watermark_params structure.
  902. *
  903. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  904. * on the pixel size. When it reaches the watermark level, it'll start
  905. * fetching FIFO line sized based chunks from memory until the FIFO fills
  906. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  907. * will occur, and a display engine hang could result.
  908. */
  909. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  910. const struct intel_watermark_params *wm,
  911. int fifo_size,
  912. int pixel_size,
  913. unsigned long latency_ns)
  914. {
  915. long entries_required, wm_size;
  916. /*
  917. * Note: we need to make sure we don't overflow for various clock &
  918. * latency values.
  919. * clocks go from a few thousand to several hundred thousand.
  920. * latency is usually a few thousand
  921. */
  922. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  923. 1000;
  924. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  925. DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
  926. wm_size = fifo_size - (entries_required + wm->guard_size);
  927. DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
  928. /* Don't promote wm_size to unsigned... */
  929. if (wm_size > (long)wm->max_wm)
  930. wm_size = wm->max_wm;
  931. if (wm_size <= 0)
  932. wm_size = wm->default_wm;
  933. return wm_size;
  934. }
  935. static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  936. {
  937. struct drm_crtc *crtc, *enabled = NULL;
  938. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  939. if (intel_crtc_active(crtc)) {
  940. if (enabled)
  941. return NULL;
  942. enabled = crtc;
  943. }
  944. }
  945. return enabled;
  946. }
  947. static void pineview_update_wm(struct drm_device *dev)
  948. {
  949. struct drm_i915_private *dev_priv = dev->dev_private;
  950. struct drm_crtc *crtc;
  951. const struct cxsr_latency *latency;
  952. u32 reg;
  953. unsigned long wm;
  954. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  955. dev_priv->fsb_freq, dev_priv->mem_freq);
  956. if (!latency) {
  957. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  958. pineview_disable_cxsr(dev);
  959. return;
  960. }
  961. crtc = single_enabled_crtc(dev);
  962. if (crtc) {
  963. int clock = crtc->mode.clock;
  964. int pixel_size = crtc->fb->bits_per_pixel / 8;
  965. /* Display SR */
  966. wm = intel_calculate_wm(clock, &pineview_display_wm,
  967. pineview_display_wm.fifo_size,
  968. pixel_size, latency->display_sr);
  969. reg = I915_READ(DSPFW1);
  970. reg &= ~DSPFW_SR_MASK;
  971. reg |= wm << DSPFW_SR_SHIFT;
  972. I915_WRITE(DSPFW1, reg);
  973. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  974. /* cursor SR */
  975. wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  976. pineview_display_wm.fifo_size,
  977. pixel_size, latency->cursor_sr);
  978. reg = I915_READ(DSPFW3);
  979. reg &= ~DSPFW_CURSOR_SR_MASK;
  980. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  981. I915_WRITE(DSPFW3, reg);
  982. /* Display HPLL off SR */
  983. wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  984. pineview_display_hplloff_wm.fifo_size,
  985. pixel_size, latency->display_hpll_disable);
  986. reg = I915_READ(DSPFW3);
  987. reg &= ~DSPFW_HPLL_SR_MASK;
  988. reg |= wm & DSPFW_HPLL_SR_MASK;
  989. I915_WRITE(DSPFW3, reg);
  990. /* cursor HPLL off SR */
  991. wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  992. pineview_display_hplloff_wm.fifo_size,
  993. pixel_size, latency->cursor_hpll_disable);
  994. reg = I915_READ(DSPFW3);
  995. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  996. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  997. I915_WRITE(DSPFW3, reg);
  998. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  999. /* activate cxsr */
  1000. I915_WRITE(DSPFW3,
  1001. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  1002. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  1003. } else {
  1004. pineview_disable_cxsr(dev);
  1005. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  1006. }
  1007. }
  1008. static bool g4x_compute_wm0(struct drm_device *dev,
  1009. int plane,
  1010. const struct intel_watermark_params *display,
  1011. int display_latency_ns,
  1012. const struct intel_watermark_params *cursor,
  1013. int cursor_latency_ns,
  1014. int *plane_wm,
  1015. int *cursor_wm)
  1016. {
  1017. struct drm_crtc *crtc;
  1018. int htotal, hdisplay, clock, pixel_size;
  1019. int line_time_us, line_count;
  1020. int entries, tlb_miss;
  1021. crtc = intel_get_crtc_for_plane(dev, plane);
  1022. if (!intel_crtc_active(crtc)) {
  1023. *cursor_wm = cursor->guard_size;
  1024. *plane_wm = display->guard_size;
  1025. return false;
  1026. }
  1027. htotal = crtc->mode.htotal;
  1028. hdisplay = crtc->mode.hdisplay;
  1029. clock = crtc->mode.clock;
  1030. pixel_size = crtc->fb->bits_per_pixel / 8;
  1031. /* Use the small buffer method to calculate plane watermark */
  1032. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  1033. tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  1034. if (tlb_miss > 0)
  1035. entries += tlb_miss;
  1036. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  1037. *plane_wm = entries + display->guard_size;
  1038. if (*plane_wm > (int)display->max_wm)
  1039. *plane_wm = display->max_wm;
  1040. /* Use the large buffer method to calculate cursor watermark */
  1041. line_time_us = ((htotal * 1000) / clock);
  1042. line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
  1043. entries = line_count * 64 * pixel_size;
  1044. tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  1045. if (tlb_miss > 0)
  1046. entries += tlb_miss;
  1047. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1048. *cursor_wm = entries + cursor->guard_size;
  1049. if (*cursor_wm > (int)cursor->max_wm)
  1050. *cursor_wm = (int)cursor->max_wm;
  1051. return true;
  1052. }
  1053. /*
  1054. * Check the wm result.
  1055. *
  1056. * If any calculated watermark values is larger than the maximum value that
  1057. * can be programmed into the associated watermark register, that watermark
  1058. * must be disabled.
  1059. */
  1060. static bool g4x_check_srwm(struct drm_device *dev,
  1061. int display_wm, int cursor_wm,
  1062. const struct intel_watermark_params *display,
  1063. const struct intel_watermark_params *cursor)
  1064. {
  1065. DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
  1066. display_wm, cursor_wm);
  1067. if (display_wm > display->max_wm) {
  1068. DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
  1069. display_wm, display->max_wm);
  1070. return false;
  1071. }
  1072. if (cursor_wm > cursor->max_wm) {
  1073. DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
  1074. cursor_wm, cursor->max_wm);
  1075. return false;
  1076. }
  1077. if (!(display_wm || cursor_wm)) {
  1078. DRM_DEBUG_KMS("SR latency is 0, disabling\n");
  1079. return false;
  1080. }
  1081. return true;
  1082. }
  1083. static bool g4x_compute_srwm(struct drm_device *dev,
  1084. int plane,
  1085. int latency_ns,
  1086. const struct intel_watermark_params *display,
  1087. const struct intel_watermark_params *cursor,
  1088. int *display_wm, int *cursor_wm)
  1089. {
  1090. struct drm_crtc *crtc;
  1091. int hdisplay, htotal, pixel_size, clock;
  1092. unsigned long line_time_us;
  1093. int line_count, line_size;
  1094. int small, large;
  1095. int entries;
  1096. if (!latency_ns) {
  1097. *display_wm = *cursor_wm = 0;
  1098. return false;
  1099. }
  1100. crtc = intel_get_crtc_for_plane(dev, plane);
  1101. hdisplay = crtc->mode.hdisplay;
  1102. htotal = crtc->mode.htotal;
  1103. clock = crtc->mode.clock;
  1104. pixel_size = crtc->fb->bits_per_pixel / 8;
  1105. line_time_us = (htotal * 1000) / clock;
  1106. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1107. line_size = hdisplay * pixel_size;
  1108. /* Use the minimum of the small and large buffer method for primary */
  1109. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1110. large = line_count * line_size;
  1111. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1112. *display_wm = entries + display->guard_size;
  1113. /* calculate the self-refresh watermark for display cursor */
  1114. entries = line_count * pixel_size * 64;
  1115. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1116. *cursor_wm = entries + cursor->guard_size;
  1117. return g4x_check_srwm(dev,
  1118. *display_wm, *cursor_wm,
  1119. display, cursor);
  1120. }
  1121. static bool vlv_compute_drain_latency(struct drm_device *dev,
  1122. int plane,
  1123. int *plane_prec_mult,
  1124. int *plane_dl,
  1125. int *cursor_prec_mult,
  1126. int *cursor_dl)
  1127. {
  1128. struct drm_crtc *crtc;
  1129. int clock, pixel_size;
  1130. int entries;
  1131. crtc = intel_get_crtc_for_plane(dev, plane);
  1132. if (!intel_crtc_active(crtc))
  1133. return false;
  1134. clock = crtc->mode.clock; /* VESA DOT Clock */
  1135. pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
  1136. entries = (clock / 1000) * pixel_size;
  1137. *plane_prec_mult = (entries > 256) ?
  1138. DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1139. *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
  1140. pixel_size);
  1141. entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
  1142. *cursor_prec_mult = (entries > 256) ?
  1143. DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1144. *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
  1145. return true;
  1146. }
  1147. /*
  1148. * Update drain latency registers of memory arbiter
  1149. *
  1150. * Valleyview SoC has a new memory arbiter and needs drain latency registers
  1151. * to be programmed. Each plane has a drain latency multiplier and a drain
  1152. * latency value.
  1153. */
  1154. static void vlv_update_drain_latency(struct drm_device *dev)
  1155. {
  1156. struct drm_i915_private *dev_priv = dev->dev_private;
  1157. int planea_prec, planea_dl, planeb_prec, planeb_dl;
  1158. int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
  1159. int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
  1160. either 16 or 32 */
  1161. /* For plane A, Cursor A */
  1162. if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
  1163. &cursor_prec_mult, &cursora_dl)) {
  1164. cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1165. DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
  1166. planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1167. DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
  1168. I915_WRITE(VLV_DDL1, cursora_prec |
  1169. (cursora_dl << DDL_CURSORA_SHIFT) |
  1170. planea_prec | planea_dl);
  1171. }
  1172. /* For plane B, Cursor B */
  1173. if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
  1174. &cursor_prec_mult, &cursorb_dl)) {
  1175. cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1176. DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
  1177. planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1178. DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
  1179. I915_WRITE(VLV_DDL2, cursorb_prec |
  1180. (cursorb_dl << DDL_CURSORB_SHIFT) |
  1181. planeb_prec | planeb_dl);
  1182. }
  1183. }
  1184. #define single_plane_enabled(mask) is_power_of_2(mask)
  1185. static void valleyview_update_wm(struct drm_device *dev)
  1186. {
  1187. static const int sr_latency_ns = 12000;
  1188. struct drm_i915_private *dev_priv = dev->dev_private;
  1189. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1190. int plane_sr, cursor_sr;
  1191. int ignore_plane_sr, ignore_cursor_sr;
  1192. unsigned int enabled = 0;
  1193. vlv_update_drain_latency(dev);
  1194. if (g4x_compute_wm0(dev, PIPE_A,
  1195. &valleyview_wm_info, latency_ns,
  1196. &valleyview_cursor_wm_info, latency_ns,
  1197. &planea_wm, &cursora_wm))
  1198. enabled |= 1 << PIPE_A;
  1199. if (g4x_compute_wm0(dev, PIPE_B,
  1200. &valleyview_wm_info, latency_ns,
  1201. &valleyview_cursor_wm_info, latency_ns,
  1202. &planeb_wm, &cursorb_wm))
  1203. enabled |= 1 << PIPE_B;
  1204. if (single_plane_enabled(enabled) &&
  1205. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1206. sr_latency_ns,
  1207. &valleyview_wm_info,
  1208. &valleyview_cursor_wm_info,
  1209. &plane_sr, &ignore_cursor_sr) &&
  1210. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1211. 2*sr_latency_ns,
  1212. &valleyview_wm_info,
  1213. &valleyview_cursor_wm_info,
  1214. &ignore_plane_sr, &cursor_sr)) {
  1215. I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
  1216. } else {
  1217. I915_WRITE(FW_BLC_SELF_VLV,
  1218. I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
  1219. plane_sr = cursor_sr = 0;
  1220. }
  1221. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1222. planea_wm, cursora_wm,
  1223. planeb_wm, cursorb_wm,
  1224. plane_sr, cursor_sr);
  1225. I915_WRITE(DSPFW1,
  1226. (plane_sr << DSPFW_SR_SHIFT) |
  1227. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1228. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1229. planea_wm);
  1230. I915_WRITE(DSPFW2,
  1231. (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
  1232. (cursora_wm << DSPFW_CURSORA_SHIFT));
  1233. I915_WRITE(DSPFW3,
  1234. (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
  1235. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1236. }
  1237. static void g4x_update_wm(struct drm_device *dev)
  1238. {
  1239. static const int sr_latency_ns = 12000;
  1240. struct drm_i915_private *dev_priv = dev->dev_private;
  1241. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1242. int plane_sr, cursor_sr;
  1243. unsigned int enabled = 0;
  1244. if (g4x_compute_wm0(dev, PIPE_A,
  1245. &g4x_wm_info, latency_ns,
  1246. &g4x_cursor_wm_info, latency_ns,
  1247. &planea_wm, &cursora_wm))
  1248. enabled |= 1 << PIPE_A;
  1249. if (g4x_compute_wm0(dev, PIPE_B,
  1250. &g4x_wm_info, latency_ns,
  1251. &g4x_cursor_wm_info, latency_ns,
  1252. &planeb_wm, &cursorb_wm))
  1253. enabled |= 1 << PIPE_B;
  1254. if (single_plane_enabled(enabled) &&
  1255. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1256. sr_latency_ns,
  1257. &g4x_wm_info,
  1258. &g4x_cursor_wm_info,
  1259. &plane_sr, &cursor_sr)) {
  1260. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1261. } else {
  1262. I915_WRITE(FW_BLC_SELF,
  1263. I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
  1264. plane_sr = cursor_sr = 0;
  1265. }
  1266. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1267. planea_wm, cursora_wm,
  1268. planeb_wm, cursorb_wm,
  1269. plane_sr, cursor_sr);
  1270. I915_WRITE(DSPFW1,
  1271. (plane_sr << DSPFW_SR_SHIFT) |
  1272. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1273. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1274. planea_wm);
  1275. I915_WRITE(DSPFW2,
  1276. (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
  1277. (cursora_wm << DSPFW_CURSORA_SHIFT));
  1278. /* HPLL off in SR has some issues on G4x... disable it */
  1279. I915_WRITE(DSPFW3,
  1280. (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
  1281. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1282. }
  1283. static void i965_update_wm(struct drm_device *dev)
  1284. {
  1285. struct drm_i915_private *dev_priv = dev->dev_private;
  1286. struct drm_crtc *crtc;
  1287. int srwm = 1;
  1288. int cursor_sr = 16;
  1289. /* Calc sr entries for one plane configs */
  1290. crtc = single_enabled_crtc(dev);
  1291. if (crtc) {
  1292. /* self-refresh has much higher latency */
  1293. static const int sr_latency_ns = 12000;
  1294. int clock = crtc->mode.clock;
  1295. int htotal = crtc->mode.htotal;
  1296. int hdisplay = crtc->mode.hdisplay;
  1297. int pixel_size = crtc->fb->bits_per_pixel / 8;
  1298. unsigned long line_time_us;
  1299. int entries;
  1300. line_time_us = ((htotal * 1000) / clock);
  1301. /* Use ns/us then divide to preserve precision */
  1302. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1303. pixel_size * hdisplay;
  1304. entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  1305. srwm = I965_FIFO_SIZE - entries;
  1306. if (srwm < 0)
  1307. srwm = 1;
  1308. srwm &= 0x1ff;
  1309. DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
  1310. entries, srwm);
  1311. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1312. pixel_size * 64;
  1313. entries = DIV_ROUND_UP(entries,
  1314. i965_cursor_wm_info.cacheline_size);
  1315. cursor_sr = i965_cursor_wm_info.fifo_size -
  1316. (entries + i965_cursor_wm_info.guard_size);
  1317. if (cursor_sr > i965_cursor_wm_info.max_wm)
  1318. cursor_sr = i965_cursor_wm_info.max_wm;
  1319. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  1320. "cursor %d\n", srwm, cursor_sr);
  1321. if (IS_CRESTLINE(dev))
  1322. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1323. } else {
  1324. /* Turn off self refresh if both pipes are enabled */
  1325. if (IS_CRESTLINE(dev))
  1326. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  1327. & ~FW_BLC_SELF_EN);
  1328. }
  1329. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  1330. srwm);
  1331. /* 965 has limitations... */
  1332. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
  1333. (8 << 16) | (8 << 8) | (8 << 0));
  1334. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  1335. /* update cursor SR watermark */
  1336. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1337. }
  1338. static void i9xx_update_wm(struct drm_device *dev)
  1339. {
  1340. struct drm_i915_private *dev_priv = dev->dev_private;
  1341. const struct intel_watermark_params *wm_info;
  1342. uint32_t fwater_lo;
  1343. uint32_t fwater_hi;
  1344. int cwm, srwm = 1;
  1345. int fifo_size;
  1346. int planea_wm, planeb_wm;
  1347. struct drm_crtc *crtc, *enabled = NULL;
  1348. if (IS_I945GM(dev))
  1349. wm_info = &i945_wm_info;
  1350. else if (!IS_GEN2(dev))
  1351. wm_info = &i915_wm_info;
  1352. else
  1353. wm_info = &i855_wm_info;
  1354. fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  1355. crtc = intel_get_crtc_for_plane(dev, 0);
  1356. if (intel_crtc_active(crtc)) {
  1357. int cpp = crtc->fb->bits_per_pixel / 8;
  1358. if (IS_GEN2(dev))
  1359. cpp = 4;
  1360. planea_wm = intel_calculate_wm(crtc->mode.clock,
  1361. wm_info, fifo_size, cpp,
  1362. latency_ns);
  1363. enabled = crtc;
  1364. } else
  1365. planea_wm = fifo_size - wm_info->guard_size;
  1366. fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  1367. crtc = intel_get_crtc_for_plane(dev, 1);
  1368. if (intel_crtc_active(crtc)) {
  1369. int cpp = crtc->fb->bits_per_pixel / 8;
  1370. if (IS_GEN2(dev))
  1371. cpp = 4;
  1372. planeb_wm = intel_calculate_wm(crtc->mode.clock,
  1373. wm_info, fifo_size, cpp,
  1374. latency_ns);
  1375. if (enabled == NULL)
  1376. enabled = crtc;
  1377. else
  1378. enabled = NULL;
  1379. } else
  1380. planeb_wm = fifo_size - wm_info->guard_size;
  1381. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  1382. /*
  1383. * Overlay gets an aggressive default since video jitter is bad.
  1384. */
  1385. cwm = 2;
  1386. /* Play safe and disable self-refresh before adjusting watermarks. */
  1387. if (IS_I945G(dev) || IS_I945GM(dev))
  1388. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
  1389. else if (IS_I915GM(dev))
  1390. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  1391. /* Calc sr entries for one plane configs */
  1392. if (HAS_FW_BLC(dev) && enabled) {
  1393. /* self-refresh has much higher latency */
  1394. static const int sr_latency_ns = 6000;
  1395. int clock = enabled->mode.clock;
  1396. int htotal = enabled->mode.htotal;
  1397. int hdisplay = enabled->mode.hdisplay;
  1398. int pixel_size = enabled->fb->bits_per_pixel / 8;
  1399. unsigned long line_time_us;
  1400. int entries;
  1401. line_time_us = (htotal * 1000) / clock;
  1402. /* Use ns/us then divide to preserve precision */
  1403. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1404. pixel_size * hdisplay;
  1405. entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  1406. DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
  1407. srwm = wm_info->fifo_size - entries;
  1408. if (srwm < 0)
  1409. srwm = 1;
  1410. if (IS_I945G(dev) || IS_I945GM(dev))
  1411. I915_WRITE(FW_BLC_SELF,
  1412. FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  1413. else if (IS_I915GM(dev))
  1414. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  1415. }
  1416. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  1417. planea_wm, planeb_wm, cwm, srwm);
  1418. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  1419. fwater_hi = (cwm & 0x1f);
  1420. /* Set request length to 8 cachelines per fetch */
  1421. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  1422. fwater_hi = fwater_hi | (1 << 8);
  1423. I915_WRITE(FW_BLC, fwater_lo);
  1424. I915_WRITE(FW_BLC2, fwater_hi);
  1425. if (HAS_FW_BLC(dev)) {
  1426. if (enabled) {
  1427. if (IS_I945G(dev) || IS_I945GM(dev))
  1428. I915_WRITE(FW_BLC_SELF,
  1429. FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  1430. else if (IS_I915GM(dev))
  1431. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  1432. DRM_DEBUG_KMS("memory self refresh enabled\n");
  1433. } else
  1434. DRM_DEBUG_KMS("memory self refresh disabled\n");
  1435. }
  1436. }
  1437. static void i830_update_wm(struct drm_device *dev)
  1438. {
  1439. struct drm_i915_private *dev_priv = dev->dev_private;
  1440. struct drm_crtc *crtc;
  1441. uint32_t fwater_lo;
  1442. int planea_wm;
  1443. crtc = single_enabled_crtc(dev);
  1444. if (crtc == NULL)
  1445. return;
  1446. planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
  1447. dev_priv->display.get_fifo_size(dev, 0),
  1448. 4, latency_ns);
  1449. fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  1450. fwater_lo |= (3<<8) | planea_wm;
  1451. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  1452. I915_WRITE(FW_BLC, fwater_lo);
  1453. }
  1454. /*
  1455. * Check the wm result.
  1456. *
  1457. * If any calculated watermark values is larger than the maximum value that
  1458. * can be programmed into the associated watermark register, that watermark
  1459. * must be disabled.
  1460. */
  1461. static bool ironlake_check_srwm(struct drm_device *dev, int level,
  1462. int fbc_wm, int display_wm, int cursor_wm,
  1463. const struct intel_watermark_params *display,
  1464. const struct intel_watermark_params *cursor)
  1465. {
  1466. struct drm_i915_private *dev_priv = dev->dev_private;
  1467. DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
  1468. " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
  1469. if (fbc_wm > SNB_FBC_MAX_SRWM) {
  1470. DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
  1471. fbc_wm, SNB_FBC_MAX_SRWM, level);
  1472. /* fbc has it's own way to disable FBC WM */
  1473. I915_WRITE(DISP_ARB_CTL,
  1474. I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
  1475. return false;
  1476. } else if (INTEL_INFO(dev)->gen >= 6) {
  1477. /* enable FBC WM (except on ILK, where it must remain off) */
  1478. I915_WRITE(DISP_ARB_CTL,
  1479. I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
  1480. }
  1481. if (display_wm > display->max_wm) {
  1482. DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
  1483. display_wm, SNB_DISPLAY_MAX_SRWM, level);
  1484. return false;
  1485. }
  1486. if (cursor_wm > cursor->max_wm) {
  1487. DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
  1488. cursor_wm, SNB_CURSOR_MAX_SRWM, level);
  1489. return false;
  1490. }
  1491. if (!(fbc_wm || display_wm || cursor_wm)) {
  1492. DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
  1493. return false;
  1494. }
  1495. return true;
  1496. }
  1497. /*
  1498. * Compute watermark values of WM[1-3],
  1499. */
  1500. static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
  1501. int latency_ns,
  1502. const struct intel_watermark_params *display,
  1503. const struct intel_watermark_params *cursor,
  1504. int *fbc_wm, int *display_wm, int *cursor_wm)
  1505. {
  1506. struct drm_crtc *crtc;
  1507. unsigned long line_time_us;
  1508. int hdisplay, htotal, pixel_size, clock;
  1509. int line_count, line_size;
  1510. int small, large;
  1511. int entries;
  1512. if (!latency_ns) {
  1513. *fbc_wm = *display_wm = *cursor_wm = 0;
  1514. return false;
  1515. }
  1516. crtc = intel_get_crtc_for_plane(dev, plane);
  1517. hdisplay = crtc->mode.hdisplay;
  1518. htotal = crtc->mode.htotal;
  1519. clock = crtc->mode.clock;
  1520. pixel_size = crtc->fb->bits_per_pixel / 8;
  1521. line_time_us = (htotal * 1000) / clock;
  1522. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1523. line_size = hdisplay * pixel_size;
  1524. /* Use the minimum of the small and large buffer method for primary */
  1525. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1526. large = line_count * line_size;
  1527. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1528. *display_wm = entries + display->guard_size;
  1529. /*
  1530. * Spec says:
  1531. * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
  1532. */
  1533. *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
  1534. /* calculate the self-refresh watermark for display cursor */
  1535. entries = line_count * pixel_size * 64;
  1536. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1537. *cursor_wm = entries + cursor->guard_size;
  1538. return ironlake_check_srwm(dev, level,
  1539. *fbc_wm, *display_wm, *cursor_wm,
  1540. display, cursor);
  1541. }
  1542. static void ironlake_update_wm(struct drm_device *dev)
  1543. {
  1544. struct drm_i915_private *dev_priv = dev->dev_private;
  1545. int fbc_wm, plane_wm, cursor_wm;
  1546. unsigned int enabled;
  1547. enabled = 0;
  1548. if (g4x_compute_wm0(dev, PIPE_A,
  1549. &ironlake_display_wm_info,
  1550. dev_priv->wm.pri_latency[0] * 100,
  1551. &ironlake_cursor_wm_info,
  1552. dev_priv->wm.cur_latency[0] * 100,
  1553. &plane_wm, &cursor_wm)) {
  1554. I915_WRITE(WM0_PIPEA_ILK,
  1555. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1556. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1557. " plane %d, " "cursor: %d\n",
  1558. plane_wm, cursor_wm);
  1559. enabled |= 1 << PIPE_A;
  1560. }
  1561. if (g4x_compute_wm0(dev, PIPE_B,
  1562. &ironlake_display_wm_info,
  1563. dev_priv->wm.pri_latency[0] * 100,
  1564. &ironlake_cursor_wm_info,
  1565. dev_priv->wm.cur_latency[0] * 100,
  1566. &plane_wm, &cursor_wm)) {
  1567. I915_WRITE(WM0_PIPEB_ILK,
  1568. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1569. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1570. " plane %d, cursor: %d\n",
  1571. plane_wm, cursor_wm);
  1572. enabled |= 1 << PIPE_B;
  1573. }
  1574. /*
  1575. * Calculate and update the self-refresh watermark only when one
  1576. * display plane is used.
  1577. */
  1578. I915_WRITE(WM3_LP_ILK, 0);
  1579. I915_WRITE(WM2_LP_ILK, 0);
  1580. I915_WRITE(WM1_LP_ILK, 0);
  1581. if (!single_plane_enabled(enabled))
  1582. return;
  1583. enabled = ffs(enabled) - 1;
  1584. /* WM1 */
  1585. if (!ironlake_compute_srwm(dev, 1, enabled,
  1586. dev_priv->wm.pri_latency[1] * 500,
  1587. &ironlake_display_srwm_info,
  1588. &ironlake_cursor_srwm_info,
  1589. &fbc_wm, &plane_wm, &cursor_wm))
  1590. return;
  1591. I915_WRITE(WM1_LP_ILK,
  1592. WM1_LP_SR_EN |
  1593. (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
  1594. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1595. (plane_wm << WM1_LP_SR_SHIFT) |
  1596. cursor_wm);
  1597. /* WM2 */
  1598. if (!ironlake_compute_srwm(dev, 2, enabled,
  1599. dev_priv->wm.pri_latency[2] * 500,
  1600. &ironlake_display_srwm_info,
  1601. &ironlake_cursor_srwm_info,
  1602. &fbc_wm, &plane_wm, &cursor_wm))
  1603. return;
  1604. I915_WRITE(WM2_LP_ILK,
  1605. WM2_LP_EN |
  1606. (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
  1607. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1608. (plane_wm << WM1_LP_SR_SHIFT) |
  1609. cursor_wm);
  1610. /*
  1611. * WM3 is unsupported on ILK, probably because we don't have latency
  1612. * data for that power state
  1613. */
  1614. }
  1615. static void sandybridge_update_wm(struct drm_device *dev)
  1616. {
  1617. struct drm_i915_private *dev_priv = dev->dev_private;
  1618. int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
  1619. u32 val;
  1620. int fbc_wm, plane_wm, cursor_wm;
  1621. unsigned int enabled;
  1622. enabled = 0;
  1623. if (g4x_compute_wm0(dev, PIPE_A,
  1624. &sandybridge_display_wm_info, latency,
  1625. &sandybridge_cursor_wm_info, latency,
  1626. &plane_wm, &cursor_wm)) {
  1627. val = I915_READ(WM0_PIPEA_ILK);
  1628. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1629. I915_WRITE(WM0_PIPEA_ILK, val |
  1630. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1631. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1632. " plane %d, " "cursor: %d\n",
  1633. plane_wm, cursor_wm);
  1634. enabled |= 1 << PIPE_A;
  1635. }
  1636. if (g4x_compute_wm0(dev, PIPE_B,
  1637. &sandybridge_display_wm_info, latency,
  1638. &sandybridge_cursor_wm_info, latency,
  1639. &plane_wm, &cursor_wm)) {
  1640. val = I915_READ(WM0_PIPEB_ILK);
  1641. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1642. I915_WRITE(WM0_PIPEB_ILK, val |
  1643. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1644. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1645. " plane %d, cursor: %d\n",
  1646. plane_wm, cursor_wm);
  1647. enabled |= 1 << PIPE_B;
  1648. }
  1649. /*
  1650. * Calculate and update the self-refresh watermark only when one
  1651. * display plane is used.
  1652. *
  1653. * SNB support 3 levels of watermark.
  1654. *
  1655. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  1656. * and disabled in the descending order
  1657. *
  1658. */
  1659. I915_WRITE(WM3_LP_ILK, 0);
  1660. I915_WRITE(WM2_LP_ILK, 0);
  1661. I915_WRITE(WM1_LP_ILK, 0);
  1662. if (!single_plane_enabled(enabled) ||
  1663. dev_priv->sprite_scaling_enabled)
  1664. return;
  1665. enabled = ffs(enabled) - 1;
  1666. /* WM1 */
  1667. if (!ironlake_compute_srwm(dev, 1, enabled,
  1668. dev_priv->wm.pri_latency[1] * 500,
  1669. &sandybridge_display_srwm_info,
  1670. &sandybridge_cursor_srwm_info,
  1671. &fbc_wm, &plane_wm, &cursor_wm))
  1672. return;
  1673. I915_WRITE(WM1_LP_ILK,
  1674. WM1_LP_SR_EN |
  1675. (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
  1676. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1677. (plane_wm << WM1_LP_SR_SHIFT) |
  1678. cursor_wm);
  1679. /* WM2 */
  1680. if (!ironlake_compute_srwm(dev, 2, enabled,
  1681. dev_priv->wm.pri_latency[2] * 500,
  1682. &sandybridge_display_srwm_info,
  1683. &sandybridge_cursor_srwm_info,
  1684. &fbc_wm, &plane_wm, &cursor_wm))
  1685. return;
  1686. I915_WRITE(WM2_LP_ILK,
  1687. WM2_LP_EN |
  1688. (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
  1689. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1690. (plane_wm << WM1_LP_SR_SHIFT) |
  1691. cursor_wm);
  1692. /* WM3 */
  1693. if (!ironlake_compute_srwm(dev, 3, enabled,
  1694. dev_priv->wm.pri_latency[3] * 500,
  1695. &sandybridge_display_srwm_info,
  1696. &sandybridge_cursor_srwm_info,
  1697. &fbc_wm, &plane_wm, &cursor_wm))
  1698. return;
  1699. I915_WRITE(WM3_LP_ILK,
  1700. WM3_LP_EN |
  1701. (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
  1702. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1703. (plane_wm << WM1_LP_SR_SHIFT) |
  1704. cursor_wm);
  1705. }
  1706. static void ivybridge_update_wm(struct drm_device *dev)
  1707. {
  1708. struct drm_i915_private *dev_priv = dev->dev_private;
  1709. int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
  1710. u32 val;
  1711. int fbc_wm, plane_wm, cursor_wm;
  1712. int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
  1713. unsigned int enabled;
  1714. enabled = 0;
  1715. if (g4x_compute_wm0(dev, PIPE_A,
  1716. &sandybridge_display_wm_info, latency,
  1717. &sandybridge_cursor_wm_info, latency,
  1718. &plane_wm, &cursor_wm)) {
  1719. val = I915_READ(WM0_PIPEA_ILK);
  1720. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1721. I915_WRITE(WM0_PIPEA_ILK, val |
  1722. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1723. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1724. " plane %d, " "cursor: %d\n",
  1725. plane_wm, cursor_wm);
  1726. enabled |= 1 << PIPE_A;
  1727. }
  1728. if (g4x_compute_wm0(dev, PIPE_B,
  1729. &sandybridge_display_wm_info, latency,
  1730. &sandybridge_cursor_wm_info, latency,
  1731. &plane_wm, &cursor_wm)) {
  1732. val = I915_READ(WM0_PIPEB_ILK);
  1733. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1734. I915_WRITE(WM0_PIPEB_ILK, val |
  1735. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1736. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1737. " plane %d, cursor: %d\n",
  1738. plane_wm, cursor_wm);
  1739. enabled |= 1 << PIPE_B;
  1740. }
  1741. if (g4x_compute_wm0(dev, PIPE_C,
  1742. &sandybridge_display_wm_info, latency,
  1743. &sandybridge_cursor_wm_info, latency,
  1744. &plane_wm, &cursor_wm)) {
  1745. val = I915_READ(WM0_PIPEC_IVB);
  1746. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1747. I915_WRITE(WM0_PIPEC_IVB, val |
  1748. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1749. DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
  1750. " plane %d, cursor: %d\n",
  1751. plane_wm, cursor_wm);
  1752. enabled |= 1 << PIPE_C;
  1753. }
  1754. /*
  1755. * Calculate and update the self-refresh watermark only when one
  1756. * display plane is used.
  1757. *
  1758. * SNB support 3 levels of watermark.
  1759. *
  1760. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  1761. * and disabled in the descending order
  1762. *
  1763. */
  1764. I915_WRITE(WM3_LP_ILK, 0);
  1765. I915_WRITE(WM2_LP_ILK, 0);
  1766. I915_WRITE(WM1_LP_ILK, 0);
  1767. if (!single_plane_enabled(enabled) ||
  1768. dev_priv->sprite_scaling_enabled)
  1769. return;
  1770. enabled = ffs(enabled) - 1;
  1771. /* WM1 */
  1772. if (!ironlake_compute_srwm(dev, 1, enabled,
  1773. dev_priv->wm.pri_latency[1] * 500,
  1774. &sandybridge_display_srwm_info,
  1775. &sandybridge_cursor_srwm_info,
  1776. &fbc_wm, &plane_wm, &cursor_wm))
  1777. return;
  1778. I915_WRITE(WM1_LP_ILK,
  1779. WM1_LP_SR_EN |
  1780. (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
  1781. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1782. (plane_wm << WM1_LP_SR_SHIFT) |
  1783. cursor_wm);
  1784. /* WM2 */
  1785. if (!ironlake_compute_srwm(dev, 2, enabled,
  1786. dev_priv->wm.pri_latency[2] * 500,
  1787. &sandybridge_display_srwm_info,
  1788. &sandybridge_cursor_srwm_info,
  1789. &fbc_wm, &plane_wm, &cursor_wm))
  1790. return;
  1791. I915_WRITE(WM2_LP_ILK,
  1792. WM2_LP_EN |
  1793. (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
  1794. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1795. (plane_wm << WM1_LP_SR_SHIFT) |
  1796. cursor_wm);
  1797. /* WM3, note we have to correct the cursor latency */
  1798. if (!ironlake_compute_srwm(dev, 3, enabled,
  1799. dev_priv->wm.pri_latency[3] * 500,
  1800. &sandybridge_display_srwm_info,
  1801. &sandybridge_cursor_srwm_info,
  1802. &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
  1803. !ironlake_compute_srwm(dev, 3, enabled,
  1804. dev_priv->wm.cur_latency[3] * 500,
  1805. &sandybridge_display_srwm_info,
  1806. &sandybridge_cursor_srwm_info,
  1807. &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
  1808. return;
  1809. I915_WRITE(WM3_LP_ILK,
  1810. WM3_LP_EN |
  1811. (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
  1812. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1813. (plane_wm << WM1_LP_SR_SHIFT) |
  1814. cursor_wm);
  1815. }
  1816. static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
  1817. struct drm_crtc *crtc)
  1818. {
  1819. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1820. uint32_t pixel_rate, pfit_size;
  1821. pixel_rate = intel_crtc->config.adjusted_mode.clock;
  1822. /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
  1823. * adjust the pixel_rate here. */
  1824. pfit_size = intel_crtc->config.pch_pfit.size;
  1825. if (pfit_size) {
  1826. uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
  1827. pipe_w = intel_crtc->config.requested_mode.hdisplay;
  1828. pipe_h = intel_crtc->config.requested_mode.vdisplay;
  1829. pfit_w = (pfit_size >> 16) & 0xFFFF;
  1830. pfit_h = pfit_size & 0xFFFF;
  1831. if (pipe_w < pfit_w)
  1832. pipe_w = pfit_w;
  1833. if (pipe_h < pfit_h)
  1834. pipe_h = pfit_h;
  1835. pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
  1836. pfit_w * pfit_h);
  1837. }
  1838. return pixel_rate;
  1839. }
  1840. /* latency must be in 0.1us units. */
  1841. static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
  1842. uint32_t latency)
  1843. {
  1844. uint64_t ret;
  1845. if (WARN(latency == 0, "Latency value missing\n"))
  1846. return UINT_MAX;
  1847. ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
  1848. ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
  1849. return ret;
  1850. }
  1851. /* latency must be in 0.1us units. */
  1852. static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
  1853. uint32_t horiz_pixels, uint8_t bytes_per_pixel,
  1854. uint32_t latency)
  1855. {
  1856. uint32_t ret;
  1857. if (WARN(latency == 0, "Latency value missing\n"))
  1858. return UINT_MAX;
  1859. ret = (latency * pixel_rate) / (pipe_htotal * 10000);
  1860. ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
  1861. ret = DIV_ROUND_UP(ret, 64) + 2;
  1862. return ret;
  1863. }
  1864. static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
  1865. uint8_t bytes_per_pixel)
  1866. {
  1867. return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
  1868. }
  1869. struct hsw_pipe_wm_parameters {
  1870. bool active;
  1871. bool sprite_enabled;
  1872. uint8_t pri_bytes_per_pixel;
  1873. uint8_t spr_bytes_per_pixel;
  1874. uint8_t cur_bytes_per_pixel;
  1875. uint32_t pri_horiz_pixels;
  1876. uint32_t spr_horiz_pixels;
  1877. uint32_t cur_horiz_pixels;
  1878. uint32_t pipe_htotal;
  1879. uint32_t pixel_rate;
  1880. };
  1881. struct hsw_wm_maximums {
  1882. uint16_t pri;
  1883. uint16_t spr;
  1884. uint16_t cur;
  1885. uint16_t fbc;
  1886. };
  1887. struct hsw_lp_wm_result {
  1888. bool enable;
  1889. bool fbc_enable;
  1890. uint32_t pri_val;
  1891. uint32_t spr_val;
  1892. uint32_t cur_val;
  1893. uint32_t fbc_val;
  1894. };
  1895. struct hsw_wm_values {
  1896. uint32_t wm_pipe[3];
  1897. uint32_t wm_lp[3];
  1898. uint32_t wm_lp_spr[3];
  1899. uint32_t wm_linetime[3];
  1900. bool enable_fbc_wm;
  1901. };
  1902. enum hsw_data_buf_partitioning {
  1903. HSW_DATA_BUF_PART_1_2,
  1904. HSW_DATA_BUF_PART_5_6,
  1905. };
  1906. /*
  1907. * For both WM_PIPE and WM_LP.
  1908. * mem_value must be in 0.1us units.
  1909. */
  1910. static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
  1911. uint32_t mem_value,
  1912. bool is_lp)
  1913. {
  1914. uint32_t method1, method2;
  1915. /* TODO: for now, assume the primary plane is always enabled. */
  1916. if (!params->active)
  1917. return 0;
  1918. method1 = ilk_wm_method1(params->pixel_rate,
  1919. params->pri_bytes_per_pixel,
  1920. mem_value);
  1921. if (!is_lp)
  1922. return method1;
  1923. method2 = ilk_wm_method2(params->pixel_rate,
  1924. params->pipe_htotal,
  1925. params->pri_horiz_pixels,
  1926. params->pri_bytes_per_pixel,
  1927. mem_value);
  1928. return min(method1, method2);
  1929. }
  1930. /*
  1931. * For both WM_PIPE and WM_LP.
  1932. * mem_value must be in 0.1us units.
  1933. */
  1934. static uint32_t ilk_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
  1935. uint32_t mem_value)
  1936. {
  1937. uint32_t method1, method2;
  1938. if (!params->active || !params->sprite_enabled)
  1939. return 0;
  1940. method1 = ilk_wm_method1(params->pixel_rate,
  1941. params->spr_bytes_per_pixel,
  1942. mem_value);
  1943. method2 = ilk_wm_method2(params->pixel_rate,
  1944. params->pipe_htotal,
  1945. params->spr_horiz_pixels,
  1946. params->spr_bytes_per_pixel,
  1947. mem_value);
  1948. return min(method1, method2);
  1949. }
  1950. /*
  1951. * For both WM_PIPE and WM_LP.
  1952. * mem_value must be in 0.1us units.
  1953. */
  1954. static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
  1955. uint32_t mem_value)
  1956. {
  1957. if (!params->active)
  1958. return 0;
  1959. return ilk_wm_method2(params->pixel_rate,
  1960. params->pipe_htotal,
  1961. params->cur_horiz_pixels,
  1962. params->cur_bytes_per_pixel,
  1963. mem_value);
  1964. }
  1965. /* Only for WM_LP. */
  1966. static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
  1967. uint32_t pri_val)
  1968. {
  1969. if (!params->active)
  1970. return 0;
  1971. return ilk_wm_fbc(pri_val,
  1972. params->pri_horiz_pixels,
  1973. params->pri_bytes_per_pixel);
  1974. }
  1975. static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
  1976. int level, struct hsw_wm_maximums *max,
  1977. struct hsw_pipe_wm_parameters *params,
  1978. struct hsw_lp_wm_result *result)
  1979. {
  1980. enum pipe pipe;
  1981. uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
  1982. for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
  1983. struct hsw_pipe_wm_parameters *p = &params[pipe];
  1984. /* WM1+ latency values stored in 0.5us units */
  1985. uint16_t pri_latency = dev_priv->wm.pri_latency[level] * 5;
  1986. uint16_t spr_latency = dev_priv->wm.spr_latency[level] * 5;
  1987. uint16_t cur_latency = dev_priv->wm.cur_latency[level] * 5;
  1988. pri_val[pipe] = ilk_compute_pri_wm(p, pri_latency, true);
  1989. spr_val[pipe] = ilk_compute_spr_wm(p, spr_latency);
  1990. cur_val[pipe] = ilk_compute_cur_wm(p, cur_latency);
  1991. fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe]);
  1992. }
  1993. result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
  1994. result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
  1995. result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
  1996. result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
  1997. if (result->fbc_val > max->fbc) {
  1998. result->fbc_enable = false;
  1999. result->fbc_val = 0;
  2000. } else {
  2001. result->fbc_enable = true;
  2002. }
  2003. result->enable = result->pri_val <= max->pri &&
  2004. result->spr_val <= max->spr &&
  2005. result->cur_val <= max->cur;
  2006. return result->enable;
  2007. }
  2008. static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
  2009. enum pipe pipe,
  2010. struct hsw_pipe_wm_parameters *params)
  2011. {
  2012. uint32_t pri_val, cur_val, spr_val;
  2013. /* WM0 latency values stored in 0.1us units */
  2014. uint16_t pri_latency = dev_priv->wm.pri_latency[0];
  2015. uint16_t spr_latency = dev_priv->wm.spr_latency[0];
  2016. uint16_t cur_latency = dev_priv->wm.cur_latency[0];
  2017. pri_val = ilk_compute_pri_wm(params, pri_latency, false);
  2018. spr_val = ilk_compute_spr_wm(params, spr_latency);
  2019. cur_val = ilk_compute_cur_wm(params, cur_latency);
  2020. WARN(pri_val > 127,
  2021. "Primary WM error, mode not supported for pipe %c\n",
  2022. pipe_name(pipe));
  2023. WARN(spr_val > 127,
  2024. "Sprite WM error, mode not supported for pipe %c\n",
  2025. pipe_name(pipe));
  2026. WARN(cur_val > 63,
  2027. "Cursor WM error, mode not supported for pipe %c\n",
  2028. pipe_name(pipe));
  2029. return (pri_val << WM0_PIPE_PLANE_SHIFT) |
  2030. (spr_val << WM0_PIPE_SPRITE_SHIFT) |
  2031. cur_val;
  2032. }
  2033. static uint32_t
  2034. hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
  2035. {
  2036. struct drm_i915_private *dev_priv = dev->dev_private;
  2037. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2038. struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
  2039. u32 linetime, ips_linetime;
  2040. if (!intel_crtc_active(crtc))
  2041. return 0;
  2042. /* The WM are computed with base on how long it takes to fill a single
  2043. * row at the given clock rate, multiplied by 8.
  2044. * */
  2045. linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
  2046. ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
  2047. intel_ddi_get_cdclk_freq(dev_priv));
  2048. return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
  2049. PIPE_WM_LINETIME_TIME(linetime);
  2050. }
  2051. static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
  2052. {
  2053. struct drm_i915_private *dev_priv = dev->dev_private;
  2054. if (IS_HASWELL(dev)) {
  2055. uint64_t sskpd = I915_READ64(MCH_SSKPD);
  2056. wm[0] = (sskpd >> 56) & 0xFF;
  2057. if (wm[0] == 0)
  2058. wm[0] = sskpd & 0xF;
  2059. wm[1] = (sskpd >> 4) & 0xFF;
  2060. wm[2] = (sskpd >> 12) & 0xFF;
  2061. wm[3] = (sskpd >> 20) & 0x1FF;
  2062. wm[4] = (sskpd >> 32) & 0x1FF;
  2063. } else if (INTEL_INFO(dev)->gen >= 6) {
  2064. uint32_t sskpd = I915_READ(MCH_SSKPD);
  2065. wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
  2066. wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
  2067. wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
  2068. wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
  2069. } else if (INTEL_INFO(dev)->gen >= 5) {
  2070. uint32_t mltr = I915_READ(MLTR_ILK);
  2071. /* ILK primary LP0 latency is 700 ns */
  2072. wm[0] = 7;
  2073. wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
  2074. wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
  2075. }
  2076. }
  2077. static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
  2078. {
  2079. /* ILK sprite LP0 latency is 1300 ns */
  2080. if (INTEL_INFO(dev)->gen == 5)
  2081. wm[0] = 13;
  2082. }
  2083. static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
  2084. {
  2085. /* ILK cursor LP0 latency is 1300 ns */
  2086. if (INTEL_INFO(dev)->gen == 5)
  2087. wm[0] = 13;
  2088. /* WaDoubleCursorLP3Latency:ivb */
  2089. if (IS_IVYBRIDGE(dev))
  2090. wm[3] *= 2;
  2091. }
  2092. static void intel_print_wm_latency(struct drm_device *dev,
  2093. const char *name,
  2094. const uint16_t wm[5])
  2095. {
  2096. int level, max_level;
  2097. /* how many WM levels are we expecting */
  2098. if (IS_HASWELL(dev))
  2099. max_level = 4;
  2100. else if (INTEL_INFO(dev)->gen >= 6)
  2101. max_level = 3;
  2102. else
  2103. max_level = 2;
  2104. for (level = 0; level <= max_level; level++) {
  2105. unsigned int latency = wm[level];
  2106. if (latency == 0) {
  2107. DRM_ERROR("%s WM%d latency not provided\n",
  2108. name, level);
  2109. continue;
  2110. }
  2111. /* WM1+ latency values in 0.5us units */
  2112. if (level > 0)
  2113. latency *= 5;
  2114. DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
  2115. name, level, wm[level],
  2116. latency / 10, latency % 10);
  2117. }
  2118. }
  2119. static void intel_setup_wm_latency(struct drm_device *dev)
  2120. {
  2121. struct drm_i915_private *dev_priv = dev->dev_private;
  2122. intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
  2123. memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
  2124. sizeof(dev_priv->wm.pri_latency));
  2125. memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
  2126. sizeof(dev_priv->wm.pri_latency));
  2127. intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
  2128. intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
  2129. intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
  2130. intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
  2131. intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
  2132. }
  2133. static void hsw_compute_wm_parameters(struct drm_device *dev,
  2134. struct hsw_pipe_wm_parameters *params,
  2135. struct hsw_wm_maximums *lp_max_1_2,
  2136. struct hsw_wm_maximums *lp_max_5_6)
  2137. {
  2138. struct drm_crtc *crtc;
  2139. struct drm_plane *plane;
  2140. enum pipe pipe;
  2141. int pipes_active = 0, sprites_enabled = 0;
  2142. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2143. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2144. struct hsw_pipe_wm_parameters *p;
  2145. pipe = intel_crtc->pipe;
  2146. p = &params[pipe];
  2147. p->active = intel_crtc_active(crtc);
  2148. if (!p->active)
  2149. continue;
  2150. pipes_active++;
  2151. p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
  2152. p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
  2153. p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
  2154. p->cur_bytes_per_pixel = 4;
  2155. p->pri_horiz_pixels =
  2156. intel_crtc->config.requested_mode.hdisplay;
  2157. p->cur_horiz_pixels = 64;
  2158. }
  2159. list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
  2160. struct intel_plane *intel_plane = to_intel_plane(plane);
  2161. struct hsw_pipe_wm_parameters *p;
  2162. pipe = intel_plane->pipe;
  2163. p = &params[pipe];
  2164. p->sprite_enabled = intel_plane->wm.enabled;
  2165. p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
  2166. p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
  2167. if (p->sprite_enabled)
  2168. sprites_enabled++;
  2169. }
  2170. if (pipes_active > 1) {
  2171. lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
  2172. lp_max_1_2->spr = lp_max_5_6->spr = 128;
  2173. lp_max_1_2->cur = lp_max_5_6->cur = 64;
  2174. } else {
  2175. lp_max_1_2->pri = sprites_enabled ? 384 : 768;
  2176. lp_max_5_6->pri = sprites_enabled ? 128 : 768;
  2177. lp_max_1_2->spr = 384;
  2178. lp_max_5_6->spr = 640;
  2179. lp_max_1_2->cur = lp_max_5_6->cur = 255;
  2180. }
  2181. lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
  2182. }
  2183. static void hsw_compute_wm_results(struct drm_device *dev,
  2184. struct hsw_pipe_wm_parameters *params,
  2185. struct hsw_wm_maximums *lp_maximums,
  2186. struct hsw_wm_values *results)
  2187. {
  2188. struct drm_i915_private *dev_priv = dev->dev_private;
  2189. struct drm_crtc *crtc;
  2190. struct hsw_lp_wm_result lp_results[4] = {};
  2191. enum pipe pipe;
  2192. int level, max_level, wm_lp;
  2193. for (level = 1; level <= 4; level++)
  2194. if (!hsw_compute_lp_wm(dev_priv, level,
  2195. lp_maximums, params,
  2196. &lp_results[level - 1]))
  2197. break;
  2198. max_level = level - 1;
  2199. /* The spec says it is preferred to disable FBC WMs instead of disabling
  2200. * a WM level. */
  2201. results->enable_fbc_wm = true;
  2202. for (level = 1; level <= max_level; level++) {
  2203. if (!lp_results[level - 1].fbc_enable) {
  2204. results->enable_fbc_wm = false;
  2205. break;
  2206. }
  2207. }
  2208. memset(results, 0, sizeof(*results));
  2209. for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
  2210. const struct hsw_lp_wm_result *r;
  2211. level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
  2212. if (level > max_level)
  2213. break;
  2214. r = &lp_results[level - 1];
  2215. results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
  2216. r->fbc_val,
  2217. r->pri_val,
  2218. r->cur_val);
  2219. results->wm_lp_spr[wm_lp - 1] = r->spr_val;
  2220. }
  2221. for_each_pipe(pipe)
  2222. results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, pipe,
  2223. &params[pipe]);
  2224. for_each_pipe(pipe) {
  2225. crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  2226. results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
  2227. }
  2228. }
  2229. /* Find the result with the highest level enabled. Check for enable_fbc_wm in
  2230. * case both are at the same level. Prefer r1 in case they're the same. */
  2231. static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
  2232. struct hsw_wm_values *r2)
  2233. {
  2234. int i, val_r1 = 0, val_r2 = 0;
  2235. for (i = 0; i < 3; i++) {
  2236. if (r1->wm_lp[i] & WM3_LP_EN)
  2237. val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
  2238. if (r2->wm_lp[i] & WM3_LP_EN)
  2239. val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
  2240. }
  2241. if (val_r1 == val_r2) {
  2242. if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
  2243. return r2;
  2244. else
  2245. return r1;
  2246. } else if (val_r1 > val_r2) {
  2247. return r1;
  2248. } else {
  2249. return r2;
  2250. }
  2251. }
  2252. /*
  2253. * The spec says we shouldn't write when we don't need, because every write
  2254. * causes WMs to be re-evaluated, expending some power.
  2255. */
  2256. static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
  2257. struct hsw_wm_values *results,
  2258. enum hsw_data_buf_partitioning partitioning)
  2259. {
  2260. struct hsw_wm_values previous;
  2261. uint32_t val;
  2262. enum hsw_data_buf_partitioning prev_partitioning;
  2263. bool prev_enable_fbc_wm;
  2264. previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
  2265. previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
  2266. previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
  2267. previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
  2268. previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
  2269. previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
  2270. previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
  2271. previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
  2272. previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
  2273. previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
  2274. previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
  2275. previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
  2276. prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
  2277. HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
  2278. prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
  2279. if (memcmp(results->wm_pipe, previous.wm_pipe,
  2280. sizeof(results->wm_pipe)) == 0 &&
  2281. memcmp(results->wm_lp, previous.wm_lp,
  2282. sizeof(results->wm_lp)) == 0 &&
  2283. memcmp(results->wm_lp_spr, previous.wm_lp_spr,
  2284. sizeof(results->wm_lp_spr)) == 0 &&
  2285. memcmp(results->wm_linetime, previous.wm_linetime,
  2286. sizeof(results->wm_linetime)) == 0 &&
  2287. partitioning == prev_partitioning &&
  2288. results->enable_fbc_wm == prev_enable_fbc_wm)
  2289. return;
  2290. if (previous.wm_lp[2] != 0)
  2291. I915_WRITE(WM3_LP_ILK, 0);
  2292. if (previous.wm_lp[1] != 0)
  2293. I915_WRITE(WM2_LP_ILK, 0);
  2294. if (previous.wm_lp[0] != 0)
  2295. I915_WRITE(WM1_LP_ILK, 0);
  2296. if (previous.wm_pipe[0] != results->wm_pipe[0])
  2297. I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
  2298. if (previous.wm_pipe[1] != results->wm_pipe[1])
  2299. I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
  2300. if (previous.wm_pipe[2] != results->wm_pipe[2])
  2301. I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
  2302. if (previous.wm_linetime[0] != results->wm_linetime[0])
  2303. I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
  2304. if (previous.wm_linetime[1] != results->wm_linetime[1])
  2305. I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
  2306. if (previous.wm_linetime[2] != results->wm_linetime[2])
  2307. I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
  2308. if (prev_partitioning != partitioning) {
  2309. val = I915_READ(WM_MISC);
  2310. if (partitioning == HSW_DATA_BUF_PART_1_2)
  2311. val &= ~WM_MISC_DATA_PARTITION_5_6;
  2312. else
  2313. val |= WM_MISC_DATA_PARTITION_5_6;
  2314. I915_WRITE(WM_MISC, val);
  2315. }
  2316. if (prev_enable_fbc_wm != results->enable_fbc_wm) {
  2317. val = I915_READ(DISP_ARB_CTL);
  2318. if (results->enable_fbc_wm)
  2319. val &= ~DISP_FBC_WM_DIS;
  2320. else
  2321. val |= DISP_FBC_WM_DIS;
  2322. I915_WRITE(DISP_ARB_CTL, val);
  2323. }
  2324. if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
  2325. I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
  2326. if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
  2327. I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
  2328. if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
  2329. I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
  2330. if (results->wm_lp[0] != 0)
  2331. I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
  2332. if (results->wm_lp[1] != 0)
  2333. I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
  2334. if (results->wm_lp[2] != 0)
  2335. I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
  2336. }
  2337. static void haswell_update_wm(struct drm_device *dev)
  2338. {
  2339. struct drm_i915_private *dev_priv = dev->dev_private;
  2340. struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
  2341. struct hsw_pipe_wm_parameters params[3];
  2342. struct hsw_wm_values results_1_2, results_5_6, *best_results;
  2343. enum hsw_data_buf_partitioning partitioning;
  2344. hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
  2345. hsw_compute_wm_results(dev, params,
  2346. &lp_max_1_2, &results_1_2);
  2347. if (lp_max_1_2.pri != lp_max_5_6.pri) {
  2348. hsw_compute_wm_results(dev, params,
  2349. &lp_max_5_6, &results_5_6);
  2350. best_results = hsw_find_best_result(&results_1_2, &results_5_6);
  2351. } else {
  2352. best_results = &results_1_2;
  2353. }
  2354. partitioning = (best_results == &results_1_2) ?
  2355. HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
  2356. hsw_write_wm_values(dev_priv, best_results, partitioning);
  2357. }
  2358. static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
  2359. uint32_t sprite_width, int pixel_size,
  2360. bool enabled, bool scaled)
  2361. {
  2362. struct drm_plane *plane;
  2363. list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
  2364. struct intel_plane *intel_plane = to_intel_plane(plane);
  2365. if (intel_plane->pipe == pipe) {
  2366. intel_plane->wm.enabled = enabled;
  2367. intel_plane->wm.scaled = scaled;
  2368. intel_plane->wm.horiz_pixels = sprite_width;
  2369. intel_plane->wm.bytes_per_pixel = pixel_size;
  2370. break;
  2371. }
  2372. }
  2373. haswell_update_wm(dev);
  2374. }
  2375. static bool
  2376. sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
  2377. uint32_t sprite_width, int pixel_size,
  2378. const struct intel_watermark_params *display,
  2379. int display_latency_ns, int *sprite_wm)
  2380. {
  2381. struct drm_crtc *crtc;
  2382. int clock;
  2383. int entries, tlb_miss;
  2384. crtc = intel_get_crtc_for_plane(dev, plane);
  2385. if (!intel_crtc_active(crtc)) {
  2386. *sprite_wm = display->guard_size;
  2387. return false;
  2388. }
  2389. clock = crtc->mode.clock;
  2390. /* Use the small buffer method to calculate the sprite watermark */
  2391. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  2392. tlb_miss = display->fifo_size*display->cacheline_size -
  2393. sprite_width * 8;
  2394. if (tlb_miss > 0)
  2395. entries += tlb_miss;
  2396. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  2397. *sprite_wm = entries + display->guard_size;
  2398. if (*sprite_wm > (int)display->max_wm)
  2399. *sprite_wm = display->max_wm;
  2400. return true;
  2401. }
  2402. static bool
  2403. sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
  2404. uint32_t sprite_width, int pixel_size,
  2405. const struct intel_watermark_params *display,
  2406. int latency_ns, int *sprite_wm)
  2407. {
  2408. struct drm_crtc *crtc;
  2409. unsigned long line_time_us;
  2410. int clock;
  2411. int line_count, line_size;
  2412. int small, large;
  2413. int entries;
  2414. if (!latency_ns) {
  2415. *sprite_wm = 0;
  2416. return false;
  2417. }
  2418. crtc = intel_get_crtc_for_plane(dev, plane);
  2419. clock = crtc->mode.clock;
  2420. if (!clock) {
  2421. *sprite_wm = 0;
  2422. return false;
  2423. }
  2424. line_time_us = (sprite_width * 1000) / clock;
  2425. if (!line_time_us) {
  2426. *sprite_wm = 0;
  2427. return false;
  2428. }
  2429. line_count = (latency_ns / line_time_us + 1000) / 1000;
  2430. line_size = sprite_width * pixel_size;
  2431. /* Use the minimum of the small and large buffer method for primary */
  2432. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  2433. large = line_count * line_size;
  2434. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  2435. *sprite_wm = entries + display->guard_size;
  2436. return *sprite_wm > 0x3ff ? false : true;
  2437. }
  2438. static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
  2439. uint32_t sprite_width, int pixel_size,
  2440. bool enable, bool scaled)
  2441. {
  2442. struct drm_i915_private *dev_priv = dev->dev_private;
  2443. int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
  2444. u32 val;
  2445. int sprite_wm, reg;
  2446. int ret;
  2447. if (!enable)
  2448. return;
  2449. switch (pipe) {
  2450. case 0:
  2451. reg = WM0_PIPEA_ILK;
  2452. break;
  2453. case 1:
  2454. reg = WM0_PIPEB_ILK;
  2455. break;
  2456. case 2:
  2457. reg = WM0_PIPEC_IVB;
  2458. break;
  2459. default:
  2460. return; /* bad pipe */
  2461. }
  2462. ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
  2463. &sandybridge_display_wm_info,
  2464. latency, &sprite_wm);
  2465. if (!ret) {
  2466. DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
  2467. pipe_name(pipe));
  2468. return;
  2469. }
  2470. val = I915_READ(reg);
  2471. val &= ~WM0_PIPE_SPRITE_MASK;
  2472. I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
  2473. DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
  2474. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2475. pixel_size,
  2476. &sandybridge_display_srwm_info,
  2477. dev_priv->wm.spr_latency[1] * 500,
  2478. &sprite_wm);
  2479. if (!ret) {
  2480. DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
  2481. pipe_name(pipe));
  2482. return;
  2483. }
  2484. I915_WRITE(WM1S_LP_ILK, sprite_wm);
  2485. /* Only IVB has two more LP watermarks for sprite */
  2486. if (!IS_IVYBRIDGE(dev))
  2487. return;
  2488. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2489. pixel_size,
  2490. &sandybridge_display_srwm_info,
  2491. dev_priv->wm.spr_latency[2] * 500,
  2492. &sprite_wm);
  2493. if (!ret) {
  2494. DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
  2495. pipe_name(pipe));
  2496. return;
  2497. }
  2498. I915_WRITE(WM2S_LP_IVB, sprite_wm);
  2499. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2500. pixel_size,
  2501. &sandybridge_display_srwm_info,
  2502. dev_priv->wm.spr_latency[3] * 500,
  2503. &sprite_wm);
  2504. if (!ret) {
  2505. DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
  2506. pipe_name(pipe));
  2507. return;
  2508. }
  2509. I915_WRITE(WM3S_LP_IVB, sprite_wm);
  2510. }
  2511. /**
  2512. * intel_update_watermarks - update FIFO watermark values based on current modes
  2513. *
  2514. * Calculate watermark values for the various WM regs based on current mode
  2515. * and plane configuration.
  2516. *
  2517. * There are several cases to deal with here:
  2518. * - normal (i.e. non-self-refresh)
  2519. * - self-refresh (SR) mode
  2520. * - lines are large relative to FIFO size (buffer can hold up to 2)
  2521. * - lines are small relative to FIFO size (buffer can hold more than 2
  2522. * lines), so need to account for TLB latency
  2523. *
  2524. * The normal calculation is:
  2525. * watermark = dotclock * bytes per pixel * latency
  2526. * where latency is platform & configuration dependent (we assume pessimal
  2527. * values here).
  2528. *
  2529. * The SR calculation is:
  2530. * watermark = (trunc(latency/line time)+1) * surface width *
  2531. * bytes per pixel
  2532. * where
  2533. * line time = htotal / dotclock
  2534. * surface width = hdisplay for normal plane and 64 for cursor
  2535. * and latency is assumed to be high, as above.
  2536. *
  2537. * The final value programmed to the register should always be rounded up,
  2538. * and include an extra 2 entries to account for clock crossings.
  2539. *
  2540. * We don't use the sprite, so we can ignore that. And on Crestline we have
  2541. * to set the non-SR watermarks to 8.
  2542. */
  2543. void intel_update_watermarks(struct drm_device *dev)
  2544. {
  2545. struct drm_i915_private *dev_priv = dev->dev_private;
  2546. if (dev_priv->display.update_wm)
  2547. dev_priv->display.update_wm(dev);
  2548. }
  2549. void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  2550. uint32_t sprite_width, int pixel_size,
  2551. bool enable, bool scaled)
  2552. {
  2553. struct drm_i915_private *dev_priv = dev->dev_private;
  2554. if (dev_priv->display.update_sprite_wm)
  2555. dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
  2556. pixel_size, enable, scaled);
  2557. }
  2558. static struct drm_i915_gem_object *
  2559. intel_alloc_context_page(struct drm_device *dev)
  2560. {
  2561. struct drm_i915_gem_object *ctx;
  2562. int ret;
  2563. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2564. ctx = i915_gem_alloc_object(dev, 4096);
  2565. if (!ctx) {
  2566. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  2567. return NULL;
  2568. }
  2569. ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
  2570. if (ret) {
  2571. DRM_ERROR("failed to pin power context: %d\n", ret);
  2572. goto err_unref;
  2573. }
  2574. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  2575. if (ret) {
  2576. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  2577. goto err_unpin;
  2578. }
  2579. return ctx;
  2580. err_unpin:
  2581. i915_gem_object_unpin(ctx);
  2582. err_unref:
  2583. drm_gem_object_unreference(&ctx->base);
  2584. return NULL;
  2585. }
  2586. /**
  2587. * Lock protecting IPS related data structures
  2588. */
  2589. DEFINE_SPINLOCK(mchdev_lock);
  2590. /* Global for IPS driver to get at the current i915 device. Protected by
  2591. * mchdev_lock. */
  2592. static struct drm_i915_private *i915_mch_dev;
  2593. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  2594. {
  2595. struct drm_i915_private *dev_priv = dev->dev_private;
  2596. u16 rgvswctl;
  2597. assert_spin_locked(&mchdev_lock);
  2598. rgvswctl = I915_READ16(MEMSWCTL);
  2599. if (rgvswctl & MEMCTL_CMD_STS) {
  2600. DRM_DEBUG("gpu busy, RCS change rejected\n");
  2601. return false; /* still busy with another command */
  2602. }
  2603. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  2604. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  2605. I915_WRITE16(MEMSWCTL, rgvswctl);
  2606. POSTING_READ16(MEMSWCTL);
  2607. rgvswctl |= MEMCTL_CMD_STS;
  2608. I915_WRITE16(MEMSWCTL, rgvswctl);
  2609. return true;
  2610. }
  2611. static void ironlake_enable_drps(struct drm_device *dev)
  2612. {
  2613. struct drm_i915_private *dev_priv = dev->dev_private;
  2614. u32 rgvmodectl = I915_READ(MEMMODECTL);
  2615. u8 fmax, fmin, fstart, vstart;
  2616. spin_lock_irq(&mchdev_lock);
  2617. /* Enable temp reporting */
  2618. I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  2619. I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  2620. /* 100ms RC evaluation intervals */
  2621. I915_WRITE(RCUPEI, 100000);
  2622. I915_WRITE(RCDNEI, 100000);
  2623. /* Set max/min thresholds to 90ms and 80ms respectively */
  2624. I915_WRITE(RCBMAXAVG, 90000);
  2625. I915_WRITE(RCBMINAVG, 80000);
  2626. I915_WRITE(MEMIHYST, 1);
  2627. /* Set up min, max, and cur for interrupt handling */
  2628. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  2629. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  2630. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  2631. MEMMODE_FSTART_SHIFT;
  2632. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  2633. PXVFREQ_PX_SHIFT;
  2634. dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
  2635. dev_priv->ips.fstart = fstart;
  2636. dev_priv->ips.max_delay = fstart;
  2637. dev_priv->ips.min_delay = fmin;
  2638. dev_priv->ips.cur_delay = fstart;
  2639. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
  2640. fmax, fmin, fstart);
  2641. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  2642. /*
  2643. * Interrupts will be enabled in ironlake_irq_postinstall
  2644. */
  2645. I915_WRITE(VIDSTART, vstart);
  2646. POSTING_READ(VIDSTART);
  2647. rgvmodectl |= MEMMODE_SWMODE_EN;
  2648. I915_WRITE(MEMMODECTL, rgvmodectl);
  2649. if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  2650. DRM_ERROR("stuck trying to change perf mode\n");
  2651. mdelay(1);
  2652. ironlake_set_drps(dev, fstart);
  2653. dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  2654. I915_READ(0x112e0);
  2655. dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
  2656. dev_priv->ips.last_count2 = I915_READ(0x112f4);
  2657. getrawmonotonic(&dev_priv->ips.last_time2);
  2658. spin_unlock_irq(&mchdev_lock);
  2659. }
  2660. static void ironlake_disable_drps(struct drm_device *dev)
  2661. {
  2662. struct drm_i915_private *dev_priv = dev->dev_private;
  2663. u16 rgvswctl;
  2664. spin_lock_irq(&mchdev_lock);
  2665. rgvswctl = I915_READ16(MEMSWCTL);
  2666. /* Ack interrupts, disable EFC interrupt */
  2667. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  2668. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  2669. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  2670. I915_WRITE(DEIIR, DE_PCU_EVENT);
  2671. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  2672. /* Go back to the starting frequency */
  2673. ironlake_set_drps(dev, dev_priv->ips.fstart);
  2674. mdelay(1);
  2675. rgvswctl |= MEMCTL_CMD_STS;
  2676. I915_WRITE(MEMSWCTL, rgvswctl);
  2677. mdelay(1);
  2678. spin_unlock_irq(&mchdev_lock);
  2679. }
  2680. /* There's a funny hw issue where the hw returns all 0 when reading from
  2681. * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
  2682. * ourselves, instead of doing a rmw cycle (which might result in us clearing
  2683. * all limits and the gpu stuck at whatever frequency it is at atm).
  2684. */
  2685. static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
  2686. {
  2687. u32 limits;
  2688. limits = 0;
  2689. if (*val >= dev_priv->rps.max_delay)
  2690. *val = dev_priv->rps.max_delay;
  2691. limits |= dev_priv->rps.max_delay << 24;
  2692. /* Only set the down limit when we've reached the lowest level to avoid
  2693. * getting more interrupts, otherwise leave this clear. This prevents a
  2694. * race in the hw when coming out of rc6: There's a tiny window where
  2695. * the hw runs at the minimal clock before selecting the desired
  2696. * frequency, if the down threshold expires in that window we will not
  2697. * receive a down interrupt. */
  2698. if (*val <= dev_priv->rps.min_delay) {
  2699. *val = dev_priv->rps.min_delay;
  2700. limits |= dev_priv->rps.min_delay << 16;
  2701. }
  2702. return limits;
  2703. }
  2704. void gen6_set_rps(struct drm_device *dev, u8 val)
  2705. {
  2706. struct drm_i915_private *dev_priv = dev->dev_private;
  2707. u32 limits = gen6_rps_limits(dev_priv, &val);
  2708. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2709. WARN_ON(val > dev_priv->rps.max_delay);
  2710. WARN_ON(val < dev_priv->rps.min_delay);
  2711. if (val == dev_priv->rps.cur_delay)
  2712. return;
  2713. if (IS_HASWELL(dev))
  2714. I915_WRITE(GEN6_RPNSWREQ,
  2715. HSW_FREQUENCY(val));
  2716. else
  2717. I915_WRITE(GEN6_RPNSWREQ,
  2718. GEN6_FREQUENCY(val) |
  2719. GEN6_OFFSET(0) |
  2720. GEN6_AGGRESSIVE_TURBO);
  2721. /* Make sure we continue to get interrupts
  2722. * until we hit the minimum or maximum frequencies.
  2723. */
  2724. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
  2725. POSTING_READ(GEN6_RPNSWREQ);
  2726. dev_priv->rps.cur_delay = val;
  2727. trace_intel_gpu_freq_change(val * 50);
  2728. }
  2729. /*
  2730. * Wait until the previous freq change has completed,
  2731. * or the timeout elapsed, and then update our notion
  2732. * of the current GPU frequency.
  2733. */
  2734. static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
  2735. {
  2736. u32 pval;
  2737. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2738. if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
  2739. DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
  2740. pval >>= 8;
  2741. if (pval != dev_priv->rps.cur_delay)
  2742. DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
  2743. vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
  2744. dev_priv->rps.cur_delay,
  2745. vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
  2746. dev_priv->rps.cur_delay = pval;
  2747. }
  2748. void valleyview_set_rps(struct drm_device *dev, u8 val)
  2749. {
  2750. struct drm_i915_private *dev_priv = dev->dev_private;
  2751. gen6_rps_limits(dev_priv, &val);
  2752. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2753. WARN_ON(val > dev_priv->rps.max_delay);
  2754. WARN_ON(val < dev_priv->rps.min_delay);
  2755. vlv_update_rps_cur_delay(dev_priv);
  2756. DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
  2757. vlv_gpu_freq(dev_priv->mem_freq,
  2758. dev_priv->rps.cur_delay),
  2759. dev_priv->rps.cur_delay,
  2760. vlv_gpu_freq(dev_priv->mem_freq, val), val);
  2761. if (val == dev_priv->rps.cur_delay)
  2762. return;
  2763. vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
  2764. dev_priv->rps.cur_delay = val;
  2765. trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
  2766. }
  2767. static void gen6_disable_rps_interrupts(struct drm_device *dev)
  2768. {
  2769. struct drm_i915_private *dev_priv = dev->dev_private;
  2770. I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  2771. I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
  2772. /* Complete PM interrupt masking here doesn't race with the rps work
  2773. * item again unmasking PM interrupts because that is using a different
  2774. * register (PMIMR) to mask PM interrupts. The only risk is in leaving
  2775. * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
  2776. spin_lock_irq(&dev_priv->irq_lock);
  2777. dev_priv->rps.pm_iir = 0;
  2778. spin_unlock_irq(&dev_priv->irq_lock);
  2779. I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
  2780. }
  2781. static void gen6_disable_rps(struct drm_device *dev)
  2782. {
  2783. struct drm_i915_private *dev_priv = dev->dev_private;
  2784. I915_WRITE(GEN6_RC_CONTROL, 0);
  2785. I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
  2786. gen6_disable_rps_interrupts(dev);
  2787. }
  2788. static void valleyview_disable_rps(struct drm_device *dev)
  2789. {
  2790. struct drm_i915_private *dev_priv = dev->dev_private;
  2791. I915_WRITE(GEN6_RC_CONTROL, 0);
  2792. gen6_disable_rps_interrupts(dev);
  2793. if (dev_priv->vlv_pctx) {
  2794. drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
  2795. dev_priv->vlv_pctx = NULL;
  2796. }
  2797. }
  2798. int intel_enable_rc6(const struct drm_device *dev)
  2799. {
  2800. /* No RC6 before Ironlake */
  2801. if (INTEL_INFO(dev)->gen < 5)
  2802. return 0;
  2803. /* Respect the kernel parameter if it is set */
  2804. if (i915_enable_rc6 >= 0)
  2805. return i915_enable_rc6;
  2806. /* Disable RC6 on Ironlake */
  2807. if (INTEL_INFO(dev)->gen == 5)
  2808. return 0;
  2809. if (IS_HASWELL(dev)) {
  2810. DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
  2811. return INTEL_RC6_ENABLE;
  2812. }
  2813. /* snb/ivb have more than one rc6 state. */
  2814. if (INTEL_INFO(dev)->gen == 6) {
  2815. DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
  2816. return INTEL_RC6_ENABLE;
  2817. }
  2818. DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
  2819. return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
  2820. }
  2821. static void gen6_enable_rps_interrupts(struct drm_device *dev)
  2822. {
  2823. struct drm_i915_private *dev_priv = dev->dev_private;
  2824. spin_lock_irq(&dev_priv->irq_lock);
  2825. WARN_ON(dev_priv->rps.pm_iir);
  2826. I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
  2827. I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
  2828. spin_unlock_irq(&dev_priv->irq_lock);
  2829. /* unmask all PM interrupts */
  2830. I915_WRITE(GEN6_PMINTRMSK, 0);
  2831. }
  2832. static void gen6_enable_rps(struct drm_device *dev)
  2833. {
  2834. struct drm_i915_private *dev_priv = dev->dev_private;
  2835. struct intel_ring_buffer *ring;
  2836. u32 rp_state_cap;
  2837. u32 gt_perf_status;
  2838. u32 rc6vids, pcu_mbox, rc6_mask = 0;
  2839. u32 gtfifodbg;
  2840. int rc6_mode;
  2841. int i, ret;
  2842. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2843. /* Here begins a magic sequence of register writes to enable
  2844. * auto-downclocking.
  2845. *
  2846. * Perhaps there might be some value in exposing these to
  2847. * userspace...
  2848. */
  2849. I915_WRITE(GEN6_RC_STATE, 0);
  2850. /* Clear the DBG now so we don't confuse earlier errors */
  2851. if ((gtfifodbg = I915_READ(GTFIFODBG))) {
  2852. DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
  2853. I915_WRITE(GTFIFODBG, gtfifodbg);
  2854. }
  2855. gen6_gt_force_wake_get(dev_priv);
  2856. rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  2857. gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  2858. /* In units of 50MHz */
  2859. dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
  2860. dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
  2861. dev_priv->rps.cur_delay = 0;
  2862. /* disable the counters and set deterministic thresholds */
  2863. I915_WRITE(GEN6_RC_CONTROL, 0);
  2864. I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
  2865. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
  2866. I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
  2867. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  2868. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  2869. for_each_ring(ring, dev_priv, i)
  2870. I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
  2871. I915_WRITE(GEN6_RC_SLEEP, 0);
  2872. I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
  2873. I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
  2874. I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
  2875. I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  2876. /* Check if we are enabling RC6 */
  2877. rc6_mode = intel_enable_rc6(dev_priv->dev);
  2878. if (rc6_mode & INTEL_RC6_ENABLE)
  2879. rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
  2880. /* We don't use those on Haswell */
  2881. if (!IS_HASWELL(dev)) {
  2882. if (rc6_mode & INTEL_RC6p_ENABLE)
  2883. rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
  2884. if (rc6_mode & INTEL_RC6pp_ENABLE)
  2885. rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
  2886. }
  2887. DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
  2888. (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
  2889. (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
  2890. (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
  2891. I915_WRITE(GEN6_RC_CONTROL,
  2892. rc6_mask |
  2893. GEN6_RC_CTL_EI_MODE(1) |
  2894. GEN6_RC_CTL_HW_ENABLE);
  2895. if (IS_HASWELL(dev)) {
  2896. I915_WRITE(GEN6_RPNSWREQ,
  2897. HSW_FREQUENCY(10));
  2898. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  2899. HSW_FREQUENCY(12));
  2900. } else {
  2901. I915_WRITE(GEN6_RPNSWREQ,
  2902. GEN6_FREQUENCY(10) |
  2903. GEN6_OFFSET(0) |
  2904. GEN6_AGGRESSIVE_TURBO);
  2905. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  2906. GEN6_FREQUENCY(12));
  2907. }
  2908. I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
  2909. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
  2910. dev_priv->rps.max_delay << 24 |
  2911. dev_priv->rps.min_delay << 16);
  2912. I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
  2913. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
  2914. I915_WRITE(GEN6_RP_UP_EI, 66000);
  2915. I915_WRITE(GEN6_RP_DOWN_EI, 350000);
  2916. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  2917. I915_WRITE(GEN6_RP_CONTROL,
  2918. GEN6_RP_MEDIA_TURBO |
  2919. GEN6_RP_MEDIA_HW_NORMAL_MODE |
  2920. GEN6_RP_MEDIA_IS_GFX |
  2921. GEN6_RP_ENABLE |
  2922. GEN6_RP_UP_BUSY_AVG |
  2923. (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
  2924. ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
  2925. if (!ret) {
  2926. pcu_mbox = 0;
  2927. ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
  2928. if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
  2929. DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
  2930. (dev_priv->rps.max_delay & 0xff) * 50,
  2931. (pcu_mbox & 0xff) * 50);
  2932. dev_priv->rps.hw_max = pcu_mbox & 0xff;
  2933. }
  2934. } else {
  2935. DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
  2936. }
  2937. gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
  2938. gen6_enable_rps_interrupts(dev);
  2939. rc6vids = 0;
  2940. ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
  2941. if (IS_GEN6(dev) && ret) {
  2942. DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
  2943. } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
  2944. DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
  2945. GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
  2946. rc6vids &= 0xffff00;
  2947. rc6vids |= GEN6_ENCODE_RC6_VID(450);
  2948. ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
  2949. if (ret)
  2950. DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
  2951. }
  2952. gen6_gt_force_wake_put(dev_priv);
  2953. }
  2954. static void gen6_update_ring_freq(struct drm_device *dev)
  2955. {
  2956. struct drm_i915_private *dev_priv = dev->dev_private;
  2957. int min_freq = 15;
  2958. unsigned int gpu_freq;
  2959. unsigned int max_ia_freq, min_ring_freq;
  2960. int scaling_factor = 180;
  2961. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2962. max_ia_freq = cpufreq_quick_get_max(0);
  2963. /*
  2964. * Default to measured freq if none found, PCU will ensure we don't go
  2965. * over
  2966. */
  2967. if (!max_ia_freq)
  2968. max_ia_freq = tsc_khz;
  2969. /* Convert from kHz to MHz */
  2970. max_ia_freq /= 1000;
  2971. min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
  2972. /* convert DDR frequency from units of 133.3MHz to bandwidth */
  2973. min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
  2974. /*
  2975. * For each potential GPU frequency, load a ring frequency we'd like
  2976. * to use for memory access. We do this by specifying the IA frequency
  2977. * the PCU should use as a reference to determine the ring frequency.
  2978. */
  2979. for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
  2980. gpu_freq--) {
  2981. int diff = dev_priv->rps.max_delay - gpu_freq;
  2982. unsigned int ia_freq = 0, ring_freq = 0;
  2983. if (IS_HASWELL(dev)) {
  2984. ring_freq = (gpu_freq * 5 + 3) / 4;
  2985. ring_freq = max(min_ring_freq, ring_freq);
  2986. /* leave ia_freq as the default, chosen by cpufreq */
  2987. } else {
  2988. /* On older processors, there is no separate ring
  2989. * clock domain, so in order to boost the bandwidth
  2990. * of the ring, we need to upclock the CPU (ia_freq).
  2991. *
  2992. * For GPU frequencies less than 750MHz,
  2993. * just use the lowest ring freq.
  2994. */
  2995. if (gpu_freq < min_freq)
  2996. ia_freq = 800;
  2997. else
  2998. ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
  2999. ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
  3000. }
  3001. sandybridge_pcode_write(dev_priv,
  3002. GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
  3003. ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
  3004. ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
  3005. gpu_freq);
  3006. }
  3007. }
  3008. int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
  3009. {
  3010. u32 val, rp0;
  3011. val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
  3012. rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
  3013. /* Clamp to max */
  3014. rp0 = min_t(u32, rp0, 0xea);
  3015. return rp0;
  3016. }
  3017. static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
  3018. {
  3019. u32 val, rpe;
  3020. val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
  3021. rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
  3022. val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
  3023. rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
  3024. return rpe;
  3025. }
  3026. int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
  3027. {
  3028. return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
  3029. }
  3030. static void vlv_rps_timer_work(struct work_struct *work)
  3031. {
  3032. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  3033. rps.vlv_work.work);
  3034. /*
  3035. * Timer fired, we must be idle. Drop to min voltage state.
  3036. * Note: we use RPe here since it should match the
  3037. * Vmin we were shooting for. That should give us better
  3038. * perf when we come back out of RC6 than if we used the
  3039. * min freq available.
  3040. */
  3041. mutex_lock(&dev_priv->rps.hw_lock);
  3042. if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
  3043. valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
  3044. mutex_unlock(&dev_priv->rps.hw_lock);
  3045. }
  3046. static void valleyview_setup_pctx(struct drm_device *dev)
  3047. {
  3048. struct drm_i915_private *dev_priv = dev->dev_private;
  3049. struct drm_i915_gem_object *pctx;
  3050. unsigned long pctx_paddr;
  3051. u32 pcbr;
  3052. int pctx_size = 24*1024;
  3053. pcbr = I915_READ(VLV_PCBR);
  3054. if (pcbr) {
  3055. /* BIOS set it up already, grab the pre-alloc'd space */
  3056. int pcbr_offset;
  3057. pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
  3058. pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
  3059. pcbr_offset,
  3060. I915_GTT_OFFSET_NONE,
  3061. pctx_size);
  3062. goto out;
  3063. }
  3064. /*
  3065. * From the Gunit register HAS:
  3066. * The Gfx driver is expected to program this register and ensure
  3067. * proper allocation within Gfx stolen memory. For example, this
  3068. * register should be programmed such than the PCBR range does not
  3069. * overlap with other ranges, such as the frame buffer, protected
  3070. * memory, or any other relevant ranges.
  3071. */
  3072. pctx = i915_gem_object_create_stolen(dev, pctx_size);
  3073. if (!pctx) {
  3074. DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
  3075. return;
  3076. }
  3077. pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
  3078. I915_WRITE(VLV_PCBR, pctx_paddr);
  3079. out:
  3080. dev_priv->vlv_pctx = pctx;
  3081. }
  3082. static void valleyview_enable_rps(struct drm_device *dev)
  3083. {
  3084. struct drm_i915_private *dev_priv = dev->dev_private;
  3085. struct intel_ring_buffer *ring;
  3086. u32 gtfifodbg, val;
  3087. int i;
  3088. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  3089. if ((gtfifodbg = I915_READ(GTFIFODBG))) {
  3090. DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
  3091. I915_WRITE(GTFIFODBG, gtfifodbg);
  3092. }
  3093. valleyview_setup_pctx(dev);
  3094. gen6_gt_force_wake_get(dev_priv);
  3095. I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
  3096. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
  3097. I915_WRITE(GEN6_RP_UP_EI, 66000);
  3098. I915_WRITE(GEN6_RP_DOWN_EI, 350000);
  3099. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  3100. I915_WRITE(GEN6_RP_CONTROL,
  3101. GEN6_RP_MEDIA_TURBO |
  3102. GEN6_RP_MEDIA_HW_NORMAL_MODE |
  3103. GEN6_RP_MEDIA_IS_GFX |
  3104. GEN6_RP_ENABLE |
  3105. GEN6_RP_UP_BUSY_AVG |
  3106. GEN6_RP_DOWN_IDLE_CONT);
  3107. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
  3108. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  3109. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  3110. for_each_ring(ring, dev_priv, i)
  3111. I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
  3112. I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
  3113. /* allows RC6 residency counter to work */
  3114. I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
  3115. I915_WRITE(GEN6_RC_CONTROL,
  3116. GEN7_RC_CTL_TO_MODE);
  3117. val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
  3118. switch ((val >> 6) & 3) {
  3119. case 0:
  3120. case 1:
  3121. dev_priv->mem_freq = 800;
  3122. break;
  3123. case 2:
  3124. dev_priv->mem_freq = 1066;
  3125. break;
  3126. case 3:
  3127. dev_priv->mem_freq = 1333;
  3128. break;
  3129. }
  3130. DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
  3131. DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
  3132. DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
  3133. dev_priv->rps.cur_delay = (val >> 8) & 0xff;
  3134. DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
  3135. vlv_gpu_freq(dev_priv->mem_freq,
  3136. dev_priv->rps.cur_delay),
  3137. dev_priv->rps.cur_delay);
  3138. dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
  3139. dev_priv->rps.hw_max = dev_priv->rps.max_delay;
  3140. DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
  3141. vlv_gpu_freq(dev_priv->mem_freq,
  3142. dev_priv->rps.max_delay),
  3143. dev_priv->rps.max_delay);
  3144. dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
  3145. DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
  3146. vlv_gpu_freq(dev_priv->mem_freq,
  3147. dev_priv->rps.rpe_delay),
  3148. dev_priv->rps.rpe_delay);
  3149. dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
  3150. DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
  3151. vlv_gpu_freq(dev_priv->mem_freq,
  3152. dev_priv->rps.min_delay),
  3153. dev_priv->rps.min_delay);
  3154. DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
  3155. vlv_gpu_freq(dev_priv->mem_freq,
  3156. dev_priv->rps.rpe_delay),
  3157. dev_priv->rps.rpe_delay);
  3158. INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
  3159. valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
  3160. gen6_enable_rps_interrupts(dev);
  3161. gen6_gt_force_wake_put(dev_priv);
  3162. }
  3163. void ironlake_teardown_rc6(struct drm_device *dev)
  3164. {
  3165. struct drm_i915_private *dev_priv = dev->dev_private;
  3166. if (dev_priv->ips.renderctx) {
  3167. i915_gem_object_unpin(dev_priv->ips.renderctx);
  3168. drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
  3169. dev_priv->ips.renderctx = NULL;
  3170. }
  3171. if (dev_priv->ips.pwrctx) {
  3172. i915_gem_object_unpin(dev_priv->ips.pwrctx);
  3173. drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
  3174. dev_priv->ips.pwrctx = NULL;
  3175. }
  3176. }
  3177. static void ironlake_disable_rc6(struct drm_device *dev)
  3178. {
  3179. struct drm_i915_private *dev_priv = dev->dev_private;
  3180. if (I915_READ(PWRCTXA)) {
  3181. /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
  3182. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
  3183. wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
  3184. 50);
  3185. I915_WRITE(PWRCTXA, 0);
  3186. POSTING_READ(PWRCTXA);
  3187. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  3188. POSTING_READ(RSTDBYCTL);
  3189. }
  3190. }
  3191. static int ironlake_setup_rc6(struct drm_device *dev)
  3192. {
  3193. struct drm_i915_private *dev_priv = dev->dev_private;
  3194. if (dev_priv->ips.renderctx == NULL)
  3195. dev_priv->ips.renderctx = intel_alloc_context_page(dev);
  3196. if (!dev_priv->ips.renderctx)
  3197. return -ENOMEM;
  3198. if (dev_priv->ips.pwrctx == NULL)
  3199. dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
  3200. if (!dev_priv->ips.pwrctx) {
  3201. ironlake_teardown_rc6(dev);
  3202. return -ENOMEM;
  3203. }
  3204. return 0;
  3205. }
  3206. static void ironlake_enable_rc6(struct drm_device *dev)
  3207. {
  3208. struct drm_i915_private *dev_priv = dev->dev_private;
  3209. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  3210. bool was_interruptible;
  3211. int ret;
  3212. /* rc6 disabled by default due to repeated reports of hanging during
  3213. * boot and resume.
  3214. */
  3215. if (!intel_enable_rc6(dev))
  3216. return;
  3217. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  3218. ret = ironlake_setup_rc6(dev);
  3219. if (ret)
  3220. return;
  3221. was_interruptible = dev_priv->mm.interruptible;
  3222. dev_priv->mm.interruptible = false;
  3223. /*
  3224. * GPU can automatically power down the render unit if given a page
  3225. * to save state.
  3226. */
  3227. ret = intel_ring_begin(ring, 6);
  3228. if (ret) {
  3229. ironlake_teardown_rc6(dev);
  3230. dev_priv->mm.interruptible = was_interruptible;
  3231. return;
  3232. }
  3233. intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
  3234. intel_ring_emit(ring, MI_SET_CONTEXT);
  3235. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
  3236. MI_MM_SPACE_GTT |
  3237. MI_SAVE_EXT_STATE_EN |
  3238. MI_RESTORE_EXT_STATE_EN |
  3239. MI_RESTORE_INHIBIT);
  3240. intel_ring_emit(ring, MI_SUSPEND_FLUSH);
  3241. intel_ring_emit(ring, MI_NOOP);
  3242. intel_ring_emit(ring, MI_FLUSH);
  3243. intel_ring_advance(ring);
  3244. /*
  3245. * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
  3246. * does an implicit flush, combined with MI_FLUSH above, it should be
  3247. * safe to assume that renderctx is valid
  3248. */
  3249. ret = intel_ring_idle(ring);
  3250. dev_priv->mm.interruptible = was_interruptible;
  3251. if (ret) {
  3252. DRM_ERROR("failed to enable ironlake power savings\n");
  3253. ironlake_teardown_rc6(dev);
  3254. return;
  3255. }
  3256. I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
  3257. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  3258. }
  3259. static unsigned long intel_pxfreq(u32 vidfreq)
  3260. {
  3261. unsigned long freq;
  3262. int div = (vidfreq & 0x3f0000) >> 16;
  3263. int post = (vidfreq & 0x3000) >> 12;
  3264. int pre = (vidfreq & 0x7);
  3265. if (!pre)
  3266. return 0;
  3267. freq = ((div * 133333) / ((1<<post) * pre));
  3268. return freq;
  3269. }
  3270. static const struct cparams {
  3271. u16 i;
  3272. u16 t;
  3273. u16 m;
  3274. u16 c;
  3275. } cparams[] = {
  3276. { 1, 1333, 301, 28664 },
  3277. { 1, 1066, 294, 24460 },
  3278. { 1, 800, 294, 25192 },
  3279. { 0, 1333, 276, 27605 },
  3280. { 0, 1066, 276, 27605 },
  3281. { 0, 800, 231, 23784 },
  3282. };
  3283. static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
  3284. {
  3285. u64 total_count, diff, ret;
  3286. u32 count1, count2, count3, m = 0, c = 0;
  3287. unsigned long now = jiffies_to_msecs(jiffies), diff1;
  3288. int i;
  3289. assert_spin_locked(&mchdev_lock);
  3290. diff1 = now - dev_priv->ips.last_time1;
  3291. /* Prevent division-by-zero if we are asking too fast.
  3292. * Also, we don't get interesting results if we are polling
  3293. * faster than once in 10ms, so just return the saved value
  3294. * in such cases.
  3295. */
  3296. if (diff1 <= 10)
  3297. return dev_priv->ips.chipset_power;
  3298. count1 = I915_READ(DMIEC);
  3299. count2 = I915_READ(DDREC);
  3300. count3 = I915_READ(CSIEC);
  3301. total_count = count1 + count2 + count3;
  3302. /* FIXME: handle per-counter overflow */
  3303. if (total_count < dev_priv->ips.last_count1) {
  3304. diff = ~0UL - dev_priv->ips.last_count1;
  3305. diff += total_count;
  3306. } else {
  3307. diff = total_count - dev_priv->ips.last_count1;
  3308. }
  3309. for (i = 0; i < ARRAY_SIZE(cparams); i++) {
  3310. if (cparams[i].i == dev_priv->ips.c_m &&
  3311. cparams[i].t == dev_priv->ips.r_t) {
  3312. m = cparams[i].m;
  3313. c = cparams[i].c;
  3314. break;
  3315. }
  3316. }
  3317. diff = div_u64(diff, diff1);
  3318. ret = ((m * diff) + c);
  3319. ret = div_u64(ret, 10);
  3320. dev_priv->ips.last_count1 = total_count;
  3321. dev_priv->ips.last_time1 = now;
  3322. dev_priv->ips.chipset_power = ret;
  3323. return ret;
  3324. }
  3325. unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
  3326. {
  3327. unsigned long val;
  3328. if (dev_priv->info->gen != 5)
  3329. return 0;
  3330. spin_lock_irq(&mchdev_lock);
  3331. val = __i915_chipset_val(dev_priv);
  3332. spin_unlock_irq(&mchdev_lock);
  3333. return val;
  3334. }
  3335. unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
  3336. {
  3337. unsigned long m, x, b;
  3338. u32 tsfs;
  3339. tsfs = I915_READ(TSFS);
  3340. m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
  3341. x = I915_READ8(TR1);
  3342. b = tsfs & TSFS_INTR_MASK;
  3343. return ((m * x) / 127) - b;
  3344. }
  3345. static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
  3346. {
  3347. static const struct v_table {
  3348. u16 vd; /* in .1 mil */
  3349. u16 vm; /* in .1 mil */
  3350. } v_table[] = {
  3351. { 0, 0, },
  3352. { 375, 0, },
  3353. { 500, 0, },
  3354. { 625, 0, },
  3355. { 750, 0, },
  3356. { 875, 0, },
  3357. { 1000, 0, },
  3358. { 1125, 0, },
  3359. { 4125, 3000, },
  3360. { 4125, 3000, },
  3361. { 4125, 3000, },
  3362. { 4125, 3000, },
  3363. { 4125, 3000, },
  3364. { 4125, 3000, },
  3365. { 4125, 3000, },
  3366. { 4125, 3000, },
  3367. { 4125, 3000, },
  3368. { 4125, 3000, },
  3369. { 4125, 3000, },
  3370. { 4125, 3000, },
  3371. { 4125, 3000, },
  3372. { 4125, 3000, },
  3373. { 4125, 3000, },
  3374. { 4125, 3000, },
  3375. { 4125, 3000, },
  3376. { 4125, 3000, },
  3377. { 4125, 3000, },
  3378. { 4125, 3000, },
  3379. { 4125, 3000, },
  3380. { 4125, 3000, },
  3381. { 4125, 3000, },
  3382. { 4125, 3000, },
  3383. { 4250, 3125, },
  3384. { 4375, 3250, },
  3385. { 4500, 3375, },
  3386. { 4625, 3500, },
  3387. { 4750, 3625, },
  3388. { 4875, 3750, },
  3389. { 5000, 3875, },
  3390. { 5125, 4000, },
  3391. { 5250, 4125, },
  3392. { 5375, 4250, },
  3393. { 5500, 4375, },
  3394. { 5625, 4500, },
  3395. { 5750, 4625, },
  3396. { 5875, 4750, },
  3397. { 6000, 4875, },
  3398. { 6125, 5000, },
  3399. { 6250, 5125, },
  3400. { 6375, 5250, },
  3401. { 6500, 5375, },
  3402. { 6625, 5500, },
  3403. { 6750, 5625, },
  3404. { 6875, 5750, },
  3405. { 7000, 5875, },
  3406. { 7125, 6000, },
  3407. { 7250, 6125, },
  3408. { 7375, 6250, },
  3409. { 7500, 6375, },
  3410. { 7625, 6500, },
  3411. { 7750, 6625, },
  3412. { 7875, 6750, },
  3413. { 8000, 6875, },
  3414. { 8125, 7000, },
  3415. { 8250, 7125, },
  3416. { 8375, 7250, },
  3417. { 8500, 7375, },
  3418. { 8625, 7500, },
  3419. { 8750, 7625, },
  3420. { 8875, 7750, },
  3421. { 9000, 7875, },
  3422. { 9125, 8000, },
  3423. { 9250, 8125, },
  3424. { 9375, 8250, },
  3425. { 9500, 8375, },
  3426. { 9625, 8500, },
  3427. { 9750, 8625, },
  3428. { 9875, 8750, },
  3429. { 10000, 8875, },
  3430. { 10125, 9000, },
  3431. { 10250, 9125, },
  3432. { 10375, 9250, },
  3433. { 10500, 9375, },
  3434. { 10625, 9500, },
  3435. { 10750, 9625, },
  3436. { 10875, 9750, },
  3437. { 11000, 9875, },
  3438. { 11125, 10000, },
  3439. { 11250, 10125, },
  3440. { 11375, 10250, },
  3441. { 11500, 10375, },
  3442. { 11625, 10500, },
  3443. { 11750, 10625, },
  3444. { 11875, 10750, },
  3445. { 12000, 10875, },
  3446. { 12125, 11000, },
  3447. { 12250, 11125, },
  3448. { 12375, 11250, },
  3449. { 12500, 11375, },
  3450. { 12625, 11500, },
  3451. { 12750, 11625, },
  3452. { 12875, 11750, },
  3453. { 13000, 11875, },
  3454. { 13125, 12000, },
  3455. { 13250, 12125, },
  3456. { 13375, 12250, },
  3457. { 13500, 12375, },
  3458. { 13625, 12500, },
  3459. { 13750, 12625, },
  3460. { 13875, 12750, },
  3461. { 14000, 12875, },
  3462. { 14125, 13000, },
  3463. { 14250, 13125, },
  3464. { 14375, 13250, },
  3465. { 14500, 13375, },
  3466. { 14625, 13500, },
  3467. { 14750, 13625, },
  3468. { 14875, 13750, },
  3469. { 15000, 13875, },
  3470. { 15125, 14000, },
  3471. { 15250, 14125, },
  3472. { 15375, 14250, },
  3473. { 15500, 14375, },
  3474. { 15625, 14500, },
  3475. { 15750, 14625, },
  3476. { 15875, 14750, },
  3477. { 16000, 14875, },
  3478. { 16125, 15000, },
  3479. };
  3480. if (dev_priv->info->is_mobile)
  3481. return v_table[pxvid].vm;
  3482. else
  3483. return v_table[pxvid].vd;
  3484. }
  3485. static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
  3486. {
  3487. struct timespec now, diff1;
  3488. u64 diff;
  3489. unsigned long diffms;
  3490. u32 count;
  3491. assert_spin_locked(&mchdev_lock);
  3492. getrawmonotonic(&now);
  3493. diff1 = timespec_sub(now, dev_priv->ips.last_time2);
  3494. /* Don't divide by 0 */
  3495. diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
  3496. if (!diffms)
  3497. return;
  3498. count = I915_READ(GFXEC);
  3499. if (count < dev_priv->ips.last_count2) {
  3500. diff = ~0UL - dev_priv->ips.last_count2;
  3501. diff += count;
  3502. } else {
  3503. diff = count - dev_priv->ips.last_count2;
  3504. }
  3505. dev_priv->ips.last_count2 = count;
  3506. dev_priv->ips.last_time2 = now;
  3507. /* More magic constants... */
  3508. diff = diff * 1181;
  3509. diff = div_u64(diff, diffms * 10);
  3510. dev_priv->ips.gfx_power = diff;
  3511. }
  3512. void i915_update_gfx_val(struct drm_i915_private *dev_priv)
  3513. {
  3514. if (dev_priv->info->gen != 5)
  3515. return;
  3516. spin_lock_irq(&mchdev_lock);
  3517. __i915_update_gfx_val(dev_priv);
  3518. spin_unlock_irq(&mchdev_lock);
  3519. }
  3520. static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
  3521. {
  3522. unsigned long t, corr, state1, corr2, state2;
  3523. u32 pxvid, ext_v;
  3524. assert_spin_locked(&mchdev_lock);
  3525. pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
  3526. pxvid = (pxvid >> 24) & 0x7f;
  3527. ext_v = pvid_to_extvid(dev_priv, pxvid);
  3528. state1 = ext_v;
  3529. t = i915_mch_val(dev_priv);
  3530. /* Revel in the empirically derived constants */
  3531. /* Correction factor in 1/100000 units */
  3532. if (t > 80)
  3533. corr = ((t * 2349) + 135940);
  3534. else if (t >= 50)
  3535. corr = ((t * 964) + 29317);
  3536. else /* < 50 */
  3537. corr = ((t * 301) + 1004);
  3538. corr = corr * ((150142 * state1) / 10000 - 78642);
  3539. corr /= 100000;
  3540. corr2 = (corr * dev_priv->ips.corr);
  3541. state2 = (corr2 * state1) / 10000;
  3542. state2 /= 100; /* convert to mW */
  3543. __i915_update_gfx_val(dev_priv);
  3544. return dev_priv->ips.gfx_power + state2;
  3545. }
  3546. unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
  3547. {
  3548. unsigned long val;
  3549. if (dev_priv->info->gen != 5)
  3550. return 0;
  3551. spin_lock_irq(&mchdev_lock);
  3552. val = __i915_gfx_val(dev_priv);
  3553. spin_unlock_irq(&mchdev_lock);
  3554. return val;
  3555. }
  3556. /**
  3557. * i915_read_mch_val - return value for IPS use
  3558. *
  3559. * Calculate and return a value for the IPS driver to use when deciding whether
  3560. * we have thermal and power headroom to increase CPU or GPU power budget.
  3561. */
  3562. unsigned long i915_read_mch_val(void)
  3563. {
  3564. struct drm_i915_private *dev_priv;
  3565. unsigned long chipset_val, graphics_val, ret = 0;
  3566. spin_lock_irq(&mchdev_lock);
  3567. if (!i915_mch_dev)
  3568. goto out_unlock;
  3569. dev_priv = i915_mch_dev;
  3570. chipset_val = __i915_chipset_val(dev_priv);
  3571. graphics_val = __i915_gfx_val(dev_priv);
  3572. ret = chipset_val + graphics_val;
  3573. out_unlock:
  3574. spin_unlock_irq(&mchdev_lock);
  3575. return ret;
  3576. }
  3577. EXPORT_SYMBOL_GPL(i915_read_mch_val);
  3578. /**
  3579. * i915_gpu_raise - raise GPU frequency limit
  3580. *
  3581. * Raise the limit; IPS indicates we have thermal headroom.
  3582. */
  3583. bool i915_gpu_raise(void)
  3584. {
  3585. struct drm_i915_private *dev_priv;
  3586. bool ret = true;
  3587. spin_lock_irq(&mchdev_lock);
  3588. if (!i915_mch_dev) {
  3589. ret = false;
  3590. goto out_unlock;
  3591. }
  3592. dev_priv = i915_mch_dev;
  3593. if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
  3594. dev_priv->ips.max_delay--;
  3595. out_unlock:
  3596. spin_unlock_irq(&mchdev_lock);
  3597. return ret;
  3598. }
  3599. EXPORT_SYMBOL_GPL(i915_gpu_raise);
  3600. /**
  3601. * i915_gpu_lower - lower GPU frequency limit
  3602. *
  3603. * IPS indicates we're close to a thermal limit, so throttle back the GPU
  3604. * frequency maximum.
  3605. */
  3606. bool i915_gpu_lower(void)
  3607. {
  3608. struct drm_i915_private *dev_priv;
  3609. bool ret = true;
  3610. spin_lock_irq(&mchdev_lock);
  3611. if (!i915_mch_dev) {
  3612. ret = false;
  3613. goto out_unlock;
  3614. }
  3615. dev_priv = i915_mch_dev;
  3616. if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
  3617. dev_priv->ips.max_delay++;
  3618. out_unlock:
  3619. spin_unlock_irq(&mchdev_lock);
  3620. return ret;
  3621. }
  3622. EXPORT_SYMBOL_GPL(i915_gpu_lower);
  3623. /**
  3624. * i915_gpu_busy - indicate GPU business to IPS
  3625. *
  3626. * Tell the IPS driver whether or not the GPU is busy.
  3627. */
  3628. bool i915_gpu_busy(void)
  3629. {
  3630. struct drm_i915_private *dev_priv;
  3631. struct intel_ring_buffer *ring;
  3632. bool ret = false;
  3633. int i;
  3634. spin_lock_irq(&mchdev_lock);
  3635. if (!i915_mch_dev)
  3636. goto out_unlock;
  3637. dev_priv = i915_mch_dev;
  3638. for_each_ring(ring, dev_priv, i)
  3639. ret |= !list_empty(&ring->request_list);
  3640. out_unlock:
  3641. spin_unlock_irq(&mchdev_lock);
  3642. return ret;
  3643. }
  3644. EXPORT_SYMBOL_GPL(i915_gpu_busy);
  3645. /**
  3646. * i915_gpu_turbo_disable - disable graphics turbo
  3647. *
  3648. * Disable graphics turbo by resetting the max frequency and setting the
  3649. * current frequency to the default.
  3650. */
  3651. bool i915_gpu_turbo_disable(void)
  3652. {
  3653. struct drm_i915_private *dev_priv;
  3654. bool ret = true;
  3655. spin_lock_irq(&mchdev_lock);
  3656. if (!i915_mch_dev) {
  3657. ret = false;
  3658. goto out_unlock;
  3659. }
  3660. dev_priv = i915_mch_dev;
  3661. dev_priv->ips.max_delay = dev_priv->ips.fstart;
  3662. if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
  3663. ret = false;
  3664. out_unlock:
  3665. spin_unlock_irq(&mchdev_lock);
  3666. return ret;
  3667. }
  3668. EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
  3669. /**
  3670. * Tells the intel_ips driver that the i915 driver is now loaded, if
  3671. * IPS got loaded first.
  3672. *
  3673. * This awkward dance is so that neither module has to depend on the
  3674. * other in order for IPS to do the appropriate communication of
  3675. * GPU turbo limits to i915.
  3676. */
  3677. static void
  3678. ips_ping_for_i915_load(void)
  3679. {
  3680. void (*link)(void);
  3681. link = symbol_get(ips_link_to_i915_driver);
  3682. if (link) {
  3683. link();
  3684. symbol_put(ips_link_to_i915_driver);
  3685. }
  3686. }
  3687. void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
  3688. {
  3689. /* We only register the i915 ips part with intel-ips once everything is
  3690. * set up, to avoid intel-ips sneaking in and reading bogus values. */
  3691. spin_lock_irq(&mchdev_lock);
  3692. i915_mch_dev = dev_priv;
  3693. spin_unlock_irq(&mchdev_lock);
  3694. ips_ping_for_i915_load();
  3695. }
  3696. void intel_gpu_ips_teardown(void)
  3697. {
  3698. spin_lock_irq(&mchdev_lock);
  3699. i915_mch_dev = NULL;
  3700. spin_unlock_irq(&mchdev_lock);
  3701. }
  3702. static void intel_init_emon(struct drm_device *dev)
  3703. {
  3704. struct drm_i915_private *dev_priv = dev->dev_private;
  3705. u32 lcfuse;
  3706. u8 pxw[16];
  3707. int i;
  3708. /* Disable to program */
  3709. I915_WRITE(ECR, 0);
  3710. POSTING_READ(ECR);
  3711. /* Program energy weights for various events */
  3712. I915_WRITE(SDEW, 0x15040d00);
  3713. I915_WRITE(CSIEW0, 0x007f0000);
  3714. I915_WRITE(CSIEW1, 0x1e220004);
  3715. I915_WRITE(CSIEW2, 0x04000004);
  3716. for (i = 0; i < 5; i++)
  3717. I915_WRITE(PEW + (i * 4), 0);
  3718. for (i = 0; i < 3; i++)
  3719. I915_WRITE(DEW + (i * 4), 0);
  3720. /* Program P-state weights to account for frequency power adjustment */
  3721. for (i = 0; i < 16; i++) {
  3722. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  3723. unsigned long freq = intel_pxfreq(pxvidfreq);
  3724. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  3725. PXVFREQ_PX_SHIFT;
  3726. unsigned long val;
  3727. val = vid * vid;
  3728. val *= (freq / 1000);
  3729. val *= 255;
  3730. val /= (127*127*900);
  3731. if (val > 0xff)
  3732. DRM_ERROR("bad pxval: %ld\n", val);
  3733. pxw[i] = val;
  3734. }
  3735. /* Render standby states get 0 weight */
  3736. pxw[14] = 0;
  3737. pxw[15] = 0;
  3738. for (i = 0; i < 4; i++) {
  3739. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  3740. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  3741. I915_WRITE(PXW + (i * 4), val);
  3742. }
  3743. /* Adjust magic regs to magic values (more experimental results) */
  3744. I915_WRITE(OGW0, 0);
  3745. I915_WRITE(OGW1, 0);
  3746. I915_WRITE(EG0, 0x00007f00);
  3747. I915_WRITE(EG1, 0x0000000e);
  3748. I915_WRITE(EG2, 0x000e0000);
  3749. I915_WRITE(EG3, 0x68000300);
  3750. I915_WRITE(EG4, 0x42000000);
  3751. I915_WRITE(EG5, 0x00140031);
  3752. I915_WRITE(EG6, 0);
  3753. I915_WRITE(EG7, 0);
  3754. for (i = 0; i < 8; i++)
  3755. I915_WRITE(PXWL + (i * 4), 0);
  3756. /* Enable PMON + select events */
  3757. I915_WRITE(ECR, 0x80000019);
  3758. lcfuse = I915_READ(LCFUSE02);
  3759. dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
  3760. }
  3761. void intel_disable_gt_powersave(struct drm_device *dev)
  3762. {
  3763. struct drm_i915_private *dev_priv = dev->dev_private;
  3764. /* Interrupts should be disabled already to avoid re-arming. */
  3765. WARN_ON(dev->irq_enabled);
  3766. if (IS_IRONLAKE_M(dev)) {
  3767. ironlake_disable_drps(dev);
  3768. ironlake_disable_rc6(dev);
  3769. } else if (INTEL_INFO(dev)->gen >= 6) {
  3770. cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
  3771. cancel_work_sync(&dev_priv->rps.work);
  3772. if (IS_VALLEYVIEW(dev))
  3773. cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
  3774. mutex_lock(&dev_priv->rps.hw_lock);
  3775. if (IS_VALLEYVIEW(dev))
  3776. valleyview_disable_rps(dev);
  3777. else
  3778. gen6_disable_rps(dev);
  3779. mutex_unlock(&dev_priv->rps.hw_lock);
  3780. }
  3781. }
  3782. static void intel_gen6_powersave_work(struct work_struct *work)
  3783. {
  3784. struct drm_i915_private *dev_priv =
  3785. container_of(work, struct drm_i915_private,
  3786. rps.delayed_resume_work.work);
  3787. struct drm_device *dev = dev_priv->dev;
  3788. mutex_lock(&dev_priv->rps.hw_lock);
  3789. if (IS_VALLEYVIEW(dev)) {
  3790. valleyview_enable_rps(dev);
  3791. } else {
  3792. gen6_enable_rps(dev);
  3793. gen6_update_ring_freq(dev);
  3794. }
  3795. mutex_unlock(&dev_priv->rps.hw_lock);
  3796. }
  3797. void intel_enable_gt_powersave(struct drm_device *dev)
  3798. {
  3799. struct drm_i915_private *dev_priv = dev->dev_private;
  3800. if (IS_IRONLAKE_M(dev)) {
  3801. ironlake_enable_drps(dev);
  3802. ironlake_enable_rc6(dev);
  3803. intel_init_emon(dev);
  3804. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  3805. /*
  3806. * PCU communication is slow and this doesn't need to be
  3807. * done at any specific time, so do this out of our fast path
  3808. * to make resume and init faster.
  3809. */
  3810. schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
  3811. round_jiffies_up_relative(HZ));
  3812. }
  3813. }
  3814. static void ibx_init_clock_gating(struct drm_device *dev)
  3815. {
  3816. struct drm_i915_private *dev_priv = dev->dev_private;
  3817. /*
  3818. * On Ibex Peak and Cougar Point, we need to disable clock
  3819. * gating for the panel power sequencer or it will fail to
  3820. * start up when no ports are active.
  3821. */
  3822. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  3823. }
  3824. static void g4x_disable_trickle_feed(struct drm_device *dev)
  3825. {
  3826. struct drm_i915_private *dev_priv = dev->dev_private;
  3827. int pipe;
  3828. for_each_pipe(pipe) {
  3829. I915_WRITE(DSPCNTR(pipe),
  3830. I915_READ(DSPCNTR(pipe)) |
  3831. DISPPLANE_TRICKLE_FEED_DISABLE);
  3832. intel_flush_display_plane(dev_priv, pipe);
  3833. }
  3834. }
  3835. static void ironlake_init_clock_gating(struct drm_device *dev)
  3836. {
  3837. struct drm_i915_private *dev_priv = dev->dev_private;
  3838. uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
  3839. /*
  3840. * Required for FBC
  3841. * WaFbcDisableDpfcClockGating:ilk
  3842. */
  3843. dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
  3844. ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
  3845. ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
  3846. I915_WRITE(PCH_3DCGDIS0,
  3847. MARIUNIT_CLOCK_GATE_DISABLE |
  3848. SVSMUNIT_CLOCK_GATE_DISABLE);
  3849. I915_WRITE(PCH_3DCGDIS1,
  3850. VFMUNIT_CLOCK_GATE_DISABLE);
  3851. /*
  3852. * According to the spec the following bits should be set in
  3853. * order to enable memory self-refresh
  3854. * The bit 22/21 of 0x42004
  3855. * The bit 5 of 0x42020
  3856. * The bit 15 of 0x45000
  3857. */
  3858. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3859. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  3860. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  3861. dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
  3862. I915_WRITE(DISP_ARB_CTL,
  3863. (I915_READ(DISP_ARB_CTL) |
  3864. DISP_FBC_WM_DIS));
  3865. I915_WRITE(WM3_LP_ILK, 0);
  3866. I915_WRITE(WM2_LP_ILK, 0);
  3867. I915_WRITE(WM1_LP_ILK, 0);
  3868. /*
  3869. * Based on the document from hardware guys the following bits
  3870. * should be set unconditionally in order to enable FBC.
  3871. * The bit 22 of 0x42000
  3872. * The bit 22 of 0x42004
  3873. * The bit 7,8,9 of 0x42020.
  3874. */
  3875. if (IS_IRONLAKE_M(dev)) {
  3876. /* WaFbcAsynchFlipDisableFbcQueue:ilk */
  3877. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  3878. I915_READ(ILK_DISPLAY_CHICKEN1) |
  3879. ILK_FBCQ_DIS);
  3880. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3881. I915_READ(ILK_DISPLAY_CHICKEN2) |
  3882. ILK_DPARB_GATE);
  3883. }
  3884. I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
  3885. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3886. I915_READ(ILK_DISPLAY_CHICKEN2) |
  3887. ILK_ELPIN_409_SELECT);
  3888. I915_WRITE(_3D_CHICKEN2,
  3889. _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
  3890. _3D_CHICKEN2_WM_READ_PIPELINED);
  3891. /* WaDisableRenderCachePipelinedFlush:ilk */
  3892. I915_WRITE(CACHE_MODE_0,
  3893. _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
  3894. g4x_disable_trickle_feed(dev);
  3895. ibx_init_clock_gating(dev);
  3896. }
  3897. static void cpt_init_clock_gating(struct drm_device *dev)
  3898. {
  3899. struct drm_i915_private *dev_priv = dev->dev_private;
  3900. int pipe;
  3901. uint32_t val;
  3902. /*
  3903. * On Ibex Peak and Cougar Point, we need to disable clock
  3904. * gating for the panel power sequencer or it will fail to
  3905. * start up when no ports are active.
  3906. */
  3907. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  3908. I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
  3909. DPLS_EDP_PPS_FIX_DIS);
  3910. /* The below fixes the weird display corruption, a few pixels shifted
  3911. * downward, on (only) LVDS of some HP laptops with IVY.
  3912. */
  3913. for_each_pipe(pipe) {
  3914. val = I915_READ(TRANS_CHICKEN2(pipe));
  3915. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  3916. val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
  3917. if (dev_priv->vbt.fdi_rx_polarity_inverted)
  3918. val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
  3919. val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
  3920. val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
  3921. val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
  3922. I915_WRITE(TRANS_CHICKEN2(pipe), val);
  3923. }
  3924. /* WADP0ClockGatingDisable */
  3925. for_each_pipe(pipe) {
  3926. I915_WRITE(TRANS_CHICKEN1(pipe),
  3927. TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
  3928. }
  3929. }
  3930. static void gen6_check_mch_setup(struct drm_device *dev)
  3931. {
  3932. struct drm_i915_private *dev_priv = dev->dev_private;
  3933. uint32_t tmp;
  3934. tmp = I915_READ(MCH_SSKPD);
  3935. if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
  3936. DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
  3937. DRM_INFO("This can cause pipe underruns and display issues.\n");
  3938. DRM_INFO("Please upgrade your BIOS to fix this.\n");
  3939. }
  3940. }
  3941. static void gen6_init_clock_gating(struct drm_device *dev)
  3942. {
  3943. struct drm_i915_private *dev_priv = dev->dev_private;
  3944. uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
  3945. I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
  3946. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3947. I915_READ(ILK_DISPLAY_CHICKEN2) |
  3948. ILK_ELPIN_409_SELECT);
  3949. /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
  3950. I915_WRITE(_3D_CHICKEN,
  3951. _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
  3952. /* WaSetupGtModeTdRowDispatch:snb */
  3953. if (IS_SNB_GT1(dev))
  3954. I915_WRITE(GEN6_GT_MODE,
  3955. _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
  3956. I915_WRITE(WM3_LP_ILK, 0);
  3957. I915_WRITE(WM2_LP_ILK, 0);
  3958. I915_WRITE(WM1_LP_ILK, 0);
  3959. I915_WRITE(CACHE_MODE_0,
  3960. _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
  3961. I915_WRITE(GEN6_UCGCTL1,
  3962. I915_READ(GEN6_UCGCTL1) |
  3963. GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
  3964. GEN6_CSUNIT_CLOCK_GATE_DISABLE);
  3965. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  3966. * gating disable must be set. Failure to set it results in
  3967. * flickering pixels due to Z write ordering failures after
  3968. * some amount of runtime in the Mesa "fire" demo, and Unigine
  3969. * Sanctuary and Tropics, and apparently anything else with
  3970. * alpha test or pixel discard.
  3971. *
  3972. * According to the spec, bit 11 (RCCUNIT) must also be set,
  3973. * but we didn't debug actual testcases to find it out.
  3974. *
  3975. * Also apply WaDisableVDSUnitClockGating:snb and
  3976. * WaDisableRCPBUnitClockGating:snb.
  3977. */
  3978. I915_WRITE(GEN6_UCGCTL2,
  3979. GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
  3980. GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  3981. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  3982. /* Bspec says we need to always set all mask bits. */
  3983. I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
  3984. _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
  3985. /*
  3986. * According to the spec the following bits should be
  3987. * set in order to enable memory self-refresh and fbc:
  3988. * The bit21 and bit22 of 0x42000
  3989. * The bit21 and bit22 of 0x42004
  3990. * The bit5 and bit7 of 0x42020
  3991. * The bit14 of 0x70180
  3992. * The bit14 of 0x71180
  3993. *
  3994. * WaFbcAsynchFlipDisableFbcQueue:snb
  3995. */
  3996. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  3997. I915_READ(ILK_DISPLAY_CHICKEN1) |
  3998. ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
  3999. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  4000. I915_READ(ILK_DISPLAY_CHICKEN2) |
  4001. ILK_DPARB_GATE | ILK_VSDPFD_FULL);
  4002. I915_WRITE(ILK_DSPCLK_GATE_D,
  4003. I915_READ(ILK_DSPCLK_GATE_D) |
  4004. ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
  4005. ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
  4006. /* WaMbcDriverBootEnable:snb */
  4007. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  4008. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  4009. g4x_disable_trickle_feed(dev);
  4010. /* The default value should be 0x200 according to docs, but the two
  4011. * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
  4012. I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
  4013. I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
  4014. cpt_init_clock_gating(dev);
  4015. gen6_check_mch_setup(dev);
  4016. }
  4017. static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
  4018. {
  4019. uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
  4020. reg &= ~GEN7_FF_SCHED_MASK;
  4021. reg |= GEN7_FF_TS_SCHED_HW;
  4022. reg |= GEN7_FF_VS_SCHED_HW;
  4023. reg |= GEN7_FF_DS_SCHED_HW;
  4024. if (IS_HASWELL(dev_priv->dev))
  4025. reg &= ~GEN7_FF_VS_REF_CNT_FFME;
  4026. I915_WRITE(GEN7_FF_THREAD_MODE, reg);
  4027. }
  4028. static void lpt_init_clock_gating(struct drm_device *dev)
  4029. {
  4030. struct drm_i915_private *dev_priv = dev->dev_private;
  4031. /*
  4032. * TODO: this bit should only be enabled when really needed, then
  4033. * disabled when not needed anymore in order to save power.
  4034. */
  4035. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
  4036. I915_WRITE(SOUTH_DSPCLK_GATE_D,
  4037. I915_READ(SOUTH_DSPCLK_GATE_D) |
  4038. PCH_LP_PARTITION_LEVEL_DISABLE);
  4039. /* WADPOClockGatingDisable:hsw */
  4040. I915_WRITE(_TRANSA_CHICKEN1,
  4041. I915_READ(_TRANSA_CHICKEN1) |
  4042. TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
  4043. }
  4044. static void lpt_suspend_hw(struct drm_device *dev)
  4045. {
  4046. struct drm_i915_private *dev_priv = dev->dev_private;
  4047. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  4048. uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
  4049. val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
  4050. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  4051. }
  4052. }
  4053. static void haswell_init_clock_gating(struct drm_device *dev)
  4054. {
  4055. struct drm_i915_private *dev_priv = dev->dev_private;
  4056. I915_WRITE(WM3_LP_ILK, 0);
  4057. I915_WRITE(WM2_LP_ILK, 0);
  4058. I915_WRITE(WM1_LP_ILK, 0);
  4059. /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  4060. * This implements the WaDisableRCZUnitClockGating:hsw workaround.
  4061. */
  4062. I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
  4063. /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
  4064. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  4065. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  4066. /* WaApplyL3ControlAndL3ChickenMode:hsw */
  4067. I915_WRITE(GEN7_L3CNTLREG1,
  4068. GEN7_WA_FOR_GEN7_L3_CONTROL);
  4069. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  4070. GEN7_WA_L3_CHICKEN_MODE);
  4071. /* This is required by WaCatErrorRejectionIssue:hsw */
  4072. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  4073. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  4074. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  4075. g4x_disable_trickle_feed(dev);
  4076. /* WaVSRefCountFullforceMissDisable:hsw */
  4077. gen7_setup_fixed_func_scheduler(dev_priv);
  4078. /* WaDisable4x2SubspanOptimization:hsw */
  4079. I915_WRITE(CACHE_MODE_1,
  4080. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  4081. /* WaMbcDriverBootEnable:hsw */
  4082. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  4083. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  4084. /* WaSwitchSolVfFArbitrationPriority:hsw */
  4085. I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
  4086. /* WaRsPkgCStateDisplayPMReq:hsw */
  4087. I915_WRITE(CHICKEN_PAR1_1,
  4088. I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
  4089. lpt_init_clock_gating(dev);
  4090. }
  4091. static void ivybridge_init_clock_gating(struct drm_device *dev)
  4092. {
  4093. struct drm_i915_private *dev_priv = dev->dev_private;
  4094. uint32_t snpcr;
  4095. I915_WRITE(WM3_LP_ILK, 0);
  4096. I915_WRITE(WM2_LP_ILK, 0);
  4097. I915_WRITE(WM1_LP_ILK, 0);
  4098. I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
  4099. /* WaDisableEarlyCull:ivb */
  4100. I915_WRITE(_3D_CHICKEN3,
  4101. _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
  4102. /* WaDisableBackToBackFlipFix:ivb */
  4103. I915_WRITE(IVB_CHICKEN3,
  4104. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  4105. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  4106. /* WaDisablePSDDualDispatchEnable:ivb */
  4107. if (IS_IVB_GT1(dev))
  4108. I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
  4109. _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
  4110. else
  4111. I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
  4112. _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
  4113. /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
  4114. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  4115. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  4116. /* WaApplyL3ControlAndL3ChickenMode:ivb */
  4117. I915_WRITE(GEN7_L3CNTLREG1,
  4118. GEN7_WA_FOR_GEN7_L3_CONTROL);
  4119. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  4120. GEN7_WA_L3_CHICKEN_MODE);
  4121. if (IS_IVB_GT1(dev))
  4122. I915_WRITE(GEN7_ROW_CHICKEN2,
  4123. _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
  4124. else
  4125. I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
  4126. _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
  4127. /* WaForceL3Serialization:ivb */
  4128. I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
  4129. ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
  4130. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  4131. * gating disable must be set. Failure to set it results in
  4132. * flickering pixels due to Z write ordering failures after
  4133. * some amount of runtime in the Mesa "fire" demo, and Unigine
  4134. * Sanctuary and Tropics, and apparently anything else with
  4135. * alpha test or pixel discard.
  4136. *
  4137. * According to the spec, bit 11 (RCCUNIT) must also be set,
  4138. * but we didn't debug actual testcases to find it out.
  4139. *
  4140. * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  4141. * This implements the WaDisableRCZUnitClockGating:ivb workaround.
  4142. */
  4143. I915_WRITE(GEN6_UCGCTL2,
  4144. GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
  4145. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  4146. /* This is required by WaCatErrorRejectionIssue:ivb */
  4147. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  4148. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  4149. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  4150. g4x_disable_trickle_feed(dev);
  4151. /* WaMbcDriverBootEnable:ivb */
  4152. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  4153. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  4154. /* WaVSRefCountFullforceMissDisable:ivb */
  4155. gen7_setup_fixed_func_scheduler(dev_priv);
  4156. /* WaDisable4x2SubspanOptimization:ivb */
  4157. I915_WRITE(CACHE_MODE_1,
  4158. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  4159. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  4160. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  4161. snpcr |= GEN6_MBC_SNPCR_MED;
  4162. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  4163. if (!HAS_PCH_NOP(dev))
  4164. cpt_init_clock_gating(dev);
  4165. gen6_check_mch_setup(dev);
  4166. }
  4167. static void valleyview_init_clock_gating(struct drm_device *dev)
  4168. {
  4169. struct drm_i915_private *dev_priv = dev->dev_private;
  4170. I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
  4171. /* WaDisableEarlyCull:vlv */
  4172. I915_WRITE(_3D_CHICKEN3,
  4173. _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
  4174. /* WaDisableBackToBackFlipFix:vlv */
  4175. I915_WRITE(IVB_CHICKEN3,
  4176. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  4177. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  4178. /* WaDisablePSDDualDispatchEnable:vlv */
  4179. I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
  4180. _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
  4181. GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
  4182. /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
  4183. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  4184. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  4185. /* WaApplyL3ControlAndL3ChickenMode:vlv */
  4186. I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
  4187. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
  4188. /* WaForceL3Serialization:vlv */
  4189. I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
  4190. ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
  4191. /* WaDisableDopClockGating:vlv */
  4192. I915_WRITE(GEN7_ROW_CHICKEN2,
  4193. _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
  4194. /* This is required by WaCatErrorRejectionIssue:vlv */
  4195. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  4196. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  4197. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  4198. /* WaMbcDriverBootEnable:vlv */
  4199. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  4200. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  4201. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  4202. * gating disable must be set. Failure to set it results in
  4203. * flickering pixels due to Z write ordering failures after
  4204. * some amount of runtime in the Mesa "fire" demo, and Unigine
  4205. * Sanctuary and Tropics, and apparently anything else with
  4206. * alpha test or pixel discard.
  4207. *
  4208. * According to the spec, bit 11 (RCCUNIT) must also be set,
  4209. * but we didn't debug actual testcases to find it out.
  4210. *
  4211. * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  4212. * This implements the WaDisableRCZUnitClockGating:vlv workaround.
  4213. *
  4214. * Also apply WaDisableVDSUnitClockGating:vlv and
  4215. * WaDisableRCPBUnitClockGating:vlv.
  4216. */
  4217. I915_WRITE(GEN6_UCGCTL2,
  4218. GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
  4219. GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
  4220. GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
  4221. GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  4222. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  4223. I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
  4224. I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
  4225. I915_WRITE(CACHE_MODE_1,
  4226. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  4227. /*
  4228. * WaDisableVLVClockGating_VBIIssue:vlv
  4229. * Disable clock gating on th GCFG unit to prevent a delay
  4230. * in the reporting of vblank events.
  4231. */
  4232. I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
  4233. /* Conservative clock gating settings for now */
  4234. I915_WRITE(0x9400, 0xffffffff);
  4235. I915_WRITE(0x9404, 0xffffffff);
  4236. I915_WRITE(0x9408, 0xffffffff);
  4237. I915_WRITE(0x940c, 0xffffffff);
  4238. I915_WRITE(0x9410, 0xffffffff);
  4239. I915_WRITE(0x9414, 0xffffffff);
  4240. I915_WRITE(0x9418, 0xffffffff);
  4241. }
  4242. static void g4x_init_clock_gating(struct drm_device *dev)
  4243. {
  4244. struct drm_i915_private *dev_priv = dev->dev_private;
  4245. uint32_t dspclk_gate;
  4246. I915_WRITE(RENCLK_GATE_D1, 0);
  4247. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  4248. GS_UNIT_CLOCK_GATE_DISABLE |
  4249. CL_UNIT_CLOCK_GATE_DISABLE);
  4250. I915_WRITE(RAMCLK_GATE_D, 0);
  4251. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  4252. OVRUNIT_CLOCK_GATE_DISABLE |
  4253. OVCUNIT_CLOCK_GATE_DISABLE;
  4254. if (IS_GM45(dev))
  4255. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  4256. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  4257. /* WaDisableRenderCachePipelinedFlush */
  4258. I915_WRITE(CACHE_MODE_0,
  4259. _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
  4260. g4x_disable_trickle_feed(dev);
  4261. }
  4262. static void crestline_init_clock_gating(struct drm_device *dev)
  4263. {
  4264. struct drm_i915_private *dev_priv = dev->dev_private;
  4265. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  4266. I915_WRITE(RENCLK_GATE_D2, 0);
  4267. I915_WRITE(DSPCLK_GATE_D, 0);
  4268. I915_WRITE(RAMCLK_GATE_D, 0);
  4269. I915_WRITE16(DEUC, 0);
  4270. I915_WRITE(MI_ARB_STATE,
  4271. _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
  4272. }
  4273. static void broadwater_init_clock_gating(struct drm_device *dev)
  4274. {
  4275. struct drm_i915_private *dev_priv = dev->dev_private;
  4276. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  4277. I965_RCC_CLOCK_GATE_DISABLE |
  4278. I965_RCPB_CLOCK_GATE_DISABLE |
  4279. I965_ISC_CLOCK_GATE_DISABLE |
  4280. I965_FBC_CLOCK_GATE_DISABLE);
  4281. I915_WRITE(RENCLK_GATE_D2, 0);
  4282. I915_WRITE(MI_ARB_STATE,
  4283. _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
  4284. }
  4285. static void gen3_init_clock_gating(struct drm_device *dev)
  4286. {
  4287. struct drm_i915_private *dev_priv = dev->dev_private;
  4288. u32 dstate = I915_READ(D_STATE);
  4289. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  4290. DSTATE_DOT_CLOCK_GATING;
  4291. I915_WRITE(D_STATE, dstate);
  4292. if (IS_PINEVIEW(dev))
  4293. I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
  4294. /* IIR "flip pending" means done if this bit is set */
  4295. I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
  4296. }
  4297. static void i85x_init_clock_gating(struct drm_device *dev)
  4298. {
  4299. struct drm_i915_private *dev_priv = dev->dev_private;
  4300. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  4301. }
  4302. static void i830_init_clock_gating(struct drm_device *dev)
  4303. {
  4304. struct drm_i915_private *dev_priv = dev->dev_private;
  4305. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  4306. }
  4307. void intel_init_clock_gating(struct drm_device *dev)
  4308. {
  4309. struct drm_i915_private *dev_priv = dev->dev_private;
  4310. dev_priv->display.init_clock_gating(dev);
  4311. }
  4312. void intel_suspend_hw(struct drm_device *dev)
  4313. {
  4314. if (HAS_PCH_LPT(dev))
  4315. lpt_suspend_hw(dev);
  4316. }
  4317. /**
  4318. * We should only use the power well if we explicitly asked the hardware to
  4319. * enable it, so check if it's enabled and also check if we've requested it to
  4320. * be enabled.
  4321. */
  4322. bool intel_display_power_enabled(struct drm_device *dev,
  4323. enum intel_display_power_domain domain)
  4324. {
  4325. struct drm_i915_private *dev_priv = dev->dev_private;
  4326. if (!HAS_POWER_WELL(dev))
  4327. return true;
  4328. switch (domain) {
  4329. case POWER_DOMAIN_PIPE_A:
  4330. case POWER_DOMAIN_TRANSCODER_EDP:
  4331. return true;
  4332. case POWER_DOMAIN_PIPE_B:
  4333. case POWER_DOMAIN_PIPE_C:
  4334. case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  4335. case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  4336. case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  4337. case POWER_DOMAIN_TRANSCODER_A:
  4338. case POWER_DOMAIN_TRANSCODER_B:
  4339. case POWER_DOMAIN_TRANSCODER_C:
  4340. return I915_READ(HSW_PWR_WELL_DRIVER) ==
  4341. (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
  4342. default:
  4343. BUG();
  4344. }
  4345. }
  4346. static void __intel_set_power_well(struct drm_device *dev, bool enable)
  4347. {
  4348. struct drm_i915_private *dev_priv = dev->dev_private;
  4349. bool is_enabled, enable_requested;
  4350. uint32_t tmp;
  4351. tmp = I915_READ(HSW_PWR_WELL_DRIVER);
  4352. is_enabled = tmp & HSW_PWR_WELL_STATE;
  4353. enable_requested = tmp & HSW_PWR_WELL_ENABLE;
  4354. if (enable) {
  4355. if (!enable_requested)
  4356. I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
  4357. if (!is_enabled) {
  4358. DRM_DEBUG_KMS("Enabling power well\n");
  4359. if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
  4360. HSW_PWR_WELL_STATE), 20))
  4361. DRM_ERROR("Timeout enabling power well\n");
  4362. }
  4363. } else {
  4364. if (enable_requested) {
  4365. I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
  4366. DRM_DEBUG_KMS("Requesting to disable the power well\n");
  4367. }
  4368. }
  4369. }
  4370. static struct i915_power_well *hsw_pwr;
  4371. /* Display audio driver power well request */
  4372. void i915_request_power_well(void)
  4373. {
  4374. if (WARN_ON(!hsw_pwr))
  4375. return;
  4376. spin_lock_irq(&hsw_pwr->lock);
  4377. if (!hsw_pwr->count++ &&
  4378. !hsw_pwr->i915_request)
  4379. __intel_set_power_well(hsw_pwr->device, true);
  4380. spin_unlock_irq(&hsw_pwr->lock);
  4381. }
  4382. EXPORT_SYMBOL_GPL(i915_request_power_well);
  4383. /* Display audio driver power well release */
  4384. void i915_release_power_well(void)
  4385. {
  4386. if (WARN_ON(!hsw_pwr))
  4387. return;
  4388. spin_lock_irq(&hsw_pwr->lock);
  4389. WARN_ON(!hsw_pwr->count);
  4390. if (!--hsw_pwr->count &&
  4391. !hsw_pwr->i915_request)
  4392. __intel_set_power_well(hsw_pwr->device, false);
  4393. spin_unlock_irq(&hsw_pwr->lock);
  4394. }
  4395. EXPORT_SYMBOL_GPL(i915_release_power_well);
  4396. int i915_init_power_well(struct drm_device *dev)
  4397. {
  4398. struct drm_i915_private *dev_priv = dev->dev_private;
  4399. hsw_pwr = &dev_priv->power_well;
  4400. hsw_pwr->device = dev;
  4401. spin_lock_init(&hsw_pwr->lock);
  4402. hsw_pwr->count = 0;
  4403. return 0;
  4404. }
  4405. void i915_remove_power_well(struct drm_device *dev)
  4406. {
  4407. hsw_pwr = NULL;
  4408. }
  4409. void intel_set_power_well(struct drm_device *dev, bool enable)
  4410. {
  4411. struct drm_i915_private *dev_priv = dev->dev_private;
  4412. struct i915_power_well *power_well = &dev_priv->power_well;
  4413. if (!HAS_POWER_WELL(dev))
  4414. return;
  4415. if (!i915_disable_power_well && !enable)
  4416. return;
  4417. spin_lock_irq(&power_well->lock);
  4418. power_well->i915_request = enable;
  4419. /* only reject "disable" power well request */
  4420. if (power_well->count && !enable) {
  4421. spin_unlock_irq(&power_well->lock);
  4422. return;
  4423. }
  4424. __intel_set_power_well(dev, enable);
  4425. spin_unlock_irq(&power_well->lock);
  4426. }
  4427. /*
  4428. * Starting with Haswell, we have a "Power Down Well" that can be turned off
  4429. * when not needed anymore. We have 4 registers that can request the power well
  4430. * to be enabled, and it will only be disabled if none of the registers is
  4431. * requesting it to be enabled.
  4432. */
  4433. void intel_init_power_well(struct drm_device *dev)
  4434. {
  4435. struct drm_i915_private *dev_priv = dev->dev_private;
  4436. if (!HAS_POWER_WELL(dev))
  4437. return;
  4438. /* For now, we need the power well to be always enabled. */
  4439. intel_set_power_well(dev, true);
  4440. /* We're taking over the BIOS, so clear any requests made by it since
  4441. * the driver is in charge now. */
  4442. if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
  4443. I915_WRITE(HSW_PWR_WELL_BIOS, 0);
  4444. }
  4445. /* Set up chip specific power management-related functions */
  4446. void intel_init_pm(struct drm_device *dev)
  4447. {
  4448. struct drm_i915_private *dev_priv = dev->dev_private;
  4449. if (I915_HAS_FBC(dev)) {
  4450. if (HAS_PCH_SPLIT(dev)) {
  4451. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  4452. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  4453. dev_priv->display.enable_fbc =
  4454. gen7_enable_fbc;
  4455. else
  4456. dev_priv->display.enable_fbc =
  4457. ironlake_enable_fbc;
  4458. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  4459. } else if (IS_GM45(dev)) {
  4460. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  4461. dev_priv->display.enable_fbc = g4x_enable_fbc;
  4462. dev_priv->display.disable_fbc = g4x_disable_fbc;
  4463. } else if (IS_CRESTLINE(dev)) {
  4464. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  4465. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  4466. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  4467. }
  4468. /* 855GM needs testing */
  4469. }
  4470. /* For cxsr */
  4471. if (IS_PINEVIEW(dev))
  4472. i915_pineview_get_mem_freq(dev);
  4473. else if (IS_GEN5(dev))
  4474. i915_ironlake_get_mem_freq(dev);
  4475. /* For FIFO watermark updates */
  4476. if (HAS_PCH_SPLIT(dev)) {
  4477. intel_setup_wm_latency(dev);
  4478. if (IS_GEN5(dev)) {
  4479. if (dev_priv->wm.pri_latency[1] &&
  4480. dev_priv->wm.spr_latency[1] &&
  4481. dev_priv->wm.cur_latency[1])
  4482. dev_priv->display.update_wm = ironlake_update_wm;
  4483. else {
  4484. DRM_DEBUG_KMS("Failed to get proper latency. "
  4485. "Disable CxSR\n");
  4486. dev_priv->display.update_wm = NULL;
  4487. }
  4488. dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
  4489. } else if (IS_GEN6(dev)) {
  4490. if (dev_priv->wm.pri_latency[0] &&
  4491. dev_priv->wm.spr_latency[0] &&
  4492. dev_priv->wm.cur_latency[0]) {
  4493. dev_priv->display.update_wm = sandybridge_update_wm;
  4494. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  4495. } else {
  4496. DRM_DEBUG_KMS("Failed to read display plane latency. "
  4497. "Disable CxSR\n");
  4498. dev_priv->display.update_wm = NULL;
  4499. }
  4500. dev_priv->display.init_clock_gating = gen6_init_clock_gating;
  4501. } else if (IS_IVYBRIDGE(dev)) {
  4502. if (dev_priv->wm.pri_latency[0] &&
  4503. dev_priv->wm.spr_latency[0] &&
  4504. dev_priv->wm.cur_latency[0]) {
  4505. dev_priv->display.update_wm = ivybridge_update_wm;
  4506. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  4507. } else {
  4508. DRM_DEBUG_KMS("Failed to read display plane latency. "
  4509. "Disable CxSR\n");
  4510. dev_priv->display.update_wm = NULL;
  4511. }
  4512. dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
  4513. } else if (IS_HASWELL(dev)) {
  4514. if (dev_priv->wm.pri_latency[0] &&
  4515. dev_priv->wm.spr_latency[0] &&
  4516. dev_priv->wm.cur_latency[0]) {
  4517. dev_priv->display.update_wm = haswell_update_wm;
  4518. dev_priv->display.update_sprite_wm =
  4519. haswell_update_sprite_wm;
  4520. } else {
  4521. DRM_DEBUG_KMS("Failed to read display plane latency. "
  4522. "Disable CxSR\n");
  4523. dev_priv->display.update_wm = NULL;
  4524. }
  4525. dev_priv->display.init_clock_gating = haswell_init_clock_gating;
  4526. } else
  4527. dev_priv->display.update_wm = NULL;
  4528. } else if (IS_VALLEYVIEW(dev)) {
  4529. dev_priv->display.update_wm = valleyview_update_wm;
  4530. dev_priv->display.init_clock_gating =
  4531. valleyview_init_clock_gating;
  4532. } else if (IS_PINEVIEW(dev)) {
  4533. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  4534. dev_priv->is_ddr3,
  4535. dev_priv->fsb_freq,
  4536. dev_priv->mem_freq)) {
  4537. DRM_INFO("failed to find known CxSR latency "
  4538. "(found ddr%s fsb freq %d, mem freq %d), "
  4539. "disabling CxSR\n",
  4540. (dev_priv->is_ddr3 == 1) ? "3" : "2",
  4541. dev_priv->fsb_freq, dev_priv->mem_freq);
  4542. /* Disable CxSR and never update its watermark again */
  4543. pineview_disable_cxsr(dev);
  4544. dev_priv->display.update_wm = NULL;
  4545. } else
  4546. dev_priv->display.update_wm = pineview_update_wm;
  4547. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  4548. } else if (IS_G4X(dev)) {
  4549. dev_priv->display.update_wm = g4x_update_wm;
  4550. dev_priv->display.init_clock_gating = g4x_init_clock_gating;
  4551. } else if (IS_GEN4(dev)) {
  4552. dev_priv->display.update_wm = i965_update_wm;
  4553. if (IS_CRESTLINE(dev))
  4554. dev_priv->display.init_clock_gating = crestline_init_clock_gating;
  4555. else if (IS_BROADWATER(dev))
  4556. dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
  4557. } else if (IS_GEN3(dev)) {
  4558. dev_priv->display.update_wm = i9xx_update_wm;
  4559. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  4560. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  4561. } else if (IS_I865G(dev)) {
  4562. dev_priv->display.update_wm = i830_update_wm;
  4563. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  4564. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  4565. } else if (IS_I85X(dev)) {
  4566. dev_priv->display.update_wm = i9xx_update_wm;
  4567. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  4568. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  4569. } else {
  4570. dev_priv->display.update_wm = i830_update_wm;
  4571. dev_priv->display.init_clock_gating = i830_init_clock_gating;
  4572. if (IS_845G(dev))
  4573. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  4574. else
  4575. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  4576. }
  4577. }
  4578. int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
  4579. {
  4580. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  4581. if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
  4582. DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
  4583. return -EAGAIN;
  4584. }
  4585. I915_WRITE(GEN6_PCODE_DATA, *val);
  4586. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
  4587. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  4588. 500)) {
  4589. DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
  4590. return -ETIMEDOUT;
  4591. }
  4592. *val = I915_READ(GEN6_PCODE_DATA);
  4593. I915_WRITE(GEN6_PCODE_DATA, 0);
  4594. return 0;
  4595. }
  4596. int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
  4597. {
  4598. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  4599. if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
  4600. DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
  4601. return -EAGAIN;
  4602. }
  4603. I915_WRITE(GEN6_PCODE_DATA, val);
  4604. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
  4605. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  4606. 500)) {
  4607. DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
  4608. return -ETIMEDOUT;
  4609. }
  4610. I915_WRITE(GEN6_PCODE_DATA, 0);
  4611. return 0;
  4612. }
  4613. int vlv_gpu_freq(int ddr_freq, int val)
  4614. {
  4615. int mult, base;
  4616. switch (ddr_freq) {
  4617. case 800:
  4618. mult = 20;
  4619. base = 120;
  4620. break;
  4621. case 1066:
  4622. mult = 22;
  4623. base = 133;
  4624. break;
  4625. case 1333:
  4626. mult = 21;
  4627. base = 125;
  4628. break;
  4629. default:
  4630. return -1;
  4631. }
  4632. return ((val - 0xbd) * mult) + base;
  4633. }
  4634. int vlv_freq_opcode(int ddr_freq, int val)
  4635. {
  4636. int mult, base;
  4637. switch (ddr_freq) {
  4638. case 800:
  4639. mult = 20;
  4640. base = 120;
  4641. break;
  4642. case 1066:
  4643. mult = 22;
  4644. base = 133;
  4645. break;
  4646. case 1333:
  4647. mult = 21;
  4648. base = 125;
  4649. break;
  4650. default:
  4651. return -1;
  4652. }
  4653. val /= mult;
  4654. val -= base / mult;
  4655. val += 0xbd;
  4656. if (val > 0xea)
  4657. val = 0xea;
  4658. return val;
  4659. }
  4660. void intel_pm_init(struct drm_device *dev)
  4661. {
  4662. struct drm_i915_private *dev_priv = dev->dev_private;
  4663. INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
  4664. intel_gen6_powersave_work);
  4665. }