i8259.c 12 KB

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  1. /*
  2. * 8259 interrupt controller emulation
  3. *
  4. * Copyright (c) 2003-2004 Fabrice Bellard
  5. * Copyright (c) 2007 Intel Corporation
  6. * Copyright 2009 Red Hat, Inc. and/or its affilates.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice shall be included in
  16. * all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. * Authors:
  26. * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  27. * Port from Qemu.
  28. */
  29. #include <linux/mm.h>
  30. #include <linux/slab.h>
  31. #include <linux/bitops.h>
  32. #include "irq.h"
  33. #include <linux/kvm_host.h>
  34. #include "trace.h"
  35. static void pic_irq_request(struct kvm *kvm, int level);
  36. static void pic_lock(struct kvm_pic *s)
  37. __acquires(&s->lock)
  38. {
  39. raw_spin_lock(&s->lock);
  40. }
  41. static void pic_unlock(struct kvm_pic *s)
  42. __releases(&s->lock)
  43. {
  44. bool wakeup = s->wakeup_needed;
  45. struct kvm_vcpu *vcpu;
  46. s->wakeup_needed = false;
  47. raw_spin_unlock(&s->lock);
  48. if (wakeup) {
  49. vcpu = s->kvm->bsp_vcpu;
  50. if (vcpu)
  51. kvm_vcpu_kick(vcpu);
  52. }
  53. }
  54. static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  55. {
  56. s->isr &= ~(1 << irq);
  57. s->isr_ack |= (1 << irq);
  58. if (s != &s->pics_state->pics[0])
  59. irq += 8;
  60. /*
  61. * We are dropping lock while calling ack notifiers since ack
  62. * notifier callbacks for assigned devices call into PIC recursively.
  63. * Other interrupt may be delivered to PIC while lock is dropped but
  64. * it should be safe since PIC state is already updated at this stage.
  65. */
  66. pic_unlock(s->pics_state);
  67. kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
  68. pic_lock(s->pics_state);
  69. }
  70. void kvm_pic_clear_isr_ack(struct kvm *kvm)
  71. {
  72. struct kvm_pic *s = pic_irqchip(kvm);
  73. pic_lock(s);
  74. s->pics[0].isr_ack = 0xff;
  75. s->pics[1].isr_ack = 0xff;
  76. pic_unlock(s);
  77. }
  78. /*
  79. * set irq level. If an edge is detected, then the IRR is set to 1
  80. */
  81. static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  82. {
  83. int mask, ret = 1;
  84. mask = 1 << irq;
  85. if (s->elcr & mask) /* level triggered */
  86. if (level) {
  87. ret = !(s->irr & mask);
  88. s->irr |= mask;
  89. s->last_irr |= mask;
  90. } else {
  91. s->irr &= ~mask;
  92. s->last_irr &= ~mask;
  93. }
  94. else /* edge triggered */
  95. if (level) {
  96. if ((s->last_irr & mask) == 0) {
  97. ret = !(s->irr & mask);
  98. s->irr |= mask;
  99. }
  100. s->last_irr |= mask;
  101. } else
  102. s->last_irr &= ~mask;
  103. return (s->imr & mask) ? -1 : ret;
  104. }
  105. /*
  106. * return the highest priority found in mask (highest = smallest
  107. * number). Return 8 if no irq
  108. */
  109. static inline int get_priority(struct kvm_kpic_state *s, int mask)
  110. {
  111. int priority;
  112. if (mask == 0)
  113. return 8;
  114. priority = 0;
  115. while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  116. priority++;
  117. return priority;
  118. }
  119. /*
  120. * return the pic wanted interrupt. return -1 if none
  121. */
  122. static int pic_get_irq(struct kvm_kpic_state *s)
  123. {
  124. int mask, cur_priority, priority;
  125. mask = s->irr & ~s->imr;
  126. priority = get_priority(s, mask);
  127. if (priority == 8)
  128. return -1;
  129. /*
  130. * compute current priority. If special fully nested mode on the
  131. * master, the IRQ coming from the slave is not taken into account
  132. * for the priority computation.
  133. */
  134. mask = s->isr;
  135. if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
  136. mask &= ~(1 << 2);
  137. cur_priority = get_priority(s, mask);
  138. if (priority < cur_priority)
  139. /*
  140. * higher priority found: an irq should be generated
  141. */
  142. return (priority + s->priority_add) & 7;
  143. else
  144. return -1;
  145. }
  146. /*
  147. * raise irq to CPU if necessary. must be called every time the active
  148. * irq may change
  149. */
  150. static void pic_update_irq(struct kvm_pic *s)
  151. {
  152. int irq2, irq;
  153. irq2 = pic_get_irq(&s->pics[1]);
  154. if (irq2 >= 0) {
  155. /*
  156. * if irq request by slave pic, signal master PIC
  157. */
  158. pic_set_irq1(&s->pics[0], 2, 1);
  159. pic_set_irq1(&s->pics[0], 2, 0);
  160. }
  161. irq = pic_get_irq(&s->pics[0]);
  162. pic_irq_request(s->kvm, irq >= 0);
  163. }
  164. void kvm_pic_update_irq(struct kvm_pic *s)
  165. {
  166. pic_lock(s);
  167. pic_update_irq(s);
  168. pic_unlock(s);
  169. }
  170. int kvm_pic_set_irq(void *opaque, int irq, int level)
  171. {
  172. struct kvm_pic *s = opaque;
  173. int ret = -1;
  174. pic_lock(s);
  175. if (irq >= 0 && irq < PIC_NUM_PINS) {
  176. ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
  177. pic_update_irq(s);
  178. trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
  179. s->pics[irq >> 3].imr, ret == 0);
  180. }
  181. pic_unlock(s);
  182. return ret;
  183. }
  184. /*
  185. * acknowledge interrupt 'irq'
  186. */
  187. static inline void pic_intack(struct kvm_kpic_state *s, int irq)
  188. {
  189. s->isr |= 1 << irq;
  190. /*
  191. * We don't clear a level sensitive interrupt here
  192. */
  193. if (!(s->elcr & (1 << irq)))
  194. s->irr &= ~(1 << irq);
  195. if (s->auto_eoi) {
  196. if (s->rotate_on_auto_eoi)
  197. s->priority_add = (irq + 1) & 7;
  198. pic_clear_isr(s, irq);
  199. }
  200. }
  201. int kvm_pic_read_irq(struct kvm *kvm)
  202. {
  203. int irq, irq2, intno;
  204. struct kvm_pic *s = pic_irqchip(kvm);
  205. pic_lock(s);
  206. irq = pic_get_irq(&s->pics[0]);
  207. if (irq >= 0) {
  208. pic_intack(&s->pics[0], irq);
  209. if (irq == 2) {
  210. irq2 = pic_get_irq(&s->pics[1]);
  211. if (irq2 >= 0)
  212. pic_intack(&s->pics[1], irq2);
  213. else
  214. /*
  215. * spurious IRQ on slave controller
  216. */
  217. irq2 = 7;
  218. intno = s->pics[1].irq_base + irq2;
  219. irq = irq2 + 8;
  220. } else
  221. intno = s->pics[0].irq_base + irq;
  222. } else {
  223. /*
  224. * spurious IRQ on host controller
  225. */
  226. irq = 7;
  227. intno = s->pics[0].irq_base + irq;
  228. }
  229. pic_update_irq(s);
  230. pic_unlock(s);
  231. return intno;
  232. }
  233. void kvm_pic_reset(struct kvm_kpic_state *s)
  234. {
  235. int irq;
  236. struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
  237. u8 irr = s->irr, isr = s->imr;
  238. s->last_irr = 0;
  239. s->irr = 0;
  240. s->imr = 0;
  241. s->isr = 0;
  242. s->isr_ack = 0xff;
  243. s->priority_add = 0;
  244. s->irq_base = 0;
  245. s->read_reg_select = 0;
  246. s->poll = 0;
  247. s->special_mask = 0;
  248. s->init_state = 0;
  249. s->auto_eoi = 0;
  250. s->rotate_on_auto_eoi = 0;
  251. s->special_fully_nested_mode = 0;
  252. s->init4 = 0;
  253. for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
  254. if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
  255. if (irr & (1 << irq) || isr & (1 << irq)) {
  256. pic_clear_isr(s, irq);
  257. }
  258. }
  259. }
  260. static void pic_ioport_write(void *opaque, u32 addr, u32 val)
  261. {
  262. struct kvm_kpic_state *s = opaque;
  263. int priority, cmd, irq;
  264. addr &= 1;
  265. if (addr == 0) {
  266. if (val & 0x10) {
  267. kvm_pic_reset(s); /* init */
  268. /*
  269. * deassert a pending interrupt
  270. */
  271. pic_irq_request(s->pics_state->kvm, 0);
  272. s->init_state = 1;
  273. s->init4 = val & 1;
  274. if (val & 0x02)
  275. printk(KERN_ERR "single mode not supported");
  276. if (val & 0x08)
  277. printk(KERN_ERR
  278. "level sensitive irq not supported");
  279. } else if (val & 0x08) {
  280. if (val & 0x04)
  281. s->poll = 1;
  282. if (val & 0x02)
  283. s->read_reg_select = val & 1;
  284. if (val & 0x40)
  285. s->special_mask = (val >> 5) & 1;
  286. } else {
  287. cmd = val >> 5;
  288. switch (cmd) {
  289. case 0:
  290. case 4:
  291. s->rotate_on_auto_eoi = cmd >> 2;
  292. break;
  293. case 1: /* end of interrupt */
  294. case 5:
  295. priority = get_priority(s, s->isr);
  296. if (priority != 8) {
  297. irq = (priority + s->priority_add) & 7;
  298. if (cmd == 5)
  299. s->priority_add = (irq + 1) & 7;
  300. pic_clear_isr(s, irq);
  301. pic_update_irq(s->pics_state);
  302. }
  303. break;
  304. case 3:
  305. irq = val & 7;
  306. pic_clear_isr(s, irq);
  307. pic_update_irq(s->pics_state);
  308. break;
  309. case 6:
  310. s->priority_add = (val + 1) & 7;
  311. pic_update_irq(s->pics_state);
  312. break;
  313. case 7:
  314. irq = val & 7;
  315. s->priority_add = (irq + 1) & 7;
  316. pic_clear_isr(s, irq);
  317. pic_update_irq(s->pics_state);
  318. break;
  319. default:
  320. break; /* no operation */
  321. }
  322. }
  323. } else
  324. switch (s->init_state) {
  325. case 0: /* normal mode */
  326. s->imr = val;
  327. pic_update_irq(s->pics_state);
  328. break;
  329. case 1:
  330. s->irq_base = val & 0xf8;
  331. s->init_state = 2;
  332. break;
  333. case 2:
  334. if (s->init4)
  335. s->init_state = 3;
  336. else
  337. s->init_state = 0;
  338. break;
  339. case 3:
  340. s->special_fully_nested_mode = (val >> 4) & 1;
  341. s->auto_eoi = (val >> 1) & 1;
  342. s->init_state = 0;
  343. break;
  344. }
  345. }
  346. static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
  347. {
  348. int ret;
  349. ret = pic_get_irq(s);
  350. if (ret >= 0) {
  351. if (addr1 >> 7) {
  352. s->pics_state->pics[0].isr &= ~(1 << 2);
  353. s->pics_state->pics[0].irr &= ~(1 << 2);
  354. }
  355. s->irr &= ~(1 << ret);
  356. pic_clear_isr(s, ret);
  357. if (addr1 >> 7 || ret != 2)
  358. pic_update_irq(s->pics_state);
  359. } else {
  360. ret = 0x07;
  361. pic_update_irq(s->pics_state);
  362. }
  363. return ret;
  364. }
  365. static u32 pic_ioport_read(void *opaque, u32 addr1)
  366. {
  367. struct kvm_kpic_state *s = opaque;
  368. unsigned int addr;
  369. int ret;
  370. addr = addr1;
  371. addr &= 1;
  372. if (s->poll) {
  373. ret = pic_poll_read(s, addr1);
  374. s->poll = 0;
  375. } else
  376. if (addr == 0)
  377. if (s->read_reg_select)
  378. ret = s->isr;
  379. else
  380. ret = s->irr;
  381. else
  382. ret = s->imr;
  383. return ret;
  384. }
  385. static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
  386. {
  387. struct kvm_kpic_state *s = opaque;
  388. s->elcr = val & s->elcr_mask;
  389. }
  390. static u32 elcr_ioport_read(void *opaque, u32 addr1)
  391. {
  392. struct kvm_kpic_state *s = opaque;
  393. return s->elcr;
  394. }
  395. static int picdev_in_range(gpa_t addr)
  396. {
  397. switch (addr) {
  398. case 0x20:
  399. case 0x21:
  400. case 0xa0:
  401. case 0xa1:
  402. case 0x4d0:
  403. case 0x4d1:
  404. return 1;
  405. default:
  406. return 0;
  407. }
  408. }
  409. static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
  410. {
  411. return container_of(dev, struct kvm_pic, dev);
  412. }
  413. static int picdev_write(struct kvm_io_device *this,
  414. gpa_t addr, int len, const void *val)
  415. {
  416. struct kvm_pic *s = to_pic(this);
  417. unsigned char data = *(unsigned char *)val;
  418. if (!picdev_in_range(addr))
  419. return -EOPNOTSUPP;
  420. if (len != 1) {
  421. if (printk_ratelimit())
  422. printk(KERN_ERR "PIC: non byte write\n");
  423. return 0;
  424. }
  425. pic_lock(s);
  426. switch (addr) {
  427. case 0x20:
  428. case 0x21:
  429. case 0xa0:
  430. case 0xa1:
  431. pic_ioport_write(&s->pics[addr >> 7], addr, data);
  432. break;
  433. case 0x4d0:
  434. case 0x4d1:
  435. elcr_ioport_write(&s->pics[addr & 1], addr, data);
  436. break;
  437. }
  438. pic_unlock(s);
  439. return 0;
  440. }
  441. static int picdev_read(struct kvm_io_device *this,
  442. gpa_t addr, int len, void *val)
  443. {
  444. struct kvm_pic *s = to_pic(this);
  445. unsigned char data = 0;
  446. if (!picdev_in_range(addr))
  447. return -EOPNOTSUPP;
  448. if (len != 1) {
  449. if (printk_ratelimit())
  450. printk(KERN_ERR "PIC: non byte read\n");
  451. return 0;
  452. }
  453. pic_lock(s);
  454. switch (addr) {
  455. case 0x20:
  456. case 0x21:
  457. case 0xa0:
  458. case 0xa1:
  459. data = pic_ioport_read(&s->pics[addr >> 7], addr);
  460. break;
  461. case 0x4d0:
  462. case 0x4d1:
  463. data = elcr_ioport_read(&s->pics[addr & 1], addr);
  464. break;
  465. }
  466. *(unsigned char *)val = data;
  467. pic_unlock(s);
  468. return 0;
  469. }
  470. /*
  471. * callback when PIC0 irq status changed
  472. */
  473. static void pic_irq_request(struct kvm *kvm, int level)
  474. {
  475. struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
  476. struct kvm_pic *s = pic_irqchip(kvm);
  477. int irq = pic_get_irq(&s->pics[0]);
  478. s->output = level;
  479. if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
  480. s->pics[0].isr_ack &= ~(1 << irq);
  481. s->wakeup_needed = true;
  482. }
  483. }
  484. static const struct kvm_io_device_ops picdev_ops = {
  485. .read = picdev_read,
  486. .write = picdev_write,
  487. };
  488. struct kvm_pic *kvm_create_pic(struct kvm *kvm)
  489. {
  490. struct kvm_pic *s;
  491. int ret;
  492. s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
  493. if (!s)
  494. return NULL;
  495. raw_spin_lock_init(&s->lock);
  496. s->kvm = kvm;
  497. s->pics[0].elcr_mask = 0xf8;
  498. s->pics[1].elcr_mask = 0xde;
  499. s->pics[0].pics_state = s;
  500. s->pics[1].pics_state = s;
  501. /*
  502. * Initialize PIO device
  503. */
  504. kvm_iodevice_init(&s->dev, &picdev_ops);
  505. mutex_lock(&kvm->slots_lock);
  506. ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
  507. mutex_unlock(&kvm->slots_lock);
  508. if (ret < 0) {
  509. kfree(s);
  510. return NULL;
  511. }
  512. return s;
  513. }
  514. void kvm_destroy_pic(struct kvm *kvm)
  515. {
  516. struct kvm_pic *vpic = kvm->arch.vpic;
  517. if (vpic) {
  518. kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
  519. kvm->arch.vpic = NULL;
  520. kfree(vpic);
  521. }
  522. }