iwl-4965.c 104 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-eeprom.h"
  40. #include "iwl-dev.h"
  41. #include "iwl-core.h"
  42. #include "iwl-io.h"
  43. #include "iwl-helpers.h"
  44. #include "iwl-calib.h"
  45. /* module parameters */
  46. static struct iwl_mod_params iwl4965_mod_params = {
  47. .num_of_queues = IWL49_NUM_QUEUES,
  48. .enable_qos = 1,
  49. .amsdu_size_8K = 1,
  50. .restart_fw = 1,
  51. /* the rest are 0 by default */
  52. };
  53. #ifdef CONFIG_IWL4965_HT
  54. static const u16 default_tid_to_tx_fifo[] = {
  55. IWL_TX_FIFO_AC1,
  56. IWL_TX_FIFO_AC0,
  57. IWL_TX_FIFO_AC0,
  58. IWL_TX_FIFO_AC1,
  59. IWL_TX_FIFO_AC2,
  60. IWL_TX_FIFO_AC2,
  61. IWL_TX_FIFO_AC3,
  62. IWL_TX_FIFO_AC3,
  63. IWL_TX_FIFO_NONE,
  64. IWL_TX_FIFO_NONE,
  65. IWL_TX_FIFO_NONE,
  66. IWL_TX_FIFO_NONE,
  67. IWL_TX_FIFO_NONE,
  68. IWL_TX_FIFO_NONE,
  69. IWL_TX_FIFO_NONE,
  70. IWL_TX_FIFO_NONE,
  71. IWL_TX_FIFO_AC3
  72. };
  73. #endif /*CONFIG_IWL4965_HT */
  74. /* check contents of special bootstrap uCode SRAM */
  75. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  76. {
  77. __le32 *image = priv->ucode_boot.v_addr;
  78. u32 len = priv->ucode_boot.len;
  79. u32 reg;
  80. u32 val;
  81. IWL_DEBUG_INFO("Begin verify bsm\n");
  82. /* verify BSM SRAM contents */
  83. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  84. for (reg = BSM_SRAM_LOWER_BOUND;
  85. reg < BSM_SRAM_LOWER_BOUND + len;
  86. reg += sizeof(u32), image++) {
  87. val = iwl_read_prph(priv, reg);
  88. if (val != le32_to_cpu(*image)) {
  89. IWL_ERROR("BSM uCode verification failed at "
  90. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  91. BSM_SRAM_LOWER_BOUND,
  92. reg - BSM_SRAM_LOWER_BOUND, len,
  93. val, le32_to_cpu(*image));
  94. return -EIO;
  95. }
  96. }
  97. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  98. return 0;
  99. }
  100. /**
  101. * iwl4965_load_bsm - Load bootstrap instructions
  102. *
  103. * BSM operation:
  104. *
  105. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  106. * in special SRAM that does not power down during RFKILL. When powering back
  107. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  108. * the bootstrap program into the on-board processor, and starts it.
  109. *
  110. * The bootstrap program loads (via DMA) instructions and data for a new
  111. * program from host DRAM locations indicated by the host driver in the
  112. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  113. * automatically.
  114. *
  115. * When initializing the NIC, the host driver points the BSM to the
  116. * "initialize" uCode image. This uCode sets up some internal data, then
  117. * notifies host via "initialize alive" that it is complete.
  118. *
  119. * The host then replaces the BSM_DRAM_* pointer values to point to the
  120. * normal runtime uCode instructions and a backup uCode data cache buffer
  121. * (filled initially with starting data values for the on-board processor),
  122. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  123. * which begins normal operation.
  124. *
  125. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  126. * the backup data cache in DRAM before SRAM is powered down.
  127. *
  128. * When powering back up, the BSM loads the bootstrap program. This reloads
  129. * the runtime uCode instructions and the backup data cache into SRAM,
  130. * and re-launches the runtime uCode from where it left off.
  131. */
  132. static int iwl4965_load_bsm(struct iwl_priv *priv)
  133. {
  134. __le32 *image = priv->ucode_boot.v_addr;
  135. u32 len = priv->ucode_boot.len;
  136. dma_addr_t pinst;
  137. dma_addr_t pdata;
  138. u32 inst_len;
  139. u32 data_len;
  140. int i;
  141. u32 done;
  142. u32 reg_offset;
  143. int ret;
  144. IWL_DEBUG_INFO("Begin load bsm\n");
  145. /* make sure bootstrap program is no larger than BSM's SRAM size */
  146. if (len > IWL_MAX_BSM_SIZE)
  147. return -EINVAL;
  148. /* Tell bootstrap uCode where to find the "Initialize" uCode
  149. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  150. * NOTE: iwl4965_initialize_alive_start() will replace these values,
  151. * after the "initialize" uCode has run, to point to
  152. * runtime/protocol instructions and backup data cache. */
  153. pinst = priv->ucode_init.p_addr >> 4;
  154. pdata = priv->ucode_init_data.p_addr >> 4;
  155. inst_len = priv->ucode_init.len;
  156. data_len = priv->ucode_init_data.len;
  157. ret = iwl_grab_nic_access(priv);
  158. if (ret)
  159. return ret;
  160. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  161. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  162. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  163. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  164. /* Fill BSM memory with bootstrap instructions */
  165. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  166. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  167. reg_offset += sizeof(u32), image++)
  168. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  169. ret = iwl4965_verify_bsm(priv);
  170. if (ret) {
  171. iwl_release_nic_access(priv);
  172. return ret;
  173. }
  174. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  175. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  176. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
  177. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  178. /* Load bootstrap code into instruction SRAM now,
  179. * to prepare to load "initialize" uCode */
  180. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  181. /* Wait for load of bootstrap uCode to finish */
  182. for (i = 0; i < 100; i++) {
  183. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  184. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  185. break;
  186. udelay(10);
  187. }
  188. if (i < 100)
  189. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  190. else {
  191. IWL_ERROR("BSM write did not complete!\n");
  192. return -EIO;
  193. }
  194. /* Enable future boot loads whenever power management unit triggers it
  195. * (e.g. when powering back up after power-save shutdown) */
  196. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  197. iwl_release_nic_access(priv);
  198. return 0;
  199. }
  200. /**
  201. * iwl4965_set_ucode_ptrs - Set uCode address location
  202. *
  203. * Tell initialization uCode where to find runtime uCode.
  204. *
  205. * BSM registers initially contain pointers to initialization uCode.
  206. * We need to replace them to load runtime uCode inst and data,
  207. * and to save runtime data when powering down.
  208. */
  209. static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
  210. {
  211. dma_addr_t pinst;
  212. dma_addr_t pdata;
  213. unsigned long flags;
  214. int ret = 0;
  215. /* bits 35:4 for 4965 */
  216. pinst = priv->ucode_code.p_addr >> 4;
  217. pdata = priv->ucode_data_backup.p_addr >> 4;
  218. spin_lock_irqsave(&priv->lock, flags);
  219. ret = iwl_grab_nic_access(priv);
  220. if (ret) {
  221. spin_unlock_irqrestore(&priv->lock, flags);
  222. return ret;
  223. }
  224. /* Tell bootstrap uCode where to find image to load */
  225. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  226. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  227. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  228. priv->ucode_data.len);
  229. /* Inst bytecount must be last to set up, bit 31 signals uCode
  230. * that all new ptr/size info is in place */
  231. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  232. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  233. iwl_release_nic_access(priv);
  234. spin_unlock_irqrestore(&priv->lock, flags);
  235. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  236. return ret;
  237. }
  238. /**
  239. * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
  240. *
  241. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  242. *
  243. * The 4965 "initialize" ALIVE reply contains calibration data for:
  244. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  245. * (3945 does not contain this data).
  246. *
  247. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  248. */
  249. static void iwl4965_init_alive_start(struct iwl_priv *priv)
  250. {
  251. /* Check alive response for "valid" sign from uCode */
  252. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  253. /* We had an error bringing up the hardware, so take it
  254. * all the way back down so we can try again */
  255. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  256. goto restart;
  257. }
  258. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  259. * This is a paranoid check, because we would not have gotten the
  260. * "initialize" alive if code weren't properly loaded. */
  261. if (iwl_verify_ucode(priv)) {
  262. /* Runtime instruction load was bad;
  263. * take it all the way back down so we can try again */
  264. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  265. goto restart;
  266. }
  267. /* Calculate temperature */
  268. priv->temperature = iwl4965_get_temperature(priv);
  269. /* Send pointers to protocol/runtime uCode image ... init code will
  270. * load and launch runtime uCode, which will send us another "Alive"
  271. * notification. */
  272. IWL_DEBUG_INFO("Initialization Alive received.\n");
  273. if (iwl4965_set_ucode_ptrs(priv)) {
  274. /* Runtime instruction load won't happen;
  275. * take it all the way back down so we can try again */
  276. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  277. goto restart;
  278. }
  279. return;
  280. restart:
  281. queue_work(priv->workqueue, &priv->restart);
  282. }
  283. static int is_fat_channel(__le32 rxon_flags)
  284. {
  285. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  286. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  287. }
  288. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  289. {
  290. int idx = 0;
  291. /* 4965 HT rate format */
  292. if (rate_n_flags & RATE_MCS_HT_MSK) {
  293. idx = (rate_n_flags & 0xff);
  294. if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  295. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  296. idx += IWL_FIRST_OFDM_RATE;
  297. /* skip 9M not supported in ht*/
  298. if (idx >= IWL_RATE_9M_INDEX)
  299. idx += 1;
  300. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  301. return idx;
  302. /* 4965 legacy rate format, search for match in table */
  303. } else {
  304. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  305. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  306. return idx;
  307. }
  308. return -1;
  309. }
  310. /**
  311. * translate ucode response to mac80211 tx status control values
  312. */
  313. void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  314. struct ieee80211_tx_control *control)
  315. {
  316. int rate_index;
  317. control->antenna_sel_tx =
  318. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  319. if (rate_n_flags & RATE_MCS_HT_MSK)
  320. control->flags |= IEEE80211_TXCTL_OFDM_HT;
  321. if (rate_n_flags & RATE_MCS_GF_MSK)
  322. control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
  323. if (rate_n_flags & RATE_MCS_FAT_MSK)
  324. control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
  325. if (rate_n_flags & RATE_MCS_DUP_MSK)
  326. control->flags |= IEEE80211_TXCTL_DUP_DATA;
  327. if (rate_n_flags & RATE_MCS_SGI_MSK)
  328. control->flags |= IEEE80211_TXCTL_SHORT_GI;
  329. /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
  330. * IEEE80211_BAND_2GHZ band as it contains all the rates */
  331. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  332. if (rate_index == -1)
  333. control->tx_rate = NULL;
  334. else
  335. control->tx_rate =
  336. &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
  337. }
  338. int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
  339. {
  340. int rc;
  341. unsigned long flags;
  342. spin_lock_irqsave(&priv->lock, flags);
  343. rc = iwl_grab_nic_access(priv);
  344. if (rc) {
  345. spin_unlock_irqrestore(&priv->lock, flags);
  346. return rc;
  347. }
  348. /* stop Rx DMA */
  349. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  350. rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  351. (1 << 24), 1000);
  352. if (rc < 0)
  353. IWL_ERROR("Can't stop Rx DMA.\n");
  354. iwl_release_nic_access(priv);
  355. spin_unlock_irqrestore(&priv->lock, flags);
  356. return 0;
  357. }
  358. /*
  359. * EEPROM handlers
  360. */
  361. static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
  362. {
  363. u16 eeprom_ver;
  364. u16 calib_ver;
  365. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  366. calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
  367. if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
  368. calib_ver < EEPROM_4965_TX_POWER_VERSION)
  369. goto err;
  370. return 0;
  371. err:
  372. IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
  373. eeprom_ver, EEPROM_4965_EEPROM_VERSION,
  374. calib_ver, EEPROM_4965_TX_POWER_VERSION);
  375. return -EINVAL;
  376. }
  377. int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  378. {
  379. int ret;
  380. unsigned long flags;
  381. spin_lock_irqsave(&priv->lock, flags);
  382. ret = iwl_grab_nic_access(priv);
  383. if (ret) {
  384. spin_unlock_irqrestore(&priv->lock, flags);
  385. return ret;
  386. }
  387. if (src == IWL_PWR_SRC_VAUX) {
  388. u32 val;
  389. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  390. &val);
  391. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
  392. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  393. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  394. ~APMG_PS_CTRL_MSK_PWR_SRC);
  395. }
  396. } else {
  397. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  398. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  399. ~APMG_PS_CTRL_MSK_PWR_SRC);
  400. }
  401. iwl_release_nic_access(priv);
  402. spin_unlock_irqrestore(&priv->lock, flags);
  403. return ret;
  404. }
  405. static int iwl4965_disable_tx_fifo(struct iwl_priv *priv)
  406. {
  407. unsigned long flags;
  408. int ret;
  409. spin_lock_irqsave(&priv->lock, flags);
  410. ret = iwl_grab_nic_access(priv);
  411. if (unlikely(ret)) {
  412. IWL_ERROR("Tx fifo reset failed");
  413. spin_unlock_irqrestore(&priv->lock, flags);
  414. return ret;
  415. }
  416. iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
  417. iwl_release_nic_access(priv);
  418. spin_unlock_irqrestore(&priv->lock, flags);
  419. return 0;
  420. }
  421. static int iwl4965_apm_init(struct iwl_priv *priv)
  422. {
  423. int ret = 0;
  424. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  425. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  426. /* set "initialization complete" bit to move adapter
  427. * D0U* --> D0A* state */
  428. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  429. /* wait for clock stabilization */
  430. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  431. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  432. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  433. if (ret < 0) {
  434. IWL_DEBUG_INFO("Failed to init the card\n");
  435. goto out;
  436. }
  437. ret = iwl_grab_nic_access(priv);
  438. if (ret)
  439. goto out;
  440. /* enable DMA */
  441. iwl_write_prph(priv, APMG_CLK_CTRL_REG,
  442. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  443. udelay(20);
  444. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  445. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  446. iwl_release_nic_access(priv);
  447. out:
  448. return ret;
  449. }
  450. static void iwl4965_nic_config(struct iwl_priv *priv)
  451. {
  452. unsigned long flags;
  453. u32 val;
  454. u16 radio_cfg;
  455. u8 val_link;
  456. spin_lock_irqsave(&priv->lock, flags);
  457. if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
  458. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  459. /* Enable No Snoop field */
  460. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  461. val & ~(1 << 11));
  462. }
  463. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  464. /* disable L1 entry -- workaround for pre-B1 */
  465. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  466. radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  467. /* write radio config values to register */
  468. if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
  469. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  470. EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  471. EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  472. EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  473. /* set CSR_HW_CONFIG_REG for uCode use */
  474. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  475. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  476. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  477. priv->calib_info = (struct iwl_eeprom_calib_info *)
  478. iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
  479. spin_unlock_irqrestore(&priv->lock, flags);
  480. }
  481. int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
  482. {
  483. int rc = 0;
  484. u32 reg_val;
  485. unsigned long flags;
  486. spin_lock_irqsave(&priv->lock, flags);
  487. /* set stop master bit */
  488. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  489. reg_val = iwl_read32(priv, CSR_GP_CNTRL);
  490. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  491. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  492. IWL_DEBUG_INFO("Card in power save, master is already "
  493. "stopped\n");
  494. else {
  495. rc = iwl_poll_bit(priv, CSR_RESET,
  496. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  497. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  498. if (rc < 0) {
  499. spin_unlock_irqrestore(&priv->lock, flags);
  500. return rc;
  501. }
  502. }
  503. spin_unlock_irqrestore(&priv->lock, flags);
  504. IWL_DEBUG_INFO("stop master\n");
  505. return rc;
  506. }
  507. /**
  508. * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
  509. */
  510. void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
  511. {
  512. int txq_id;
  513. unsigned long flags;
  514. /* Stop each Tx DMA channel, and wait for it to be idle */
  515. for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
  516. spin_lock_irqsave(&priv->lock, flags);
  517. if (iwl_grab_nic_access(priv)) {
  518. spin_unlock_irqrestore(&priv->lock, flags);
  519. continue;
  520. }
  521. iwl_write_direct32(priv,
  522. FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
  523. iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
  524. FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  525. (txq_id), 200);
  526. iwl_release_nic_access(priv);
  527. spin_unlock_irqrestore(&priv->lock, flags);
  528. }
  529. /* Deallocate memory for all Tx queues */
  530. iwl_hw_txq_ctx_free(priv);
  531. }
  532. int iwl4965_hw_nic_reset(struct iwl_priv *priv)
  533. {
  534. int rc = 0;
  535. unsigned long flags;
  536. iwl4965_hw_nic_stop_master(priv);
  537. spin_lock_irqsave(&priv->lock, flags);
  538. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  539. udelay(10);
  540. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  541. rc = iwl_poll_bit(priv, CSR_RESET,
  542. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  543. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  544. udelay(10);
  545. rc = iwl_grab_nic_access(priv);
  546. if (!rc) {
  547. iwl_write_prph(priv, APMG_CLK_EN_REG,
  548. APMG_CLK_VAL_DMA_CLK_RQT |
  549. APMG_CLK_VAL_BSM_CLK_RQT);
  550. udelay(10);
  551. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  552. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  553. iwl_release_nic_access(priv);
  554. }
  555. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  556. wake_up_interruptible(&priv->wait_command_queue);
  557. spin_unlock_irqrestore(&priv->lock, flags);
  558. return rc;
  559. }
  560. #define REG_RECALIB_PERIOD (60)
  561. /**
  562. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  563. *
  564. * This callback is provided in order to send a statistics request.
  565. *
  566. * This timer function is continually reset to execute within
  567. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  568. * was received. We need to ensure we receive the statistics in order
  569. * to update the temperature used for calibrating the TXPOWER.
  570. */
  571. static void iwl4965_bg_statistics_periodic(unsigned long data)
  572. {
  573. struct iwl_priv *priv = (struct iwl_priv *)data;
  574. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  575. return;
  576. iwl_send_statistics_request(priv, CMD_ASYNC);
  577. }
  578. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  579. {
  580. struct iwl4965_ct_kill_config cmd;
  581. unsigned long flags;
  582. int ret = 0;
  583. spin_lock_irqsave(&priv->lock, flags);
  584. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  585. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  586. spin_unlock_irqrestore(&priv->lock, flags);
  587. cmd.critical_temperature_R =
  588. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  589. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  590. sizeof(cmd), &cmd);
  591. if (ret)
  592. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  593. else
  594. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
  595. "critical temperature is %d\n",
  596. cmd.critical_temperature_R);
  597. }
  598. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  599. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  600. * Called after every association, but this runs only once!
  601. * ... once chain noise is calibrated the first time, it's good forever. */
  602. static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  603. {
  604. struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
  605. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  606. struct iwl4965_calibration_cmd cmd;
  607. memset(&cmd, 0, sizeof(cmd));
  608. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  609. cmd.diff_gain_a = 0;
  610. cmd.diff_gain_b = 0;
  611. cmd.diff_gain_c = 0;
  612. if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  613. sizeof(cmd), &cmd))
  614. IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
  615. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  616. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  617. }
  618. }
  619. static void iwl4965_gain_computation(struct iwl_priv *priv,
  620. u32 *average_noise,
  621. u16 min_average_noise_antenna_i,
  622. u32 min_average_noise)
  623. {
  624. int i, ret;
  625. struct iwl_chain_noise_data *data = &priv->chain_noise_data;
  626. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  627. for (i = 0; i < NUM_RX_CHAINS; i++) {
  628. s32 delta_g = 0;
  629. if (!(data->disconn_array[i]) &&
  630. (data->delta_gain_code[i] ==
  631. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  632. delta_g = average_noise[i] - min_average_noise;
  633. data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
  634. data->delta_gain_code[i] =
  635. min(data->delta_gain_code[i],
  636. (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
  637. data->delta_gain_code[i] =
  638. (data->delta_gain_code[i] | (1 << 2));
  639. } else {
  640. data->delta_gain_code[i] = 0;
  641. }
  642. }
  643. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  644. data->delta_gain_code[0],
  645. data->delta_gain_code[1],
  646. data->delta_gain_code[2]);
  647. /* Differential gain gets sent to uCode only once */
  648. if (!data->radio_write) {
  649. struct iwl4965_calibration_cmd cmd;
  650. data->radio_write = 1;
  651. memset(&cmd, 0, sizeof(cmd));
  652. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  653. cmd.diff_gain_a = data->delta_gain_code[0];
  654. cmd.diff_gain_b = data->delta_gain_code[1];
  655. cmd.diff_gain_c = data->delta_gain_code[2];
  656. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  657. sizeof(cmd), &cmd);
  658. if (ret)
  659. IWL_DEBUG_CALIB("fail sending cmd "
  660. "REPLY_PHY_CALIBRATION_CMD \n");
  661. /* TODO we might want recalculate
  662. * rx_chain in rxon cmd */
  663. /* Mark so we run this algo only once! */
  664. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  665. }
  666. data->chain_noise_a = 0;
  667. data->chain_noise_b = 0;
  668. data->chain_noise_c = 0;
  669. data->chain_signal_a = 0;
  670. data->chain_signal_b = 0;
  671. data->chain_signal_c = 0;
  672. data->beacon_count = 0;
  673. }
  674. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  675. {
  676. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  677. sensitivity_work);
  678. mutex_lock(&priv->mutex);
  679. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  680. test_bit(STATUS_SCANNING, &priv->status)) {
  681. mutex_unlock(&priv->mutex);
  682. return;
  683. }
  684. if (priv->start_calib) {
  685. iwl_chain_noise_calibration(priv, &priv->statistics);
  686. iwl_sensitivity_calibration(priv, &priv->statistics);
  687. }
  688. mutex_unlock(&priv->mutex);
  689. return;
  690. }
  691. #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
  692. static void iwl4965_bg_txpower_work(struct work_struct *work)
  693. {
  694. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  695. txpower_work);
  696. /* If a scan happened to start before we got here
  697. * then just return; the statistics notification will
  698. * kick off another scheduled work to compensate for
  699. * any temperature delta we missed here. */
  700. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  701. test_bit(STATUS_SCANNING, &priv->status))
  702. return;
  703. mutex_lock(&priv->mutex);
  704. /* Regardless of if we are assocaited, we must reconfigure the
  705. * TX power since frames can be sent on non-radar channels while
  706. * not associated */
  707. iwl4965_hw_reg_send_txpower(priv);
  708. /* Update last_temperature to keep is_calib_needed from running
  709. * when it isn't needed... */
  710. priv->last_temperature = priv->temperature;
  711. mutex_unlock(&priv->mutex);
  712. }
  713. /*
  714. * Acquire priv->lock before calling this function !
  715. */
  716. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  717. {
  718. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  719. (index & 0xff) | (txq_id << 8));
  720. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  721. }
  722. /**
  723. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  724. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  725. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  726. *
  727. * NOTE: Acquire priv->lock before calling this function !
  728. */
  729. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  730. struct iwl_tx_queue *txq,
  731. int tx_fifo_id, int scd_retry)
  732. {
  733. int txq_id = txq->q.id;
  734. /* Find out whether to activate Tx queue */
  735. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  736. /* Set up and activate */
  737. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  738. (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  739. (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  740. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  741. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  742. IWL49_SCD_QUEUE_STTS_REG_MSK);
  743. txq->sched_retry = scd_retry;
  744. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  745. active ? "Activate" : "Deactivate",
  746. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  747. }
  748. static const u16 default_queue_to_tx_fifo[] = {
  749. IWL_TX_FIFO_AC3,
  750. IWL_TX_FIFO_AC2,
  751. IWL_TX_FIFO_AC1,
  752. IWL_TX_FIFO_AC0,
  753. IWL49_CMD_FIFO_NUM,
  754. IWL_TX_FIFO_HCCA_1,
  755. IWL_TX_FIFO_HCCA_2
  756. };
  757. int iwl4965_alive_notify(struct iwl_priv *priv)
  758. {
  759. u32 a;
  760. int i = 0;
  761. unsigned long flags;
  762. int ret;
  763. spin_lock_irqsave(&priv->lock, flags);
  764. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  765. memset(&(priv->sensitivity_data), 0,
  766. sizeof(struct iwl_sensitivity_data));
  767. memset(&(priv->chain_noise_data), 0,
  768. sizeof(struct iwl_chain_noise_data));
  769. for (i = 0; i < NUM_RX_CHAINS; i++)
  770. priv->chain_noise_data.delta_gain_code[i] =
  771. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  772. #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
  773. ret = iwl_grab_nic_access(priv);
  774. if (ret) {
  775. spin_unlock_irqrestore(&priv->lock, flags);
  776. return ret;
  777. }
  778. /* Clear 4965's internal Tx Scheduler data base */
  779. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  780. a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
  781. for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  782. iwl_write_targ_mem(priv, a, 0);
  783. for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  784. iwl_write_targ_mem(priv, a, 0);
  785. for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
  786. iwl_write_targ_mem(priv, a, 0);
  787. /* Tel 4965 where to find Tx byte count tables */
  788. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  789. (priv->shared_phys +
  790. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  791. /* Disable chain mode for all queues */
  792. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  793. /* Initialize each Tx queue (including the command queue) */
  794. for (i = 0; i < priv->hw_params.max_txq_num; i++) {
  795. /* TFD circular buffer read/write indexes */
  796. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  797. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  798. /* Max Tx Window size for Scheduler-ACK mode */
  799. iwl_write_targ_mem(priv, priv->scd_base_addr +
  800. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  801. (SCD_WIN_SIZE <<
  802. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  803. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  804. /* Frame limit */
  805. iwl_write_targ_mem(priv, priv->scd_base_addr +
  806. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  807. sizeof(u32),
  808. (SCD_FRAME_LIMIT <<
  809. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  810. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  811. }
  812. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  813. (1 << priv->hw_params.max_txq_num) - 1);
  814. /* Activate all Tx DMA/FIFO channels */
  815. iwl_write_prph(priv, IWL49_SCD_TXFACT,
  816. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  817. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  818. /* Map each Tx/cmd queue to its corresponding fifo */
  819. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  820. int ac = default_queue_to_tx_fifo[i];
  821. iwl_txq_ctx_activate(priv, i);
  822. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  823. }
  824. iwl_release_nic_access(priv);
  825. spin_unlock_irqrestore(&priv->lock, flags);
  826. /* Ask for statistics now, the uCode will send statistics notification
  827. * periodically after association */
  828. iwl_send_statistics_request(priv, CMD_ASYNC);
  829. return ret;
  830. }
  831. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  832. static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
  833. .min_nrg_cck = 97,
  834. .max_nrg_cck = 0,
  835. .auto_corr_min_ofdm = 85,
  836. .auto_corr_min_ofdm_mrc = 170,
  837. .auto_corr_min_ofdm_x1 = 105,
  838. .auto_corr_min_ofdm_mrc_x1 = 220,
  839. .auto_corr_max_ofdm = 120,
  840. .auto_corr_max_ofdm_mrc = 210,
  841. .auto_corr_max_ofdm_x1 = 140,
  842. .auto_corr_max_ofdm_mrc_x1 = 270,
  843. .auto_corr_min_cck = 125,
  844. .auto_corr_max_cck = 200,
  845. .auto_corr_min_cck_mrc = 200,
  846. .auto_corr_max_cck_mrc = 400,
  847. .nrg_th_cck = 100,
  848. .nrg_th_ofdm = 100,
  849. };
  850. #endif
  851. /**
  852. * iwl4965_hw_set_hw_params
  853. *
  854. * Called when initializing driver
  855. */
  856. int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
  857. {
  858. if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
  859. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  860. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  861. IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
  862. return -EINVAL;
  863. }
  864. priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
  865. priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
  866. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  867. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  868. if (priv->cfg->mod_params->amsdu_size_8K)
  869. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  870. else
  871. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  872. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  873. priv->hw_params.max_stations = IWL4965_STATION_COUNT;
  874. priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
  875. priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
  876. priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
  877. priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
  878. priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
  879. priv->hw_params.tx_chains_num = 2;
  880. priv->hw_params.rx_chains_num = 2;
  881. priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
  882. priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
  883. priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
  884. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  885. priv->hw_params.sens = &iwl4965_sensitivity;
  886. #endif
  887. return 0;
  888. }
  889. /* set card power command */
  890. static int iwl4965_set_power(struct iwl_priv *priv,
  891. void *cmd)
  892. {
  893. int ret = 0;
  894. ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
  895. sizeof(struct iwl4965_powertable_cmd),
  896. cmd, NULL);
  897. return ret;
  898. }
  899. int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  900. {
  901. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  902. return -EINVAL;
  903. }
  904. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  905. {
  906. s32 sign = 1;
  907. if (num < 0) {
  908. sign = -sign;
  909. num = -num;
  910. }
  911. if (denom < 0) {
  912. sign = -sign;
  913. denom = -denom;
  914. }
  915. *res = 1;
  916. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  917. return 1;
  918. }
  919. /**
  920. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  921. *
  922. * Determines power supply voltage compensation for txpower calculations.
  923. * Returns number of 1/2-dB steps to subtract from gain table index,
  924. * to compensate for difference between power supply voltage during
  925. * factory measurements, vs. current power supply voltage.
  926. *
  927. * Voltage indication is higher for lower voltage.
  928. * Lower voltage requires more gain (lower gain table index).
  929. */
  930. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  931. s32 current_voltage)
  932. {
  933. s32 comp = 0;
  934. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  935. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  936. return 0;
  937. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  938. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  939. if (current_voltage > eeprom_voltage)
  940. comp *= 2;
  941. if ((comp < -2) || (comp > 2))
  942. comp = 0;
  943. return comp;
  944. }
  945. static const struct iwl_channel_info *
  946. iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
  947. enum ieee80211_band band, u16 channel)
  948. {
  949. const struct iwl_channel_info *ch_info;
  950. ch_info = iwl_get_channel_info(priv, band, channel);
  951. if (!is_channel_valid(ch_info))
  952. return NULL;
  953. return ch_info;
  954. }
  955. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  956. {
  957. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  958. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  959. return CALIB_CH_GROUP_5;
  960. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  961. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  962. return CALIB_CH_GROUP_1;
  963. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  964. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  965. return CALIB_CH_GROUP_2;
  966. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  967. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  968. return CALIB_CH_GROUP_3;
  969. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  970. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  971. return CALIB_CH_GROUP_4;
  972. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  973. return -1;
  974. }
  975. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  976. {
  977. s32 b = -1;
  978. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  979. if (priv->calib_info->band_info[b].ch_from == 0)
  980. continue;
  981. if ((channel >= priv->calib_info->band_info[b].ch_from)
  982. && (channel <= priv->calib_info->band_info[b].ch_to))
  983. break;
  984. }
  985. return b;
  986. }
  987. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  988. {
  989. s32 val;
  990. if (x2 == x1)
  991. return y1;
  992. else {
  993. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  994. return val + y2;
  995. }
  996. }
  997. /**
  998. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  999. *
  1000. * Interpolates factory measurements from the two sample channels within a
  1001. * sub-band, to apply to channel of interest. Interpolation is proportional to
  1002. * differences in channel frequencies, which is proportional to differences
  1003. * in channel number.
  1004. */
  1005. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  1006. struct iwl_eeprom_calib_ch_info *chan_info)
  1007. {
  1008. s32 s = -1;
  1009. u32 c;
  1010. u32 m;
  1011. const struct iwl_eeprom_calib_measure *m1;
  1012. const struct iwl_eeprom_calib_measure *m2;
  1013. struct iwl_eeprom_calib_measure *omeas;
  1014. u32 ch_i1;
  1015. u32 ch_i2;
  1016. s = iwl4965_get_sub_band(priv, channel);
  1017. if (s >= EEPROM_TX_POWER_BANDS) {
  1018. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1019. return -1;
  1020. }
  1021. ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
  1022. ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
  1023. chan_info->ch_num = (u8) channel;
  1024. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1025. channel, s, ch_i1, ch_i2);
  1026. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1027. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1028. m1 = &(priv->calib_info->band_info[s].ch1.
  1029. measurements[c][m]);
  1030. m2 = &(priv->calib_info->band_info[s].ch2.
  1031. measurements[c][m]);
  1032. omeas = &(chan_info->measurements[c][m]);
  1033. omeas->actual_pow =
  1034. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1035. m1->actual_pow,
  1036. ch_i2,
  1037. m2->actual_pow);
  1038. omeas->gain_idx =
  1039. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1040. m1->gain_idx, ch_i2,
  1041. m2->gain_idx);
  1042. omeas->temperature =
  1043. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1044. m1->temperature,
  1045. ch_i2,
  1046. m2->temperature);
  1047. omeas->pa_det =
  1048. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1049. m1->pa_det, ch_i2,
  1050. m2->pa_det);
  1051. IWL_DEBUG_TXPOWER
  1052. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1053. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1054. IWL_DEBUG_TXPOWER
  1055. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1056. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1057. IWL_DEBUG_TXPOWER
  1058. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1059. m1->pa_det, m2->pa_det, omeas->pa_det);
  1060. IWL_DEBUG_TXPOWER
  1061. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1062. m1->temperature, m2->temperature,
  1063. omeas->temperature);
  1064. }
  1065. }
  1066. return 0;
  1067. }
  1068. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1069. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1070. static s32 back_off_table[] = {
  1071. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1072. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1073. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1074. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1075. 10 /* CCK */
  1076. };
  1077. /* Thermal compensation values for txpower for various frequency ranges ...
  1078. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1079. static struct iwl4965_txpower_comp_entry {
  1080. s32 degrees_per_05db_a;
  1081. s32 degrees_per_05db_a_denom;
  1082. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1083. {9, 2}, /* group 0 5.2, ch 34-43 */
  1084. {4, 1}, /* group 1 5.2, ch 44-70 */
  1085. {4, 1}, /* group 2 5.2, ch 71-124 */
  1086. {4, 1}, /* group 3 5.2, ch 125-200 */
  1087. {3, 1} /* group 4 2.4, ch all */
  1088. };
  1089. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1090. {
  1091. if (!band) {
  1092. if ((rate_power_index & 7) <= 4)
  1093. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1094. }
  1095. return MIN_TX_GAIN_INDEX;
  1096. }
  1097. struct gain_entry {
  1098. u8 dsp;
  1099. u8 radio;
  1100. };
  1101. static const struct gain_entry gain_table[2][108] = {
  1102. /* 5.2GHz power gain index table */
  1103. {
  1104. {123, 0x3F}, /* highest txpower */
  1105. {117, 0x3F},
  1106. {110, 0x3F},
  1107. {104, 0x3F},
  1108. {98, 0x3F},
  1109. {110, 0x3E},
  1110. {104, 0x3E},
  1111. {98, 0x3E},
  1112. {110, 0x3D},
  1113. {104, 0x3D},
  1114. {98, 0x3D},
  1115. {110, 0x3C},
  1116. {104, 0x3C},
  1117. {98, 0x3C},
  1118. {110, 0x3B},
  1119. {104, 0x3B},
  1120. {98, 0x3B},
  1121. {110, 0x3A},
  1122. {104, 0x3A},
  1123. {98, 0x3A},
  1124. {110, 0x39},
  1125. {104, 0x39},
  1126. {98, 0x39},
  1127. {110, 0x38},
  1128. {104, 0x38},
  1129. {98, 0x38},
  1130. {110, 0x37},
  1131. {104, 0x37},
  1132. {98, 0x37},
  1133. {110, 0x36},
  1134. {104, 0x36},
  1135. {98, 0x36},
  1136. {110, 0x35},
  1137. {104, 0x35},
  1138. {98, 0x35},
  1139. {110, 0x34},
  1140. {104, 0x34},
  1141. {98, 0x34},
  1142. {110, 0x33},
  1143. {104, 0x33},
  1144. {98, 0x33},
  1145. {110, 0x32},
  1146. {104, 0x32},
  1147. {98, 0x32},
  1148. {110, 0x31},
  1149. {104, 0x31},
  1150. {98, 0x31},
  1151. {110, 0x30},
  1152. {104, 0x30},
  1153. {98, 0x30},
  1154. {110, 0x25},
  1155. {104, 0x25},
  1156. {98, 0x25},
  1157. {110, 0x24},
  1158. {104, 0x24},
  1159. {98, 0x24},
  1160. {110, 0x23},
  1161. {104, 0x23},
  1162. {98, 0x23},
  1163. {110, 0x22},
  1164. {104, 0x18},
  1165. {98, 0x18},
  1166. {110, 0x17},
  1167. {104, 0x17},
  1168. {98, 0x17},
  1169. {110, 0x16},
  1170. {104, 0x16},
  1171. {98, 0x16},
  1172. {110, 0x15},
  1173. {104, 0x15},
  1174. {98, 0x15},
  1175. {110, 0x14},
  1176. {104, 0x14},
  1177. {98, 0x14},
  1178. {110, 0x13},
  1179. {104, 0x13},
  1180. {98, 0x13},
  1181. {110, 0x12},
  1182. {104, 0x08},
  1183. {98, 0x08},
  1184. {110, 0x07},
  1185. {104, 0x07},
  1186. {98, 0x07},
  1187. {110, 0x06},
  1188. {104, 0x06},
  1189. {98, 0x06},
  1190. {110, 0x05},
  1191. {104, 0x05},
  1192. {98, 0x05},
  1193. {110, 0x04},
  1194. {104, 0x04},
  1195. {98, 0x04},
  1196. {110, 0x03},
  1197. {104, 0x03},
  1198. {98, 0x03},
  1199. {110, 0x02},
  1200. {104, 0x02},
  1201. {98, 0x02},
  1202. {110, 0x01},
  1203. {104, 0x01},
  1204. {98, 0x01},
  1205. {110, 0x00},
  1206. {104, 0x00},
  1207. {98, 0x00},
  1208. {93, 0x00},
  1209. {88, 0x00},
  1210. {83, 0x00},
  1211. {78, 0x00},
  1212. },
  1213. /* 2.4GHz power gain index table */
  1214. {
  1215. {110, 0x3f}, /* highest txpower */
  1216. {104, 0x3f},
  1217. {98, 0x3f},
  1218. {110, 0x3e},
  1219. {104, 0x3e},
  1220. {98, 0x3e},
  1221. {110, 0x3d},
  1222. {104, 0x3d},
  1223. {98, 0x3d},
  1224. {110, 0x3c},
  1225. {104, 0x3c},
  1226. {98, 0x3c},
  1227. {110, 0x3b},
  1228. {104, 0x3b},
  1229. {98, 0x3b},
  1230. {110, 0x3a},
  1231. {104, 0x3a},
  1232. {98, 0x3a},
  1233. {110, 0x39},
  1234. {104, 0x39},
  1235. {98, 0x39},
  1236. {110, 0x38},
  1237. {104, 0x38},
  1238. {98, 0x38},
  1239. {110, 0x37},
  1240. {104, 0x37},
  1241. {98, 0x37},
  1242. {110, 0x36},
  1243. {104, 0x36},
  1244. {98, 0x36},
  1245. {110, 0x35},
  1246. {104, 0x35},
  1247. {98, 0x35},
  1248. {110, 0x34},
  1249. {104, 0x34},
  1250. {98, 0x34},
  1251. {110, 0x33},
  1252. {104, 0x33},
  1253. {98, 0x33},
  1254. {110, 0x32},
  1255. {104, 0x32},
  1256. {98, 0x32},
  1257. {110, 0x31},
  1258. {104, 0x31},
  1259. {98, 0x31},
  1260. {110, 0x30},
  1261. {104, 0x30},
  1262. {98, 0x30},
  1263. {110, 0x6},
  1264. {104, 0x6},
  1265. {98, 0x6},
  1266. {110, 0x5},
  1267. {104, 0x5},
  1268. {98, 0x5},
  1269. {110, 0x4},
  1270. {104, 0x4},
  1271. {98, 0x4},
  1272. {110, 0x3},
  1273. {104, 0x3},
  1274. {98, 0x3},
  1275. {110, 0x2},
  1276. {104, 0x2},
  1277. {98, 0x2},
  1278. {110, 0x1},
  1279. {104, 0x1},
  1280. {98, 0x1},
  1281. {110, 0x0},
  1282. {104, 0x0},
  1283. {98, 0x0},
  1284. {97, 0},
  1285. {96, 0},
  1286. {95, 0},
  1287. {94, 0},
  1288. {93, 0},
  1289. {92, 0},
  1290. {91, 0},
  1291. {90, 0},
  1292. {89, 0},
  1293. {88, 0},
  1294. {87, 0},
  1295. {86, 0},
  1296. {85, 0},
  1297. {84, 0},
  1298. {83, 0},
  1299. {82, 0},
  1300. {81, 0},
  1301. {80, 0},
  1302. {79, 0},
  1303. {78, 0},
  1304. {77, 0},
  1305. {76, 0},
  1306. {75, 0},
  1307. {74, 0},
  1308. {73, 0},
  1309. {72, 0},
  1310. {71, 0},
  1311. {70, 0},
  1312. {69, 0},
  1313. {68, 0},
  1314. {67, 0},
  1315. {66, 0},
  1316. {65, 0},
  1317. {64, 0},
  1318. {63, 0},
  1319. {62, 0},
  1320. {61, 0},
  1321. {60, 0},
  1322. {59, 0},
  1323. }
  1324. };
  1325. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1326. u8 is_fat, u8 ctrl_chan_high,
  1327. struct iwl4965_tx_power_db *tx_power_tbl)
  1328. {
  1329. u8 saturation_power;
  1330. s32 target_power;
  1331. s32 user_target_power;
  1332. s32 power_limit;
  1333. s32 current_temp;
  1334. s32 reg_limit;
  1335. s32 current_regulatory;
  1336. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1337. int i;
  1338. int c;
  1339. const struct iwl_channel_info *ch_info = NULL;
  1340. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1341. const struct iwl_eeprom_calib_measure *measurement;
  1342. s16 voltage;
  1343. s32 init_voltage;
  1344. s32 voltage_compensation;
  1345. s32 degrees_per_05db_num;
  1346. s32 degrees_per_05db_denom;
  1347. s32 factory_temp;
  1348. s32 temperature_comp[2];
  1349. s32 factory_gain_index[2];
  1350. s32 factory_actual_pwr[2];
  1351. s32 power_index;
  1352. /* Sanity check requested level (dBm) */
  1353. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  1354. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  1355. priv->user_txpower_limit);
  1356. return -EINVAL;
  1357. }
  1358. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  1359. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  1360. priv->user_txpower_limit);
  1361. return -EINVAL;
  1362. }
  1363. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  1364. * are used for indexing into txpower table) */
  1365. user_target_power = 2 * priv->user_txpower_limit;
  1366. /* Get current (RXON) channel, band, width */
  1367. ch_info =
  1368. iwl4965_get_channel_txpower_info(priv, priv->band, channel);
  1369. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  1370. is_fat);
  1371. if (!ch_info)
  1372. return -EINVAL;
  1373. /* get txatten group, used to select 1) thermal txpower adjustment
  1374. * and 2) mimo txpower balance between Tx chains. */
  1375. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1376. if (txatten_grp < 0)
  1377. return -EINVAL;
  1378. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  1379. channel, txatten_grp);
  1380. if (is_fat) {
  1381. if (ctrl_chan_high)
  1382. channel -= 2;
  1383. else
  1384. channel += 2;
  1385. }
  1386. /* hardware txpower limits ...
  1387. * saturation (clipping distortion) txpowers are in half-dBm */
  1388. if (band)
  1389. saturation_power = priv->calib_info->saturation_power24;
  1390. else
  1391. saturation_power = priv->calib_info->saturation_power52;
  1392. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1393. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1394. if (band)
  1395. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1396. else
  1397. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1398. }
  1399. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1400. * max_power_avg values are in dBm, convert * 2 */
  1401. if (is_fat)
  1402. reg_limit = ch_info->fat_max_power_avg * 2;
  1403. else
  1404. reg_limit = ch_info->max_power_avg * 2;
  1405. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1406. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1407. if (band)
  1408. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1409. else
  1410. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1411. }
  1412. /* Interpolate txpower calibration values for this channel,
  1413. * based on factory calibration tests on spaced channels. */
  1414. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1415. /* calculate tx gain adjustment based on power supply voltage */
  1416. voltage = priv->calib_info->voltage;
  1417. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1418. voltage_compensation =
  1419. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1420. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  1421. init_voltage,
  1422. voltage, voltage_compensation);
  1423. /* get current temperature (Celsius) */
  1424. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1425. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1426. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1427. /* select thermal txpower adjustment params, based on channel group
  1428. * (same frequency group used for mimo txatten adjustment) */
  1429. degrees_per_05db_num =
  1430. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1431. degrees_per_05db_denom =
  1432. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  1433. /* get per-chain txpower values from factory measurements */
  1434. for (c = 0; c < 2; c++) {
  1435. measurement = &ch_eeprom_info.measurements[c][1];
  1436. /* txgain adjustment (in half-dB steps) based on difference
  1437. * between factory and current temperature */
  1438. factory_temp = measurement->temperature;
  1439. iwl4965_math_div_round((current_temp - factory_temp) *
  1440. degrees_per_05db_denom,
  1441. degrees_per_05db_num,
  1442. &temperature_comp[c]);
  1443. factory_gain_index[c] = measurement->gain_idx;
  1444. factory_actual_pwr[c] = measurement->actual_pow;
  1445. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  1446. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  1447. "curr tmp %d, comp %d steps\n",
  1448. factory_temp, current_temp,
  1449. temperature_comp[c]);
  1450. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  1451. factory_gain_index[c],
  1452. factory_actual_pwr[c]);
  1453. }
  1454. /* for each of 33 bit-rates (including 1 for CCK) */
  1455. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  1456. u8 is_mimo_rate;
  1457. union iwl4965_tx_power_dual_stream tx_power;
  1458. /* for mimo, reduce each chain's txpower by half
  1459. * (3dB, 6 steps), so total output power is regulatory
  1460. * compliant. */
  1461. if (i & 0x8) {
  1462. current_regulatory = reg_limit -
  1463. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  1464. is_mimo_rate = 1;
  1465. } else {
  1466. current_regulatory = reg_limit;
  1467. is_mimo_rate = 0;
  1468. }
  1469. /* find txpower limit, either hardware or regulatory */
  1470. power_limit = saturation_power - back_off_table[i];
  1471. if (power_limit > current_regulatory)
  1472. power_limit = current_regulatory;
  1473. /* reduce user's txpower request if necessary
  1474. * for this rate on this channel */
  1475. target_power = user_target_power;
  1476. if (target_power > power_limit)
  1477. target_power = power_limit;
  1478. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  1479. i, saturation_power - back_off_table[i],
  1480. current_regulatory, user_target_power,
  1481. target_power);
  1482. /* for each of 2 Tx chains (radio transmitters) */
  1483. for (c = 0; c < 2; c++) {
  1484. s32 atten_value;
  1485. if (is_mimo_rate)
  1486. atten_value =
  1487. (s32)le32_to_cpu(priv->card_alive_init.
  1488. tx_atten[txatten_grp][c]);
  1489. else
  1490. atten_value = 0;
  1491. /* calculate index; higher index means lower txpower */
  1492. power_index = (u8) (factory_gain_index[c] -
  1493. (target_power -
  1494. factory_actual_pwr[c]) -
  1495. temperature_comp[c] -
  1496. voltage_compensation +
  1497. atten_value);
  1498. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  1499. power_index); */
  1500. if (power_index < get_min_power_index(i, band))
  1501. power_index = get_min_power_index(i, band);
  1502. /* adjust 5 GHz index to support negative indexes */
  1503. if (!band)
  1504. power_index += 9;
  1505. /* CCK, rate 32, reduce txpower for CCK */
  1506. if (i == POWER_TABLE_CCK_ENTRY)
  1507. power_index +=
  1508. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  1509. /* stay within the table! */
  1510. if (power_index > 107) {
  1511. IWL_WARNING("txpower index %d > 107\n",
  1512. power_index);
  1513. power_index = 107;
  1514. }
  1515. if (power_index < 0) {
  1516. IWL_WARNING("txpower index %d < 0\n",
  1517. power_index);
  1518. power_index = 0;
  1519. }
  1520. /* fill txpower command for this rate/chain */
  1521. tx_power.s.radio_tx_gain[c] =
  1522. gain_table[band][power_index].radio;
  1523. tx_power.s.dsp_predis_atten[c] =
  1524. gain_table[band][power_index].dsp;
  1525. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  1526. "gain 0x%02x dsp %d\n",
  1527. c, atten_value, power_index,
  1528. tx_power.s.radio_tx_gain[c],
  1529. tx_power.s.dsp_predis_atten[c]);
  1530. }/* for each chain */
  1531. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  1532. }/* for each rate */
  1533. return 0;
  1534. }
  1535. /**
  1536. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  1537. *
  1538. * Uses the active RXON for channel, band, and characteristics (fat, high)
  1539. * The power limit is taken from priv->user_txpower_limit.
  1540. */
  1541. int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
  1542. {
  1543. struct iwl4965_txpowertable_cmd cmd = { 0 };
  1544. int ret;
  1545. u8 band = 0;
  1546. u8 is_fat = 0;
  1547. u8 ctrl_chan_high = 0;
  1548. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1549. /* If this gets hit a lot, switch it to a BUG() and catch
  1550. * the stack trace to find out who is calling this during
  1551. * a scan. */
  1552. IWL_WARNING("TX Power requested while scanning!\n");
  1553. return -EAGAIN;
  1554. }
  1555. band = priv->band == IEEE80211_BAND_2GHZ;
  1556. is_fat = is_fat_channel(priv->active_rxon.flags);
  1557. if (is_fat &&
  1558. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1559. ctrl_chan_high = 1;
  1560. cmd.band = band;
  1561. cmd.channel = priv->active_rxon.channel;
  1562. ret = iwl4965_fill_txpower_tbl(priv, band,
  1563. le16_to_cpu(priv->active_rxon.channel),
  1564. is_fat, ctrl_chan_high, &cmd.tx_power);
  1565. if (ret)
  1566. goto out;
  1567. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  1568. out:
  1569. return ret;
  1570. }
  1571. static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
  1572. {
  1573. int ret = 0;
  1574. struct iwl4965_rxon_assoc_cmd rxon_assoc;
  1575. const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
  1576. const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
  1577. if ((rxon1->flags == rxon2->flags) &&
  1578. (rxon1->filter_flags == rxon2->filter_flags) &&
  1579. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  1580. (rxon1->ofdm_ht_single_stream_basic_rates ==
  1581. rxon2->ofdm_ht_single_stream_basic_rates) &&
  1582. (rxon1->ofdm_ht_dual_stream_basic_rates ==
  1583. rxon2->ofdm_ht_dual_stream_basic_rates) &&
  1584. (rxon1->rx_chain == rxon2->rx_chain) &&
  1585. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  1586. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  1587. return 0;
  1588. }
  1589. rxon_assoc.flags = priv->staging_rxon.flags;
  1590. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  1591. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  1592. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  1593. rxon_assoc.reserved = 0;
  1594. rxon_assoc.ofdm_ht_single_stream_basic_rates =
  1595. priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
  1596. rxon_assoc.ofdm_ht_dual_stream_basic_rates =
  1597. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
  1598. rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
  1599. ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
  1600. sizeof(rxon_assoc), &rxon_assoc, NULL);
  1601. if (ret)
  1602. return ret;
  1603. return ret;
  1604. }
  1605. int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  1606. {
  1607. int rc;
  1608. u8 band = 0;
  1609. u8 is_fat = 0;
  1610. u8 ctrl_chan_high = 0;
  1611. struct iwl4965_channel_switch_cmd cmd = { 0 };
  1612. const struct iwl_channel_info *ch_info;
  1613. band = priv->band == IEEE80211_BAND_2GHZ;
  1614. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1615. is_fat = is_fat_channel(priv->staging_rxon.flags);
  1616. if (is_fat &&
  1617. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1618. ctrl_chan_high = 1;
  1619. cmd.band = band;
  1620. cmd.expect_beacon = 0;
  1621. cmd.channel = cpu_to_le16(channel);
  1622. cmd.rxon_flags = priv->active_rxon.flags;
  1623. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  1624. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  1625. if (ch_info)
  1626. cmd.expect_beacon = is_channel_radar(ch_info);
  1627. else
  1628. cmd.expect_beacon = 1;
  1629. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  1630. ctrl_chan_high, &cmd.tx_power);
  1631. if (rc) {
  1632. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  1633. return rc;
  1634. }
  1635. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  1636. return rc;
  1637. }
  1638. static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
  1639. {
  1640. struct iwl4965_shared *s = priv->shared_virt;
  1641. return le32_to_cpu(s->rb_closed) & 0xFFF;
  1642. }
  1643. int iwl4965_hw_get_temperature(struct iwl_priv *priv)
  1644. {
  1645. return priv->temperature;
  1646. }
  1647. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  1648. struct iwl_frame *frame, u8 rate)
  1649. {
  1650. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  1651. unsigned int frame_size;
  1652. tx_beacon_cmd = &frame->u.beacon;
  1653. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  1654. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  1655. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1656. frame_size = iwl4965_fill_beacon_frame(priv,
  1657. tx_beacon_cmd->frame,
  1658. iwl_bcast_addr,
  1659. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  1660. BUG_ON(frame_size > MAX_MPDU_SIZE);
  1661. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  1662. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  1663. tx_beacon_cmd->tx.rate_n_flags =
  1664. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  1665. else
  1666. tx_beacon_cmd->tx.rate_n_flags =
  1667. iwl4965_hw_set_rate_n_flags(rate, 0);
  1668. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  1669. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  1670. return (sizeof(*tx_beacon_cmd) + frame_size);
  1671. }
  1672. static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
  1673. {
  1674. priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
  1675. sizeof(struct iwl4965_shared),
  1676. &priv->shared_phys);
  1677. if (!priv->shared_virt)
  1678. return -ENOMEM;
  1679. memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
  1680. priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
  1681. return 0;
  1682. }
  1683. static void iwl4965_free_shared_mem(struct iwl_priv *priv)
  1684. {
  1685. if (priv->shared_virt)
  1686. pci_free_consistent(priv->pci_dev,
  1687. sizeof(struct iwl4965_shared),
  1688. priv->shared_virt,
  1689. priv->shared_phys);
  1690. }
  1691. /**
  1692. * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  1693. */
  1694. static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
  1695. struct iwl_tx_queue *txq,
  1696. u16 byte_cnt)
  1697. {
  1698. int len;
  1699. int txq_id = txq->q.id;
  1700. struct iwl4965_shared *shared_data = priv->shared_virt;
  1701. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  1702. /* Set up byte count within first 256 entries */
  1703. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1704. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  1705. /* If within first 64 entries, duplicate at end */
  1706. if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
  1707. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1708. tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
  1709. byte_cnt, len);
  1710. }
  1711. /**
  1712. * sign_extend - Sign extend a value using specified bit as sign-bit
  1713. *
  1714. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  1715. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  1716. *
  1717. * @param oper value to sign extend
  1718. * @param index 0 based bit index (0<=index<32) to sign bit
  1719. */
  1720. static s32 sign_extend(u32 oper, int index)
  1721. {
  1722. u8 shift = 31 - index;
  1723. return (s32)(oper << shift) >> shift;
  1724. }
  1725. /**
  1726. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  1727. * @statistics: Provides the temperature reading from the uCode
  1728. *
  1729. * A return of <0 indicates bogus data in the statistics
  1730. */
  1731. int iwl4965_get_temperature(const struct iwl_priv *priv)
  1732. {
  1733. s32 temperature;
  1734. s32 vt;
  1735. s32 R1, R2, R3;
  1736. u32 R4;
  1737. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  1738. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  1739. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  1740. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  1741. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  1742. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  1743. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  1744. } else {
  1745. IWL_DEBUG_TEMP("Running temperature calibration\n");
  1746. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  1747. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  1748. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  1749. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  1750. }
  1751. /*
  1752. * Temperature is only 23 bits, so sign extend out to 32.
  1753. *
  1754. * NOTE If we haven't received a statistics notification yet
  1755. * with an updated temperature, use R4 provided to us in the
  1756. * "initialize" ALIVE response.
  1757. */
  1758. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  1759. vt = sign_extend(R4, 23);
  1760. else
  1761. vt = sign_extend(
  1762. le32_to_cpu(priv->statistics.general.temperature), 23);
  1763. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  1764. R1, R2, R3, vt);
  1765. if (R3 == R1) {
  1766. IWL_ERROR("Calibration conflict R1 == R3\n");
  1767. return -1;
  1768. }
  1769. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  1770. * Add offset to center the adjustment around 0 degrees Centigrade. */
  1771. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  1772. temperature /= (R3 - R1);
  1773. temperature = (temperature * 97) / 100 +
  1774. TEMPERATURE_CALIB_KELVIN_OFFSET;
  1775. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  1776. KELVIN_TO_CELSIUS(temperature));
  1777. return temperature;
  1778. }
  1779. /* Adjust Txpower only if temperature variance is greater than threshold. */
  1780. #define IWL_TEMPERATURE_THRESHOLD 3
  1781. /**
  1782. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  1783. *
  1784. * If the temperature changed has changed sufficiently, then a recalibration
  1785. * is needed.
  1786. *
  1787. * Assumes caller will replace priv->last_temperature once calibration
  1788. * executed.
  1789. */
  1790. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  1791. {
  1792. int temp_diff;
  1793. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  1794. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  1795. return 0;
  1796. }
  1797. temp_diff = priv->temperature - priv->last_temperature;
  1798. /* get absolute value */
  1799. if (temp_diff < 0) {
  1800. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  1801. temp_diff = -temp_diff;
  1802. } else if (temp_diff == 0)
  1803. IWL_DEBUG_POWER("Same temp, \n");
  1804. else
  1805. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  1806. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  1807. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  1808. return 0;
  1809. }
  1810. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  1811. return 1;
  1812. }
  1813. /* Calculate noise level, based on measurements during network silence just
  1814. * before arriving beacon. This measurement can be done only if we know
  1815. * exactly when to expect beacons, therefore only when we're associated. */
  1816. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  1817. {
  1818. struct statistics_rx_non_phy *rx_info
  1819. = &(priv->statistics.rx.general);
  1820. int num_active_rx = 0;
  1821. int total_silence = 0;
  1822. int bcn_silence_a =
  1823. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  1824. int bcn_silence_b =
  1825. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  1826. int bcn_silence_c =
  1827. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  1828. if (bcn_silence_a) {
  1829. total_silence += bcn_silence_a;
  1830. num_active_rx++;
  1831. }
  1832. if (bcn_silence_b) {
  1833. total_silence += bcn_silence_b;
  1834. num_active_rx++;
  1835. }
  1836. if (bcn_silence_c) {
  1837. total_silence += bcn_silence_c;
  1838. num_active_rx++;
  1839. }
  1840. /* Average among active antennas */
  1841. if (num_active_rx)
  1842. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  1843. else
  1844. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1845. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  1846. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  1847. priv->last_rx_noise);
  1848. }
  1849. void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
  1850. struct iwl_rx_mem_buffer *rxb)
  1851. {
  1852. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1853. int change;
  1854. s32 temp;
  1855. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  1856. (int)sizeof(priv->statistics), pkt->len);
  1857. change = ((priv->statistics.general.temperature !=
  1858. pkt->u.stats.general.temperature) ||
  1859. ((priv->statistics.flag &
  1860. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  1861. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  1862. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  1863. set_bit(STATUS_STATISTICS, &priv->status);
  1864. /* Reschedule the statistics timer to occur in
  1865. * REG_RECALIB_PERIOD seconds to ensure we get a
  1866. * thermal update even if the uCode doesn't give
  1867. * us one */
  1868. mod_timer(&priv->statistics_periodic, jiffies +
  1869. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  1870. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1871. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  1872. iwl4965_rx_calc_noise(priv);
  1873. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  1874. queue_work(priv->workqueue, &priv->sensitivity_work);
  1875. #endif
  1876. }
  1877. iwl_leds_background(priv);
  1878. /* If the hardware hasn't reported a change in
  1879. * temperature then don't bother computing a
  1880. * calibrated temperature value */
  1881. if (!change)
  1882. return;
  1883. temp = iwl4965_get_temperature(priv);
  1884. if (temp < 0)
  1885. return;
  1886. if (priv->temperature != temp) {
  1887. if (priv->temperature)
  1888. IWL_DEBUG_TEMP("Temperature changed "
  1889. "from %dC to %dC\n",
  1890. KELVIN_TO_CELSIUS(priv->temperature),
  1891. KELVIN_TO_CELSIUS(temp));
  1892. else
  1893. IWL_DEBUG_TEMP("Temperature "
  1894. "initialized to %dC\n",
  1895. KELVIN_TO_CELSIUS(temp));
  1896. }
  1897. priv->temperature = temp;
  1898. set_bit(STATUS_TEMPERATURE, &priv->status);
  1899. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1900. iwl4965_is_temp_calib_needed(priv))
  1901. queue_work(priv->workqueue, &priv->txpower_work);
  1902. }
  1903. static void iwl4965_add_radiotap(struct iwl_priv *priv,
  1904. struct sk_buff *skb,
  1905. struct iwl4965_rx_phy_res *rx_start,
  1906. struct ieee80211_rx_status *stats,
  1907. u32 ampdu_status)
  1908. {
  1909. s8 signal = stats->signal;
  1910. s8 noise = 0;
  1911. int rate = stats->rate_idx;
  1912. u64 tsf = stats->mactime;
  1913. __le16 antenna;
  1914. __le16 phy_flags_hw = rx_start->phy_flags;
  1915. struct iwl4965_rt_rx_hdr {
  1916. struct ieee80211_radiotap_header rt_hdr;
  1917. __le64 rt_tsf; /* TSF */
  1918. u8 rt_flags; /* radiotap packet flags */
  1919. u8 rt_rate; /* rate in 500kb/s */
  1920. __le16 rt_channelMHz; /* channel in MHz */
  1921. __le16 rt_chbitmask; /* channel bitfield */
  1922. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  1923. s8 rt_dbmnoise;
  1924. u8 rt_antenna; /* antenna number */
  1925. } __attribute__ ((packed)) *iwl4965_rt;
  1926. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  1927. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  1928. if (net_ratelimit())
  1929. printk(KERN_ERR "not enough headroom [%d] for "
  1930. "radiotap head [%zd]\n",
  1931. skb_headroom(skb), sizeof(*iwl4965_rt));
  1932. return;
  1933. }
  1934. /* put radiotap header in front of 802.11 header and data */
  1935. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  1936. /* initialise radiotap header */
  1937. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  1938. iwl4965_rt->rt_hdr.it_pad = 0;
  1939. /* total header + data */
  1940. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  1941. &iwl4965_rt->rt_hdr.it_len);
  1942. /* Indicate all the fields we add to the radiotap header */
  1943. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  1944. (1 << IEEE80211_RADIOTAP_FLAGS) |
  1945. (1 << IEEE80211_RADIOTAP_RATE) |
  1946. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  1947. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  1948. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  1949. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  1950. &iwl4965_rt->rt_hdr.it_present);
  1951. /* Zero the flags, we'll add to them as we go */
  1952. iwl4965_rt->rt_flags = 0;
  1953. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  1954. iwl4965_rt->rt_dbmsignal = signal;
  1955. iwl4965_rt->rt_dbmnoise = noise;
  1956. /* Convert the channel frequency and set the flags */
  1957. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  1958. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  1959. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1960. IEEE80211_CHAN_5GHZ),
  1961. &iwl4965_rt->rt_chbitmask);
  1962. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  1963. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  1964. IEEE80211_CHAN_2GHZ),
  1965. &iwl4965_rt->rt_chbitmask);
  1966. else /* 802.11g */
  1967. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1968. IEEE80211_CHAN_2GHZ),
  1969. &iwl4965_rt->rt_chbitmask);
  1970. if (rate == -1)
  1971. iwl4965_rt->rt_rate = 0;
  1972. else
  1973. iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
  1974. /*
  1975. * "antenna number"
  1976. *
  1977. * It seems that the antenna field in the phy flags value
  1978. * is actually a bitfield. This is undefined by radiotap,
  1979. * it wants an actual antenna number but I always get "7"
  1980. * for most legacy frames I receive indicating that the
  1981. * same frame was received on all three RX chains.
  1982. *
  1983. * I think this field should be removed in favour of a
  1984. * new 802.11n radiotap field "RX chains" that is defined
  1985. * as a bitmask.
  1986. */
  1987. antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
  1988. iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
  1989. /* set the preamble flag if appropriate */
  1990. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1991. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  1992. stats->flag |= RX_FLAG_RADIOTAP;
  1993. }
  1994. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  1995. {
  1996. /* 0 - mgmt, 1 - cnt, 2 - data */
  1997. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  1998. priv->rx_stats[idx].cnt++;
  1999. priv->rx_stats[idx].bytes += len;
  2000. }
  2001. /*
  2002. * returns non-zero if packet should be dropped
  2003. */
  2004. static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
  2005. struct ieee80211_hdr *hdr,
  2006. u32 decrypt_res,
  2007. struct ieee80211_rx_status *stats)
  2008. {
  2009. u16 fc = le16_to_cpu(hdr->frame_control);
  2010. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2011. return 0;
  2012. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2013. return 0;
  2014. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2015. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2016. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2017. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2018. * Decryption will be done in SW. */
  2019. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2020. RX_RES_STATUS_BAD_KEY_TTAK)
  2021. break;
  2022. case RX_RES_STATUS_SEC_TYPE_WEP:
  2023. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2024. RX_RES_STATUS_BAD_ICV_MIC) {
  2025. /* bad ICV, the packet is destroyed since the
  2026. * decryption is inplace, drop it */
  2027. IWL_DEBUG_RX("Packet destroyed\n");
  2028. return -1;
  2029. }
  2030. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2031. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2032. RX_RES_STATUS_DECRYPT_OK) {
  2033. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2034. stats->flag |= RX_FLAG_DECRYPTED;
  2035. }
  2036. break;
  2037. default:
  2038. break;
  2039. }
  2040. return 0;
  2041. }
  2042. static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  2043. {
  2044. u32 decrypt_out = 0;
  2045. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  2046. RX_RES_STATUS_STATION_FOUND)
  2047. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  2048. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  2049. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  2050. /* packet was not encrypted */
  2051. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2052. RX_RES_STATUS_SEC_TYPE_NONE)
  2053. return decrypt_out;
  2054. /* packet was encrypted with unknown alg */
  2055. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2056. RX_RES_STATUS_SEC_TYPE_ERR)
  2057. return decrypt_out;
  2058. /* decryption was not done in HW */
  2059. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  2060. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  2061. return decrypt_out;
  2062. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  2063. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2064. /* alg is CCM: check MIC only */
  2065. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  2066. /* Bad MIC */
  2067. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  2068. else
  2069. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  2070. break;
  2071. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2072. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  2073. /* Bad TTAK */
  2074. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  2075. break;
  2076. }
  2077. /* fall through if TTAK OK */
  2078. default:
  2079. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  2080. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  2081. else
  2082. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  2083. break;
  2084. };
  2085. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  2086. decrypt_in, decrypt_out);
  2087. return decrypt_out;
  2088. }
  2089. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  2090. int include_phy,
  2091. struct iwl_rx_mem_buffer *rxb,
  2092. struct ieee80211_rx_status *stats)
  2093. {
  2094. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2095. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2096. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  2097. struct ieee80211_hdr *hdr;
  2098. u16 len;
  2099. __le32 *rx_end;
  2100. unsigned int skblen;
  2101. u32 ampdu_status;
  2102. u32 ampdu_status_legacy;
  2103. if (!include_phy && priv->last_phy_res[0])
  2104. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2105. if (!rx_start) {
  2106. IWL_ERROR("MPDU frame without a PHY data\n");
  2107. return;
  2108. }
  2109. if (include_phy) {
  2110. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  2111. rx_start->cfg_phy_cnt);
  2112. len = le16_to_cpu(rx_start->byte_count);
  2113. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  2114. sizeof(struct iwl4965_rx_phy_res) +
  2115. rx_start->cfg_phy_cnt + len);
  2116. } else {
  2117. struct iwl4965_rx_mpdu_res_start *amsdu =
  2118. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2119. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  2120. sizeof(struct iwl4965_rx_mpdu_res_start));
  2121. len = le16_to_cpu(amsdu->byte_count);
  2122. rx_start->byte_count = amsdu->byte_count;
  2123. rx_end = (__le32 *) (((u8 *) hdr) + len);
  2124. }
  2125. /* In monitor mode allow 802.11 ACk frames (10 bytes) */
  2126. if (len > priv->hw_params.max_pkt_size ||
  2127. len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
  2128. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  2129. return;
  2130. }
  2131. ampdu_status = le32_to_cpu(*rx_end);
  2132. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  2133. if (!include_phy) {
  2134. /* New status scheme, need to translate */
  2135. ampdu_status_legacy = ampdu_status;
  2136. ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
  2137. }
  2138. /* start from MAC */
  2139. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2140. skb_put(rxb->skb, len); /* end where data ends */
  2141. /* We only process data packets if the interface is open */
  2142. if (unlikely(!priv->is_open)) {
  2143. IWL_DEBUG_DROP_LIMIT
  2144. ("Dropping packet while interface is not open.\n");
  2145. return;
  2146. }
  2147. stats->flag = 0;
  2148. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2149. /* in case of HW accelerated crypto and bad decryption, drop */
  2150. if (!priv->hw_params.sw_crypto &&
  2151. iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  2152. return;
  2153. if (priv->add_radiotap)
  2154. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  2155. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  2156. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2157. priv->alloc_rxb_skb--;
  2158. rxb->skb = NULL;
  2159. }
  2160. /* Calc max signal level (dBm) among 3 possible receivers */
  2161. static int iwl4965_calc_rssi(struct iwl_priv *priv,
  2162. struct iwl4965_rx_phy_res *rx_resp)
  2163. {
  2164. /* data from PHY/DSP regarding signal strength, etc.,
  2165. * contents are always there, not configurable by host. */
  2166. struct iwl4965_rx_non_cfg_phy *ncphy =
  2167. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2168. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  2169. >> IWL_AGC_DB_POS;
  2170. u32 valid_antennae =
  2171. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  2172. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  2173. u8 max_rssi = 0;
  2174. u32 i;
  2175. /* Find max rssi among 3 possible receivers.
  2176. * These values are measured by the digital signal processor (DSP).
  2177. * They should stay fairly constant even as the signal strength varies,
  2178. * if the radio's automatic gain control (AGC) is working right.
  2179. * AGC value (see below) will provide the "interesting" info. */
  2180. for (i = 0; i < 3; i++)
  2181. if (valid_antennae & (1 << i))
  2182. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  2183. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  2184. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  2185. max_rssi, agc);
  2186. /* dBm = max_rssi dB - agc dB - constant.
  2187. * Higher AGC (higher radio gain) means lower signal. */
  2188. return (max_rssi - agc - IWL_RSSI_OFFSET);
  2189. }
  2190. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  2191. {
  2192. unsigned long flags;
  2193. spin_lock_irqsave(&priv->sta_lock, flags);
  2194. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  2195. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  2196. priv->stations[sta_id].sta.sta.modify_mask = 0;
  2197. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2198. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2199. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2200. }
  2201. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  2202. {
  2203. /* FIXME: need locking over ps_status ??? */
  2204. u8 sta_id = iwl_find_station(priv, addr);
  2205. if (sta_id != IWL_INVALID_STATION) {
  2206. u8 sta_awake = priv->stations[sta_id].
  2207. ps_status == STA_PS_STATUS_WAKE;
  2208. if (sta_awake && ps_bit)
  2209. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  2210. else if (!sta_awake && !ps_bit) {
  2211. iwl4965_sta_modify_ps_wake(priv, sta_id);
  2212. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  2213. }
  2214. }
  2215. }
  2216. #ifdef CONFIG_IWLWIFI_DEBUG
  2217. /**
  2218. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  2219. *
  2220. * You may hack this function to show different aspects of received frames,
  2221. * including selective frame dumps.
  2222. * group100 parameter selects whether to show 1 out of 100 good frames.
  2223. *
  2224. * TODO: This was originally written for 3945, need to audit for
  2225. * proper operation with 4965.
  2226. */
  2227. static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2228. struct iwl_rx_packet *pkt,
  2229. struct ieee80211_hdr *header, int group100)
  2230. {
  2231. u32 to_us;
  2232. u32 print_summary = 0;
  2233. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  2234. u32 hundred = 0;
  2235. u32 dataframe = 0;
  2236. u16 fc;
  2237. u16 seq_ctl;
  2238. u16 channel;
  2239. u16 phy_flags;
  2240. int rate_sym;
  2241. u16 length;
  2242. u16 status;
  2243. u16 bcn_tmr;
  2244. u32 tsf_low;
  2245. u64 tsf;
  2246. u8 rssi;
  2247. u8 agc;
  2248. u16 sig_avg;
  2249. u16 noise_diff;
  2250. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  2251. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  2252. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  2253. u8 *data = IWL_RX_DATA(pkt);
  2254. if (likely(!(priv->debug_level & IWL_DL_RX)))
  2255. return;
  2256. /* MAC header */
  2257. fc = le16_to_cpu(header->frame_control);
  2258. seq_ctl = le16_to_cpu(header->seq_ctrl);
  2259. /* metadata */
  2260. channel = le16_to_cpu(rx_hdr->channel);
  2261. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  2262. rate_sym = rx_hdr->rate;
  2263. length = le16_to_cpu(rx_hdr->len);
  2264. /* end-of-frame status and timestamp */
  2265. status = le32_to_cpu(rx_end->status);
  2266. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  2267. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  2268. tsf = le64_to_cpu(rx_end->timestamp);
  2269. /* signal statistics */
  2270. rssi = rx_stats->rssi;
  2271. agc = rx_stats->agc;
  2272. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  2273. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  2274. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  2275. /* if data frame is to us and all is good,
  2276. * (optionally) print summary for only 1 out of every 100 */
  2277. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  2278. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  2279. dataframe = 1;
  2280. if (!group100)
  2281. print_summary = 1; /* print each frame */
  2282. else if (priv->framecnt_to_us < 100) {
  2283. priv->framecnt_to_us++;
  2284. print_summary = 0;
  2285. } else {
  2286. priv->framecnt_to_us = 0;
  2287. print_summary = 1;
  2288. hundred = 1;
  2289. }
  2290. } else {
  2291. /* print summary for all other frames */
  2292. print_summary = 1;
  2293. }
  2294. if (print_summary) {
  2295. char *title;
  2296. int rate_idx;
  2297. u32 bitrate;
  2298. if (hundred)
  2299. title = "100Frames";
  2300. else if (fc & IEEE80211_FCTL_RETRY)
  2301. title = "Retry";
  2302. else if (ieee80211_is_assoc_response(fc))
  2303. title = "AscRsp";
  2304. else if (ieee80211_is_reassoc_response(fc))
  2305. title = "RasRsp";
  2306. else if (ieee80211_is_probe_response(fc)) {
  2307. title = "PrbRsp";
  2308. print_dump = 1; /* dump frame contents */
  2309. } else if (ieee80211_is_beacon(fc)) {
  2310. title = "Beacon";
  2311. print_dump = 1; /* dump frame contents */
  2312. } else if (ieee80211_is_atim(fc))
  2313. title = "ATIM";
  2314. else if (ieee80211_is_auth(fc))
  2315. title = "Auth";
  2316. else if (ieee80211_is_deauth(fc))
  2317. title = "DeAuth";
  2318. else if (ieee80211_is_disassoc(fc))
  2319. title = "DisAssoc";
  2320. else
  2321. title = "Frame";
  2322. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  2323. if (unlikely(rate_idx == -1))
  2324. bitrate = 0;
  2325. else
  2326. bitrate = iwl_rates[rate_idx].ieee / 2;
  2327. /* print frame summary.
  2328. * MAC addresses show just the last byte (for brevity),
  2329. * but you can hack it to show more, if you'd like to. */
  2330. if (dataframe)
  2331. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  2332. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  2333. title, fc, header->addr1[5],
  2334. length, rssi, channel, bitrate);
  2335. else {
  2336. /* src/dst addresses assume managed mode */
  2337. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  2338. "src=0x%02x, rssi=%u, tim=%lu usec, "
  2339. "phy=0x%02x, chnl=%d\n",
  2340. title, fc, header->addr1[5],
  2341. header->addr3[5], rssi,
  2342. tsf_low - priv->scan_start_tsf,
  2343. phy_flags, channel);
  2344. }
  2345. }
  2346. if (print_dump)
  2347. iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
  2348. }
  2349. #else
  2350. static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2351. struct iwl_rx_packet *pkt,
  2352. struct ieee80211_hdr *header,
  2353. int group100)
  2354. {
  2355. }
  2356. #endif
  2357. /* Called for REPLY_RX (legacy ABG frames), or
  2358. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  2359. static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  2360. struct iwl_rx_mem_buffer *rxb)
  2361. {
  2362. struct ieee80211_hdr *header;
  2363. struct ieee80211_rx_status rx_status;
  2364. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2365. /* Use phy data (Rx signal strength, etc.) contained within
  2366. * this rx packet for legacy frames,
  2367. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  2368. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  2369. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2370. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  2371. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2372. __le32 *rx_end;
  2373. unsigned int len = 0;
  2374. u16 fc;
  2375. u8 network_packet;
  2376. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  2377. rx_status.freq =
  2378. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  2379. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  2380. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  2381. rx_status.rate_idx =
  2382. iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  2383. if (rx_status.band == IEEE80211_BAND_5GHZ)
  2384. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  2385. rx_status.antenna = 0;
  2386. rx_status.flag = 0;
  2387. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  2388. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  2389. rx_start->cfg_phy_cnt);
  2390. return;
  2391. }
  2392. if (!include_phy) {
  2393. if (priv->last_phy_res[0])
  2394. rx_start = (struct iwl4965_rx_phy_res *)
  2395. &priv->last_phy_res[1];
  2396. else
  2397. rx_start = NULL;
  2398. }
  2399. if (!rx_start) {
  2400. IWL_ERROR("MPDU frame without a PHY data\n");
  2401. return;
  2402. }
  2403. if (include_phy) {
  2404. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  2405. + rx_start->cfg_phy_cnt);
  2406. len = le16_to_cpu(rx_start->byte_count);
  2407. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  2408. sizeof(struct iwl4965_rx_phy_res) + len);
  2409. } else {
  2410. struct iwl4965_rx_mpdu_res_start *amsdu =
  2411. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2412. header = (void *)(pkt->u.raw +
  2413. sizeof(struct iwl4965_rx_mpdu_res_start));
  2414. len = le16_to_cpu(amsdu->byte_count);
  2415. rx_end = (__le32 *) (pkt->u.raw +
  2416. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  2417. }
  2418. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  2419. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  2420. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  2421. le32_to_cpu(*rx_end));
  2422. return;
  2423. }
  2424. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  2425. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  2426. rx_status.signal = iwl4965_calc_rssi(priv, rx_start);
  2427. /* Meaningful noise values are available only from beacon statistics,
  2428. * which are gathered only when associated, and indicate noise
  2429. * only for the associated network channel ...
  2430. * Ignore these noise values while scanning (other channels) */
  2431. if (iwl_is_associated(priv) &&
  2432. !test_bit(STATUS_SCANNING, &priv->status)) {
  2433. rx_status.noise = priv->last_rx_noise;
  2434. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal,
  2435. rx_status.noise);
  2436. } else {
  2437. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2438. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal, 0);
  2439. }
  2440. /* Reset beacon noise level if not associated. */
  2441. if (!iwl_is_associated(priv))
  2442. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2443. /* Set "1" to report good data frames in groups of 100 */
  2444. /* FIXME: need to optimze the call: */
  2445. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  2446. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  2447. rx_status.signal, rx_status.noise, rx_status.signal,
  2448. (unsigned long long)rx_status.mactime);
  2449. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  2450. iwl4965_handle_data_packet(priv, 1, include_phy,
  2451. rxb, &rx_status);
  2452. return;
  2453. }
  2454. network_packet = iwl4965_is_network_packet(priv, header);
  2455. if (network_packet) {
  2456. priv->last_rx_rssi = rx_status.signal;
  2457. priv->last_beacon_time = priv->ucode_beacon_time;
  2458. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  2459. }
  2460. fc = le16_to_cpu(header->frame_control);
  2461. switch (fc & IEEE80211_FCTL_FTYPE) {
  2462. case IEEE80211_FTYPE_MGMT:
  2463. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2464. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2465. header->addr2);
  2466. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  2467. break;
  2468. case IEEE80211_FTYPE_CTL:
  2469. #ifdef CONFIG_IWL4965_HT
  2470. switch (fc & IEEE80211_FCTL_STYPE) {
  2471. case IEEE80211_STYPE_BACK_REQ:
  2472. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  2473. iwl4965_handle_data_packet(priv, 0, include_phy,
  2474. rxb, &rx_status);
  2475. break;
  2476. default:
  2477. break;
  2478. }
  2479. #endif
  2480. break;
  2481. case IEEE80211_FTYPE_DATA: {
  2482. DECLARE_MAC_BUF(mac1);
  2483. DECLARE_MAC_BUF(mac2);
  2484. DECLARE_MAC_BUF(mac3);
  2485. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2486. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2487. header->addr2);
  2488. if (unlikely(!network_packet))
  2489. IWL_DEBUG_DROP("Dropping (non network): "
  2490. "%s, %s, %s\n",
  2491. print_mac(mac1, header->addr1),
  2492. print_mac(mac2, header->addr2),
  2493. print_mac(mac3, header->addr3));
  2494. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  2495. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  2496. print_mac(mac1, header->addr1),
  2497. print_mac(mac2, header->addr2),
  2498. print_mac(mac3, header->addr3));
  2499. else
  2500. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  2501. &rx_status);
  2502. break;
  2503. }
  2504. default:
  2505. break;
  2506. }
  2507. }
  2508. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  2509. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  2510. static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
  2511. struct iwl_rx_mem_buffer *rxb)
  2512. {
  2513. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2514. priv->last_phy_res[0] = 1;
  2515. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  2516. sizeof(struct iwl4965_rx_phy_res));
  2517. }
  2518. static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
  2519. struct iwl_rx_mem_buffer *rxb)
  2520. {
  2521. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  2522. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2523. struct iwl4965_missed_beacon_notif *missed_beacon;
  2524. missed_beacon = &pkt->u.missed_beacon;
  2525. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  2526. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  2527. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  2528. le32_to_cpu(missed_beacon->total_missed_becons),
  2529. le32_to_cpu(missed_beacon->num_recvd_beacons),
  2530. le32_to_cpu(missed_beacon->num_expected_beacons));
  2531. if (!test_bit(STATUS_SCANNING, &priv->status))
  2532. iwl_init_sensitivity(priv);
  2533. }
  2534. #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
  2535. }
  2536. #ifdef CONFIG_IWL4965_HT
  2537. /**
  2538. * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
  2539. */
  2540. static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
  2541. int sta_id, int tid)
  2542. {
  2543. unsigned long flags;
  2544. /* Remove "disable" flag, to enable Tx for this TID */
  2545. spin_lock_irqsave(&priv->sta_lock, flags);
  2546. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  2547. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  2548. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2549. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2550. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2551. }
  2552. /**
  2553. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  2554. *
  2555. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  2556. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  2557. */
  2558. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  2559. struct iwl_ht_agg *agg,
  2560. struct iwl4965_compressed_ba_resp*
  2561. ba_resp)
  2562. {
  2563. int i, sh, ack;
  2564. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  2565. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2566. u64 bitmap;
  2567. int successes = 0;
  2568. struct ieee80211_tx_status *tx_status;
  2569. if (unlikely(!agg->wait_for_ba)) {
  2570. IWL_ERROR("Received BA when not expected\n");
  2571. return -EINVAL;
  2572. }
  2573. /* Mark that the expected block-ack response arrived */
  2574. agg->wait_for_ba = 0;
  2575. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  2576. /* Calculate shift to align block-ack bits with our Tx window bits */
  2577. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  2578. if (sh < 0) /* tbw something is wrong with indices */
  2579. sh += 0x100;
  2580. /* don't use 64-bit values for now */
  2581. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  2582. if (agg->frame_count > (64 - sh)) {
  2583. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  2584. return -1;
  2585. }
  2586. /* check for success or failure according to the
  2587. * transmitted bitmap and block-ack bitmap */
  2588. bitmap &= agg->bitmap;
  2589. /* For each frame attempted in aggregation,
  2590. * update driver's record of tx frame's status. */
  2591. for (i = 0; i < agg->frame_count ; i++) {
  2592. ack = bitmap & (1 << i);
  2593. successes += !!ack;
  2594. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  2595. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  2596. agg->start_idx + i);
  2597. }
  2598. tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
  2599. tx_status->flags = IEEE80211_TX_STATUS_ACK;
  2600. tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
  2601. tx_status->ampdu_ack_map = successes;
  2602. tx_status->ampdu_ack_len = agg->frame_count;
  2603. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
  2604. &tx_status->control);
  2605. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
  2606. return 0;
  2607. }
  2608. /**
  2609. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  2610. */
  2611. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  2612. u16 txq_id)
  2613. {
  2614. /* Simply stop the queue, but don't change any configuration;
  2615. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  2616. iwl_write_prph(priv,
  2617. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  2618. (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  2619. (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  2620. }
  2621. /**
  2622. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  2623. * priv->lock must be held by the caller
  2624. */
  2625. static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
  2626. u16 ssn_idx, u8 tx_fifo)
  2627. {
  2628. int ret = 0;
  2629. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  2630. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2631. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  2632. return -EINVAL;
  2633. }
  2634. ret = iwl_grab_nic_access(priv);
  2635. if (ret)
  2636. return ret;
  2637. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2638. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2639. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2640. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2641. /* supposes that ssn_idx is valid (!= 0xFFF) */
  2642. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2643. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2644. iwl_txq_ctx_deactivate(priv, txq_id);
  2645. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  2646. iwl_release_nic_access(priv);
  2647. return 0;
  2648. }
  2649. int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
  2650. u8 tid, int txq_id)
  2651. {
  2652. struct iwl_queue *q = &priv->txq[txq_id].q;
  2653. u8 *addr = priv->stations[sta_id].sta.sta.addr;
  2654. struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
  2655. switch (priv->stations[sta_id].tid[tid].agg.state) {
  2656. case IWL_EMPTYING_HW_QUEUE_DELBA:
  2657. /* We are reclaiming the last packet of the */
  2658. /* aggregated HW queue */
  2659. if (txq_id == tid_data->agg.txq_id &&
  2660. q->read_ptr == q->write_ptr) {
  2661. u16 ssn = SEQ_TO_SN(tid_data->seq_number);
  2662. int tx_fifo = default_tid_to_tx_fifo[tid];
  2663. IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
  2664. iwl4965_tx_queue_agg_disable(priv, txq_id,
  2665. ssn, tx_fifo);
  2666. tid_data->agg.state = IWL_AGG_OFF;
  2667. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  2668. }
  2669. break;
  2670. case IWL_EMPTYING_HW_QUEUE_ADDBA:
  2671. /* We are reclaiming the last packet of the queue */
  2672. if (tid_data->tfds_in_queue == 0) {
  2673. IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
  2674. tid_data->agg.state = IWL_AGG_ON;
  2675. ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  2676. }
  2677. break;
  2678. }
  2679. return 0;
  2680. }
  2681. /**
  2682. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  2683. *
  2684. * Handles block-acknowledge notification from device, which reports success
  2685. * of frames sent via aggregation.
  2686. */
  2687. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  2688. struct iwl_rx_mem_buffer *rxb)
  2689. {
  2690. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2691. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  2692. int index;
  2693. struct iwl_tx_queue *txq = NULL;
  2694. struct iwl_ht_agg *agg;
  2695. DECLARE_MAC_BUF(mac);
  2696. /* "flow" corresponds to Tx queue */
  2697. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2698. /* "ssn" is start of block-ack Tx window, corresponds to index
  2699. * (in Tx queue's circular buffer) of first TFD/frame in window */
  2700. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  2701. if (scd_flow >= priv->hw_params.max_txq_num) {
  2702. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  2703. return;
  2704. }
  2705. txq = &priv->txq[scd_flow];
  2706. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  2707. /* Find index just before block-ack window */
  2708. index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  2709. /* TODO: Need to get this copy more safely - now good for debug */
  2710. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  2711. "sta_id = %d\n",
  2712. agg->wait_for_ba,
  2713. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  2714. ba_resp->sta_id);
  2715. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  2716. "%d, scd_ssn = %d\n",
  2717. ba_resp->tid,
  2718. ba_resp->seq_ctl,
  2719. (unsigned long long)le64_to_cpu(ba_resp->bitmap),
  2720. ba_resp->scd_flow,
  2721. ba_resp->scd_ssn);
  2722. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  2723. agg->start_idx,
  2724. (unsigned long long)agg->bitmap);
  2725. /* Update driver's record of ACK vs. not for each frame in window */
  2726. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  2727. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  2728. * block-ack window (we assume that they've been successfully
  2729. * transmitted ... if not, it's too late anyway). */
  2730. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  2731. /* calculate mac80211 ampdu sw queue to wake */
  2732. int ampdu_q =
  2733. scd_flow - IWL_BACK_QUEUE_FIRST_ID + priv->hw->queues;
  2734. int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
  2735. priv->stations[ba_resp->sta_id].
  2736. tid[ba_resp->tid].tfds_in_queue -= freed;
  2737. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2738. priv->mac80211_registered &&
  2739. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  2740. ieee80211_wake_queue(priv->hw, ampdu_q);
  2741. iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
  2742. ba_resp->tid, scd_flow);
  2743. }
  2744. }
  2745. /**
  2746. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  2747. */
  2748. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  2749. u16 txq_id)
  2750. {
  2751. u32 tbl_dw_addr;
  2752. u32 tbl_dw;
  2753. u16 scd_q2ratid;
  2754. scd_q2ratid = ra_tid & IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  2755. tbl_dw_addr = priv->scd_base_addr +
  2756. IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  2757. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  2758. if (txq_id & 0x1)
  2759. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  2760. else
  2761. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  2762. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  2763. return 0;
  2764. }
  2765. /**
  2766. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  2767. *
  2768. * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
  2769. * i.e. it must be one of the higher queues used for aggregation
  2770. */
  2771. static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
  2772. int tx_fifo, int sta_id, int tid,
  2773. u16 ssn_idx)
  2774. {
  2775. unsigned long flags;
  2776. int rc;
  2777. u16 ra_tid;
  2778. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  2779. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2780. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  2781. ra_tid = BUILD_RAxTID(sta_id, tid);
  2782. /* Modify device's station table to Tx this TID */
  2783. iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
  2784. spin_lock_irqsave(&priv->lock, flags);
  2785. rc = iwl_grab_nic_access(priv);
  2786. if (rc) {
  2787. spin_unlock_irqrestore(&priv->lock, flags);
  2788. return rc;
  2789. }
  2790. /* Stop this Tx queue before configuring it */
  2791. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2792. /* Map receiver-address / traffic-ID to this queue */
  2793. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  2794. /* Set this queue as a chain-building queue */
  2795. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2796. /* Place first TFD at index corresponding to start sequence number.
  2797. * Assumes that ssn_idx is valid (!= 0xFFF) */
  2798. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2799. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2800. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2801. /* Set up Tx window size and frame limit for this queue */
  2802. iwl_write_targ_mem(priv,
  2803. priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  2804. (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  2805. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  2806. iwl_write_targ_mem(priv, priv->scd_base_addr +
  2807. IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  2808. (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  2809. & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  2810. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2811. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  2812. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  2813. iwl_release_nic_access(priv);
  2814. spin_unlock_irqrestore(&priv->lock, flags);
  2815. return 0;
  2816. }
  2817. #endif /* CONFIG_IWL4965_HT */
  2818. #ifdef CONFIG_IWL4965_HT
  2819. static int iwl4965_rx_agg_start(struct iwl_priv *priv,
  2820. const u8 *addr, int tid, u16 ssn)
  2821. {
  2822. unsigned long flags;
  2823. int sta_id;
  2824. sta_id = iwl_find_station(priv, addr);
  2825. if (sta_id == IWL_INVALID_STATION)
  2826. return -ENXIO;
  2827. spin_lock_irqsave(&priv->sta_lock, flags);
  2828. priv->stations[sta_id].sta.station_flags_msk = 0;
  2829. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  2830. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  2831. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  2832. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2833. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2834. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2835. CMD_ASYNC);
  2836. }
  2837. static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
  2838. const u8 *addr, int tid)
  2839. {
  2840. unsigned long flags;
  2841. int sta_id;
  2842. sta_id = iwl_find_station(priv, addr);
  2843. if (sta_id == IWL_INVALID_STATION)
  2844. return -ENXIO;
  2845. spin_lock_irqsave(&priv->sta_lock, flags);
  2846. priv->stations[sta_id].sta.station_flags_msk = 0;
  2847. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  2848. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  2849. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2850. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2851. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2852. CMD_ASYNC);
  2853. }
  2854. /*
  2855. * Find first available (lowest unused) Tx Queue, mark it "active".
  2856. * Called only when finding queue for aggregation.
  2857. * Should never return anything < 7, because they should already
  2858. * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
  2859. */
  2860. static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
  2861. {
  2862. int txq_id;
  2863. for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
  2864. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  2865. return txq_id;
  2866. return -1;
  2867. }
  2868. static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
  2869. u16 tid, u16 *start_seq_num)
  2870. {
  2871. struct iwl_priv *priv = hw->priv;
  2872. int sta_id;
  2873. int tx_fifo;
  2874. int txq_id;
  2875. int ssn = -1;
  2876. int ret = 0;
  2877. unsigned long flags;
  2878. struct iwl_tid_data *tid_data;
  2879. DECLARE_MAC_BUF(mac);
  2880. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  2881. tx_fifo = default_tid_to_tx_fifo[tid];
  2882. else
  2883. return -EINVAL;
  2884. IWL_WARNING("%s on ra = %s tid = %d\n",
  2885. __func__, print_mac(mac, ra), tid);
  2886. sta_id = iwl_find_station(priv, ra);
  2887. if (sta_id == IWL_INVALID_STATION)
  2888. return -ENXIO;
  2889. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
  2890. IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
  2891. return -ENXIO;
  2892. }
  2893. txq_id = iwl4965_txq_ctx_activate_free(priv);
  2894. if (txq_id == -1)
  2895. return -ENXIO;
  2896. spin_lock_irqsave(&priv->sta_lock, flags);
  2897. tid_data = &priv->stations[sta_id].tid[tid];
  2898. ssn = SEQ_TO_SN(tid_data->seq_number);
  2899. tid_data->agg.txq_id = txq_id;
  2900. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2901. *start_seq_num = ssn;
  2902. ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  2903. sta_id, tid, ssn);
  2904. if (ret)
  2905. return ret;
  2906. ret = 0;
  2907. if (tid_data->tfds_in_queue == 0) {
  2908. printk(KERN_ERR "HW queue is empty\n");
  2909. tid_data->agg.state = IWL_AGG_ON;
  2910. ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
  2911. } else {
  2912. IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
  2913. tid_data->tfds_in_queue);
  2914. tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
  2915. }
  2916. return ret;
  2917. }
  2918. static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
  2919. {
  2920. struct iwl_priv *priv = hw->priv;
  2921. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  2922. struct iwl_tid_data *tid_data;
  2923. int ret, write_ptr, read_ptr;
  2924. unsigned long flags;
  2925. DECLARE_MAC_BUF(mac);
  2926. if (!ra) {
  2927. IWL_ERROR("ra = NULL\n");
  2928. return -EINVAL;
  2929. }
  2930. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  2931. tx_fifo_id = default_tid_to_tx_fifo[tid];
  2932. else
  2933. return -EINVAL;
  2934. sta_id = iwl_find_station(priv, ra);
  2935. if (sta_id == IWL_INVALID_STATION)
  2936. return -ENXIO;
  2937. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
  2938. IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
  2939. tid_data = &priv->stations[sta_id].tid[tid];
  2940. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  2941. txq_id = tid_data->agg.txq_id;
  2942. write_ptr = priv->txq[txq_id].q.write_ptr;
  2943. read_ptr = priv->txq[txq_id].q.read_ptr;
  2944. /* The queue is not empty */
  2945. if (write_ptr != read_ptr) {
  2946. IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
  2947. priv->stations[sta_id].tid[tid].agg.state =
  2948. IWL_EMPTYING_HW_QUEUE_DELBA;
  2949. return 0;
  2950. }
  2951. IWL_DEBUG_HT("HW queue is empty\n");
  2952. priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
  2953. spin_lock_irqsave(&priv->lock, flags);
  2954. ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  2955. spin_unlock_irqrestore(&priv->lock, flags);
  2956. if (ret)
  2957. return ret;
  2958. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
  2959. return 0;
  2960. }
  2961. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  2962. enum ieee80211_ampdu_mlme_action action,
  2963. const u8 *addr, u16 tid, u16 *ssn)
  2964. {
  2965. struct iwl_priv *priv = hw->priv;
  2966. DECLARE_MAC_BUF(mac);
  2967. IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
  2968. print_mac(mac, addr), tid);
  2969. switch (action) {
  2970. case IEEE80211_AMPDU_RX_START:
  2971. IWL_DEBUG_HT("start Rx\n");
  2972. return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
  2973. case IEEE80211_AMPDU_RX_STOP:
  2974. IWL_DEBUG_HT("stop Rx\n");
  2975. return iwl4965_rx_agg_stop(priv, addr, tid);
  2976. case IEEE80211_AMPDU_TX_START:
  2977. IWL_DEBUG_HT("start Tx\n");
  2978. return iwl4965_tx_agg_start(hw, addr, tid, ssn);
  2979. case IEEE80211_AMPDU_TX_STOP:
  2980. IWL_DEBUG_HT("stop Tx\n");
  2981. return iwl4965_tx_agg_stop(hw, addr, tid);
  2982. default:
  2983. IWL_DEBUG_HT("unknown\n");
  2984. return -EINVAL;
  2985. break;
  2986. }
  2987. return 0;
  2988. }
  2989. #endif /* CONFIG_IWL4965_HT */
  2990. static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
  2991. {
  2992. switch (cmd_id) {
  2993. case REPLY_RXON:
  2994. return (u16) sizeof(struct iwl4965_rxon_cmd);
  2995. default:
  2996. return len;
  2997. }
  2998. }
  2999. static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
  3000. {
  3001. struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
  3002. addsta->mode = cmd->mode;
  3003. memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
  3004. memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
  3005. addsta->station_flags = cmd->station_flags;
  3006. addsta->station_flags_msk = cmd->station_flags_msk;
  3007. addsta->tid_disable_tx = cmd->tid_disable_tx;
  3008. addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
  3009. addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
  3010. addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
  3011. addsta->reserved1 = __constant_cpu_to_le16(0);
  3012. addsta->reserved2 = __constant_cpu_to_le32(0);
  3013. return (u16)sizeof(struct iwl4965_addsta_cmd);
  3014. }
  3015. /* Set up 4965-specific Rx frame reply handlers */
  3016. static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
  3017. {
  3018. /* Legacy Rx frames */
  3019. priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
  3020. /* High-throughput (HT) Rx frames */
  3021. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  3022. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  3023. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  3024. iwl4965_rx_missed_beacon_notif;
  3025. #ifdef CONFIG_IWL4965_HT
  3026. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  3027. #endif /* CONFIG_IWL4965_HT */
  3028. }
  3029. void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
  3030. {
  3031. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  3032. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  3033. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  3034. #endif
  3035. init_timer(&priv->statistics_periodic);
  3036. priv->statistics_periodic.data = (unsigned long)priv;
  3037. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  3038. }
  3039. void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
  3040. {
  3041. del_timer_sync(&priv->statistics_periodic);
  3042. cancel_delayed_work(&priv->init_alive_start);
  3043. }
  3044. static struct iwl_hcmd_ops iwl4965_hcmd = {
  3045. .rxon_assoc = iwl4965_send_rxon_assoc,
  3046. };
  3047. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  3048. .get_hcmd_size = iwl4965_get_hcmd_size,
  3049. .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
  3050. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  3051. .chain_noise_reset = iwl4965_chain_noise_reset,
  3052. .gain_computation = iwl4965_gain_computation,
  3053. #endif
  3054. };
  3055. static struct iwl_lib_ops iwl4965_lib = {
  3056. .set_hw_params = iwl4965_hw_set_hw_params,
  3057. .alloc_shared_mem = iwl4965_alloc_shared_mem,
  3058. .free_shared_mem = iwl4965_free_shared_mem,
  3059. .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
  3060. .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
  3061. .disable_tx_fifo = iwl4965_disable_tx_fifo,
  3062. .rx_handler_setup = iwl4965_rx_handler_setup,
  3063. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  3064. .alive_notify = iwl4965_alive_notify,
  3065. .init_alive_start = iwl4965_init_alive_start,
  3066. .load_ucode = iwl4965_load_bsm,
  3067. .apm_ops = {
  3068. .init = iwl4965_apm_init,
  3069. .config = iwl4965_nic_config,
  3070. .set_pwr_src = iwl4965_set_pwr_src,
  3071. },
  3072. .eeprom_ops = {
  3073. .regulatory_bands = {
  3074. EEPROM_REGULATORY_BAND_1_CHANNELS,
  3075. EEPROM_REGULATORY_BAND_2_CHANNELS,
  3076. EEPROM_REGULATORY_BAND_3_CHANNELS,
  3077. EEPROM_REGULATORY_BAND_4_CHANNELS,
  3078. EEPROM_REGULATORY_BAND_5_CHANNELS,
  3079. EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
  3080. EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
  3081. },
  3082. .verify_signature = iwlcore_eeprom_verify_signature,
  3083. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  3084. .release_semaphore = iwlcore_eeprom_release_semaphore,
  3085. .check_version = iwl4965_eeprom_check_version,
  3086. .query_addr = iwlcore_eeprom_query_addr,
  3087. },
  3088. .radio_kill_sw = iwl4965_radio_kill_sw,
  3089. .set_power = iwl4965_set_power,
  3090. .update_chain_flags = iwl4965_update_chain_flags,
  3091. };
  3092. static struct iwl_ops iwl4965_ops = {
  3093. .lib = &iwl4965_lib,
  3094. .hcmd = &iwl4965_hcmd,
  3095. .utils = &iwl4965_hcmd_utils,
  3096. };
  3097. struct iwl_cfg iwl4965_agn_cfg = {
  3098. .name = "4965AGN",
  3099. .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
  3100. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  3101. .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
  3102. .ops = &iwl4965_ops,
  3103. .mod_params = &iwl4965_mod_params,
  3104. };
  3105. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  3106. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3107. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  3108. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  3109. module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
  3110. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
  3111. module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
  3112. MODULE_PARM_DESC(debug, "debug output mask");
  3113. module_param_named(
  3114. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  3115. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3116. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  3117. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3118. /* QoS */
  3119. module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
  3120. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  3121. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  3122. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3123. module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
  3124. MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");