qla_mbx.c 125 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/gfp.h>
  11. /*
  12. * qla2x00_mailbox_command
  13. * Issue mailbox command and waits for completion.
  14. *
  15. * Input:
  16. * ha = adapter block pointer.
  17. * mcp = driver internal mbx struct pointer.
  18. *
  19. * Output:
  20. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  21. *
  22. * Returns:
  23. * 0 : QLA_SUCCESS = cmd performed success
  24. * 1 : QLA_FUNCTION_FAILED (error encountered)
  25. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  26. *
  27. * Context:
  28. * Kernel context.
  29. */
  30. static int
  31. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  32. {
  33. int rval;
  34. unsigned long flags = 0;
  35. device_reg_t __iomem *reg;
  36. uint8_t abort_active;
  37. uint8_t io_lock_on;
  38. uint16_t command = 0;
  39. uint16_t *iptr;
  40. uint16_t __iomem *optr;
  41. uint32_t cnt;
  42. uint32_t mboxes;
  43. unsigned long wait_time;
  44. struct qla_hw_data *ha = vha->hw;
  45. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  46. ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
  47. if (ha->pdev->error_state > pci_channel_io_frozen) {
  48. ql_log(ql_log_warn, vha, 0x1001,
  49. "error_state is greater than pci_channel_io_frozen, "
  50. "exiting.\n");
  51. return QLA_FUNCTION_TIMEOUT;
  52. }
  53. if (vha->device_flags & DFLG_DEV_FAILED) {
  54. ql_log(ql_log_warn, vha, 0x1002,
  55. "Device in failed state, exiting.\n");
  56. return QLA_FUNCTION_TIMEOUT;
  57. }
  58. reg = ha->iobase;
  59. io_lock_on = base_vha->flags.init_done;
  60. rval = QLA_SUCCESS;
  61. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  62. if (ha->flags.pci_channel_io_perm_failure) {
  63. ql_log(ql_log_warn, vha, 0x1003,
  64. "Perm failure on EEH timeout MBX, exiting.\n");
  65. return QLA_FUNCTION_TIMEOUT;
  66. }
  67. if (IS_QLA82XX(ha) && ha->flags.isp82xx_fw_hung) {
  68. /* Setting Link-Down error */
  69. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  70. ql_log(ql_log_warn, vha, 0x1004,
  71. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  72. return QLA_FUNCTION_TIMEOUT;
  73. }
  74. /*
  75. * Wait for active mailbox commands to finish by waiting at most tov
  76. * seconds. This is to serialize actual issuing of mailbox cmds during
  77. * non ISP abort time.
  78. */
  79. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  80. /* Timeout occurred. Return error. */
  81. ql_log(ql_log_warn, vha, 0x1005,
  82. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  83. mcp->mb[0]);
  84. return QLA_FUNCTION_TIMEOUT;
  85. }
  86. ha->flags.mbox_busy = 1;
  87. /* Save mailbox command for debug */
  88. ha->mcp = mcp;
  89. ql_dbg(ql_dbg_mbx, vha, 0x1006,
  90. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  91. spin_lock_irqsave(&ha->hardware_lock, flags);
  92. /* Load mailbox registers. */
  93. if (IS_QLA82XX(ha))
  94. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  95. else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
  96. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  97. else
  98. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  99. iptr = mcp->mb;
  100. command = mcp->mb[0];
  101. mboxes = mcp->out_mb;
  102. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  103. if (IS_QLA2200(ha) && cnt == 8)
  104. optr =
  105. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  106. if (mboxes & BIT_0)
  107. WRT_REG_WORD(optr, *iptr);
  108. mboxes >>= 1;
  109. optr++;
  110. iptr++;
  111. }
  112. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
  113. "Loaded MBX registers (displayed in bytes) =.\n");
  114. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1112,
  115. (uint8_t *)mcp->mb, 16);
  116. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1113,
  117. ".\n");
  118. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1114,
  119. ((uint8_t *)mcp->mb + 0x10), 16);
  120. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1115,
  121. ".\n");
  122. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1116,
  123. ((uint8_t *)mcp->mb + 0x20), 8);
  124. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
  125. "I/O Address = %p.\n", optr);
  126. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x100e);
  127. /* Issue set host interrupt command to send cmd out. */
  128. ha->flags.mbox_int = 0;
  129. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  130. /* Unlock mbx registers and wait for interrupt */
  131. ql_dbg(ql_dbg_mbx, vha, 0x100f,
  132. "Going to unlock irq & waiting for interrupts. "
  133. "jiffies=%lx.\n", jiffies);
  134. /* Wait for mbx cmd completion until timeout */
  135. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  136. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  137. if (IS_QLA82XX(ha)) {
  138. if (RD_REG_DWORD(&reg->isp82.hint) &
  139. HINT_MBX_INT_PENDING) {
  140. spin_unlock_irqrestore(&ha->hardware_lock,
  141. flags);
  142. ha->flags.mbox_busy = 0;
  143. ql_dbg(ql_dbg_mbx, vha, 0x1010,
  144. "Pending mailbox timeout, exiting.\n");
  145. rval = QLA_FUNCTION_TIMEOUT;
  146. goto premature_exit;
  147. }
  148. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  149. } else if (IS_FWI2_CAPABLE(ha))
  150. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  151. else
  152. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  153. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  154. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  155. } else {
  156. ql_dbg(ql_dbg_mbx, vha, 0x1011,
  157. "Cmd=%x Polling Mode.\n", command);
  158. if (IS_QLA82XX(ha)) {
  159. if (RD_REG_DWORD(&reg->isp82.hint) &
  160. HINT_MBX_INT_PENDING) {
  161. spin_unlock_irqrestore(&ha->hardware_lock,
  162. flags);
  163. ha->flags.mbox_busy = 0;
  164. ql_dbg(ql_dbg_mbx, vha, 0x1012,
  165. "Pending mailbox timeout, exiting.\n");
  166. rval = QLA_FUNCTION_TIMEOUT;
  167. goto premature_exit;
  168. }
  169. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  170. } else if (IS_FWI2_CAPABLE(ha))
  171. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  172. else
  173. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  174. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  175. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  176. while (!ha->flags.mbox_int) {
  177. if (time_after(jiffies, wait_time))
  178. break;
  179. /* Check for pending interrupts. */
  180. qla2x00_poll(ha->rsp_q_map[0]);
  181. if (!ha->flags.mbox_int &&
  182. !(IS_QLA2200(ha) &&
  183. command == MBC_LOAD_RISC_RAM_EXTENDED))
  184. msleep(10);
  185. } /* while */
  186. ql_dbg(ql_dbg_mbx, vha, 0x1013,
  187. "Waited %d sec.\n",
  188. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  189. }
  190. /* Check whether we timed out */
  191. if (ha->flags.mbox_int) {
  192. uint16_t *iptr2;
  193. ql_dbg(ql_dbg_mbx, vha, 0x1014,
  194. "Cmd=%x completed.\n", command);
  195. /* Got interrupt. Clear the flag. */
  196. ha->flags.mbox_int = 0;
  197. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  198. if ((IS_QLA82XX(ha) && ha->flags.isp82xx_fw_hung)) {
  199. ha->flags.mbox_busy = 0;
  200. /* Setting Link-Down error */
  201. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  202. ha->mcp = NULL;
  203. rval = QLA_FUNCTION_FAILED;
  204. ql_log(ql_log_warn, vha, 0x1015,
  205. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  206. goto premature_exit;
  207. }
  208. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  209. rval = QLA_FUNCTION_FAILED;
  210. /* Load return mailbox registers. */
  211. iptr2 = mcp->mb;
  212. iptr = (uint16_t *)&ha->mailbox_out[0];
  213. mboxes = mcp->in_mb;
  214. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  215. if (mboxes & BIT_0)
  216. *iptr2 = *iptr;
  217. mboxes >>= 1;
  218. iptr2++;
  219. iptr++;
  220. }
  221. } else {
  222. uint16_t mb0;
  223. uint32_t ictrl;
  224. if (IS_FWI2_CAPABLE(ha)) {
  225. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  226. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  227. } else {
  228. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  229. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  230. }
  231. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
  232. "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
  233. "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
  234. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
  235. /*
  236. * Attempt to capture a firmware dump for further analysis
  237. * of the current firmware state
  238. */
  239. ha->isp_ops->fw_dump(vha, 0);
  240. rval = QLA_FUNCTION_TIMEOUT;
  241. }
  242. ha->flags.mbox_busy = 0;
  243. /* Clean up */
  244. ha->mcp = NULL;
  245. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  246. ql_dbg(ql_dbg_mbx, vha, 0x101a,
  247. "Checking for additional resp interrupt.\n");
  248. /* polling mode for non isp_abort commands. */
  249. qla2x00_poll(ha->rsp_q_map[0]);
  250. }
  251. if (rval == QLA_FUNCTION_TIMEOUT &&
  252. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  253. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  254. ha->flags.eeh_busy) {
  255. /* not in dpc. schedule it for dpc to take over. */
  256. ql_dbg(ql_dbg_mbx, vha, 0x101b,
  257. "Timeout, schedule isp_abort_needed.\n");
  258. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  259. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  260. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  261. if (IS_QLA82XX(ha)) {
  262. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  263. "disabling pause transmit on port "
  264. "0 & 1.\n");
  265. qla82xx_wr_32(ha,
  266. QLA82XX_CRB_NIU + 0x98,
  267. CRB_NIU_XG_PAUSE_CTL_P0|
  268. CRB_NIU_XG_PAUSE_CTL_P1);
  269. }
  270. ql_log(ql_log_info, base_vha, 0x101c,
  271. "Mailbox cmd timeout occurred, cmd=0x%x, "
  272. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  273. "abort.\n", command, mcp->mb[0],
  274. ha->flags.eeh_busy);
  275. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  276. qla2xxx_wake_dpc(vha);
  277. }
  278. } else if (!abort_active) {
  279. /* call abort directly since we are in the DPC thread */
  280. ql_dbg(ql_dbg_mbx, vha, 0x101d,
  281. "Timeout, calling abort_isp.\n");
  282. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  283. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  284. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  285. if (IS_QLA82XX(ha)) {
  286. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  287. "disabling pause transmit on port "
  288. "0 & 1.\n");
  289. qla82xx_wr_32(ha,
  290. QLA82XX_CRB_NIU + 0x98,
  291. CRB_NIU_XG_PAUSE_CTL_P0|
  292. CRB_NIU_XG_PAUSE_CTL_P1);
  293. }
  294. ql_log(ql_log_info, base_vha, 0x101e,
  295. "Mailbox cmd timeout occurred, cmd=0x%x, "
  296. "mb[0]=0x%x. Scheduling ISP abort ",
  297. command, mcp->mb[0]);
  298. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  299. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  300. /* Allow next mbx cmd to come in. */
  301. complete(&ha->mbx_cmd_comp);
  302. if (ha->isp_ops->abort_isp(vha)) {
  303. /* Failed. retry later. */
  304. set_bit(ISP_ABORT_NEEDED,
  305. &vha->dpc_flags);
  306. }
  307. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  308. ql_dbg(ql_dbg_mbx, vha, 0x101f,
  309. "Finished abort_isp.\n");
  310. goto mbx_done;
  311. }
  312. }
  313. }
  314. premature_exit:
  315. /* Allow next mbx cmd to come in. */
  316. complete(&ha->mbx_cmd_comp);
  317. mbx_done:
  318. if (rval) {
  319. ql_log(ql_log_warn, base_vha, 0x1020,
  320. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
  321. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  322. } else {
  323. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  324. }
  325. return rval;
  326. }
  327. int
  328. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  329. uint32_t risc_code_size)
  330. {
  331. int rval;
  332. struct qla_hw_data *ha = vha->hw;
  333. mbx_cmd_t mc;
  334. mbx_cmd_t *mcp = &mc;
  335. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
  336. "Entered %s.\n", __func__);
  337. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  338. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  339. mcp->mb[8] = MSW(risc_addr);
  340. mcp->out_mb = MBX_8|MBX_0;
  341. } else {
  342. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  343. mcp->out_mb = MBX_0;
  344. }
  345. mcp->mb[1] = LSW(risc_addr);
  346. mcp->mb[2] = MSW(req_dma);
  347. mcp->mb[3] = LSW(req_dma);
  348. mcp->mb[6] = MSW(MSD(req_dma));
  349. mcp->mb[7] = LSW(MSD(req_dma));
  350. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  351. if (IS_FWI2_CAPABLE(ha)) {
  352. mcp->mb[4] = MSW(risc_code_size);
  353. mcp->mb[5] = LSW(risc_code_size);
  354. mcp->out_mb |= MBX_5|MBX_4;
  355. } else {
  356. mcp->mb[4] = LSW(risc_code_size);
  357. mcp->out_mb |= MBX_4;
  358. }
  359. mcp->in_mb = MBX_0;
  360. mcp->tov = MBX_TOV_SECONDS;
  361. mcp->flags = 0;
  362. rval = qla2x00_mailbox_command(vha, mcp);
  363. if (rval != QLA_SUCCESS) {
  364. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  365. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  366. } else {
  367. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
  368. "Done %s.\n", __func__);
  369. }
  370. return rval;
  371. }
  372. #define EXTENDED_BB_CREDITS BIT_0
  373. /*
  374. * qla2x00_execute_fw
  375. * Start adapter firmware.
  376. *
  377. * Input:
  378. * ha = adapter block pointer.
  379. * TARGET_QUEUE_LOCK must be released.
  380. * ADAPTER_STATE_LOCK must be released.
  381. *
  382. * Returns:
  383. * qla2x00 local function return status code.
  384. *
  385. * Context:
  386. * Kernel context.
  387. */
  388. int
  389. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  390. {
  391. int rval;
  392. struct qla_hw_data *ha = vha->hw;
  393. mbx_cmd_t mc;
  394. mbx_cmd_t *mcp = &mc;
  395. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
  396. "Entered %s.\n", __func__);
  397. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  398. mcp->out_mb = MBX_0;
  399. mcp->in_mb = MBX_0;
  400. if (IS_FWI2_CAPABLE(ha)) {
  401. mcp->mb[1] = MSW(risc_addr);
  402. mcp->mb[2] = LSW(risc_addr);
  403. mcp->mb[3] = 0;
  404. if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
  405. struct nvram_81xx *nv = ha->nvram;
  406. mcp->mb[4] = (nv->enhanced_features &
  407. EXTENDED_BB_CREDITS);
  408. } else
  409. mcp->mb[4] = 0;
  410. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  411. mcp->in_mb |= MBX_1;
  412. } else {
  413. mcp->mb[1] = LSW(risc_addr);
  414. mcp->out_mb |= MBX_1;
  415. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  416. mcp->mb[2] = 0;
  417. mcp->out_mb |= MBX_2;
  418. }
  419. }
  420. mcp->tov = MBX_TOV_SECONDS;
  421. mcp->flags = 0;
  422. rval = qla2x00_mailbox_command(vha, mcp);
  423. if (rval != QLA_SUCCESS) {
  424. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  425. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  426. } else {
  427. if (IS_FWI2_CAPABLE(ha)) {
  428. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
  429. "Done exchanges=%x.\n", mcp->mb[1]);
  430. } else {
  431. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
  432. "Done %s.\n", __func__);
  433. }
  434. }
  435. return rval;
  436. }
  437. /*
  438. * qla2x00_get_fw_version
  439. * Get firmware version.
  440. *
  441. * Input:
  442. * ha: adapter state pointer.
  443. * major: pointer for major number.
  444. * minor: pointer for minor number.
  445. * subminor: pointer for subminor number.
  446. *
  447. * Returns:
  448. * qla2x00 local function return status code.
  449. *
  450. * Context:
  451. * Kernel context.
  452. */
  453. int
  454. qla2x00_get_fw_version(scsi_qla_host_t *vha)
  455. {
  456. int rval;
  457. mbx_cmd_t mc;
  458. mbx_cmd_t *mcp = &mc;
  459. struct qla_hw_data *ha = vha->hw;
  460. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
  461. "Entered %s.\n", __func__);
  462. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  463. mcp->out_mb = MBX_0;
  464. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  465. if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha))
  466. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  467. if (IS_FWI2_CAPABLE(ha))
  468. mcp->in_mb |= MBX_17|MBX_16|MBX_15;
  469. mcp->flags = 0;
  470. mcp->tov = MBX_TOV_SECONDS;
  471. rval = qla2x00_mailbox_command(vha, mcp);
  472. if (rval != QLA_SUCCESS)
  473. goto failed;
  474. /* Return mailbox data. */
  475. ha->fw_major_version = mcp->mb[1];
  476. ha->fw_minor_version = mcp->mb[2];
  477. ha->fw_subminor_version = mcp->mb[3];
  478. ha->fw_attributes = mcp->mb[6];
  479. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  480. ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
  481. else
  482. ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
  483. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw)) {
  484. ha->mpi_version[0] = mcp->mb[10] & 0xff;
  485. ha->mpi_version[1] = mcp->mb[11] >> 8;
  486. ha->mpi_version[2] = mcp->mb[11] & 0xff;
  487. ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
  488. ha->phy_version[0] = mcp->mb[8] & 0xff;
  489. ha->phy_version[1] = mcp->mb[9] >> 8;
  490. ha->phy_version[2] = mcp->mb[9] & 0xff;
  491. }
  492. if (IS_FWI2_CAPABLE(ha)) {
  493. ha->fw_attributes_h = mcp->mb[15];
  494. ha->fw_attributes_ext[0] = mcp->mb[16];
  495. ha->fw_attributes_ext[1] = mcp->mb[17];
  496. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
  497. "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
  498. __func__, mcp->mb[15], mcp->mb[6]);
  499. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
  500. "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
  501. __func__, mcp->mb[17], mcp->mb[16]);
  502. }
  503. failed:
  504. if (rval != QLA_SUCCESS) {
  505. /*EMPTY*/
  506. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  507. } else {
  508. /*EMPTY*/
  509. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
  510. "Done %s.\n", __func__);
  511. }
  512. return rval;
  513. }
  514. /*
  515. * qla2x00_get_fw_options
  516. * Set firmware options.
  517. *
  518. * Input:
  519. * ha = adapter block pointer.
  520. * fwopt = pointer for firmware options.
  521. *
  522. * Returns:
  523. * qla2x00 local function return status code.
  524. *
  525. * Context:
  526. * Kernel context.
  527. */
  528. int
  529. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  530. {
  531. int rval;
  532. mbx_cmd_t mc;
  533. mbx_cmd_t *mcp = &mc;
  534. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
  535. "Entered %s.\n", __func__);
  536. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  537. mcp->out_mb = MBX_0;
  538. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  539. mcp->tov = MBX_TOV_SECONDS;
  540. mcp->flags = 0;
  541. rval = qla2x00_mailbox_command(vha, mcp);
  542. if (rval != QLA_SUCCESS) {
  543. /*EMPTY*/
  544. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  545. } else {
  546. fwopts[0] = mcp->mb[0];
  547. fwopts[1] = mcp->mb[1];
  548. fwopts[2] = mcp->mb[2];
  549. fwopts[3] = mcp->mb[3];
  550. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
  551. "Done %s.\n", __func__);
  552. }
  553. return rval;
  554. }
  555. /*
  556. * qla2x00_set_fw_options
  557. * Set firmware options.
  558. *
  559. * Input:
  560. * ha = adapter block pointer.
  561. * fwopt = pointer for firmware options.
  562. *
  563. * Returns:
  564. * qla2x00 local function return status code.
  565. *
  566. * Context:
  567. * Kernel context.
  568. */
  569. int
  570. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  571. {
  572. int rval;
  573. mbx_cmd_t mc;
  574. mbx_cmd_t *mcp = &mc;
  575. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
  576. "Entered %s.\n", __func__);
  577. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  578. mcp->mb[1] = fwopts[1];
  579. mcp->mb[2] = fwopts[2];
  580. mcp->mb[3] = fwopts[3];
  581. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  582. mcp->in_mb = MBX_0;
  583. if (IS_FWI2_CAPABLE(vha->hw)) {
  584. mcp->in_mb |= MBX_1;
  585. } else {
  586. mcp->mb[10] = fwopts[10];
  587. mcp->mb[11] = fwopts[11];
  588. mcp->mb[12] = 0; /* Undocumented, but used */
  589. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  590. }
  591. mcp->tov = MBX_TOV_SECONDS;
  592. mcp->flags = 0;
  593. rval = qla2x00_mailbox_command(vha, mcp);
  594. fwopts[0] = mcp->mb[0];
  595. if (rval != QLA_SUCCESS) {
  596. /*EMPTY*/
  597. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  598. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  599. } else {
  600. /*EMPTY*/
  601. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
  602. "Done %s.\n", __func__);
  603. }
  604. return rval;
  605. }
  606. /*
  607. * qla2x00_mbx_reg_test
  608. * Mailbox register wrap test.
  609. *
  610. * Input:
  611. * ha = adapter block pointer.
  612. * TARGET_QUEUE_LOCK must be released.
  613. * ADAPTER_STATE_LOCK must be released.
  614. *
  615. * Returns:
  616. * qla2x00 local function return status code.
  617. *
  618. * Context:
  619. * Kernel context.
  620. */
  621. int
  622. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  623. {
  624. int rval;
  625. mbx_cmd_t mc;
  626. mbx_cmd_t *mcp = &mc;
  627. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
  628. "Entered %s.\n", __func__);
  629. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  630. mcp->mb[1] = 0xAAAA;
  631. mcp->mb[2] = 0x5555;
  632. mcp->mb[3] = 0xAA55;
  633. mcp->mb[4] = 0x55AA;
  634. mcp->mb[5] = 0xA5A5;
  635. mcp->mb[6] = 0x5A5A;
  636. mcp->mb[7] = 0x2525;
  637. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  638. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  639. mcp->tov = MBX_TOV_SECONDS;
  640. mcp->flags = 0;
  641. rval = qla2x00_mailbox_command(vha, mcp);
  642. if (rval == QLA_SUCCESS) {
  643. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  644. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  645. rval = QLA_FUNCTION_FAILED;
  646. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  647. mcp->mb[7] != 0x2525)
  648. rval = QLA_FUNCTION_FAILED;
  649. }
  650. if (rval != QLA_SUCCESS) {
  651. /*EMPTY*/
  652. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  653. } else {
  654. /*EMPTY*/
  655. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
  656. "Done %s.\n", __func__);
  657. }
  658. return rval;
  659. }
  660. /*
  661. * qla2x00_verify_checksum
  662. * Verify firmware checksum.
  663. *
  664. * Input:
  665. * ha = adapter block pointer.
  666. * TARGET_QUEUE_LOCK must be released.
  667. * ADAPTER_STATE_LOCK must be released.
  668. *
  669. * Returns:
  670. * qla2x00 local function return status code.
  671. *
  672. * Context:
  673. * Kernel context.
  674. */
  675. int
  676. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  677. {
  678. int rval;
  679. mbx_cmd_t mc;
  680. mbx_cmd_t *mcp = &mc;
  681. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
  682. "Entered %s.\n", __func__);
  683. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  684. mcp->out_mb = MBX_0;
  685. mcp->in_mb = MBX_0;
  686. if (IS_FWI2_CAPABLE(vha->hw)) {
  687. mcp->mb[1] = MSW(risc_addr);
  688. mcp->mb[2] = LSW(risc_addr);
  689. mcp->out_mb |= MBX_2|MBX_1;
  690. mcp->in_mb |= MBX_2|MBX_1;
  691. } else {
  692. mcp->mb[1] = LSW(risc_addr);
  693. mcp->out_mb |= MBX_1;
  694. mcp->in_mb |= MBX_1;
  695. }
  696. mcp->tov = MBX_TOV_SECONDS;
  697. mcp->flags = 0;
  698. rval = qla2x00_mailbox_command(vha, mcp);
  699. if (rval != QLA_SUCCESS) {
  700. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  701. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  702. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  703. } else {
  704. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
  705. "Done %s.\n", __func__);
  706. }
  707. return rval;
  708. }
  709. /*
  710. * qla2x00_issue_iocb
  711. * Issue IOCB using mailbox command
  712. *
  713. * Input:
  714. * ha = adapter state pointer.
  715. * buffer = buffer pointer.
  716. * phys_addr = physical address of buffer.
  717. * size = size of buffer.
  718. * TARGET_QUEUE_LOCK must be released.
  719. * ADAPTER_STATE_LOCK must be released.
  720. *
  721. * Returns:
  722. * qla2x00 local function return status code.
  723. *
  724. * Context:
  725. * Kernel context.
  726. */
  727. int
  728. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  729. dma_addr_t phys_addr, size_t size, uint32_t tov)
  730. {
  731. int rval;
  732. mbx_cmd_t mc;
  733. mbx_cmd_t *mcp = &mc;
  734. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
  735. "Entered %s.\n", __func__);
  736. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  737. mcp->mb[1] = 0;
  738. mcp->mb[2] = MSW(phys_addr);
  739. mcp->mb[3] = LSW(phys_addr);
  740. mcp->mb[6] = MSW(MSD(phys_addr));
  741. mcp->mb[7] = LSW(MSD(phys_addr));
  742. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  743. mcp->in_mb = MBX_2|MBX_0;
  744. mcp->tov = tov;
  745. mcp->flags = 0;
  746. rval = qla2x00_mailbox_command(vha, mcp);
  747. if (rval != QLA_SUCCESS) {
  748. /*EMPTY*/
  749. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  750. } else {
  751. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  752. /* Mask reserved bits. */
  753. sts_entry->entry_status &=
  754. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  755. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
  756. "Done %s.\n", __func__);
  757. }
  758. return rval;
  759. }
  760. int
  761. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  762. size_t size)
  763. {
  764. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  765. MBX_TOV_SECONDS);
  766. }
  767. /*
  768. * qla2x00_abort_command
  769. * Abort command aborts a specified IOCB.
  770. *
  771. * Input:
  772. * ha = adapter block pointer.
  773. * sp = SB structure pointer.
  774. *
  775. * Returns:
  776. * qla2x00 local function return status code.
  777. *
  778. * Context:
  779. * Kernel context.
  780. */
  781. int
  782. qla2x00_abort_command(srb_t *sp)
  783. {
  784. unsigned long flags = 0;
  785. int rval;
  786. uint32_t handle = 0;
  787. mbx_cmd_t mc;
  788. mbx_cmd_t *mcp = &mc;
  789. fc_port_t *fcport = sp->fcport;
  790. scsi_qla_host_t *vha = fcport->vha;
  791. struct qla_hw_data *ha = vha->hw;
  792. struct req_que *req = vha->req;
  793. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  794. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
  795. "Entered %s.\n", __func__);
  796. spin_lock_irqsave(&ha->hardware_lock, flags);
  797. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  798. if (req->outstanding_cmds[handle] == sp)
  799. break;
  800. }
  801. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  802. if (handle == req->num_outstanding_cmds) {
  803. /* command not found */
  804. return QLA_FUNCTION_FAILED;
  805. }
  806. mcp->mb[0] = MBC_ABORT_COMMAND;
  807. if (HAS_EXTENDED_IDS(ha))
  808. mcp->mb[1] = fcport->loop_id;
  809. else
  810. mcp->mb[1] = fcport->loop_id << 8;
  811. mcp->mb[2] = (uint16_t)handle;
  812. mcp->mb[3] = (uint16_t)(handle >> 16);
  813. mcp->mb[6] = (uint16_t)cmd->device->lun;
  814. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  815. mcp->in_mb = MBX_0;
  816. mcp->tov = MBX_TOV_SECONDS;
  817. mcp->flags = 0;
  818. rval = qla2x00_mailbox_command(vha, mcp);
  819. if (rval != QLA_SUCCESS) {
  820. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  821. } else {
  822. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
  823. "Done %s.\n", __func__);
  824. }
  825. return rval;
  826. }
  827. int
  828. qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  829. {
  830. int rval, rval2;
  831. mbx_cmd_t mc;
  832. mbx_cmd_t *mcp = &mc;
  833. scsi_qla_host_t *vha;
  834. struct req_que *req;
  835. struct rsp_que *rsp;
  836. l = l;
  837. vha = fcport->vha;
  838. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
  839. "Entered %s.\n", __func__);
  840. req = vha->hw->req_q_map[0];
  841. rsp = req->rsp;
  842. mcp->mb[0] = MBC_ABORT_TARGET;
  843. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  844. if (HAS_EXTENDED_IDS(vha->hw)) {
  845. mcp->mb[1] = fcport->loop_id;
  846. mcp->mb[10] = 0;
  847. mcp->out_mb |= MBX_10;
  848. } else {
  849. mcp->mb[1] = fcport->loop_id << 8;
  850. }
  851. mcp->mb[2] = vha->hw->loop_reset_delay;
  852. mcp->mb[9] = vha->vp_idx;
  853. mcp->in_mb = MBX_0;
  854. mcp->tov = MBX_TOV_SECONDS;
  855. mcp->flags = 0;
  856. rval = qla2x00_mailbox_command(vha, mcp);
  857. if (rval != QLA_SUCCESS) {
  858. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
  859. "Failed=%x.\n", rval);
  860. }
  861. /* Issue marker IOCB. */
  862. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  863. MK_SYNC_ID);
  864. if (rval2 != QLA_SUCCESS) {
  865. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  866. "Failed to issue marker IOCB (%x).\n", rval2);
  867. } else {
  868. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
  869. "Done %s.\n", __func__);
  870. }
  871. return rval;
  872. }
  873. int
  874. qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  875. {
  876. int rval, rval2;
  877. mbx_cmd_t mc;
  878. mbx_cmd_t *mcp = &mc;
  879. scsi_qla_host_t *vha;
  880. struct req_que *req;
  881. struct rsp_que *rsp;
  882. vha = fcport->vha;
  883. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
  884. "Entered %s.\n", __func__);
  885. req = vha->hw->req_q_map[0];
  886. rsp = req->rsp;
  887. mcp->mb[0] = MBC_LUN_RESET;
  888. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  889. if (HAS_EXTENDED_IDS(vha->hw))
  890. mcp->mb[1] = fcport->loop_id;
  891. else
  892. mcp->mb[1] = fcport->loop_id << 8;
  893. mcp->mb[2] = l;
  894. mcp->mb[3] = 0;
  895. mcp->mb[9] = vha->vp_idx;
  896. mcp->in_mb = MBX_0;
  897. mcp->tov = MBX_TOV_SECONDS;
  898. mcp->flags = 0;
  899. rval = qla2x00_mailbox_command(vha, mcp);
  900. if (rval != QLA_SUCCESS) {
  901. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  902. }
  903. /* Issue marker IOCB. */
  904. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  905. MK_SYNC_ID_LUN);
  906. if (rval2 != QLA_SUCCESS) {
  907. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  908. "Failed to issue marker IOCB (%x).\n", rval2);
  909. } else {
  910. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
  911. "Done %s.\n", __func__);
  912. }
  913. return rval;
  914. }
  915. /*
  916. * qla2x00_get_adapter_id
  917. * Get adapter ID and topology.
  918. *
  919. * Input:
  920. * ha = adapter block pointer.
  921. * id = pointer for loop ID.
  922. * al_pa = pointer for AL_PA.
  923. * area = pointer for area.
  924. * domain = pointer for domain.
  925. * top = pointer for topology.
  926. * TARGET_QUEUE_LOCK must be released.
  927. * ADAPTER_STATE_LOCK must be released.
  928. *
  929. * Returns:
  930. * qla2x00 local function return status code.
  931. *
  932. * Context:
  933. * Kernel context.
  934. */
  935. int
  936. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  937. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  938. {
  939. int rval;
  940. mbx_cmd_t mc;
  941. mbx_cmd_t *mcp = &mc;
  942. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
  943. "Entered %s.\n", __func__);
  944. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  945. mcp->mb[9] = vha->vp_idx;
  946. mcp->out_mb = MBX_9|MBX_0;
  947. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  948. if (IS_CNA_CAPABLE(vha->hw))
  949. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  950. mcp->tov = MBX_TOV_SECONDS;
  951. mcp->flags = 0;
  952. rval = qla2x00_mailbox_command(vha, mcp);
  953. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  954. rval = QLA_COMMAND_ERROR;
  955. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  956. rval = QLA_INVALID_COMMAND;
  957. /* Return data. */
  958. *id = mcp->mb[1];
  959. *al_pa = LSB(mcp->mb[2]);
  960. *area = MSB(mcp->mb[2]);
  961. *domain = LSB(mcp->mb[3]);
  962. *top = mcp->mb[6];
  963. *sw_cap = mcp->mb[7];
  964. if (rval != QLA_SUCCESS) {
  965. /*EMPTY*/
  966. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  967. } else {
  968. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
  969. "Done %s.\n", __func__);
  970. if (IS_CNA_CAPABLE(vha->hw)) {
  971. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  972. vha->fcoe_fcf_idx = mcp->mb[10];
  973. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  974. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  975. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  976. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  977. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  978. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  979. }
  980. }
  981. return rval;
  982. }
  983. /*
  984. * qla2x00_get_retry_cnt
  985. * Get current firmware login retry count and delay.
  986. *
  987. * Input:
  988. * ha = adapter block pointer.
  989. * retry_cnt = pointer to login retry count.
  990. * tov = pointer to login timeout value.
  991. *
  992. * Returns:
  993. * qla2x00 local function return status code.
  994. *
  995. * Context:
  996. * Kernel context.
  997. */
  998. int
  999. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  1000. uint16_t *r_a_tov)
  1001. {
  1002. int rval;
  1003. uint16_t ratov;
  1004. mbx_cmd_t mc;
  1005. mbx_cmd_t *mcp = &mc;
  1006. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
  1007. "Entered %s.\n", __func__);
  1008. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  1009. mcp->out_mb = MBX_0;
  1010. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1011. mcp->tov = MBX_TOV_SECONDS;
  1012. mcp->flags = 0;
  1013. rval = qla2x00_mailbox_command(vha, mcp);
  1014. if (rval != QLA_SUCCESS) {
  1015. /*EMPTY*/
  1016. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  1017. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1018. } else {
  1019. /* Convert returned data and check our values. */
  1020. *r_a_tov = mcp->mb[3] / 2;
  1021. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  1022. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  1023. /* Update to the larger values */
  1024. *retry_cnt = (uint8_t)mcp->mb[1];
  1025. *tov = ratov;
  1026. }
  1027. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
  1028. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  1029. }
  1030. return rval;
  1031. }
  1032. /*
  1033. * qla2x00_init_firmware
  1034. * Initialize adapter firmware.
  1035. *
  1036. * Input:
  1037. * ha = adapter block pointer.
  1038. * dptr = Initialization control block pointer.
  1039. * size = size of initialization control block.
  1040. * TARGET_QUEUE_LOCK must be released.
  1041. * ADAPTER_STATE_LOCK must be released.
  1042. *
  1043. * Returns:
  1044. * qla2x00 local function return status code.
  1045. *
  1046. * Context:
  1047. * Kernel context.
  1048. */
  1049. int
  1050. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1051. {
  1052. int rval;
  1053. mbx_cmd_t mc;
  1054. mbx_cmd_t *mcp = &mc;
  1055. struct qla_hw_data *ha = vha->hw;
  1056. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
  1057. "Entered %s.\n", __func__);
  1058. if (IS_QLA82XX(ha) && ql2xdbwr)
  1059. qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
  1060. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1061. if (ha->flags.npiv_supported)
  1062. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1063. else
  1064. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1065. mcp->mb[1] = 0;
  1066. mcp->mb[2] = MSW(ha->init_cb_dma);
  1067. mcp->mb[3] = LSW(ha->init_cb_dma);
  1068. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1069. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1070. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1071. if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
  1072. mcp->mb[1] = BIT_0;
  1073. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1074. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1075. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1076. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1077. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1078. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1079. }
  1080. /* 1 and 2 should normally be captured. */
  1081. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  1082. if (IS_QLA83XX(ha))
  1083. /* mb3 is additional info about the installed SFP. */
  1084. mcp->in_mb |= MBX_3;
  1085. mcp->buf_size = size;
  1086. mcp->flags = MBX_DMA_OUT;
  1087. mcp->tov = MBX_TOV_SECONDS;
  1088. rval = qla2x00_mailbox_command(vha, mcp);
  1089. if (rval != QLA_SUCCESS) {
  1090. /*EMPTY*/
  1091. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1092. "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
  1093. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
  1094. } else {
  1095. /*EMPTY*/
  1096. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
  1097. "Done %s.\n", __func__);
  1098. }
  1099. return rval;
  1100. }
  1101. /*
  1102. * qla2x00_get_node_name_list
  1103. * Issue get node name list mailbox command, kmalloc()
  1104. * and return the resulting list. Caller must kfree() it!
  1105. *
  1106. * Input:
  1107. * ha = adapter state pointer.
  1108. * out_data = resulting list
  1109. * out_len = length of the resulting list
  1110. *
  1111. * Returns:
  1112. * qla2x00 local function return status code.
  1113. *
  1114. * Context:
  1115. * Kernel context.
  1116. */
  1117. int
  1118. qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
  1119. {
  1120. struct qla_hw_data *ha = vha->hw;
  1121. struct qla_port_24xx_data *list = NULL;
  1122. void *pmap;
  1123. mbx_cmd_t mc;
  1124. dma_addr_t pmap_dma;
  1125. ulong dma_size;
  1126. int rval, left;
  1127. left = 1;
  1128. while (left > 0) {
  1129. dma_size = left * sizeof(*list);
  1130. pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
  1131. &pmap_dma, GFP_KERNEL);
  1132. if (!pmap) {
  1133. ql_log(ql_log_warn, vha, 0x113f,
  1134. "%s(%ld): DMA Alloc failed of %ld\n",
  1135. __func__, vha->host_no, dma_size);
  1136. rval = QLA_MEMORY_ALLOC_FAILED;
  1137. goto out;
  1138. }
  1139. mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
  1140. mc.mb[1] = BIT_1 | BIT_3;
  1141. mc.mb[2] = MSW(pmap_dma);
  1142. mc.mb[3] = LSW(pmap_dma);
  1143. mc.mb[6] = MSW(MSD(pmap_dma));
  1144. mc.mb[7] = LSW(MSD(pmap_dma));
  1145. mc.mb[8] = dma_size;
  1146. mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
  1147. mc.in_mb = MBX_0|MBX_1;
  1148. mc.tov = 30;
  1149. mc.flags = MBX_DMA_IN;
  1150. rval = qla2x00_mailbox_command(vha, &mc);
  1151. if (rval != QLA_SUCCESS) {
  1152. if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
  1153. (mc.mb[1] == 0xA)) {
  1154. left += le16_to_cpu(mc.mb[2]) /
  1155. sizeof(struct qla_port_24xx_data);
  1156. goto restart;
  1157. }
  1158. goto out_free;
  1159. }
  1160. left = 0;
  1161. list = kzalloc(dma_size, GFP_KERNEL);
  1162. if (!list) {
  1163. ql_log(ql_log_warn, vha, 0x1140,
  1164. "%s(%ld): failed to allocate node names list "
  1165. "structure.\n", __func__, vha->host_no);
  1166. rval = QLA_MEMORY_ALLOC_FAILED;
  1167. goto out_free;
  1168. }
  1169. memcpy(list, pmap, dma_size);
  1170. restart:
  1171. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1172. }
  1173. *out_data = list;
  1174. *out_len = dma_size;
  1175. out:
  1176. return rval;
  1177. out_free:
  1178. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1179. return rval;
  1180. }
  1181. /*
  1182. * qla2x00_get_port_database
  1183. * Issue normal/enhanced get port database mailbox command
  1184. * and copy device name as necessary.
  1185. *
  1186. * Input:
  1187. * ha = adapter state pointer.
  1188. * dev = structure pointer.
  1189. * opt = enhanced cmd option byte.
  1190. *
  1191. * Returns:
  1192. * qla2x00 local function return status code.
  1193. *
  1194. * Context:
  1195. * Kernel context.
  1196. */
  1197. int
  1198. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1199. {
  1200. int rval;
  1201. mbx_cmd_t mc;
  1202. mbx_cmd_t *mcp = &mc;
  1203. port_database_t *pd;
  1204. struct port_database_24xx *pd24;
  1205. dma_addr_t pd_dma;
  1206. struct qla_hw_data *ha = vha->hw;
  1207. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
  1208. "Entered %s.\n", __func__);
  1209. pd24 = NULL;
  1210. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1211. if (pd == NULL) {
  1212. ql_log(ql_log_warn, vha, 0x1050,
  1213. "Failed to allocate port database structure.\n");
  1214. return QLA_MEMORY_ALLOC_FAILED;
  1215. }
  1216. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1217. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1218. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1219. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1220. mcp->mb[2] = MSW(pd_dma);
  1221. mcp->mb[3] = LSW(pd_dma);
  1222. mcp->mb[6] = MSW(MSD(pd_dma));
  1223. mcp->mb[7] = LSW(MSD(pd_dma));
  1224. mcp->mb[9] = vha->vp_idx;
  1225. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1226. mcp->in_mb = MBX_0;
  1227. if (IS_FWI2_CAPABLE(ha)) {
  1228. mcp->mb[1] = fcport->loop_id;
  1229. mcp->mb[10] = opt;
  1230. mcp->out_mb |= MBX_10|MBX_1;
  1231. mcp->in_mb |= MBX_1;
  1232. } else if (HAS_EXTENDED_IDS(ha)) {
  1233. mcp->mb[1] = fcport->loop_id;
  1234. mcp->mb[10] = opt;
  1235. mcp->out_mb |= MBX_10|MBX_1;
  1236. } else {
  1237. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1238. mcp->out_mb |= MBX_1;
  1239. }
  1240. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1241. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1242. mcp->flags = MBX_DMA_IN;
  1243. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1244. rval = qla2x00_mailbox_command(vha, mcp);
  1245. if (rval != QLA_SUCCESS)
  1246. goto gpd_error_out;
  1247. if (IS_FWI2_CAPABLE(ha)) {
  1248. uint64_t zero = 0;
  1249. pd24 = (struct port_database_24xx *) pd;
  1250. /* Check for logged in state. */
  1251. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1252. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1253. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1254. "Unable to verify login-state (%x/%x) for "
  1255. "loop_id %x.\n", pd24->current_login_state,
  1256. pd24->last_login_state, fcport->loop_id);
  1257. rval = QLA_FUNCTION_FAILED;
  1258. goto gpd_error_out;
  1259. }
  1260. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1261. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1262. memcmp(fcport->port_name, pd24->port_name, 8))) {
  1263. /* We lost the device mid way. */
  1264. rval = QLA_NOT_LOGGED_IN;
  1265. goto gpd_error_out;
  1266. }
  1267. /* Names are little-endian. */
  1268. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1269. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1270. /* Get port_id of device. */
  1271. fcport->d_id.b.domain = pd24->port_id[0];
  1272. fcport->d_id.b.area = pd24->port_id[1];
  1273. fcport->d_id.b.al_pa = pd24->port_id[2];
  1274. fcport->d_id.b.rsvd_1 = 0;
  1275. /* If not target must be initiator or unknown type. */
  1276. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1277. fcport->port_type = FCT_INITIATOR;
  1278. else
  1279. fcport->port_type = FCT_TARGET;
  1280. /* Passback COS information. */
  1281. fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
  1282. FC_COS_CLASS2 : FC_COS_CLASS3;
  1283. if (pd24->prli_svc_param_word_3[0] & BIT_7)
  1284. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1285. } else {
  1286. uint64_t zero = 0;
  1287. /* Check for logged in state. */
  1288. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1289. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1290. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1291. "Unable to verify login-state (%x/%x) - "
  1292. "portid=%02x%02x%02x.\n", pd->master_state,
  1293. pd->slave_state, fcport->d_id.b.domain,
  1294. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1295. rval = QLA_FUNCTION_FAILED;
  1296. goto gpd_error_out;
  1297. }
  1298. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1299. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1300. memcmp(fcport->port_name, pd->port_name, 8))) {
  1301. /* We lost the device mid way. */
  1302. rval = QLA_NOT_LOGGED_IN;
  1303. goto gpd_error_out;
  1304. }
  1305. /* Names are little-endian. */
  1306. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1307. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1308. /* Get port_id of device. */
  1309. fcport->d_id.b.domain = pd->port_id[0];
  1310. fcport->d_id.b.area = pd->port_id[3];
  1311. fcport->d_id.b.al_pa = pd->port_id[2];
  1312. fcport->d_id.b.rsvd_1 = 0;
  1313. /* If not target must be initiator or unknown type. */
  1314. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1315. fcport->port_type = FCT_INITIATOR;
  1316. else
  1317. fcport->port_type = FCT_TARGET;
  1318. /* Passback COS information. */
  1319. fcport->supported_classes = (pd->options & BIT_4) ?
  1320. FC_COS_CLASS2: FC_COS_CLASS3;
  1321. }
  1322. gpd_error_out:
  1323. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1324. if (rval != QLA_SUCCESS) {
  1325. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1326. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1327. mcp->mb[0], mcp->mb[1]);
  1328. } else {
  1329. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
  1330. "Done %s.\n", __func__);
  1331. }
  1332. return rval;
  1333. }
  1334. /*
  1335. * qla2x00_get_firmware_state
  1336. * Get adapter firmware state.
  1337. *
  1338. * Input:
  1339. * ha = adapter block pointer.
  1340. * dptr = pointer for firmware state.
  1341. * TARGET_QUEUE_LOCK must be released.
  1342. * ADAPTER_STATE_LOCK must be released.
  1343. *
  1344. * Returns:
  1345. * qla2x00 local function return status code.
  1346. *
  1347. * Context:
  1348. * Kernel context.
  1349. */
  1350. int
  1351. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1352. {
  1353. int rval;
  1354. mbx_cmd_t mc;
  1355. mbx_cmd_t *mcp = &mc;
  1356. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
  1357. "Entered %s.\n", __func__);
  1358. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1359. mcp->out_mb = MBX_0;
  1360. if (IS_FWI2_CAPABLE(vha->hw))
  1361. mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1362. else
  1363. mcp->in_mb = MBX_1|MBX_0;
  1364. mcp->tov = MBX_TOV_SECONDS;
  1365. mcp->flags = 0;
  1366. rval = qla2x00_mailbox_command(vha, mcp);
  1367. /* Return firmware states. */
  1368. states[0] = mcp->mb[1];
  1369. if (IS_FWI2_CAPABLE(vha->hw)) {
  1370. states[1] = mcp->mb[2];
  1371. states[2] = mcp->mb[3];
  1372. states[3] = mcp->mb[4];
  1373. states[4] = mcp->mb[5];
  1374. }
  1375. if (rval != QLA_SUCCESS) {
  1376. /*EMPTY*/
  1377. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1378. } else {
  1379. /*EMPTY*/
  1380. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
  1381. "Done %s.\n", __func__);
  1382. }
  1383. return rval;
  1384. }
  1385. /*
  1386. * qla2x00_get_port_name
  1387. * Issue get port name mailbox command.
  1388. * Returned name is in big endian format.
  1389. *
  1390. * Input:
  1391. * ha = adapter block pointer.
  1392. * loop_id = loop ID of device.
  1393. * name = pointer for name.
  1394. * TARGET_QUEUE_LOCK must be released.
  1395. * ADAPTER_STATE_LOCK must be released.
  1396. *
  1397. * Returns:
  1398. * qla2x00 local function return status code.
  1399. *
  1400. * Context:
  1401. * Kernel context.
  1402. */
  1403. int
  1404. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1405. uint8_t opt)
  1406. {
  1407. int rval;
  1408. mbx_cmd_t mc;
  1409. mbx_cmd_t *mcp = &mc;
  1410. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
  1411. "Entered %s.\n", __func__);
  1412. mcp->mb[0] = MBC_GET_PORT_NAME;
  1413. mcp->mb[9] = vha->vp_idx;
  1414. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1415. if (HAS_EXTENDED_IDS(vha->hw)) {
  1416. mcp->mb[1] = loop_id;
  1417. mcp->mb[10] = opt;
  1418. mcp->out_mb |= MBX_10;
  1419. } else {
  1420. mcp->mb[1] = loop_id << 8 | opt;
  1421. }
  1422. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1423. mcp->tov = MBX_TOV_SECONDS;
  1424. mcp->flags = 0;
  1425. rval = qla2x00_mailbox_command(vha, mcp);
  1426. if (rval != QLA_SUCCESS) {
  1427. /*EMPTY*/
  1428. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1429. } else {
  1430. if (name != NULL) {
  1431. /* This function returns name in big endian. */
  1432. name[0] = MSB(mcp->mb[2]);
  1433. name[1] = LSB(mcp->mb[2]);
  1434. name[2] = MSB(mcp->mb[3]);
  1435. name[3] = LSB(mcp->mb[3]);
  1436. name[4] = MSB(mcp->mb[6]);
  1437. name[5] = LSB(mcp->mb[6]);
  1438. name[6] = MSB(mcp->mb[7]);
  1439. name[7] = LSB(mcp->mb[7]);
  1440. }
  1441. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
  1442. "Done %s.\n", __func__);
  1443. }
  1444. return rval;
  1445. }
  1446. /*
  1447. * qla24xx_link_initialization
  1448. * Issue link initialization mailbox command.
  1449. *
  1450. * Input:
  1451. * ha = adapter block pointer.
  1452. * TARGET_QUEUE_LOCK must be released.
  1453. * ADAPTER_STATE_LOCK must be released.
  1454. *
  1455. * Returns:
  1456. * qla2x00 local function return status code.
  1457. *
  1458. * Context:
  1459. * Kernel context.
  1460. */
  1461. int
  1462. qla24xx_link_initialize(scsi_qla_host_t *vha)
  1463. {
  1464. int rval;
  1465. mbx_cmd_t mc;
  1466. mbx_cmd_t *mcp = &mc;
  1467. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
  1468. "Entered %s.\n", __func__);
  1469. if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
  1470. return QLA_FUNCTION_FAILED;
  1471. mcp->mb[0] = MBC_LINK_INITIALIZATION;
  1472. mcp->mb[1] = BIT_6|BIT_4;
  1473. mcp->mb[2] = 0;
  1474. mcp->mb[3] = 0;
  1475. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1476. mcp->in_mb = MBX_0;
  1477. mcp->tov = MBX_TOV_SECONDS;
  1478. mcp->flags = 0;
  1479. rval = qla2x00_mailbox_command(vha, mcp);
  1480. if (rval != QLA_SUCCESS) {
  1481. ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
  1482. } else {
  1483. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
  1484. "Done %s.\n", __func__);
  1485. }
  1486. return rval;
  1487. }
  1488. /*
  1489. * qla2x00_lip_reset
  1490. * Issue LIP reset mailbox command.
  1491. *
  1492. * Input:
  1493. * ha = adapter block pointer.
  1494. * TARGET_QUEUE_LOCK must be released.
  1495. * ADAPTER_STATE_LOCK must be released.
  1496. *
  1497. * Returns:
  1498. * qla2x00 local function return status code.
  1499. *
  1500. * Context:
  1501. * Kernel context.
  1502. */
  1503. int
  1504. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1505. {
  1506. int rval;
  1507. mbx_cmd_t mc;
  1508. mbx_cmd_t *mcp = &mc;
  1509. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
  1510. "Entered %s.\n", __func__);
  1511. if (IS_CNA_CAPABLE(vha->hw)) {
  1512. /* Logout across all FCFs. */
  1513. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1514. mcp->mb[1] = BIT_1;
  1515. mcp->mb[2] = 0;
  1516. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1517. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1518. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1519. mcp->mb[1] = BIT_6;
  1520. mcp->mb[2] = 0;
  1521. mcp->mb[3] = vha->hw->loop_reset_delay;
  1522. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1523. } else {
  1524. mcp->mb[0] = MBC_LIP_RESET;
  1525. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1526. if (HAS_EXTENDED_IDS(vha->hw)) {
  1527. mcp->mb[1] = 0x00ff;
  1528. mcp->mb[10] = 0;
  1529. mcp->out_mb |= MBX_10;
  1530. } else {
  1531. mcp->mb[1] = 0xff00;
  1532. }
  1533. mcp->mb[2] = vha->hw->loop_reset_delay;
  1534. mcp->mb[3] = 0;
  1535. }
  1536. mcp->in_mb = MBX_0;
  1537. mcp->tov = MBX_TOV_SECONDS;
  1538. mcp->flags = 0;
  1539. rval = qla2x00_mailbox_command(vha, mcp);
  1540. if (rval != QLA_SUCCESS) {
  1541. /*EMPTY*/
  1542. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1543. } else {
  1544. /*EMPTY*/
  1545. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
  1546. "Done %s.\n", __func__);
  1547. }
  1548. return rval;
  1549. }
  1550. /*
  1551. * qla2x00_send_sns
  1552. * Send SNS command.
  1553. *
  1554. * Input:
  1555. * ha = adapter block pointer.
  1556. * sns = pointer for command.
  1557. * cmd_size = command size.
  1558. * buf_size = response/command size.
  1559. * TARGET_QUEUE_LOCK must be released.
  1560. * ADAPTER_STATE_LOCK must be released.
  1561. *
  1562. * Returns:
  1563. * qla2x00 local function return status code.
  1564. *
  1565. * Context:
  1566. * Kernel context.
  1567. */
  1568. int
  1569. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1570. uint16_t cmd_size, size_t buf_size)
  1571. {
  1572. int rval;
  1573. mbx_cmd_t mc;
  1574. mbx_cmd_t *mcp = &mc;
  1575. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
  1576. "Entered %s.\n", __func__);
  1577. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
  1578. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1579. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1580. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1581. mcp->mb[1] = cmd_size;
  1582. mcp->mb[2] = MSW(sns_phys_address);
  1583. mcp->mb[3] = LSW(sns_phys_address);
  1584. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1585. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1586. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1587. mcp->in_mb = MBX_0|MBX_1;
  1588. mcp->buf_size = buf_size;
  1589. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1590. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1591. rval = qla2x00_mailbox_command(vha, mcp);
  1592. if (rval != QLA_SUCCESS) {
  1593. /*EMPTY*/
  1594. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1595. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1596. rval, mcp->mb[0], mcp->mb[1]);
  1597. } else {
  1598. /*EMPTY*/
  1599. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
  1600. "Done %s.\n", __func__);
  1601. }
  1602. return rval;
  1603. }
  1604. int
  1605. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1606. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1607. {
  1608. int rval;
  1609. struct logio_entry_24xx *lg;
  1610. dma_addr_t lg_dma;
  1611. uint32_t iop[2];
  1612. struct qla_hw_data *ha = vha->hw;
  1613. struct req_que *req;
  1614. struct rsp_que *rsp;
  1615. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
  1616. "Entered %s.\n", __func__);
  1617. if (ha->flags.cpu_affinity_enabled)
  1618. req = ha->req_q_map[0];
  1619. else
  1620. req = vha->req;
  1621. rsp = req->rsp;
  1622. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1623. if (lg == NULL) {
  1624. ql_log(ql_log_warn, vha, 0x1062,
  1625. "Failed to allocate login IOCB.\n");
  1626. return QLA_MEMORY_ALLOC_FAILED;
  1627. }
  1628. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1629. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1630. lg->entry_count = 1;
  1631. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1632. lg->nport_handle = cpu_to_le16(loop_id);
  1633. lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
  1634. if (opt & BIT_0)
  1635. lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
  1636. if (opt & BIT_1)
  1637. lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
  1638. lg->port_id[0] = al_pa;
  1639. lg->port_id[1] = area;
  1640. lg->port_id[2] = domain;
  1641. lg->vp_index = vha->vp_idx;
  1642. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1643. (ha->r_a_tov / 10 * 2) + 2);
  1644. if (rval != QLA_SUCCESS) {
  1645. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1646. "Failed to issue login IOCB (%x).\n", rval);
  1647. } else if (lg->entry_status != 0) {
  1648. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1649. "Failed to complete IOCB -- error status (%x).\n",
  1650. lg->entry_status);
  1651. rval = QLA_FUNCTION_FAILED;
  1652. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1653. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1654. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1655. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1656. "Failed to complete IOCB -- completion status (%x) "
  1657. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1658. iop[0], iop[1]);
  1659. switch (iop[0]) {
  1660. case LSC_SCODE_PORTID_USED:
  1661. mb[0] = MBS_PORT_ID_USED;
  1662. mb[1] = LSW(iop[1]);
  1663. break;
  1664. case LSC_SCODE_NPORT_USED:
  1665. mb[0] = MBS_LOOP_ID_USED;
  1666. break;
  1667. case LSC_SCODE_NOLINK:
  1668. case LSC_SCODE_NOIOCB:
  1669. case LSC_SCODE_NOXCB:
  1670. case LSC_SCODE_CMD_FAILED:
  1671. case LSC_SCODE_NOFABRIC:
  1672. case LSC_SCODE_FW_NOT_READY:
  1673. case LSC_SCODE_NOT_LOGGED_IN:
  1674. case LSC_SCODE_NOPCB:
  1675. case LSC_SCODE_ELS_REJECT:
  1676. case LSC_SCODE_CMD_PARAM_ERR:
  1677. case LSC_SCODE_NONPORT:
  1678. case LSC_SCODE_LOGGED_IN:
  1679. case LSC_SCODE_NOFLOGI_ACC:
  1680. default:
  1681. mb[0] = MBS_COMMAND_ERROR;
  1682. break;
  1683. }
  1684. } else {
  1685. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
  1686. "Done %s.\n", __func__);
  1687. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1688. mb[0] = MBS_COMMAND_COMPLETE;
  1689. mb[1] = 0;
  1690. if (iop[0] & BIT_4) {
  1691. if (iop[0] & BIT_8)
  1692. mb[1] |= BIT_1;
  1693. } else
  1694. mb[1] = BIT_0;
  1695. /* Passback COS information. */
  1696. mb[10] = 0;
  1697. if (lg->io_parameter[7] || lg->io_parameter[8])
  1698. mb[10] |= BIT_0; /* Class 2. */
  1699. if (lg->io_parameter[9] || lg->io_parameter[10])
  1700. mb[10] |= BIT_1; /* Class 3. */
  1701. if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
  1702. mb[10] |= BIT_7; /* Confirmed Completion
  1703. * Allowed
  1704. */
  1705. }
  1706. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1707. return rval;
  1708. }
  1709. /*
  1710. * qla2x00_login_fabric
  1711. * Issue login fabric port mailbox command.
  1712. *
  1713. * Input:
  1714. * ha = adapter block pointer.
  1715. * loop_id = device loop ID.
  1716. * domain = device domain.
  1717. * area = device area.
  1718. * al_pa = device AL_PA.
  1719. * status = pointer for return status.
  1720. * opt = command options.
  1721. * TARGET_QUEUE_LOCK must be released.
  1722. * ADAPTER_STATE_LOCK must be released.
  1723. *
  1724. * Returns:
  1725. * qla2x00 local function return status code.
  1726. *
  1727. * Context:
  1728. * Kernel context.
  1729. */
  1730. int
  1731. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1732. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1733. {
  1734. int rval;
  1735. mbx_cmd_t mc;
  1736. mbx_cmd_t *mcp = &mc;
  1737. struct qla_hw_data *ha = vha->hw;
  1738. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
  1739. "Entered %s.\n", __func__);
  1740. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1741. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1742. if (HAS_EXTENDED_IDS(ha)) {
  1743. mcp->mb[1] = loop_id;
  1744. mcp->mb[10] = opt;
  1745. mcp->out_mb |= MBX_10;
  1746. } else {
  1747. mcp->mb[1] = (loop_id << 8) | opt;
  1748. }
  1749. mcp->mb[2] = domain;
  1750. mcp->mb[3] = area << 8 | al_pa;
  1751. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1752. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1753. mcp->flags = 0;
  1754. rval = qla2x00_mailbox_command(vha, mcp);
  1755. /* Return mailbox statuses. */
  1756. if (mb != NULL) {
  1757. mb[0] = mcp->mb[0];
  1758. mb[1] = mcp->mb[1];
  1759. mb[2] = mcp->mb[2];
  1760. mb[6] = mcp->mb[6];
  1761. mb[7] = mcp->mb[7];
  1762. /* COS retrieved from Get-Port-Database mailbox command. */
  1763. mb[10] = 0;
  1764. }
  1765. if (rval != QLA_SUCCESS) {
  1766. /* RLU tmp code: need to change main mailbox_command function to
  1767. * return ok even when the mailbox completion value is not
  1768. * SUCCESS. The caller needs to be responsible to interpret
  1769. * the return values of this mailbox command if we're not
  1770. * to change too much of the existing code.
  1771. */
  1772. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1773. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1774. mcp->mb[0] == 0x4006)
  1775. rval = QLA_SUCCESS;
  1776. /*EMPTY*/
  1777. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1778. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1779. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1780. } else {
  1781. /*EMPTY*/
  1782. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
  1783. "Done %s.\n", __func__);
  1784. }
  1785. return rval;
  1786. }
  1787. /*
  1788. * qla2x00_login_local_device
  1789. * Issue login loop port mailbox command.
  1790. *
  1791. * Input:
  1792. * ha = adapter block pointer.
  1793. * loop_id = device loop ID.
  1794. * opt = command options.
  1795. *
  1796. * Returns:
  1797. * Return status code.
  1798. *
  1799. * Context:
  1800. * Kernel context.
  1801. *
  1802. */
  1803. int
  1804. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1805. uint16_t *mb_ret, uint8_t opt)
  1806. {
  1807. int rval;
  1808. mbx_cmd_t mc;
  1809. mbx_cmd_t *mcp = &mc;
  1810. struct qla_hw_data *ha = vha->hw;
  1811. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
  1812. "Entered %s.\n", __func__);
  1813. if (IS_FWI2_CAPABLE(ha))
  1814. return qla24xx_login_fabric(vha, fcport->loop_id,
  1815. fcport->d_id.b.domain, fcport->d_id.b.area,
  1816. fcport->d_id.b.al_pa, mb_ret, opt);
  1817. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1818. if (HAS_EXTENDED_IDS(ha))
  1819. mcp->mb[1] = fcport->loop_id;
  1820. else
  1821. mcp->mb[1] = fcport->loop_id << 8;
  1822. mcp->mb[2] = opt;
  1823. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1824. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1825. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1826. mcp->flags = 0;
  1827. rval = qla2x00_mailbox_command(vha, mcp);
  1828. /* Return mailbox statuses. */
  1829. if (mb_ret != NULL) {
  1830. mb_ret[0] = mcp->mb[0];
  1831. mb_ret[1] = mcp->mb[1];
  1832. mb_ret[6] = mcp->mb[6];
  1833. mb_ret[7] = mcp->mb[7];
  1834. }
  1835. if (rval != QLA_SUCCESS) {
  1836. /* AV tmp code: need to change main mailbox_command function to
  1837. * return ok even when the mailbox completion value is not
  1838. * SUCCESS. The caller needs to be responsible to interpret
  1839. * the return values of this mailbox command if we're not
  1840. * to change too much of the existing code.
  1841. */
  1842. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1843. rval = QLA_SUCCESS;
  1844. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1845. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1846. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1847. } else {
  1848. /*EMPTY*/
  1849. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
  1850. "Done %s.\n", __func__);
  1851. }
  1852. return (rval);
  1853. }
  1854. int
  1855. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1856. uint8_t area, uint8_t al_pa)
  1857. {
  1858. int rval;
  1859. struct logio_entry_24xx *lg;
  1860. dma_addr_t lg_dma;
  1861. struct qla_hw_data *ha = vha->hw;
  1862. struct req_que *req;
  1863. struct rsp_que *rsp;
  1864. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
  1865. "Entered %s.\n", __func__);
  1866. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1867. if (lg == NULL) {
  1868. ql_log(ql_log_warn, vha, 0x106e,
  1869. "Failed to allocate logout IOCB.\n");
  1870. return QLA_MEMORY_ALLOC_FAILED;
  1871. }
  1872. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1873. if (ql2xmaxqueues > 1)
  1874. req = ha->req_q_map[0];
  1875. else
  1876. req = vha->req;
  1877. rsp = req->rsp;
  1878. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1879. lg->entry_count = 1;
  1880. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1881. lg->nport_handle = cpu_to_le16(loop_id);
  1882. lg->control_flags =
  1883. __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1884. LCF_FREE_NPORT);
  1885. lg->port_id[0] = al_pa;
  1886. lg->port_id[1] = area;
  1887. lg->port_id[2] = domain;
  1888. lg->vp_index = vha->vp_idx;
  1889. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1890. (ha->r_a_tov / 10 * 2) + 2);
  1891. if (rval != QLA_SUCCESS) {
  1892. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1893. "Failed to issue logout IOCB (%x).\n", rval);
  1894. } else if (lg->entry_status != 0) {
  1895. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1896. "Failed to complete IOCB -- error status (%x).\n",
  1897. lg->entry_status);
  1898. rval = QLA_FUNCTION_FAILED;
  1899. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1900. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1901. "Failed to complete IOCB -- completion status (%x) "
  1902. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1903. le32_to_cpu(lg->io_parameter[0]),
  1904. le32_to_cpu(lg->io_parameter[1]));
  1905. } else {
  1906. /*EMPTY*/
  1907. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
  1908. "Done %s.\n", __func__);
  1909. }
  1910. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1911. return rval;
  1912. }
  1913. /*
  1914. * qla2x00_fabric_logout
  1915. * Issue logout fabric port mailbox command.
  1916. *
  1917. * Input:
  1918. * ha = adapter block pointer.
  1919. * loop_id = device loop ID.
  1920. * TARGET_QUEUE_LOCK must be released.
  1921. * ADAPTER_STATE_LOCK must be released.
  1922. *
  1923. * Returns:
  1924. * qla2x00 local function return status code.
  1925. *
  1926. * Context:
  1927. * Kernel context.
  1928. */
  1929. int
  1930. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1931. uint8_t area, uint8_t al_pa)
  1932. {
  1933. int rval;
  1934. mbx_cmd_t mc;
  1935. mbx_cmd_t *mcp = &mc;
  1936. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
  1937. "Entered %s.\n", __func__);
  1938. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1939. mcp->out_mb = MBX_1|MBX_0;
  1940. if (HAS_EXTENDED_IDS(vha->hw)) {
  1941. mcp->mb[1] = loop_id;
  1942. mcp->mb[10] = 0;
  1943. mcp->out_mb |= MBX_10;
  1944. } else {
  1945. mcp->mb[1] = loop_id << 8;
  1946. }
  1947. mcp->in_mb = MBX_1|MBX_0;
  1948. mcp->tov = MBX_TOV_SECONDS;
  1949. mcp->flags = 0;
  1950. rval = qla2x00_mailbox_command(vha, mcp);
  1951. if (rval != QLA_SUCCESS) {
  1952. /*EMPTY*/
  1953. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  1954. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  1955. } else {
  1956. /*EMPTY*/
  1957. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
  1958. "Done %s.\n", __func__);
  1959. }
  1960. return rval;
  1961. }
  1962. /*
  1963. * qla2x00_full_login_lip
  1964. * Issue full login LIP mailbox command.
  1965. *
  1966. * Input:
  1967. * ha = adapter block pointer.
  1968. * TARGET_QUEUE_LOCK must be released.
  1969. * ADAPTER_STATE_LOCK must be released.
  1970. *
  1971. * Returns:
  1972. * qla2x00 local function return status code.
  1973. *
  1974. * Context:
  1975. * Kernel context.
  1976. */
  1977. int
  1978. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  1979. {
  1980. int rval;
  1981. mbx_cmd_t mc;
  1982. mbx_cmd_t *mcp = &mc;
  1983. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
  1984. "Entered %s.\n", __func__);
  1985. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1986. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  1987. mcp->mb[2] = 0;
  1988. mcp->mb[3] = 0;
  1989. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1990. mcp->in_mb = MBX_0;
  1991. mcp->tov = MBX_TOV_SECONDS;
  1992. mcp->flags = 0;
  1993. rval = qla2x00_mailbox_command(vha, mcp);
  1994. if (rval != QLA_SUCCESS) {
  1995. /*EMPTY*/
  1996. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  1997. } else {
  1998. /*EMPTY*/
  1999. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
  2000. "Done %s.\n", __func__);
  2001. }
  2002. return rval;
  2003. }
  2004. /*
  2005. * qla2x00_get_id_list
  2006. *
  2007. * Input:
  2008. * ha = adapter block pointer.
  2009. *
  2010. * Returns:
  2011. * qla2x00 local function return status code.
  2012. *
  2013. * Context:
  2014. * Kernel context.
  2015. */
  2016. int
  2017. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  2018. uint16_t *entries)
  2019. {
  2020. int rval;
  2021. mbx_cmd_t mc;
  2022. mbx_cmd_t *mcp = &mc;
  2023. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
  2024. "Entered %s.\n", __func__);
  2025. if (id_list == NULL)
  2026. return QLA_FUNCTION_FAILED;
  2027. mcp->mb[0] = MBC_GET_ID_LIST;
  2028. mcp->out_mb = MBX_0;
  2029. if (IS_FWI2_CAPABLE(vha->hw)) {
  2030. mcp->mb[2] = MSW(id_list_dma);
  2031. mcp->mb[3] = LSW(id_list_dma);
  2032. mcp->mb[6] = MSW(MSD(id_list_dma));
  2033. mcp->mb[7] = LSW(MSD(id_list_dma));
  2034. mcp->mb[8] = 0;
  2035. mcp->mb[9] = vha->vp_idx;
  2036. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  2037. } else {
  2038. mcp->mb[1] = MSW(id_list_dma);
  2039. mcp->mb[2] = LSW(id_list_dma);
  2040. mcp->mb[3] = MSW(MSD(id_list_dma));
  2041. mcp->mb[6] = LSW(MSD(id_list_dma));
  2042. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  2043. }
  2044. mcp->in_mb = MBX_1|MBX_0;
  2045. mcp->tov = MBX_TOV_SECONDS;
  2046. mcp->flags = 0;
  2047. rval = qla2x00_mailbox_command(vha, mcp);
  2048. if (rval != QLA_SUCCESS) {
  2049. /*EMPTY*/
  2050. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  2051. } else {
  2052. *entries = mcp->mb[1];
  2053. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
  2054. "Done %s.\n", __func__);
  2055. }
  2056. return rval;
  2057. }
  2058. /*
  2059. * qla2x00_get_resource_cnts
  2060. * Get current firmware resource counts.
  2061. *
  2062. * Input:
  2063. * ha = adapter block pointer.
  2064. *
  2065. * Returns:
  2066. * qla2x00 local function return status code.
  2067. *
  2068. * Context:
  2069. * Kernel context.
  2070. */
  2071. int
  2072. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  2073. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  2074. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  2075. {
  2076. int rval;
  2077. mbx_cmd_t mc;
  2078. mbx_cmd_t *mcp = &mc;
  2079. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
  2080. "Entered %s.\n", __func__);
  2081. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  2082. mcp->out_mb = MBX_0;
  2083. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  2084. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  2085. mcp->in_mb |= MBX_12;
  2086. mcp->tov = MBX_TOV_SECONDS;
  2087. mcp->flags = 0;
  2088. rval = qla2x00_mailbox_command(vha, mcp);
  2089. if (rval != QLA_SUCCESS) {
  2090. /*EMPTY*/
  2091. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  2092. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2093. } else {
  2094. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
  2095. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  2096. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  2097. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  2098. mcp->mb[11], mcp->mb[12]);
  2099. if (cur_xchg_cnt)
  2100. *cur_xchg_cnt = mcp->mb[3];
  2101. if (orig_xchg_cnt)
  2102. *orig_xchg_cnt = mcp->mb[6];
  2103. if (cur_iocb_cnt)
  2104. *cur_iocb_cnt = mcp->mb[7];
  2105. if (orig_iocb_cnt)
  2106. *orig_iocb_cnt = mcp->mb[10];
  2107. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  2108. *max_npiv_vports = mcp->mb[11];
  2109. if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
  2110. *max_fcfs = mcp->mb[12];
  2111. }
  2112. return (rval);
  2113. }
  2114. /*
  2115. * qla2x00_get_fcal_position_map
  2116. * Get FCAL (LILP) position map using mailbox command
  2117. *
  2118. * Input:
  2119. * ha = adapter state pointer.
  2120. * pos_map = buffer pointer (can be NULL).
  2121. *
  2122. * Returns:
  2123. * qla2x00 local function return status code.
  2124. *
  2125. * Context:
  2126. * Kernel context.
  2127. */
  2128. int
  2129. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  2130. {
  2131. int rval;
  2132. mbx_cmd_t mc;
  2133. mbx_cmd_t *mcp = &mc;
  2134. char *pmap;
  2135. dma_addr_t pmap_dma;
  2136. struct qla_hw_data *ha = vha->hw;
  2137. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
  2138. "Entered %s.\n", __func__);
  2139. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  2140. if (pmap == NULL) {
  2141. ql_log(ql_log_warn, vha, 0x1080,
  2142. "Memory alloc failed.\n");
  2143. return QLA_MEMORY_ALLOC_FAILED;
  2144. }
  2145. memset(pmap, 0, FCAL_MAP_SIZE);
  2146. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  2147. mcp->mb[2] = MSW(pmap_dma);
  2148. mcp->mb[3] = LSW(pmap_dma);
  2149. mcp->mb[6] = MSW(MSD(pmap_dma));
  2150. mcp->mb[7] = LSW(MSD(pmap_dma));
  2151. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2152. mcp->in_mb = MBX_1|MBX_0;
  2153. mcp->buf_size = FCAL_MAP_SIZE;
  2154. mcp->flags = MBX_DMA_IN;
  2155. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  2156. rval = qla2x00_mailbox_command(vha, mcp);
  2157. if (rval == QLA_SUCCESS) {
  2158. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
  2159. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  2160. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  2161. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  2162. pmap, pmap[0] + 1);
  2163. if (pos_map)
  2164. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  2165. }
  2166. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  2167. if (rval != QLA_SUCCESS) {
  2168. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  2169. } else {
  2170. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
  2171. "Done %s.\n", __func__);
  2172. }
  2173. return rval;
  2174. }
  2175. /*
  2176. * qla2x00_get_link_status
  2177. *
  2178. * Input:
  2179. * ha = adapter block pointer.
  2180. * loop_id = device loop ID.
  2181. * ret_buf = pointer to link status return buffer.
  2182. *
  2183. * Returns:
  2184. * 0 = success.
  2185. * BIT_0 = mem alloc error.
  2186. * BIT_1 = mailbox error.
  2187. */
  2188. int
  2189. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  2190. struct link_statistics *stats, dma_addr_t stats_dma)
  2191. {
  2192. int rval;
  2193. mbx_cmd_t mc;
  2194. mbx_cmd_t *mcp = &mc;
  2195. uint32_t *siter, *diter, dwords;
  2196. struct qla_hw_data *ha = vha->hw;
  2197. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
  2198. "Entered %s.\n", __func__);
  2199. mcp->mb[0] = MBC_GET_LINK_STATUS;
  2200. mcp->mb[2] = MSW(stats_dma);
  2201. mcp->mb[3] = LSW(stats_dma);
  2202. mcp->mb[6] = MSW(MSD(stats_dma));
  2203. mcp->mb[7] = LSW(MSD(stats_dma));
  2204. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2205. mcp->in_mb = MBX_0;
  2206. if (IS_FWI2_CAPABLE(ha)) {
  2207. mcp->mb[1] = loop_id;
  2208. mcp->mb[4] = 0;
  2209. mcp->mb[10] = 0;
  2210. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  2211. mcp->in_mb |= MBX_1;
  2212. } else if (HAS_EXTENDED_IDS(ha)) {
  2213. mcp->mb[1] = loop_id;
  2214. mcp->mb[10] = 0;
  2215. mcp->out_mb |= MBX_10|MBX_1;
  2216. } else {
  2217. mcp->mb[1] = loop_id << 8;
  2218. mcp->out_mb |= MBX_1;
  2219. }
  2220. mcp->tov = MBX_TOV_SECONDS;
  2221. mcp->flags = IOCTL_CMD;
  2222. rval = qla2x00_mailbox_command(vha, mcp);
  2223. if (rval == QLA_SUCCESS) {
  2224. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2225. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  2226. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2227. rval = QLA_FUNCTION_FAILED;
  2228. } else {
  2229. /* Copy over data -- firmware data is LE. */
  2230. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
  2231. "Done %s.\n", __func__);
  2232. dwords = offsetof(struct link_statistics, unused1) / 4;
  2233. siter = diter = &stats->link_fail_cnt;
  2234. while (dwords--)
  2235. *diter++ = le32_to_cpu(*siter++);
  2236. }
  2237. } else {
  2238. /* Failed. */
  2239. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2240. }
  2241. return rval;
  2242. }
  2243. int
  2244. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2245. dma_addr_t stats_dma)
  2246. {
  2247. int rval;
  2248. mbx_cmd_t mc;
  2249. mbx_cmd_t *mcp = &mc;
  2250. uint32_t *siter, *diter, dwords;
  2251. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
  2252. "Entered %s.\n", __func__);
  2253. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2254. mcp->mb[2] = MSW(stats_dma);
  2255. mcp->mb[3] = LSW(stats_dma);
  2256. mcp->mb[6] = MSW(MSD(stats_dma));
  2257. mcp->mb[7] = LSW(MSD(stats_dma));
  2258. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2259. mcp->mb[9] = vha->vp_idx;
  2260. mcp->mb[10] = 0;
  2261. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2262. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2263. mcp->tov = MBX_TOV_SECONDS;
  2264. mcp->flags = IOCTL_CMD;
  2265. rval = qla2x00_mailbox_command(vha, mcp);
  2266. if (rval == QLA_SUCCESS) {
  2267. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2268. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2269. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2270. rval = QLA_FUNCTION_FAILED;
  2271. } else {
  2272. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
  2273. "Done %s.\n", __func__);
  2274. /* Copy over data -- firmware data is LE. */
  2275. dwords = sizeof(struct link_statistics) / 4;
  2276. siter = diter = &stats->link_fail_cnt;
  2277. while (dwords--)
  2278. *diter++ = le32_to_cpu(*siter++);
  2279. }
  2280. } else {
  2281. /* Failed. */
  2282. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2283. }
  2284. return rval;
  2285. }
  2286. int
  2287. qla24xx_abort_command(srb_t *sp)
  2288. {
  2289. int rval;
  2290. unsigned long flags = 0;
  2291. struct abort_entry_24xx *abt;
  2292. dma_addr_t abt_dma;
  2293. uint32_t handle;
  2294. fc_port_t *fcport = sp->fcport;
  2295. struct scsi_qla_host *vha = fcport->vha;
  2296. struct qla_hw_data *ha = vha->hw;
  2297. struct req_que *req = vha->req;
  2298. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
  2299. "Entered %s.\n", __func__);
  2300. spin_lock_irqsave(&ha->hardware_lock, flags);
  2301. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  2302. if (req->outstanding_cmds[handle] == sp)
  2303. break;
  2304. }
  2305. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2306. if (handle == req->num_outstanding_cmds) {
  2307. /* Command not found. */
  2308. return QLA_FUNCTION_FAILED;
  2309. }
  2310. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2311. if (abt == NULL) {
  2312. ql_log(ql_log_warn, vha, 0x108d,
  2313. "Failed to allocate abort IOCB.\n");
  2314. return QLA_MEMORY_ALLOC_FAILED;
  2315. }
  2316. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2317. abt->entry_type = ABORT_IOCB_TYPE;
  2318. abt->entry_count = 1;
  2319. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2320. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2321. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2322. abt->port_id[0] = fcport->d_id.b.al_pa;
  2323. abt->port_id[1] = fcport->d_id.b.area;
  2324. abt->port_id[2] = fcport->d_id.b.domain;
  2325. abt->vp_index = fcport->vha->vp_idx;
  2326. abt->req_que_no = cpu_to_le16(req->id);
  2327. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2328. if (rval != QLA_SUCCESS) {
  2329. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2330. "Failed to issue IOCB (%x).\n", rval);
  2331. } else if (abt->entry_status != 0) {
  2332. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2333. "Failed to complete IOCB -- error status (%x).\n",
  2334. abt->entry_status);
  2335. rval = QLA_FUNCTION_FAILED;
  2336. } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
  2337. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2338. "Failed to complete IOCB -- completion status (%x).\n",
  2339. le16_to_cpu(abt->nport_handle));
  2340. rval = QLA_FUNCTION_FAILED;
  2341. } else {
  2342. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
  2343. "Done %s.\n", __func__);
  2344. }
  2345. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2346. return rval;
  2347. }
  2348. struct tsk_mgmt_cmd {
  2349. union {
  2350. struct tsk_mgmt_entry tsk;
  2351. struct sts_entry_24xx sts;
  2352. } p;
  2353. };
  2354. static int
  2355. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2356. unsigned int l, int tag)
  2357. {
  2358. int rval, rval2;
  2359. struct tsk_mgmt_cmd *tsk;
  2360. struct sts_entry_24xx *sts;
  2361. dma_addr_t tsk_dma;
  2362. scsi_qla_host_t *vha;
  2363. struct qla_hw_data *ha;
  2364. struct req_que *req;
  2365. struct rsp_que *rsp;
  2366. vha = fcport->vha;
  2367. ha = vha->hw;
  2368. req = vha->req;
  2369. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
  2370. "Entered %s.\n", __func__);
  2371. if (ha->flags.cpu_affinity_enabled)
  2372. rsp = ha->rsp_q_map[tag + 1];
  2373. else
  2374. rsp = req->rsp;
  2375. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2376. if (tsk == NULL) {
  2377. ql_log(ql_log_warn, vha, 0x1093,
  2378. "Failed to allocate task management IOCB.\n");
  2379. return QLA_MEMORY_ALLOC_FAILED;
  2380. }
  2381. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2382. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2383. tsk->p.tsk.entry_count = 1;
  2384. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2385. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2386. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2387. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2388. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2389. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2390. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2391. tsk->p.tsk.vp_index = fcport->vha->vp_idx;
  2392. if (type == TCF_LUN_RESET) {
  2393. int_to_scsilun(l, &tsk->p.tsk.lun);
  2394. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2395. sizeof(tsk->p.tsk.lun));
  2396. }
  2397. sts = &tsk->p.sts;
  2398. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2399. if (rval != QLA_SUCCESS) {
  2400. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2401. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2402. } else if (sts->entry_status != 0) {
  2403. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2404. "Failed to complete IOCB -- error status (%x).\n",
  2405. sts->entry_status);
  2406. rval = QLA_FUNCTION_FAILED;
  2407. } else if (sts->comp_status !=
  2408. __constant_cpu_to_le16(CS_COMPLETE)) {
  2409. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2410. "Failed to complete IOCB -- completion status (%x).\n",
  2411. le16_to_cpu(sts->comp_status));
  2412. rval = QLA_FUNCTION_FAILED;
  2413. } else if (le16_to_cpu(sts->scsi_status) &
  2414. SS_RESPONSE_INFO_LEN_VALID) {
  2415. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2416. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
  2417. "Ignoring inconsistent data length -- not enough "
  2418. "response info (%d).\n",
  2419. le32_to_cpu(sts->rsp_data_len));
  2420. } else if (sts->data[3]) {
  2421. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2422. "Failed to complete IOCB -- response (%x).\n",
  2423. sts->data[3]);
  2424. rval = QLA_FUNCTION_FAILED;
  2425. }
  2426. }
  2427. /* Issue marker IOCB. */
  2428. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2429. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2430. if (rval2 != QLA_SUCCESS) {
  2431. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2432. "Failed to issue marker IOCB (%x).\n", rval2);
  2433. } else {
  2434. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
  2435. "Done %s.\n", __func__);
  2436. }
  2437. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2438. return rval;
  2439. }
  2440. int
  2441. qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  2442. {
  2443. struct qla_hw_data *ha = fcport->vha->hw;
  2444. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2445. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2446. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2447. }
  2448. int
  2449. qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  2450. {
  2451. struct qla_hw_data *ha = fcport->vha->hw;
  2452. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2453. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2454. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2455. }
  2456. int
  2457. qla2x00_system_error(scsi_qla_host_t *vha)
  2458. {
  2459. int rval;
  2460. mbx_cmd_t mc;
  2461. mbx_cmd_t *mcp = &mc;
  2462. struct qla_hw_data *ha = vha->hw;
  2463. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2464. return QLA_FUNCTION_FAILED;
  2465. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
  2466. "Entered %s.\n", __func__);
  2467. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2468. mcp->out_mb = MBX_0;
  2469. mcp->in_mb = MBX_0;
  2470. mcp->tov = 5;
  2471. mcp->flags = 0;
  2472. rval = qla2x00_mailbox_command(vha, mcp);
  2473. if (rval != QLA_SUCCESS) {
  2474. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2475. } else {
  2476. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
  2477. "Done %s.\n", __func__);
  2478. }
  2479. return rval;
  2480. }
  2481. /**
  2482. * qla2x00_set_serdes_params() -
  2483. * @ha: HA context
  2484. *
  2485. * Returns
  2486. */
  2487. int
  2488. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2489. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2490. {
  2491. int rval;
  2492. mbx_cmd_t mc;
  2493. mbx_cmd_t *mcp = &mc;
  2494. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
  2495. "Entered %s.\n", __func__);
  2496. mcp->mb[0] = MBC_SERDES_PARAMS;
  2497. mcp->mb[1] = BIT_0;
  2498. mcp->mb[2] = sw_em_1g | BIT_15;
  2499. mcp->mb[3] = sw_em_2g | BIT_15;
  2500. mcp->mb[4] = sw_em_4g | BIT_15;
  2501. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2502. mcp->in_mb = MBX_0;
  2503. mcp->tov = MBX_TOV_SECONDS;
  2504. mcp->flags = 0;
  2505. rval = qla2x00_mailbox_command(vha, mcp);
  2506. if (rval != QLA_SUCCESS) {
  2507. /*EMPTY*/
  2508. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2509. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2510. } else {
  2511. /*EMPTY*/
  2512. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
  2513. "Done %s.\n", __func__);
  2514. }
  2515. return rval;
  2516. }
  2517. int
  2518. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2519. {
  2520. int rval;
  2521. mbx_cmd_t mc;
  2522. mbx_cmd_t *mcp = &mc;
  2523. if (!IS_FWI2_CAPABLE(vha->hw))
  2524. return QLA_FUNCTION_FAILED;
  2525. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
  2526. "Entered %s.\n", __func__);
  2527. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2528. mcp->mb[1] = 0;
  2529. mcp->out_mb = MBX_1|MBX_0;
  2530. mcp->in_mb = MBX_0;
  2531. mcp->tov = 5;
  2532. mcp->flags = 0;
  2533. rval = qla2x00_mailbox_command(vha, mcp);
  2534. if (rval != QLA_SUCCESS) {
  2535. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2536. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2537. rval = QLA_INVALID_COMMAND;
  2538. } else {
  2539. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
  2540. "Done %s.\n", __func__);
  2541. }
  2542. return rval;
  2543. }
  2544. int
  2545. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2546. uint16_t buffers)
  2547. {
  2548. int rval;
  2549. mbx_cmd_t mc;
  2550. mbx_cmd_t *mcp = &mc;
  2551. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
  2552. "Entered %s.\n", __func__);
  2553. if (!IS_FWI2_CAPABLE(vha->hw))
  2554. return QLA_FUNCTION_FAILED;
  2555. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2556. return QLA_FUNCTION_FAILED;
  2557. mcp->mb[0] = MBC_TRACE_CONTROL;
  2558. mcp->mb[1] = TC_EFT_ENABLE;
  2559. mcp->mb[2] = LSW(eft_dma);
  2560. mcp->mb[3] = MSW(eft_dma);
  2561. mcp->mb[4] = LSW(MSD(eft_dma));
  2562. mcp->mb[5] = MSW(MSD(eft_dma));
  2563. mcp->mb[6] = buffers;
  2564. mcp->mb[7] = TC_AEN_DISABLE;
  2565. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2566. mcp->in_mb = MBX_1|MBX_0;
  2567. mcp->tov = MBX_TOV_SECONDS;
  2568. mcp->flags = 0;
  2569. rval = qla2x00_mailbox_command(vha, mcp);
  2570. if (rval != QLA_SUCCESS) {
  2571. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2572. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2573. rval, mcp->mb[0], mcp->mb[1]);
  2574. } else {
  2575. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
  2576. "Done %s.\n", __func__);
  2577. }
  2578. return rval;
  2579. }
  2580. int
  2581. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2582. {
  2583. int rval;
  2584. mbx_cmd_t mc;
  2585. mbx_cmd_t *mcp = &mc;
  2586. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
  2587. "Entered %s.\n", __func__);
  2588. if (!IS_FWI2_CAPABLE(vha->hw))
  2589. return QLA_FUNCTION_FAILED;
  2590. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2591. return QLA_FUNCTION_FAILED;
  2592. mcp->mb[0] = MBC_TRACE_CONTROL;
  2593. mcp->mb[1] = TC_EFT_DISABLE;
  2594. mcp->out_mb = MBX_1|MBX_0;
  2595. mcp->in_mb = MBX_1|MBX_0;
  2596. mcp->tov = MBX_TOV_SECONDS;
  2597. mcp->flags = 0;
  2598. rval = qla2x00_mailbox_command(vha, mcp);
  2599. if (rval != QLA_SUCCESS) {
  2600. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2601. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2602. rval, mcp->mb[0], mcp->mb[1]);
  2603. } else {
  2604. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
  2605. "Done %s.\n", __func__);
  2606. }
  2607. return rval;
  2608. }
  2609. int
  2610. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2611. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2612. {
  2613. int rval;
  2614. mbx_cmd_t mc;
  2615. mbx_cmd_t *mcp = &mc;
  2616. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
  2617. "Entered %s.\n", __func__);
  2618. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
  2619. !IS_QLA83XX(vha->hw))
  2620. return QLA_FUNCTION_FAILED;
  2621. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2622. return QLA_FUNCTION_FAILED;
  2623. mcp->mb[0] = MBC_TRACE_CONTROL;
  2624. mcp->mb[1] = TC_FCE_ENABLE;
  2625. mcp->mb[2] = LSW(fce_dma);
  2626. mcp->mb[3] = MSW(fce_dma);
  2627. mcp->mb[4] = LSW(MSD(fce_dma));
  2628. mcp->mb[5] = MSW(MSD(fce_dma));
  2629. mcp->mb[6] = buffers;
  2630. mcp->mb[7] = TC_AEN_DISABLE;
  2631. mcp->mb[8] = 0;
  2632. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2633. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2634. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2635. MBX_1|MBX_0;
  2636. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2637. mcp->tov = MBX_TOV_SECONDS;
  2638. mcp->flags = 0;
  2639. rval = qla2x00_mailbox_command(vha, mcp);
  2640. if (rval != QLA_SUCCESS) {
  2641. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2642. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2643. rval, mcp->mb[0], mcp->mb[1]);
  2644. } else {
  2645. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
  2646. "Done %s.\n", __func__);
  2647. if (mb)
  2648. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2649. if (dwords)
  2650. *dwords = buffers;
  2651. }
  2652. return rval;
  2653. }
  2654. int
  2655. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2656. {
  2657. int rval;
  2658. mbx_cmd_t mc;
  2659. mbx_cmd_t *mcp = &mc;
  2660. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
  2661. "Entered %s.\n", __func__);
  2662. if (!IS_FWI2_CAPABLE(vha->hw))
  2663. return QLA_FUNCTION_FAILED;
  2664. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2665. return QLA_FUNCTION_FAILED;
  2666. mcp->mb[0] = MBC_TRACE_CONTROL;
  2667. mcp->mb[1] = TC_FCE_DISABLE;
  2668. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2669. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2670. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2671. MBX_1|MBX_0;
  2672. mcp->tov = MBX_TOV_SECONDS;
  2673. mcp->flags = 0;
  2674. rval = qla2x00_mailbox_command(vha, mcp);
  2675. if (rval != QLA_SUCCESS) {
  2676. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2677. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2678. rval, mcp->mb[0], mcp->mb[1]);
  2679. } else {
  2680. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
  2681. "Done %s.\n", __func__);
  2682. if (wr)
  2683. *wr = (uint64_t) mcp->mb[5] << 48 |
  2684. (uint64_t) mcp->mb[4] << 32 |
  2685. (uint64_t) mcp->mb[3] << 16 |
  2686. (uint64_t) mcp->mb[2];
  2687. if (rd)
  2688. *rd = (uint64_t) mcp->mb[9] << 48 |
  2689. (uint64_t) mcp->mb[8] << 32 |
  2690. (uint64_t) mcp->mb[7] << 16 |
  2691. (uint64_t) mcp->mb[6];
  2692. }
  2693. return rval;
  2694. }
  2695. int
  2696. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2697. uint16_t *port_speed, uint16_t *mb)
  2698. {
  2699. int rval;
  2700. mbx_cmd_t mc;
  2701. mbx_cmd_t *mcp = &mc;
  2702. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
  2703. "Entered %s.\n", __func__);
  2704. if (!IS_IIDMA_CAPABLE(vha->hw))
  2705. return QLA_FUNCTION_FAILED;
  2706. mcp->mb[0] = MBC_PORT_PARAMS;
  2707. mcp->mb[1] = loop_id;
  2708. mcp->mb[2] = mcp->mb[3] = 0;
  2709. mcp->mb[9] = vha->vp_idx;
  2710. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2711. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2712. mcp->tov = MBX_TOV_SECONDS;
  2713. mcp->flags = 0;
  2714. rval = qla2x00_mailbox_command(vha, mcp);
  2715. /* Return mailbox statuses. */
  2716. if (mb != NULL) {
  2717. mb[0] = mcp->mb[0];
  2718. mb[1] = mcp->mb[1];
  2719. mb[3] = mcp->mb[3];
  2720. }
  2721. if (rval != QLA_SUCCESS) {
  2722. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2723. } else {
  2724. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
  2725. "Done %s.\n", __func__);
  2726. if (port_speed)
  2727. *port_speed = mcp->mb[3];
  2728. }
  2729. return rval;
  2730. }
  2731. int
  2732. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2733. uint16_t port_speed, uint16_t *mb)
  2734. {
  2735. int rval;
  2736. mbx_cmd_t mc;
  2737. mbx_cmd_t *mcp = &mc;
  2738. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
  2739. "Entered %s.\n", __func__);
  2740. if (!IS_IIDMA_CAPABLE(vha->hw))
  2741. return QLA_FUNCTION_FAILED;
  2742. mcp->mb[0] = MBC_PORT_PARAMS;
  2743. mcp->mb[1] = loop_id;
  2744. mcp->mb[2] = BIT_0;
  2745. if (IS_CNA_CAPABLE(vha->hw))
  2746. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2747. else
  2748. mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
  2749. mcp->mb[9] = vha->vp_idx;
  2750. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2751. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2752. mcp->tov = MBX_TOV_SECONDS;
  2753. mcp->flags = 0;
  2754. rval = qla2x00_mailbox_command(vha, mcp);
  2755. /* Return mailbox statuses. */
  2756. if (mb != NULL) {
  2757. mb[0] = mcp->mb[0];
  2758. mb[1] = mcp->mb[1];
  2759. mb[3] = mcp->mb[3];
  2760. }
  2761. if (rval != QLA_SUCCESS) {
  2762. ql_dbg(ql_dbg_mbx, vha, 0x10b4,
  2763. "Failed=%x.\n", rval);
  2764. } else {
  2765. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
  2766. "Done %s.\n", __func__);
  2767. }
  2768. return rval;
  2769. }
  2770. void
  2771. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2772. struct vp_rpt_id_entry_24xx *rptid_entry)
  2773. {
  2774. uint8_t vp_idx;
  2775. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2776. struct qla_hw_data *ha = vha->hw;
  2777. scsi_qla_host_t *vp;
  2778. unsigned long flags;
  2779. int found;
  2780. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
  2781. "Entered %s.\n", __func__);
  2782. if (rptid_entry->entry_status != 0)
  2783. return;
  2784. if (rptid_entry->format == 0) {
  2785. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
  2786. "Format 0 : Number of VPs setup %d, number of "
  2787. "VPs acquired %d.\n",
  2788. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2789. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2790. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
  2791. "Primary port id %02x%02x%02x.\n",
  2792. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2793. rptid_entry->port_id[0]);
  2794. } else if (rptid_entry->format == 1) {
  2795. vp_idx = LSB(stat);
  2796. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
  2797. "Format 1: VP[%d] enabled - status %d - with "
  2798. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2799. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2800. rptid_entry->port_id[0]);
  2801. vp = vha;
  2802. if (vp_idx == 0 && (MSB(stat) != 1))
  2803. goto reg_needed;
  2804. if (MSB(stat) != 0 && MSB(stat) != 2) {
  2805. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2806. "Could not acquire ID for VP[%d].\n", vp_idx);
  2807. return;
  2808. }
  2809. found = 0;
  2810. spin_lock_irqsave(&ha->vport_slock, flags);
  2811. list_for_each_entry(vp, &ha->vp_list, list) {
  2812. if (vp_idx == vp->vp_idx) {
  2813. found = 1;
  2814. break;
  2815. }
  2816. }
  2817. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2818. if (!found)
  2819. return;
  2820. vp->d_id.b.domain = rptid_entry->port_id[2];
  2821. vp->d_id.b.area = rptid_entry->port_id[1];
  2822. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  2823. /*
  2824. * Cannot configure here as we are still sitting on the
  2825. * response queue. Handle it in dpc context.
  2826. */
  2827. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  2828. reg_needed:
  2829. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  2830. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  2831. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  2832. qla2xxx_wake_dpc(vha);
  2833. }
  2834. }
  2835. /*
  2836. * qla24xx_modify_vp_config
  2837. * Change VP configuration for vha
  2838. *
  2839. * Input:
  2840. * vha = adapter block pointer.
  2841. *
  2842. * Returns:
  2843. * qla2xxx local function return status code.
  2844. *
  2845. * Context:
  2846. * Kernel context.
  2847. */
  2848. int
  2849. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  2850. {
  2851. int rval;
  2852. struct vp_config_entry_24xx *vpmod;
  2853. dma_addr_t vpmod_dma;
  2854. struct qla_hw_data *ha = vha->hw;
  2855. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2856. /* This can be called by the parent */
  2857. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
  2858. "Entered %s.\n", __func__);
  2859. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  2860. if (!vpmod) {
  2861. ql_log(ql_log_warn, vha, 0x10bc,
  2862. "Failed to allocate modify VP IOCB.\n");
  2863. return QLA_MEMORY_ALLOC_FAILED;
  2864. }
  2865. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  2866. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  2867. vpmod->entry_count = 1;
  2868. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  2869. vpmod->vp_count = 1;
  2870. vpmod->vp_index1 = vha->vp_idx;
  2871. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  2872. qlt_modify_vp_config(vha, vpmod);
  2873. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  2874. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  2875. vpmod->entry_count = 1;
  2876. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  2877. if (rval != QLA_SUCCESS) {
  2878. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  2879. "Failed to issue VP config IOCB (%x).\n", rval);
  2880. } else if (vpmod->comp_status != 0) {
  2881. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  2882. "Failed to complete IOCB -- error status (%x).\n",
  2883. vpmod->comp_status);
  2884. rval = QLA_FUNCTION_FAILED;
  2885. } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2886. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  2887. "Failed to complete IOCB -- completion status (%x).\n",
  2888. le16_to_cpu(vpmod->comp_status));
  2889. rval = QLA_FUNCTION_FAILED;
  2890. } else {
  2891. /* EMPTY */
  2892. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
  2893. "Done %s.\n", __func__);
  2894. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  2895. }
  2896. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  2897. return rval;
  2898. }
  2899. /*
  2900. * qla24xx_control_vp
  2901. * Enable a virtual port for given host
  2902. *
  2903. * Input:
  2904. * ha = adapter block pointer.
  2905. * vhba = virtual adapter (unused)
  2906. * index = index number for enabled VP
  2907. *
  2908. * Returns:
  2909. * qla2xxx local function return status code.
  2910. *
  2911. * Context:
  2912. * Kernel context.
  2913. */
  2914. int
  2915. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  2916. {
  2917. int rval;
  2918. int map, pos;
  2919. struct vp_ctrl_entry_24xx *vce;
  2920. dma_addr_t vce_dma;
  2921. struct qla_hw_data *ha = vha->hw;
  2922. int vp_index = vha->vp_idx;
  2923. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2924. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
  2925. "Entered %s enabling index %d.\n", __func__, vp_index);
  2926. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  2927. return QLA_PARAMETER_ERROR;
  2928. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  2929. if (!vce) {
  2930. ql_log(ql_log_warn, vha, 0x10c2,
  2931. "Failed to allocate VP control IOCB.\n");
  2932. return QLA_MEMORY_ALLOC_FAILED;
  2933. }
  2934. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  2935. vce->entry_type = VP_CTRL_IOCB_TYPE;
  2936. vce->entry_count = 1;
  2937. vce->command = cpu_to_le16(cmd);
  2938. vce->vp_count = __constant_cpu_to_le16(1);
  2939. /* index map in firmware starts with 1; decrement index
  2940. * this is ok as we never use index 0
  2941. */
  2942. map = (vp_index - 1) / 8;
  2943. pos = (vp_index - 1) & 7;
  2944. mutex_lock(&ha->vport_lock);
  2945. vce->vp_idx_map[map] |= 1 << pos;
  2946. mutex_unlock(&ha->vport_lock);
  2947. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  2948. if (rval != QLA_SUCCESS) {
  2949. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  2950. "Failed to issue VP control IOCB (%x).\n", rval);
  2951. } else if (vce->entry_status != 0) {
  2952. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  2953. "Failed to complete IOCB -- error status (%x).\n",
  2954. vce->entry_status);
  2955. rval = QLA_FUNCTION_FAILED;
  2956. } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2957. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  2958. "Failed to complet IOCB -- completion status (%x).\n",
  2959. le16_to_cpu(vce->comp_status));
  2960. rval = QLA_FUNCTION_FAILED;
  2961. } else {
  2962. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
  2963. "Done %s.\n", __func__);
  2964. }
  2965. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  2966. return rval;
  2967. }
  2968. /*
  2969. * qla2x00_send_change_request
  2970. * Receive or disable RSCN request from fabric controller
  2971. *
  2972. * Input:
  2973. * ha = adapter block pointer
  2974. * format = registration format:
  2975. * 0 - Reserved
  2976. * 1 - Fabric detected registration
  2977. * 2 - N_port detected registration
  2978. * 3 - Full registration
  2979. * FF - clear registration
  2980. * vp_idx = Virtual port index
  2981. *
  2982. * Returns:
  2983. * qla2x00 local function return status code.
  2984. *
  2985. * Context:
  2986. * Kernel Context
  2987. */
  2988. int
  2989. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  2990. uint16_t vp_idx)
  2991. {
  2992. int rval;
  2993. mbx_cmd_t mc;
  2994. mbx_cmd_t *mcp = &mc;
  2995. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
  2996. "Entered %s.\n", __func__);
  2997. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  2998. mcp->mb[1] = format;
  2999. mcp->mb[9] = vp_idx;
  3000. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  3001. mcp->in_mb = MBX_0|MBX_1;
  3002. mcp->tov = MBX_TOV_SECONDS;
  3003. mcp->flags = 0;
  3004. rval = qla2x00_mailbox_command(vha, mcp);
  3005. if (rval == QLA_SUCCESS) {
  3006. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  3007. rval = BIT_1;
  3008. }
  3009. } else
  3010. rval = BIT_1;
  3011. return rval;
  3012. }
  3013. int
  3014. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  3015. uint32_t size)
  3016. {
  3017. int rval;
  3018. mbx_cmd_t mc;
  3019. mbx_cmd_t *mcp = &mc;
  3020. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
  3021. "Entered %s.\n", __func__);
  3022. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  3023. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  3024. mcp->mb[8] = MSW(addr);
  3025. mcp->out_mb = MBX_8|MBX_0;
  3026. } else {
  3027. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  3028. mcp->out_mb = MBX_0;
  3029. }
  3030. mcp->mb[1] = LSW(addr);
  3031. mcp->mb[2] = MSW(req_dma);
  3032. mcp->mb[3] = LSW(req_dma);
  3033. mcp->mb[6] = MSW(MSD(req_dma));
  3034. mcp->mb[7] = LSW(MSD(req_dma));
  3035. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  3036. if (IS_FWI2_CAPABLE(vha->hw)) {
  3037. mcp->mb[4] = MSW(size);
  3038. mcp->mb[5] = LSW(size);
  3039. mcp->out_mb |= MBX_5|MBX_4;
  3040. } else {
  3041. mcp->mb[4] = LSW(size);
  3042. mcp->out_mb |= MBX_4;
  3043. }
  3044. mcp->in_mb = MBX_0;
  3045. mcp->tov = MBX_TOV_SECONDS;
  3046. mcp->flags = 0;
  3047. rval = qla2x00_mailbox_command(vha, mcp);
  3048. if (rval != QLA_SUCCESS) {
  3049. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  3050. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3051. } else {
  3052. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
  3053. "Done %s.\n", __func__);
  3054. }
  3055. return rval;
  3056. }
  3057. /* 84XX Support **************************************************************/
  3058. struct cs84xx_mgmt_cmd {
  3059. union {
  3060. struct verify_chip_entry_84xx req;
  3061. struct verify_chip_rsp_84xx rsp;
  3062. } p;
  3063. };
  3064. int
  3065. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  3066. {
  3067. int rval, retry;
  3068. struct cs84xx_mgmt_cmd *mn;
  3069. dma_addr_t mn_dma;
  3070. uint16_t options;
  3071. unsigned long flags;
  3072. struct qla_hw_data *ha = vha->hw;
  3073. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
  3074. "Entered %s.\n", __func__);
  3075. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  3076. if (mn == NULL) {
  3077. return QLA_MEMORY_ALLOC_FAILED;
  3078. }
  3079. /* Force Update? */
  3080. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  3081. /* Diagnostic firmware? */
  3082. /* options |= MENLO_DIAG_FW; */
  3083. /* We update the firmware with only one data sequence. */
  3084. options |= VCO_END_OF_DATA;
  3085. do {
  3086. retry = 0;
  3087. memset(mn, 0, sizeof(*mn));
  3088. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  3089. mn->p.req.entry_count = 1;
  3090. mn->p.req.options = cpu_to_le16(options);
  3091. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  3092. "Dump of Verify Request.\n");
  3093. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  3094. (uint8_t *)mn, sizeof(*mn));
  3095. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  3096. if (rval != QLA_SUCCESS) {
  3097. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  3098. "Failed to issue verify IOCB (%x).\n", rval);
  3099. goto verify_done;
  3100. }
  3101. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  3102. "Dump of Verify Response.\n");
  3103. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  3104. (uint8_t *)mn, sizeof(*mn));
  3105. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  3106. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  3107. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  3108. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
  3109. "cs=%x fc=%x.\n", status[0], status[1]);
  3110. if (status[0] != CS_COMPLETE) {
  3111. rval = QLA_FUNCTION_FAILED;
  3112. if (!(options & VCO_DONT_UPDATE_FW)) {
  3113. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  3114. "Firmware update failed. Retrying "
  3115. "without update firmware.\n");
  3116. options |= VCO_DONT_UPDATE_FW;
  3117. options &= ~VCO_FORCE_UPDATE;
  3118. retry = 1;
  3119. }
  3120. } else {
  3121. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
  3122. "Firmware updated to %x.\n",
  3123. le32_to_cpu(mn->p.rsp.fw_ver));
  3124. /* NOTE: we only update OP firmware. */
  3125. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  3126. ha->cs84xx->op_fw_version =
  3127. le32_to_cpu(mn->p.rsp.fw_ver);
  3128. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  3129. flags);
  3130. }
  3131. } while (retry);
  3132. verify_done:
  3133. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  3134. if (rval != QLA_SUCCESS) {
  3135. ql_dbg(ql_dbg_mbx, vha, 0x10d1,
  3136. "Failed=%x.\n", rval);
  3137. } else {
  3138. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
  3139. "Done %s.\n", __func__);
  3140. }
  3141. return rval;
  3142. }
  3143. int
  3144. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  3145. {
  3146. int rval;
  3147. unsigned long flags;
  3148. mbx_cmd_t mc;
  3149. mbx_cmd_t *mcp = &mc;
  3150. struct device_reg_25xxmq __iomem *reg;
  3151. struct qla_hw_data *ha = vha->hw;
  3152. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
  3153. "Entered %s.\n", __func__);
  3154. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3155. mcp->mb[1] = req->options;
  3156. mcp->mb[2] = MSW(LSD(req->dma));
  3157. mcp->mb[3] = LSW(LSD(req->dma));
  3158. mcp->mb[6] = MSW(MSD(req->dma));
  3159. mcp->mb[7] = LSW(MSD(req->dma));
  3160. mcp->mb[5] = req->length;
  3161. if (req->rsp)
  3162. mcp->mb[10] = req->rsp->id;
  3163. mcp->mb[12] = req->qos;
  3164. mcp->mb[11] = req->vp_idx;
  3165. mcp->mb[13] = req->rid;
  3166. if (IS_QLA83XX(ha))
  3167. mcp->mb[15] = 0;
  3168. reg = (struct device_reg_25xxmq __iomem *)((ha->mqiobase) +
  3169. QLA_QUE_PAGE * req->id);
  3170. mcp->mb[4] = req->id;
  3171. /* que in ptr index */
  3172. mcp->mb[8] = 0;
  3173. /* que out ptr index */
  3174. mcp->mb[9] = 0;
  3175. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  3176. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3177. mcp->in_mb = MBX_0;
  3178. mcp->flags = MBX_DMA_OUT;
  3179. mcp->tov = MBX_TOV_SECONDS * 2;
  3180. if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  3181. mcp->in_mb |= MBX_1;
  3182. if (IS_QLA83XX(ha)) {
  3183. mcp->out_mb |= MBX_15;
  3184. /* debug q create issue in SR-IOV */
  3185. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3186. }
  3187. spin_lock_irqsave(&ha->hardware_lock, flags);
  3188. if (!(req->options & BIT_0)) {
  3189. WRT_REG_DWORD(&reg->req_q_in, 0);
  3190. if (!IS_QLA83XX(ha))
  3191. WRT_REG_DWORD(&reg->req_q_out, 0);
  3192. }
  3193. req->req_q_in = &reg->req_q_in;
  3194. req->req_q_out = &reg->req_q_out;
  3195. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3196. rval = qla2x00_mailbox_command(vha, mcp);
  3197. if (rval != QLA_SUCCESS) {
  3198. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  3199. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3200. } else {
  3201. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
  3202. "Done %s.\n", __func__);
  3203. }
  3204. return rval;
  3205. }
  3206. int
  3207. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  3208. {
  3209. int rval;
  3210. unsigned long flags;
  3211. mbx_cmd_t mc;
  3212. mbx_cmd_t *mcp = &mc;
  3213. struct device_reg_25xxmq __iomem *reg;
  3214. struct qla_hw_data *ha = vha->hw;
  3215. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
  3216. "Entered %s.\n", __func__);
  3217. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3218. mcp->mb[1] = rsp->options;
  3219. mcp->mb[2] = MSW(LSD(rsp->dma));
  3220. mcp->mb[3] = LSW(LSD(rsp->dma));
  3221. mcp->mb[6] = MSW(MSD(rsp->dma));
  3222. mcp->mb[7] = LSW(MSD(rsp->dma));
  3223. mcp->mb[5] = rsp->length;
  3224. mcp->mb[14] = rsp->msix->entry;
  3225. mcp->mb[13] = rsp->rid;
  3226. if (IS_QLA83XX(ha))
  3227. mcp->mb[15] = 0;
  3228. reg = (struct device_reg_25xxmq __iomem *)((ha->mqiobase) +
  3229. QLA_QUE_PAGE * rsp->id);
  3230. mcp->mb[4] = rsp->id;
  3231. /* que in ptr index */
  3232. mcp->mb[8] = 0;
  3233. /* que out ptr index */
  3234. mcp->mb[9] = 0;
  3235. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  3236. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3237. mcp->in_mb = MBX_0;
  3238. mcp->flags = MBX_DMA_OUT;
  3239. mcp->tov = MBX_TOV_SECONDS * 2;
  3240. if (IS_QLA81XX(ha)) {
  3241. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  3242. mcp->in_mb |= MBX_1;
  3243. } else if (IS_QLA83XX(ha)) {
  3244. mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
  3245. mcp->in_mb |= MBX_1;
  3246. /* debug q create issue in SR-IOV */
  3247. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3248. }
  3249. spin_lock_irqsave(&ha->hardware_lock, flags);
  3250. if (!(rsp->options & BIT_0)) {
  3251. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  3252. if (!IS_QLA83XX(ha))
  3253. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  3254. }
  3255. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3256. rval = qla2x00_mailbox_command(vha, mcp);
  3257. if (rval != QLA_SUCCESS) {
  3258. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  3259. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3260. } else {
  3261. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
  3262. "Done %s.\n", __func__);
  3263. }
  3264. return rval;
  3265. }
  3266. int
  3267. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  3268. {
  3269. int rval;
  3270. mbx_cmd_t mc;
  3271. mbx_cmd_t *mcp = &mc;
  3272. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
  3273. "Entered %s.\n", __func__);
  3274. mcp->mb[0] = MBC_IDC_ACK;
  3275. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  3276. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3277. mcp->in_mb = MBX_0;
  3278. mcp->tov = MBX_TOV_SECONDS;
  3279. mcp->flags = 0;
  3280. rval = qla2x00_mailbox_command(vha, mcp);
  3281. if (rval != QLA_SUCCESS) {
  3282. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  3283. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3284. } else {
  3285. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
  3286. "Done %s.\n", __func__);
  3287. }
  3288. return rval;
  3289. }
  3290. int
  3291. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  3292. {
  3293. int rval;
  3294. mbx_cmd_t mc;
  3295. mbx_cmd_t *mcp = &mc;
  3296. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
  3297. "Entered %s.\n", __func__);
  3298. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3299. return QLA_FUNCTION_FAILED;
  3300. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3301. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3302. mcp->out_mb = MBX_1|MBX_0;
  3303. mcp->in_mb = MBX_1|MBX_0;
  3304. mcp->tov = MBX_TOV_SECONDS;
  3305. mcp->flags = 0;
  3306. rval = qla2x00_mailbox_command(vha, mcp);
  3307. if (rval != QLA_SUCCESS) {
  3308. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3309. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3310. rval, mcp->mb[0], mcp->mb[1]);
  3311. } else {
  3312. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
  3313. "Done %s.\n", __func__);
  3314. *sector_size = mcp->mb[1];
  3315. }
  3316. return rval;
  3317. }
  3318. int
  3319. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3320. {
  3321. int rval;
  3322. mbx_cmd_t mc;
  3323. mbx_cmd_t *mcp = &mc;
  3324. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3325. return QLA_FUNCTION_FAILED;
  3326. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
  3327. "Entered %s.\n", __func__);
  3328. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3329. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3330. FAC_OPT_CMD_WRITE_PROTECT;
  3331. mcp->out_mb = MBX_1|MBX_0;
  3332. mcp->in_mb = MBX_1|MBX_0;
  3333. mcp->tov = MBX_TOV_SECONDS;
  3334. mcp->flags = 0;
  3335. rval = qla2x00_mailbox_command(vha, mcp);
  3336. if (rval != QLA_SUCCESS) {
  3337. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3338. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3339. rval, mcp->mb[0], mcp->mb[1]);
  3340. } else {
  3341. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
  3342. "Done %s.\n", __func__);
  3343. }
  3344. return rval;
  3345. }
  3346. int
  3347. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3348. {
  3349. int rval;
  3350. mbx_cmd_t mc;
  3351. mbx_cmd_t *mcp = &mc;
  3352. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3353. return QLA_FUNCTION_FAILED;
  3354. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
  3355. "Entered %s.\n", __func__);
  3356. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3357. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3358. mcp->mb[2] = LSW(start);
  3359. mcp->mb[3] = MSW(start);
  3360. mcp->mb[4] = LSW(finish);
  3361. mcp->mb[5] = MSW(finish);
  3362. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3363. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3364. mcp->tov = MBX_TOV_SECONDS;
  3365. mcp->flags = 0;
  3366. rval = qla2x00_mailbox_command(vha, mcp);
  3367. if (rval != QLA_SUCCESS) {
  3368. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3369. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3370. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3371. } else {
  3372. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
  3373. "Done %s.\n", __func__);
  3374. }
  3375. return rval;
  3376. }
  3377. int
  3378. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3379. {
  3380. int rval = 0;
  3381. mbx_cmd_t mc;
  3382. mbx_cmd_t *mcp = &mc;
  3383. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
  3384. "Entered %s.\n", __func__);
  3385. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3386. mcp->out_mb = MBX_0;
  3387. mcp->in_mb = MBX_0|MBX_1;
  3388. mcp->tov = MBX_TOV_SECONDS;
  3389. mcp->flags = 0;
  3390. rval = qla2x00_mailbox_command(vha, mcp);
  3391. if (rval != QLA_SUCCESS) {
  3392. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3393. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3394. rval, mcp->mb[0], mcp->mb[1]);
  3395. } else {
  3396. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
  3397. "Done %s.\n", __func__);
  3398. }
  3399. return rval;
  3400. }
  3401. static int
  3402. qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
  3403. {
  3404. int rval;
  3405. mbx_cmd_t mc;
  3406. mbx_cmd_t *mcp = &mc;
  3407. if (!IS_FWI2_CAPABLE(vha->hw))
  3408. return QLA_FUNCTION_FAILED;
  3409. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
  3410. "Entered %s.\n", __func__);
  3411. mcp->mb[0] = MBC_GET_RNID_PARAMS;
  3412. mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
  3413. mcp->out_mb = MBX_1|MBX_0;
  3414. mcp->in_mb = MBX_1|MBX_0;
  3415. mcp->tov = MBX_TOV_SECONDS;
  3416. mcp->flags = 0;
  3417. rval = qla2x00_mailbox_command(vha, mcp);
  3418. *temp = mcp->mb[1];
  3419. if (rval != QLA_SUCCESS) {
  3420. ql_dbg(ql_dbg_mbx, vha, 0x115a,
  3421. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3422. } else {
  3423. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
  3424. "Done %s.\n", __func__);
  3425. }
  3426. return rval;
  3427. }
  3428. int
  3429. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3430. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3431. {
  3432. int rval;
  3433. mbx_cmd_t mc;
  3434. mbx_cmd_t *mcp = &mc;
  3435. struct qla_hw_data *ha = vha->hw;
  3436. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
  3437. "Entered %s.\n", __func__);
  3438. if (!IS_FWI2_CAPABLE(ha))
  3439. return QLA_FUNCTION_FAILED;
  3440. if (len == 1)
  3441. opt |= BIT_0;
  3442. mcp->mb[0] = MBC_READ_SFP;
  3443. mcp->mb[1] = dev;
  3444. mcp->mb[2] = MSW(sfp_dma);
  3445. mcp->mb[3] = LSW(sfp_dma);
  3446. mcp->mb[6] = MSW(MSD(sfp_dma));
  3447. mcp->mb[7] = LSW(MSD(sfp_dma));
  3448. mcp->mb[8] = len;
  3449. mcp->mb[9] = off;
  3450. mcp->mb[10] = opt;
  3451. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3452. mcp->in_mb = MBX_1|MBX_0;
  3453. mcp->tov = MBX_TOV_SECONDS;
  3454. mcp->flags = 0;
  3455. rval = qla2x00_mailbox_command(vha, mcp);
  3456. if (opt & BIT_0)
  3457. *sfp = mcp->mb[1];
  3458. if (rval != QLA_SUCCESS) {
  3459. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3460. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3461. } else {
  3462. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
  3463. "Done %s.\n", __func__);
  3464. }
  3465. return rval;
  3466. }
  3467. int
  3468. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3469. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3470. {
  3471. int rval;
  3472. mbx_cmd_t mc;
  3473. mbx_cmd_t *mcp = &mc;
  3474. struct qla_hw_data *ha = vha->hw;
  3475. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
  3476. "Entered %s.\n", __func__);
  3477. if (!IS_FWI2_CAPABLE(ha))
  3478. return QLA_FUNCTION_FAILED;
  3479. if (len == 1)
  3480. opt |= BIT_0;
  3481. if (opt & BIT_0)
  3482. len = *sfp;
  3483. mcp->mb[0] = MBC_WRITE_SFP;
  3484. mcp->mb[1] = dev;
  3485. mcp->mb[2] = MSW(sfp_dma);
  3486. mcp->mb[3] = LSW(sfp_dma);
  3487. mcp->mb[6] = MSW(MSD(sfp_dma));
  3488. mcp->mb[7] = LSW(MSD(sfp_dma));
  3489. mcp->mb[8] = len;
  3490. mcp->mb[9] = off;
  3491. mcp->mb[10] = opt;
  3492. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3493. mcp->in_mb = MBX_1|MBX_0;
  3494. mcp->tov = MBX_TOV_SECONDS;
  3495. mcp->flags = 0;
  3496. rval = qla2x00_mailbox_command(vha, mcp);
  3497. if (rval != QLA_SUCCESS) {
  3498. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3499. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3500. } else {
  3501. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
  3502. "Done %s.\n", __func__);
  3503. }
  3504. return rval;
  3505. }
  3506. int
  3507. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3508. uint16_t size_in_bytes, uint16_t *actual_size)
  3509. {
  3510. int rval;
  3511. mbx_cmd_t mc;
  3512. mbx_cmd_t *mcp = &mc;
  3513. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
  3514. "Entered %s.\n", __func__);
  3515. if (!IS_CNA_CAPABLE(vha->hw))
  3516. return QLA_FUNCTION_FAILED;
  3517. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3518. mcp->mb[2] = MSW(stats_dma);
  3519. mcp->mb[3] = LSW(stats_dma);
  3520. mcp->mb[6] = MSW(MSD(stats_dma));
  3521. mcp->mb[7] = LSW(MSD(stats_dma));
  3522. mcp->mb[8] = size_in_bytes >> 2;
  3523. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3524. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3525. mcp->tov = MBX_TOV_SECONDS;
  3526. mcp->flags = 0;
  3527. rval = qla2x00_mailbox_command(vha, mcp);
  3528. if (rval != QLA_SUCCESS) {
  3529. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3530. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3531. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3532. } else {
  3533. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
  3534. "Done %s.\n", __func__);
  3535. *actual_size = mcp->mb[2] << 2;
  3536. }
  3537. return rval;
  3538. }
  3539. int
  3540. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3541. uint16_t size)
  3542. {
  3543. int rval;
  3544. mbx_cmd_t mc;
  3545. mbx_cmd_t *mcp = &mc;
  3546. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
  3547. "Entered %s.\n", __func__);
  3548. if (!IS_CNA_CAPABLE(vha->hw))
  3549. return QLA_FUNCTION_FAILED;
  3550. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3551. mcp->mb[1] = 0;
  3552. mcp->mb[2] = MSW(tlv_dma);
  3553. mcp->mb[3] = LSW(tlv_dma);
  3554. mcp->mb[6] = MSW(MSD(tlv_dma));
  3555. mcp->mb[7] = LSW(MSD(tlv_dma));
  3556. mcp->mb[8] = size;
  3557. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3558. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3559. mcp->tov = MBX_TOV_SECONDS;
  3560. mcp->flags = 0;
  3561. rval = qla2x00_mailbox_command(vha, mcp);
  3562. if (rval != QLA_SUCCESS) {
  3563. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3564. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3565. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3566. } else {
  3567. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
  3568. "Done %s.\n", __func__);
  3569. }
  3570. return rval;
  3571. }
  3572. int
  3573. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3574. {
  3575. int rval;
  3576. mbx_cmd_t mc;
  3577. mbx_cmd_t *mcp = &mc;
  3578. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
  3579. "Entered %s.\n", __func__);
  3580. if (!IS_FWI2_CAPABLE(vha->hw))
  3581. return QLA_FUNCTION_FAILED;
  3582. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3583. mcp->mb[1] = LSW(risc_addr);
  3584. mcp->mb[8] = MSW(risc_addr);
  3585. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3586. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3587. mcp->tov = 30;
  3588. mcp->flags = 0;
  3589. rval = qla2x00_mailbox_command(vha, mcp);
  3590. if (rval != QLA_SUCCESS) {
  3591. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3592. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3593. } else {
  3594. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
  3595. "Done %s.\n", __func__);
  3596. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3597. }
  3598. return rval;
  3599. }
  3600. int
  3601. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3602. uint16_t *mresp)
  3603. {
  3604. int rval;
  3605. mbx_cmd_t mc;
  3606. mbx_cmd_t *mcp = &mc;
  3607. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
  3608. "Entered %s.\n", __func__);
  3609. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3610. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3611. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3612. /* transfer count */
  3613. mcp->mb[10] = LSW(mreq->transfer_size);
  3614. mcp->mb[11] = MSW(mreq->transfer_size);
  3615. /* send data address */
  3616. mcp->mb[14] = LSW(mreq->send_dma);
  3617. mcp->mb[15] = MSW(mreq->send_dma);
  3618. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3619. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3620. /* receive data address */
  3621. mcp->mb[16] = LSW(mreq->rcv_dma);
  3622. mcp->mb[17] = MSW(mreq->rcv_dma);
  3623. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3624. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3625. /* Iteration count */
  3626. mcp->mb[18] = LSW(mreq->iteration_count);
  3627. mcp->mb[19] = MSW(mreq->iteration_count);
  3628. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3629. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3630. if (IS_CNA_CAPABLE(vha->hw))
  3631. mcp->out_mb |= MBX_2;
  3632. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3633. mcp->buf_size = mreq->transfer_size;
  3634. mcp->tov = MBX_TOV_SECONDS;
  3635. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3636. rval = qla2x00_mailbox_command(vha, mcp);
  3637. if (rval != QLA_SUCCESS) {
  3638. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3639. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3640. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3641. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3642. } else {
  3643. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
  3644. "Done %s.\n", __func__);
  3645. }
  3646. /* Copy mailbox information */
  3647. memcpy( mresp, mcp->mb, 64);
  3648. return rval;
  3649. }
  3650. int
  3651. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3652. uint16_t *mresp)
  3653. {
  3654. int rval;
  3655. mbx_cmd_t mc;
  3656. mbx_cmd_t *mcp = &mc;
  3657. struct qla_hw_data *ha = vha->hw;
  3658. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
  3659. "Entered %s.\n", __func__);
  3660. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3661. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3662. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3663. if (IS_CNA_CAPABLE(ha)) {
  3664. mcp->mb[1] |= BIT_15;
  3665. mcp->mb[2] = vha->fcoe_fcf_idx;
  3666. }
  3667. mcp->mb[16] = LSW(mreq->rcv_dma);
  3668. mcp->mb[17] = MSW(mreq->rcv_dma);
  3669. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3670. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3671. mcp->mb[10] = LSW(mreq->transfer_size);
  3672. mcp->mb[14] = LSW(mreq->send_dma);
  3673. mcp->mb[15] = MSW(mreq->send_dma);
  3674. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3675. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3676. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3677. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3678. if (IS_CNA_CAPABLE(ha))
  3679. mcp->out_mb |= MBX_2;
  3680. mcp->in_mb = MBX_0;
  3681. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
  3682. IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3683. mcp->in_mb |= MBX_1;
  3684. if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3685. mcp->in_mb |= MBX_3;
  3686. mcp->tov = MBX_TOV_SECONDS;
  3687. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3688. mcp->buf_size = mreq->transfer_size;
  3689. rval = qla2x00_mailbox_command(vha, mcp);
  3690. if (rval != QLA_SUCCESS) {
  3691. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3692. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3693. rval, mcp->mb[0], mcp->mb[1]);
  3694. } else {
  3695. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
  3696. "Done %s.\n", __func__);
  3697. }
  3698. /* Copy mailbox information */
  3699. memcpy(mresp, mcp->mb, 64);
  3700. return rval;
  3701. }
  3702. int
  3703. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3704. {
  3705. int rval;
  3706. mbx_cmd_t mc;
  3707. mbx_cmd_t *mcp = &mc;
  3708. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
  3709. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3710. mcp->mb[0] = MBC_ISP84XX_RESET;
  3711. mcp->mb[1] = enable_diagnostic;
  3712. mcp->out_mb = MBX_1|MBX_0;
  3713. mcp->in_mb = MBX_1|MBX_0;
  3714. mcp->tov = MBX_TOV_SECONDS;
  3715. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3716. rval = qla2x00_mailbox_command(vha, mcp);
  3717. if (rval != QLA_SUCCESS)
  3718. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3719. else
  3720. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
  3721. "Done %s.\n", __func__);
  3722. return rval;
  3723. }
  3724. int
  3725. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  3726. {
  3727. int rval;
  3728. mbx_cmd_t mc;
  3729. mbx_cmd_t *mcp = &mc;
  3730. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
  3731. "Entered %s.\n", __func__);
  3732. if (!IS_FWI2_CAPABLE(vha->hw))
  3733. return QLA_FUNCTION_FAILED;
  3734. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  3735. mcp->mb[1] = LSW(risc_addr);
  3736. mcp->mb[2] = LSW(data);
  3737. mcp->mb[3] = MSW(data);
  3738. mcp->mb[8] = MSW(risc_addr);
  3739. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  3740. mcp->in_mb = MBX_0;
  3741. mcp->tov = 30;
  3742. mcp->flags = 0;
  3743. rval = qla2x00_mailbox_command(vha, mcp);
  3744. if (rval != QLA_SUCCESS) {
  3745. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  3746. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3747. } else {
  3748. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
  3749. "Done %s.\n", __func__);
  3750. }
  3751. return rval;
  3752. }
  3753. int
  3754. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  3755. {
  3756. int rval;
  3757. uint32_t stat, timer;
  3758. uint16_t mb0 = 0;
  3759. struct qla_hw_data *ha = vha->hw;
  3760. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3761. rval = QLA_SUCCESS;
  3762. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
  3763. "Entered %s.\n", __func__);
  3764. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  3765. /* Write the MBC data to the registers */
  3766. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  3767. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  3768. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  3769. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  3770. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  3771. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  3772. /* Poll for MBC interrupt */
  3773. for (timer = 6000000; timer; timer--) {
  3774. /* Check for pending interrupts. */
  3775. stat = RD_REG_DWORD(&reg->host_status);
  3776. if (stat & HSRX_RISC_INT) {
  3777. stat &= 0xff;
  3778. if (stat == 0x1 || stat == 0x2 ||
  3779. stat == 0x10 || stat == 0x11) {
  3780. set_bit(MBX_INTERRUPT,
  3781. &ha->mbx_cmd_flags);
  3782. mb0 = RD_REG_WORD(&reg->mailbox0);
  3783. WRT_REG_DWORD(&reg->hccr,
  3784. HCCRX_CLR_RISC_INT);
  3785. RD_REG_DWORD(&reg->hccr);
  3786. break;
  3787. }
  3788. }
  3789. udelay(5);
  3790. }
  3791. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  3792. rval = mb0 & MBS_MASK;
  3793. else
  3794. rval = QLA_FUNCTION_FAILED;
  3795. if (rval != QLA_SUCCESS) {
  3796. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  3797. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  3798. } else {
  3799. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
  3800. "Done %s.\n", __func__);
  3801. }
  3802. return rval;
  3803. }
  3804. int
  3805. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  3806. {
  3807. int rval;
  3808. mbx_cmd_t mc;
  3809. mbx_cmd_t *mcp = &mc;
  3810. struct qla_hw_data *ha = vha->hw;
  3811. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
  3812. "Entered %s.\n", __func__);
  3813. if (!IS_FWI2_CAPABLE(ha))
  3814. return QLA_FUNCTION_FAILED;
  3815. mcp->mb[0] = MBC_DATA_RATE;
  3816. mcp->mb[1] = 0;
  3817. mcp->out_mb = MBX_1|MBX_0;
  3818. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3819. if (IS_QLA83XX(ha))
  3820. mcp->in_mb |= MBX_3;
  3821. mcp->tov = MBX_TOV_SECONDS;
  3822. mcp->flags = 0;
  3823. rval = qla2x00_mailbox_command(vha, mcp);
  3824. if (rval != QLA_SUCCESS) {
  3825. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  3826. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3827. } else {
  3828. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
  3829. "Done %s.\n", __func__);
  3830. if (mcp->mb[1] != 0x7)
  3831. ha->link_data_rate = mcp->mb[1];
  3832. }
  3833. return rval;
  3834. }
  3835. int
  3836. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3837. {
  3838. int rval;
  3839. mbx_cmd_t mc;
  3840. mbx_cmd_t *mcp = &mc;
  3841. struct qla_hw_data *ha = vha->hw;
  3842. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
  3843. "Entered %s.\n", __func__);
  3844. if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  3845. return QLA_FUNCTION_FAILED;
  3846. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  3847. mcp->out_mb = MBX_0;
  3848. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3849. mcp->tov = MBX_TOV_SECONDS;
  3850. mcp->flags = 0;
  3851. rval = qla2x00_mailbox_command(vha, mcp);
  3852. if (rval != QLA_SUCCESS) {
  3853. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  3854. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3855. } else {
  3856. /* Copy all bits to preserve original value */
  3857. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  3858. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
  3859. "Done %s.\n", __func__);
  3860. }
  3861. return rval;
  3862. }
  3863. int
  3864. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3865. {
  3866. int rval;
  3867. mbx_cmd_t mc;
  3868. mbx_cmd_t *mcp = &mc;
  3869. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
  3870. "Entered %s.\n", __func__);
  3871. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  3872. /* Copy all bits to preserve original setting */
  3873. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  3874. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3875. mcp->in_mb = MBX_0;
  3876. mcp->tov = MBX_TOV_SECONDS;
  3877. mcp->flags = 0;
  3878. rval = qla2x00_mailbox_command(vha, mcp);
  3879. if (rval != QLA_SUCCESS) {
  3880. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  3881. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3882. } else
  3883. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
  3884. "Done %s.\n", __func__);
  3885. return rval;
  3886. }
  3887. int
  3888. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  3889. uint16_t *mb)
  3890. {
  3891. int rval;
  3892. mbx_cmd_t mc;
  3893. mbx_cmd_t *mcp = &mc;
  3894. struct qla_hw_data *ha = vha->hw;
  3895. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
  3896. "Entered %s.\n", __func__);
  3897. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  3898. return QLA_FUNCTION_FAILED;
  3899. mcp->mb[0] = MBC_PORT_PARAMS;
  3900. mcp->mb[1] = loop_id;
  3901. if (ha->flags.fcp_prio_enabled)
  3902. mcp->mb[2] = BIT_1;
  3903. else
  3904. mcp->mb[2] = BIT_2;
  3905. mcp->mb[4] = priority & 0xf;
  3906. mcp->mb[9] = vha->vp_idx;
  3907. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3908. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  3909. mcp->tov = 30;
  3910. mcp->flags = 0;
  3911. rval = qla2x00_mailbox_command(vha, mcp);
  3912. if (mb != NULL) {
  3913. mb[0] = mcp->mb[0];
  3914. mb[1] = mcp->mb[1];
  3915. mb[3] = mcp->mb[3];
  3916. mb[4] = mcp->mb[4];
  3917. }
  3918. if (rval != QLA_SUCCESS) {
  3919. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  3920. } else {
  3921. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
  3922. "Done %s.\n", __func__);
  3923. }
  3924. return rval;
  3925. }
  3926. int
  3927. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
  3928. {
  3929. int rval = QLA_FUNCTION_FAILED;
  3930. struct qla_hw_data *ha = vha->hw;
  3931. uint8_t byte;
  3932. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ca,
  3933. "Entered %s.\n", __func__);
  3934. if (ha->thermal_support & THERMAL_SUPPORT_I2C) {
  3935. rval = qla2x00_read_sfp(vha, 0, &byte,
  3936. 0x98, 0x1, 1, BIT_13|BIT_12|BIT_0);
  3937. *temp = byte;
  3938. if (rval == QLA_SUCCESS)
  3939. goto done;
  3940. ql_log(ql_log_warn, vha, 0x10c9,
  3941. "Thermal not supported through I2C bus, trying alternate "
  3942. "method (ISP access).\n");
  3943. ha->thermal_support &= ~THERMAL_SUPPORT_I2C;
  3944. }
  3945. if (ha->thermal_support & THERMAL_SUPPORT_ISP) {
  3946. rval = qla2x00_read_asic_temperature(vha, temp);
  3947. if (rval == QLA_SUCCESS)
  3948. goto done;
  3949. ql_log(ql_log_warn, vha, 0x1019,
  3950. "Thermal not supported through ISP.\n");
  3951. ha->thermal_support &= ~THERMAL_SUPPORT_ISP;
  3952. }
  3953. ql_log(ql_log_warn, vha, 0x1150,
  3954. "Thermal not supported by this card "
  3955. "(ignoring further requests).\n");
  3956. return rval;
  3957. done:
  3958. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1018,
  3959. "Done %s.\n", __func__);
  3960. return rval;
  3961. }
  3962. int
  3963. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  3964. {
  3965. int rval;
  3966. struct qla_hw_data *ha = vha->hw;
  3967. mbx_cmd_t mc;
  3968. mbx_cmd_t *mcp = &mc;
  3969. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
  3970. "Entered %s.\n", __func__);
  3971. if (!IS_FWI2_CAPABLE(ha))
  3972. return QLA_FUNCTION_FAILED;
  3973. memset(mcp, 0, sizeof(mbx_cmd_t));
  3974. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3975. mcp->mb[1] = 1;
  3976. mcp->out_mb = MBX_1|MBX_0;
  3977. mcp->in_mb = MBX_0;
  3978. mcp->tov = 30;
  3979. mcp->flags = 0;
  3980. rval = qla2x00_mailbox_command(vha, mcp);
  3981. if (rval != QLA_SUCCESS) {
  3982. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  3983. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3984. } else {
  3985. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
  3986. "Done %s.\n", __func__);
  3987. }
  3988. return rval;
  3989. }
  3990. int
  3991. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  3992. {
  3993. int rval;
  3994. struct qla_hw_data *ha = vha->hw;
  3995. mbx_cmd_t mc;
  3996. mbx_cmd_t *mcp = &mc;
  3997. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
  3998. "Entered %s.\n", __func__);
  3999. if (!IS_QLA82XX(ha))
  4000. return QLA_FUNCTION_FAILED;
  4001. memset(mcp, 0, sizeof(mbx_cmd_t));
  4002. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  4003. mcp->mb[1] = 0;
  4004. mcp->out_mb = MBX_1|MBX_0;
  4005. mcp->in_mb = MBX_0;
  4006. mcp->tov = 30;
  4007. mcp->flags = 0;
  4008. rval = qla2x00_mailbox_command(vha, mcp);
  4009. if (rval != QLA_SUCCESS) {
  4010. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  4011. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4012. } else {
  4013. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
  4014. "Done %s.\n", __func__);
  4015. }
  4016. return rval;
  4017. }
  4018. int
  4019. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  4020. {
  4021. struct qla_hw_data *ha = vha->hw;
  4022. mbx_cmd_t mc;
  4023. mbx_cmd_t *mcp = &mc;
  4024. int rval = QLA_FUNCTION_FAILED;
  4025. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
  4026. "Entered %s.\n", __func__);
  4027. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4028. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4029. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4030. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  4031. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  4032. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4033. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  4034. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4035. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4036. mcp->tov = MBX_TOV_SECONDS;
  4037. rval = qla2x00_mailbox_command(vha, mcp);
  4038. /* Always copy back return mailbox values. */
  4039. if (rval != QLA_SUCCESS) {
  4040. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  4041. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4042. (mcp->mb[1] << 16) | mcp->mb[0],
  4043. (mcp->mb[3] << 16) | mcp->mb[2]);
  4044. } else {
  4045. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
  4046. "Done %s.\n", __func__);
  4047. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  4048. if (!ha->md_template_size) {
  4049. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  4050. "Null template size obtained.\n");
  4051. rval = QLA_FUNCTION_FAILED;
  4052. }
  4053. }
  4054. return rval;
  4055. }
  4056. int
  4057. qla82xx_md_get_template(scsi_qla_host_t *vha)
  4058. {
  4059. struct qla_hw_data *ha = vha->hw;
  4060. mbx_cmd_t mc;
  4061. mbx_cmd_t *mcp = &mc;
  4062. int rval = QLA_FUNCTION_FAILED;
  4063. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
  4064. "Entered %s.\n", __func__);
  4065. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  4066. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  4067. if (!ha->md_tmplt_hdr) {
  4068. ql_log(ql_log_warn, vha, 0x1124,
  4069. "Unable to allocate memory for Minidump template.\n");
  4070. return rval;
  4071. }
  4072. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4073. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4074. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4075. mcp->mb[2] = LSW(RQST_TMPLT);
  4076. mcp->mb[3] = MSW(RQST_TMPLT);
  4077. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  4078. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  4079. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  4080. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  4081. mcp->mb[8] = LSW(ha->md_template_size);
  4082. mcp->mb[9] = MSW(ha->md_template_size);
  4083. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4084. mcp->tov = MBX_TOV_SECONDS;
  4085. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4086. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4087. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4088. rval = qla2x00_mailbox_command(vha, mcp);
  4089. if (rval != QLA_SUCCESS) {
  4090. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  4091. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4092. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4093. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4094. } else
  4095. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
  4096. "Done %s.\n", __func__);
  4097. return rval;
  4098. }
  4099. int
  4100. qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4101. {
  4102. int rval;
  4103. struct qla_hw_data *ha = vha->hw;
  4104. mbx_cmd_t mc;
  4105. mbx_cmd_t *mcp = &mc;
  4106. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4107. return QLA_FUNCTION_FAILED;
  4108. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
  4109. "Entered %s.\n", __func__);
  4110. memset(mcp, 0, sizeof(mbx_cmd_t));
  4111. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4112. mcp->mb[1] = led_cfg[0];
  4113. mcp->mb[2] = led_cfg[1];
  4114. if (IS_QLA8031(ha)) {
  4115. mcp->mb[3] = led_cfg[2];
  4116. mcp->mb[4] = led_cfg[3];
  4117. mcp->mb[5] = led_cfg[4];
  4118. mcp->mb[6] = led_cfg[5];
  4119. }
  4120. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4121. if (IS_QLA8031(ha))
  4122. mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4123. mcp->in_mb = MBX_0;
  4124. mcp->tov = 30;
  4125. mcp->flags = 0;
  4126. rval = qla2x00_mailbox_command(vha, mcp);
  4127. if (rval != QLA_SUCCESS) {
  4128. ql_dbg(ql_dbg_mbx, vha, 0x1134,
  4129. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4130. } else {
  4131. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
  4132. "Done %s.\n", __func__);
  4133. }
  4134. return rval;
  4135. }
  4136. int
  4137. qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4138. {
  4139. int rval;
  4140. struct qla_hw_data *ha = vha->hw;
  4141. mbx_cmd_t mc;
  4142. mbx_cmd_t *mcp = &mc;
  4143. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4144. return QLA_FUNCTION_FAILED;
  4145. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
  4146. "Entered %s.\n", __func__);
  4147. memset(mcp, 0, sizeof(mbx_cmd_t));
  4148. mcp->mb[0] = MBC_GET_LED_CONFIG;
  4149. mcp->out_mb = MBX_0;
  4150. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4151. if (IS_QLA8031(ha))
  4152. mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4153. mcp->tov = 30;
  4154. mcp->flags = 0;
  4155. rval = qla2x00_mailbox_command(vha, mcp);
  4156. if (rval != QLA_SUCCESS) {
  4157. ql_dbg(ql_dbg_mbx, vha, 0x1137,
  4158. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4159. } else {
  4160. led_cfg[0] = mcp->mb[1];
  4161. led_cfg[1] = mcp->mb[2];
  4162. if (IS_QLA8031(ha)) {
  4163. led_cfg[2] = mcp->mb[3];
  4164. led_cfg[3] = mcp->mb[4];
  4165. led_cfg[4] = mcp->mb[5];
  4166. led_cfg[5] = mcp->mb[6];
  4167. }
  4168. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
  4169. "Done %s.\n", __func__);
  4170. }
  4171. return rval;
  4172. }
  4173. int
  4174. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  4175. {
  4176. int rval;
  4177. struct qla_hw_data *ha = vha->hw;
  4178. mbx_cmd_t mc;
  4179. mbx_cmd_t *mcp = &mc;
  4180. if (!IS_QLA82XX(ha))
  4181. return QLA_FUNCTION_FAILED;
  4182. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
  4183. "Entered %s.\n", __func__);
  4184. memset(mcp, 0, sizeof(mbx_cmd_t));
  4185. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4186. if (enable)
  4187. mcp->mb[7] = 0xE;
  4188. else
  4189. mcp->mb[7] = 0xD;
  4190. mcp->out_mb = MBX_7|MBX_0;
  4191. mcp->in_mb = MBX_0;
  4192. mcp->tov = MBX_TOV_SECONDS;
  4193. mcp->flags = 0;
  4194. rval = qla2x00_mailbox_command(vha, mcp);
  4195. if (rval != QLA_SUCCESS) {
  4196. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  4197. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4198. } else {
  4199. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
  4200. "Done %s.\n", __func__);
  4201. }
  4202. return rval;
  4203. }
  4204. int
  4205. qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
  4206. {
  4207. int rval;
  4208. struct qla_hw_data *ha = vha->hw;
  4209. mbx_cmd_t mc;
  4210. mbx_cmd_t *mcp = &mc;
  4211. if (!IS_QLA83XX(ha))
  4212. return QLA_FUNCTION_FAILED;
  4213. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
  4214. "Entered %s.\n", __func__);
  4215. mcp->mb[0] = MBC_WRITE_REMOTE_REG;
  4216. mcp->mb[1] = LSW(reg);
  4217. mcp->mb[2] = MSW(reg);
  4218. mcp->mb[3] = LSW(data);
  4219. mcp->mb[4] = MSW(data);
  4220. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4221. mcp->in_mb = MBX_1|MBX_0;
  4222. mcp->tov = MBX_TOV_SECONDS;
  4223. mcp->flags = 0;
  4224. rval = qla2x00_mailbox_command(vha, mcp);
  4225. if (rval != QLA_SUCCESS) {
  4226. ql_dbg(ql_dbg_mbx, vha, 0x1131,
  4227. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4228. } else {
  4229. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
  4230. "Done %s.\n", __func__);
  4231. }
  4232. return rval;
  4233. }
  4234. int
  4235. qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
  4236. {
  4237. int rval;
  4238. struct qla_hw_data *ha = vha->hw;
  4239. mbx_cmd_t mc;
  4240. mbx_cmd_t *mcp = &mc;
  4241. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  4242. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
  4243. "Implicit LOGO Unsupported.\n");
  4244. return QLA_FUNCTION_FAILED;
  4245. }
  4246. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
  4247. "Entering %s.\n", __func__);
  4248. /* Perform Implicit LOGO. */
  4249. mcp->mb[0] = MBC_PORT_LOGOUT;
  4250. mcp->mb[1] = fcport->loop_id;
  4251. mcp->mb[10] = BIT_15;
  4252. mcp->out_mb = MBX_10|MBX_1|MBX_0;
  4253. mcp->in_mb = MBX_0;
  4254. mcp->tov = MBX_TOV_SECONDS;
  4255. mcp->flags = 0;
  4256. rval = qla2x00_mailbox_command(vha, mcp);
  4257. if (rval != QLA_SUCCESS)
  4258. ql_dbg(ql_dbg_mbx, vha, 0x113d,
  4259. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4260. else
  4261. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
  4262. "Done %s.\n", __func__);
  4263. return rval;
  4264. }
  4265. int
  4266. qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
  4267. {
  4268. int rval;
  4269. mbx_cmd_t mc;
  4270. mbx_cmd_t *mcp = &mc;
  4271. struct qla_hw_data *ha = vha->hw;
  4272. unsigned long retry_max_time = jiffies + (2 * HZ);
  4273. if (!IS_QLA83XX(ha))
  4274. return QLA_FUNCTION_FAILED;
  4275. ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
  4276. retry_rd_reg:
  4277. mcp->mb[0] = MBC_READ_REMOTE_REG;
  4278. mcp->mb[1] = LSW(reg);
  4279. mcp->mb[2] = MSW(reg);
  4280. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4281. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  4282. mcp->tov = MBX_TOV_SECONDS;
  4283. mcp->flags = 0;
  4284. rval = qla2x00_mailbox_command(vha, mcp);
  4285. if (rval != QLA_SUCCESS) {
  4286. ql_dbg(ql_dbg_mbx, vha, 0x114c,
  4287. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4288. rval, mcp->mb[0], mcp->mb[1]);
  4289. } else {
  4290. *data = (mcp->mb[3] | (mcp->mb[4] << 16));
  4291. if (*data == QLA8XXX_BAD_VALUE) {
  4292. /*
  4293. * During soft-reset CAMRAM register reads might
  4294. * return 0xbad0bad0. So retry for MAX of 2 sec
  4295. * while reading camram registers.
  4296. */
  4297. if (time_after(jiffies, retry_max_time)) {
  4298. ql_dbg(ql_dbg_mbx, vha, 0x1141,
  4299. "Failure to read CAMRAM register. "
  4300. "data=0x%x.\n", *data);
  4301. return QLA_FUNCTION_FAILED;
  4302. }
  4303. msleep(100);
  4304. goto retry_rd_reg;
  4305. }
  4306. ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
  4307. }
  4308. return rval;
  4309. }
  4310. int
  4311. qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
  4312. {
  4313. int rval;
  4314. mbx_cmd_t mc;
  4315. mbx_cmd_t *mcp = &mc;
  4316. struct qla_hw_data *ha = vha->hw;
  4317. if (!IS_QLA83XX(ha))
  4318. return QLA_FUNCTION_FAILED;
  4319. ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
  4320. mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
  4321. mcp->out_mb = MBX_0;
  4322. mcp->in_mb = MBX_1|MBX_0;
  4323. mcp->tov = MBX_TOV_SECONDS;
  4324. mcp->flags = 0;
  4325. rval = qla2x00_mailbox_command(vha, mcp);
  4326. if (rval != QLA_SUCCESS) {
  4327. ql_dbg(ql_dbg_mbx, vha, 0x1144,
  4328. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4329. rval, mcp->mb[0], mcp->mb[1]);
  4330. ha->isp_ops->fw_dump(vha, 0);
  4331. } else {
  4332. ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
  4333. }
  4334. return rval;
  4335. }
  4336. int
  4337. qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
  4338. uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
  4339. {
  4340. int rval;
  4341. mbx_cmd_t mc;
  4342. mbx_cmd_t *mcp = &mc;
  4343. uint8_t subcode = (uint8_t)options;
  4344. struct qla_hw_data *ha = vha->hw;
  4345. if (!IS_QLA8031(ha))
  4346. return QLA_FUNCTION_FAILED;
  4347. ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
  4348. mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
  4349. mcp->mb[1] = options;
  4350. mcp->out_mb = MBX_1|MBX_0;
  4351. if (subcode & BIT_2) {
  4352. mcp->mb[2] = LSW(start_addr);
  4353. mcp->mb[3] = MSW(start_addr);
  4354. mcp->mb[4] = LSW(end_addr);
  4355. mcp->mb[5] = MSW(end_addr);
  4356. mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
  4357. }
  4358. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4359. if (!(subcode & (BIT_2 | BIT_5)))
  4360. mcp->in_mb |= MBX_4|MBX_3;
  4361. mcp->tov = MBX_TOV_SECONDS;
  4362. mcp->flags = 0;
  4363. rval = qla2x00_mailbox_command(vha, mcp);
  4364. if (rval != QLA_SUCCESS) {
  4365. ql_dbg(ql_dbg_mbx, vha, 0x1147,
  4366. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
  4367. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
  4368. mcp->mb[4]);
  4369. ha->isp_ops->fw_dump(vha, 0);
  4370. } else {
  4371. if (subcode & BIT_5)
  4372. *sector_size = mcp->mb[1];
  4373. else if (subcode & (BIT_6 | BIT_7)) {
  4374. ql_dbg(ql_dbg_mbx, vha, 0x1148,
  4375. "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4376. } else if (subcode & (BIT_3 | BIT_4)) {
  4377. ql_dbg(ql_dbg_mbx, vha, 0x1149,
  4378. "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4379. }
  4380. ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
  4381. }
  4382. return rval;
  4383. }
  4384. int
  4385. qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  4386. uint32_t size)
  4387. {
  4388. int rval;
  4389. mbx_cmd_t mc;
  4390. mbx_cmd_t *mcp = &mc;
  4391. if (!IS_MCTP_CAPABLE(vha->hw))
  4392. return QLA_FUNCTION_FAILED;
  4393. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
  4394. "Entered %s.\n", __func__);
  4395. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  4396. mcp->mb[1] = LSW(addr);
  4397. mcp->mb[2] = MSW(req_dma);
  4398. mcp->mb[3] = LSW(req_dma);
  4399. mcp->mb[4] = MSW(size);
  4400. mcp->mb[5] = LSW(size);
  4401. mcp->mb[6] = MSW(MSD(req_dma));
  4402. mcp->mb[7] = LSW(MSD(req_dma));
  4403. mcp->mb[8] = MSW(addr);
  4404. /* Setting RAM ID to valid */
  4405. mcp->mb[10] |= BIT_7;
  4406. /* For MCTP RAM ID is 0x40 */
  4407. mcp->mb[10] |= 0x40;
  4408. mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
  4409. MBX_0;
  4410. mcp->in_mb = MBX_0;
  4411. mcp->tov = MBX_TOV_SECONDS;
  4412. mcp->flags = 0;
  4413. rval = qla2x00_mailbox_command(vha, mcp);
  4414. if (rval != QLA_SUCCESS) {
  4415. ql_dbg(ql_dbg_mbx, vha, 0x114e,
  4416. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4417. } else {
  4418. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
  4419. "Done %s.\n", __func__);
  4420. }
  4421. return rval;
  4422. }