pci.c 34 KB

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  1. /*
  2. * Sonics Silicon Backplane PCI-Hostbus related functions.
  3. *
  4. * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
  5. * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  7. * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  8. * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. *
  10. * Derived from the Broadcom 4400 device driver.
  11. * Copyright (C) 2002 David S. Miller (davem@redhat.com)
  12. * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  13. * Copyright (C) 2006 Broadcom Corporation.
  14. *
  15. * Licensed under the GNU/GPL. See COPYING for details.
  16. */
  17. #include <linux/ssb/ssb.h>
  18. #include <linux/ssb/ssb_regs.h>
  19. #include <linux/slab.h>
  20. #include <linux/pci.h>
  21. #include <linux/delay.h>
  22. #include "ssb_private.h"
  23. /* Define the following to 1 to enable a printk on each coreswitch. */
  24. #define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
  25. /* Lowlevel coreswitching */
  26. int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
  27. {
  28. int err;
  29. int attempts = 0;
  30. u32 cur_core;
  31. while (1) {
  32. err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
  33. (coreidx * SSB_CORE_SIZE)
  34. + SSB_ENUM_BASE);
  35. if (err)
  36. goto error;
  37. err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
  38. &cur_core);
  39. if (err)
  40. goto error;
  41. cur_core = (cur_core - SSB_ENUM_BASE)
  42. / SSB_CORE_SIZE;
  43. if (cur_core == coreidx)
  44. break;
  45. if (attempts++ > SSB_BAR0_MAX_RETRIES)
  46. goto error;
  47. udelay(10);
  48. }
  49. return 0;
  50. error:
  51. ssb_err("Failed to switch to core %u\n", coreidx);
  52. return -ENODEV;
  53. }
  54. int ssb_pci_switch_core(struct ssb_bus *bus,
  55. struct ssb_device *dev)
  56. {
  57. int err;
  58. unsigned long flags;
  59. #if SSB_VERBOSE_PCICORESWITCH_DEBUG
  60. ssb_info("Switching to %s core, index %d\n",
  61. ssb_core_name(dev->id.coreid),
  62. dev->core_index);
  63. #endif
  64. spin_lock_irqsave(&bus->bar_lock, flags);
  65. err = ssb_pci_switch_coreidx(bus, dev->core_index);
  66. if (!err)
  67. bus->mapped_device = dev;
  68. spin_unlock_irqrestore(&bus->bar_lock, flags);
  69. return err;
  70. }
  71. /* Enable/disable the on board crystal oscillator and/or PLL. */
  72. int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
  73. {
  74. int err;
  75. u32 in, out, outenable;
  76. u16 pci_status;
  77. if (bus->bustype != SSB_BUSTYPE_PCI)
  78. return 0;
  79. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
  80. if (err)
  81. goto err_pci;
  82. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
  83. if (err)
  84. goto err_pci;
  85. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
  86. if (err)
  87. goto err_pci;
  88. outenable |= what;
  89. if (turn_on) {
  90. /* Avoid glitching the clock if GPRS is already using it.
  91. * We can't actually read the state of the PLLPD so we infer it
  92. * by the value of XTAL_PU which *is* readable via gpioin.
  93. */
  94. if (!(in & SSB_GPIO_XTAL)) {
  95. if (what & SSB_GPIO_XTAL) {
  96. /* Turn the crystal on */
  97. out |= SSB_GPIO_XTAL;
  98. if (what & SSB_GPIO_PLL)
  99. out |= SSB_GPIO_PLL;
  100. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  101. if (err)
  102. goto err_pci;
  103. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
  104. outenable);
  105. if (err)
  106. goto err_pci;
  107. msleep(1);
  108. }
  109. if (what & SSB_GPIO_PLL) {
  110. /* Turn the PLL on */
  111. out &= ~SSB_GPIO_PLL;
  112. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  113. if (err)
  114. goto err_pci;
  115. msleep(5);
  116. }
  117. }
  118. err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
  119. if (err)
  120. goto err_pci;
  121. pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
  122. err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
  123. if (err)
  124. goto err_pci;
  125. } else {
  126. if (what & SSB_GPIO_XTAL) {
  127. /* Turn the crystal off */
  128. out &= ~SSB_GPIO_XTAL;
  129. }
  130. if (what & SSB_GPIO_PLL) {
  131. /* Turn the PLL off */
  132. out |= SSB_GPIO_PLL;
  133. }
  134. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  135. if (err)
  136. goto err_pci;
  137. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
  138. if (err)
  139. goto err_pci;
  140. }
  141. out:
  142. return err;
  143. err_pci:
  144. printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
  145. err = -EBUSY;
  146. goto out;
  147. }
  148. /* Get the word-offset for a SSB_SPROM_XXX define. */
  149. #define SPOFF(offset) ((offset) / sizeof(u16))
  150. /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
  151. #define SPEX16(_outvar, _offset, _mask, _shift) \
  152. out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
  153. #define SPEX32(_outvar, _offset, _mask, _shift) \
  154. out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
  155. in[SPOFF(_offset)]) & (_mask)) >> (_shift))
  156. #define SPEX(_outvar, _offset, _mask, _shift) \
  157. SPEX16(_outvar, _offset, _mask, _shift)
  158. #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
  159. do { \
  160. SPEX(_field[0], _offset + 0, _mask, _shift); \
  161. SPEX(_field[1], _offset + 2, _mask, _shift); \
  162. SPEX(_field[2], _offset + 4, _mask, _shift); \
  163. SPEX(_field[3], _offset + 6, _mask, _shift); \
  164. SPEX(_field[4], _offset + 8, _mask, _shift); \
  165. SPEX(_field[5], _offset + 10, _mask, _shift); \
  166. SPEX(_field[6], _offset + 12, _mask, _shift); \
  167. SPEX(_field[7], _offset + 14, _mask, _shift); \
  168. } while (0)
  169. static inline u8 ssb_crc8(u8 crc, u8 data)
  170. {
  171. /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
  172. static const u8 t[] = {
  173. 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
  174. 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
  175. 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
  176. 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
  177. 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
  178. 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
  179. 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
  180. 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
  181. 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
  182. 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
  183. 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
  184. 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
  185. 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
  186. 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
  187. 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
  188. 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
  189. 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
  190. 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
  191. 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
  192. 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
  193. 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
  194. 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
  195. 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
  196. 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
  197. 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
  198. 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
  199. 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
  200. 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
  201. 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
  202. 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
  203. 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
  204. 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
  205. };
  206. return t[crc ^ data];
  207. }
  208. static void sprom_get_mac(char *mac, const u16 *in)
  209. {
  210. int i;
  211. for (i = 0; i < 3; i++) {
  212. *mac++ = in[i] >> 8;
  213. *mac++ = in[i];
  214. }
  215. }
  216. static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
  217. {
  218. int word;
  219. u8 crc = 0xFF;
  220. for (word = 0; word < size - 1; word++) {
  221. crc = ssb_crc8(crc, sprom[word] & 0x00FF);
  222. crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
  223. }
  224. crc = ssb_crc8(crc, sprom[size - 1] & 0x00FF);
  225. crc ^= 0xFF;
  226. return crc;
  227. }
  228. static int sprom_check_crc(const u16 *sprom, size_t size)
  229. {
  230. u8 crc;
  231. u8 expected_crc;
  232. u16 tmp;
  233. crc = ssb_sprom_crc(sprom, size);
  234. tmp = sprom[size - 1] & SSB_SPROM_REVISION_CRC;
  235. expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
  236. if (crc != expected_crc)
  237. return -EPROTO;
  238. return 0;
  239. }
  240. static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
  241. {
  242. int i;
  243. for (i = 0; i < bus->sprom_size; i++)
  244. sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
  245. return 0;
  246. }
  247. static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
  248. {
  249. struct pci_dev *pdev = bus->host_pci;
  250. int i, err;
  251. u32 spromctl;
  252. u16 size = bus->sprom_size;
  253. ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
  254. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  255. if (err)
  256. goto err_ctlreg;
  257. spromctl |= SSB_SPROMCTL_WE;
  258. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  259. if (err)
  260. goto err_ctlreg;
  261. ssb_notice("[ 0%%");
  262. msleep(500);
  263. for (i = 0; i < size; i++) {
  264. if (i == size / 4)
  265. ssb_cont("25%%");
  266. else if (i == size / 2)
  267. ssb_cont("50%%");
  268. else if (i == (size * 3) / 4)
  269. ssb_cont("75%%");
  270. else if (i % 2)
  271. ssb_cont(".");
  272. writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
  273. mmiowb();
  274. msleep(20);
  275. }
  276. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  277. if (err)
  278. goto err_ctlreg;
  279. spromctl &= ~SSB_SPROMCTL_WE;
  280. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  281. if (err)
  282. goto err_ctlreg;
  283. msleep(500);
  284. ssb_cont("100%% ]\n");
  285. ssb_notice("SPROM written\n");
  286. return 0;
  287. err_ctlreg:
  288. ssb_err("Could not access SPROM control register.\n");
  289. return err;
  290. }
  291. static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
  292. u16 mask, u16 shift)
  293. {
  294. u16 v;
  295. u8 gain;
  296. v = in[SPOFF(SSB_SPROM1_AGAIN)];
  297. gain = (v & mask) >> shift;
  298. if (gain == 0xFF)
  299. gain = 2; /* If unset use 2dBm */
  300. if (sprom_revision == 1) {
  301. /* Convert to Q5.2 */
  302. gain <<= 2;
  303. } else {
  304. /* Q5.2 Fractional part is stored in 0xC0 */
  305. gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
  306. }
  307. return (s8)gain;
  308. }
  309. static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
  310. {
  311. u16 loc[3];
  312. if (out->revision == 3) /* rev 3 moved MAC */
  313. loc[0] = SSB_SPROM3_IL0MAC;
  314. else {
  315. loc[0] = SSB_SPROM1_IL0MAC;
  316. loc[1] = SSB_SPROM1_ET0MAC;
  317. loc[2] = SSB_SPROM1_ET1MAC;
  318. }
  319. sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
  320. if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
  321. sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
  322. sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
  323. }
  324. SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
  325. SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
  326. SSB_SPROM1_ETHPHY_ET1A_SHIFT);
  327. SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
  328. SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
  329. SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
  330. SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
  331. if (out->revision == 1)
  332. SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
  333. SSB_SPROM1_BINF_CCODE_SHIFT);
  334. SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
  335. SSB_SPROM1_BINF_ANTA_SHIFT);
  336. SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
  337. SSB_SPROM1_BINF_ANTBG_SHIFT);
  338. SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
  339. SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
  340. SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
  341. SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
  342. SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
  343. SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
  344. SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
  345. SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
  346. SSB_SPROM1_GPIOA_P1_SHIFT);
  347. SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
  348. SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
  349. SSB_SPROM1_GPIOB_P3_SHIFT);
  350. SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
  351. SSB_SPROM1_MAXPWR_A_SHIFT);
  352. SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
  353. SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
  354. SSB_SPROM1_ITSSI_A_SHIFT);
  355. SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
  356. SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
  357. if (out->revision >= 2)
  358. SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  359. SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
  360. SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
  361. /* Extract the antenna gain values. */
  362. out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
  363. SSB_SPROM1_AGAIN_BG,
  364. SSB_SPROM1_AGAIN_BG_SHIFT);
  365. out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
  366. SSB_SPROM1_AGAIN_A,
  367. SSB_SPROM1_AGAIN_A_SHIFT);
  368. }
  369. /* Revs 4 5 and 8 have partially shared layout */
  370. static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
  371. {
  372. SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
  373. SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
  374. SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
  375. SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
  376. SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
  377. SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
  378. SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
  379. SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
  380. SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
  381. SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
  382. SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
  383. SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
  384. SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
  385. SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
  386. SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
  387. SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
  388. SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
  389. SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
  390. SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
  391. SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
  392. SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
  393. SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
  394. SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
  395. SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
  396. SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
  397. SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
  398. SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
  399. SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
  400. SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
  401. SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
  402. SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
  403. SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
  404. }
  405. static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
  406. {
  407. u16 il0mac_offset;
  408. if (out->revision == 4)
  409. il0mac_offset = SSB_SPROM4_IL0MAC;
  410. else
  411. il0mac_offset = SSB_SPROM5_IL0MAC;
  412. sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
  413. SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
  414. SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
  415. SSB_SPROM4_ETHPHY_ET1A_SHIFT);
  416. SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
  417. SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
  418. if (out->revision == 4) {
  419. SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
  420. SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
  421. SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
  422. SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
  423. SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
  424. SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
  425. } else {
  426. SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
  427. SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
  428. SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
  429. SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
  430. SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
  431. SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
  432. }
  433. SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
  434. SSB_SPROM4_ANTAVAIL_A_SHIFT);
  435. SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
  436. SSB_SPROM4_ANTAVAIL_BG_SHIFT);
  437. SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
  438. SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
  439. SSB_SPROM4_ITSSI_BG_SHIFT);
  440. SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
  441. SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
  442. SSB_SPROM4_ITSSI_A_SHIFT);
  443. if (out->revision == 4) {
  444. SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
  445. SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
  446. SSB_SPROM4_GPIOA_P1_SHIFT);
  447. SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
  448. SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
  449. SSB_SPROM4_GPIOB_P3_SHIFT);
  450. } else {
  451. SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
  452. SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
  453. SSB_SPROM5_GPIOA_P1_SHIFT);
  454. SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
  455. SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
  456. SSB_SPROM5_GPIOB_P3_SHIFT);
  457. }
  458. /* Extract the antenna gain values. */
  459. SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
  460. SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
  461. SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
  462. SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
  463. SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
  464. SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
  465. SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
  466. SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
  467. sprom_extract_r458(out, in);
  468. /* TODO - get remaining rev 4 stuff needed */
  469. }
  470. static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
  471. {
  472. int i;
  473. u16 o;
  474. u16 pwr_info_offset[] = {
  475. SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
  476. SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
  477. };
  478. BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
  479. ARRAY_SIZE(out->core_pwr_info));
  480. /* extract the MAC address */
  481. sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
  482. SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
  483. SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
  484. SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
  485. SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
  486. SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
  487. SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
  488. SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
  489. SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
  490. SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
  491. SSB_SPROM8_ANTAVAIL_A_SHIFT);
  492. SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
  493. SSB_SPROM8_ANTAVAIL_BG_SHIFT);
  494. SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
  495. SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
  496. SSB_SPROM8_ITSSI_BG_SHIFT);
  497. SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
  498. SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
  499. SSB_SPROM8_ITSSI_A_SHIFT);
  500. SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
  501. SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
  502. SSB_SPROM8_MAXP_AL_SHIFT);
  503. SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
  504. SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
  505. SSB_SPROM8_GPIOA_P1_SHIFT);
  506. SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
  507. SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
  508. SSB_SPROM8_GPIOB_P3_SHIFT);
  509. SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
  510. SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
  511. SSB_SPROM8_TRI5G_SHIFT);
  512. SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
  513. SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
  514. SSB_SPROM8_TRI5GH_SHIFT);
  515. SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
  516. SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
  517. SSB_SPROM8_RXPO5G_SHIFT);
  518. SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
  519. SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
  520. SSB_SPROM8_RSSISMC2G_SHIFT);
  521. SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
  522. SSB_SPROM8_RSSISAV2G_SHIFT);
  523. SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
  524. SSB_SPROM8_BXA2G_SHIFT);
  525. SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
  526. SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
  527. SSB_SPROM8_RSSISMC5G_SHIFT);
  528. SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
  529. SSB_SPROM8_RSSISAV5G_SHIFT);
  530. SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
  531. SSB_SPROM8_BXA5G_SHIFT);
  532. SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
  533. SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
  534. SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
  535. SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
  536. SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
  537. SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
  538. SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
  539. SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
  540. SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
  541. SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
  542. SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
  543. SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
  544. SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
  545. SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
  546. SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
  547. SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
  548. SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
  549. /* Extract the antenna gain values. */
  550. SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
  551. SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
  552. SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
  553. SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
  554. SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
  555. SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
  556. SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
  557. SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
  558. /* Extract cores power info info */
  559. for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
  560. o = pwr_info_offset[i];
  561. SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
  562. SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
  563. SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
  564. SSB_SPROM8_2G_MAXP, 0);
  565. SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
  566. SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
  567. SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
  568. SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
  569. SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
  570. SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
  571. SSB_SPROM8_5G_MAXP, 0);
  572. SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
  573. SSB_SPROM8_5GH_MAXP, 0);
  574. SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
  575. SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
  576. SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
  577. SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
  578. SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
  579. SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
  580. SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
  581. SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
  582. SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
  583. SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
  584. SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
  585. }
  586. /* Extract FEM info */
  587. SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
  588. SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
  589. SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
  590. SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
  591. SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
  592. SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
  593. SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
  594. SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
  595. SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
  596. SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
  597. SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
  598. SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
  599. SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
  600. SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
  601. SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
  602. SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
  603. SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
  604. SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
  605. SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
  606. SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
  607. SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
  608. SSB_SPROM8_LEDDC_ON_SHIFT);
  609. SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
  610. SSB_SPROM8_LEDDC_OFF_SHIFT);
  611. SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
  612. SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
  613. SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
  614. SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
  615. SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
  616. SSB_SPROM8_TXRXC_SWITCH_SHIFT);
  617. SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
  618. SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
  619. SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
  620. SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
  621. SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
  622. SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
  623. SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
  624. SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
  625. SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
  626. SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
  627. SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
  628. SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
  629. SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
  630. SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
  631. SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
  632. SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
  633. SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
  634. SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
  635. SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
  636. SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
  637. SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
  638. SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
  639. SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
  640. SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
  641. SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
  642. SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
  643. SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
  644. SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
  645. SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
  646. SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
  647. SSB_SPROM8_THERMAL_TRESH_SHIFT);
  648. SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
  649. SSB_SPROM8_THERMAL_OFFSET_SHIFT);
  650. SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
  651. SSB_SPROM8_TEMPDELTA_PHYCAL,
  652. SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
  653. SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
  654. SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
  655. SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
  656. SSB_SPROM8_TEMPDELTA_HYSTERESIS,
  657. SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
  658. sprom_extract_r458(out, in);
  659. /* TODO - get remaining rev 8 stuff needed */
  660. }
  661. static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
  662. const u16 *in, u16 size)
  663. {
  664. memset(out, 0, sizeof(*out));
  665. out->revision = in[size - 1] & 0x00FF;
  666. ssb_dbg("SPROM revision %d detected\n", out->revision);
  667. memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
  668. memset(out->et1mac, 0xFF, 6);
  669. if ((bus->chip_id & 0xFF00) == 0x4400) {
  670. /* Workaround: The BCM44XX chip has a stupid revision
  671. * number stored in the SPROM.
  672. * Always extract r1. */
  673. out->revision = 1;
  674. ssb_dbg("SPROM treated as revision %d\n", out->revision);
  675. }
  676. switch (out->revision) {
  677. case 1:
  678. case 2:
  679. case 3:
  680. sprom_extract_r123(out, in);
  681. break;
  682. case 4:
  683. case 5:
  684. sprom_extract_r45(out, in);
  685. break;
  686. case 8:
  687. sprom_extract_r8(out, in);
  688. break;
  689. default:
  690. ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
  691. out->revision);
  692. out->revision = 1;
  693. sprom_extract_r123(out, in);
  694. }
  695. if (out->boardflags_lo == 0xFFFF)
  696. out->boardflags_lo = 0; /* per specs */
  697. if (out->boardflags_hi == 0xFFFF)
  698. out->boardflags_hi = 0; /* per specs */
  699. return 0;
  700. }
  701. static int ssb_pci_sprom_get(struct ssb_bus *bus,
  702. struct ssb_sprom *sprom)
  703. {
  704. int err;
  705. u16 *buf;
  706. if (!ssb_is_sprom_available(bus)) {
  707. ssb_err("No SPROM available!\n");
  708. return -ENODEV;
  709. }
  710. if (bus->chipco.dev) { /* can be unavailable! */
  711. /*
  712. * get SPROM offset: SSB_SPROM_BASE1 except for
  713. * chipcommon rev >= 31 or chip ID is 0x4312 and
  714. * chipcommon status & 3 == 2
  715. */
  716. if (bus->chipco.dev->id.revision >= 31)
  717. bus->sprom_offset = SSB_SPROM_BASE31;
  718. else if (bus->chip_id == 0x4312 &&
  719. (bus->chipco.status & 0x03) == 2)
  720. bus->sprom_offset = SSB_SPROM_BASE31;
  721. else
  722. bus->sprom_offset = SSB_SPROM_BASE1;
  723. } else {
  724. bus->sprom_offset = SSB_SPROM_BASE1;
  725. }
  726. ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
  727. buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
  728. if (!buf)
  729. return -ENOMEM;
  730. bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
  731. sprom_do_read(bus, buf);
  732. err = sprom_check_crc(buf, bus->sprom_size);
  733. if (err) {
  734. /* try for a 440 byte SPROM - revision 4 and higher */
  735. kfree(buf);
  736. buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
  737. GFP_KERNEL);
  738. if (!buf)
  739. return -ENOMEM;
  740. bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
  741. sprom_do_read(bus, buf);
  742. err = sprom_check_crc(buf, bus->sprom_size);
  743. if (err) {
  744. /* All CRC attempts failed.
  745. * Maybe there is no SPROM on the device?
  746. * Now we ask the arch code if there is some sprom
  747. * available for this device in some other storage */
  748. err = ssb_fill_sprom_with_fallback(bus, sprom);
  749. if (err) {
  750. ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
  751. err);
  752. } else {
  753. ssb_dbg("Using SPROM revision %d provided by platform\n",
  754. sprom->revision);
  755. err = 0;
  756. goto out_free;
  757. }
  758. ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
  759. }
  760. }
  761. err = sprom_extract(bus, sprom, buf, bus->sprom_size);
  762. out_free:
  763. kfree(buf);
  764. return err;
  765. }
  766. static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
  767. struct ssb_boardinfo *bi)
  768. {
  769. bi->vendor = bus->host_pci->subsystem_vendor;
  770. bi->type = bus->host_pci->subsystem_device;
  771. }
  772. int ssb_pci_get_invariants(struct ssb_bus *bus,
  773. struct ssb_init_invariants *iv)
  774. {
  775. int err;
  776. err = ssb_pci_sprom_get(bus, &iv->sprom);
  777. if (err)
  778. goto out;
  779. ssb_pci_get_boardinfo(bus, &iv->boardinfo);
  780. out:
  781. return err;
  782. }
  783. #ifdef CONFIG_SSB_DEBUG
  784. static int ssb_pci_assert_buspower(struct ssb_bus *bus)
  785. {
  786. if (likely(bus->powered_up))
  787. return 0;
  788. printk(KERN_ERR PFX "FATAL ERROR: Bus powered down "
  789. "while accessing PCI MMIO space\n");
  790. if (bus->power_warn_count <= 10) {
  791. bus->power_warn_count++;
  792. dump_stack();
  793. }
  794. return -ENODEV;
  795. }
  796. #else /* DEBUG */
  797. static inline int ssb_pci_assert_buspower(struct ssb_bus *bus)
  798. {
  799. return 0;
  800. }
  801. #endif /* DEBUG */
  802. static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
  803. {
  804. struct ssb_bus *bus = dev->bus;
  805. if (unlikely(ssb_pci_assert_buspower(bus)))
  806. return 0xFF;
  807. if (unlikely(bus->mapped_device != dev)) {
  808. if (unlikely(ssb_pci_switch_core(bus, dev)))
  809. return 0xFF;
  810. }
  811. return ioread8(bus->mmio + offset);
  812. }
  813. static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
  814. {
  815. struct ssb_bus *bus = dev->bus;
  816. if (unlikely(ssb_pci_assert_buspower(bus)))
  817. return 0xFFFF;
  818. if (unlikely(bus->mapped_device != dev)) {
  819. if (unlikely(ssb_pci_switch_core(bus, dev)))
  820. return 0xFFFF;
  821. }
  822. return ioread16(bus->mmio + offset);
  823. }
  824. static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
  825. {
  826. struct ssb_bus *bus = dev->bus;
  827. if (unlikely(ssb_pci_assert_buspower(bus)))
  828. return 0xFFFFFFFF;
  829. if (unlikely(bus->mapped_device != dev)) {
  830. if (unlikely(ssb_pci_switch_core(bus, dev)))
  831. return 0xFFFFFFFF;
  832. }
  833. return ioread32(bus->mmio + offset);
  834. }
  835. #ifdef CONFIG_SSB_BLOCKIO
  836. static void ssb_pci_block_read(struct ssb_device *dev, void *buffer,
  837. size_t count, u16 offset, u8 reg_width)
  838. {
  839. struct ssb_bus *bus = dev->bus;
  840. void __iomem *addr = bus->mmio + offset;
  841. if (unlikely(ssb_pci_assert_buspower(bus)))
  842. goto error;
  843. if (unlikely(bus->mapped_device != dev)) {
  844. if (unlikely(ssb_pci_switch_core(bus, dev)))
  845. goto error;
  846. }
  847. switch (reg_width) {
  848. case sizeof(u8):
  849. ioread8_rep(addr, buffer, count);
  850. break;
  851. case sizeof(u16):
  852. SSB_WARN_ON(count & 1);
  853. ioread16_rep(addr, buffer, count >> 1);
  854. break;
  855. case sizeof(u32):
  856. SSB_WARN_ON(count & 3);
  857. ioread32_rep(addr, buffer, count >> 2);
  858. break;
  859. default:
  860. SSB_WARN_ON(1);
  861. }
  862. return;
  863. error:
  864. memset(buffer, 0xFF, count);
  865. }
  866. #endif /* CONFIG_SSB_BLOCKIO */
  867. static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
  868. {
  869. struct ssb_bus *bus = dev->bus;
  870. if (unlikely(ssb_pci_assert_buspower(bus)))
  871. return;
  872. if (unlikely(bus->mapped_device != dev)) {
  873. if (unlikely(ssb_pci_switch_core(bus, dev)))
  874. return;
  875. }
  876. iowrite8(value, bus->mmio + offset);
  877. }
  878. static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
  879. {
  880. struct ssb_bus *bus = dev->bus;
  881. if (unlikely(ssb_pci_assert_buspower(bus)))
  882. return;
  883. if (unlikely(bus->mapped_device != dev)) {
  884. if (unlikely(ssb_pci_switch_core(bus, dev)))
  885. return;
  886. }
  887. iowrite16(value, bus->mmio + offset);
  888. }
  889. static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
  890. {
  891. struct ssb_bus *bus = dev->bus;
  892. if (unlikely(ssb_pci_assert_buspower(bus)))
  893. return;
  894. if (unlikely(bus->mapped_device != dev)) {
  895. if (unlikely(ssb_pci_switch_core(bus, dev)))
  896. return;
  897. }
  898. iowrite32(value, bus->mmio + offset);
  899. }
  900. #ifdef CONFIG_SSB_BLOCKIO
  901. static void ssb_pci_block_write(struct ssb_device *dev, const void *buffer,
  902. size_t count, u16 offset, u8 reg_width)
  903. {
  904. struct ssb_bus *bus = dev->bus;
  905. void __iomem *addr = bus->mmio + offset;
  906. if (unlikely(ssb_pci_assert_buspower(bus)))
  907. return;
  908. if (unlikely(bus->mapped_device != dev)) {
  909. if (unlikely(ssb_pci_switch_core(bus, dev)))
  910. return;
  911. }
  912. switch (reg_width) {
  913. case sizeof(u8):
  914. iowrite8_rep(addr, buffer, count);
  915. break;
  916. case sizeof(u16):
  917. SSB_WARN_ON(count & 1);
  918. iowrite16_rep(addr, buffer, count >> 1);
  919. break;
  920. case sizeof(u32):
  921. SSB_WARN_ON(count & 3);
  922. iowrite32_rep(addr, buffer, count >> 2);
  923. break;
  924. default:
  925. SSB_WARN_ON(1);
  926. }
  927. }
  928. #endif /* CONFIG_SSB_BLOCKIO */
  929. /* Not "static", as it's used in main.c */
  930. const struct ssb_bus_ops ssb_pci_ops = {
  931. .read8 = ssb_pci_read8,
  932. .read16 = ssb_pci_read16,
  933. .read32 = ssb_pci_read32,
  934. .write8 = ssb_pci_write8,
  935. .write16 = ssb_pci_write16,
  936. .write32 = ssb_pci_write32,
  937. #ifdef CONFIG_SSB_BLOCKIO
  938. .block_read = ssb_pci_block_read,
  939. .block_write = ssb_pci_block_write,
  940. #endif
  941. };
  942. static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
  943. struct device_attribute *attr,
  944. char *buf)
  945. {
  946. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  947. struct ssb_bus *bus;
  948. bus = ssb_pci_dev_to_bus(pdev);
  949. if (!bus)
  950. return -ENODEV;
  951. return ssb_attr_sprom_show(bus, buf, sprom_do_read);
  952. }
  953. static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
  954. struct device_attribute *attr,
  955. const char *buf, size_t count)
  956. {
  957. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  958. struct ssb_bus *bus;
  959. bus = ssb_pci_dev_to_bus(pdev);
  960. if (!bus)
  961. return -ENODEV;
  962. return ssb_attr_sprom_store(bus, buf, count,
  963. sprom_check_crc, sprom_do_write);
  964. }
  965. static DEVICE_ATTR(ssb_sprom, 0600,
  966. ssb_pci_attr_sprom_show,
  967. ssb_pci_attr_sprom_store);
  968. void ssb_pci_exit(struct ssb_bus *bus)
  969. {
  970. struct pci_dev *pdev;
  971. if (bus->bustype != SSB_BUSTYPE_PCI)
  972. return;
  973. pdev = bus->host_pci;
  974. device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
  975. }
  976. int ssb_pci_init(struct ssb_bus *bus)
  977. {
  978. struct pci_dev *pdev;
  979. int err;
  980. if (bus->bustype != SSB_BUSTYPE_PCI)
  981. return 0;
  982. pdev = bus->host_pci;
  983. mutex_init(&bus->sprom_mutex);
  984. err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
  985. if (err)
  986. goto out;
  987. out:
  988. return err;
  989. }