solos-pci.c 32 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  55. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  56. #define DATA_RAM_SIZE 32768
  57. #define BUF_SIZE 4096
  58. #define FPGA_PAGE 528 /* FPGA flash page size*/
  59. #define SOLOS_PAGE 512 /* Solos flash page size*/
  60. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  61. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  62. #define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
  63. #define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
  64. #define RX_DMA_SIZE 2048
  65. static int atmdebug = 0;
  66. static int firmware_upgrade = 0;
  67. static int fpga_upgrade = 0;
  68. struct pkt_hdr {
  69. __le16 size;
  70. __le16 vpi;
  71. __le16 vci;
  72. __le16 type;
  73. };
  74. struct solos_skb_cb {
  75. struct atm_vcc *vcc;
  76. uint32_t dma_addr;
  77. };
  78. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  79. #define PKT_DATA 0
  80. #define PKT_COMMAND 1
  81. #define PKT_POPEN 3
  82. #define PKT_PCLOSE 4
  83. #define PKT_STATUS 5
  84. struct solos_card {
  85. void __iomem *config_regs;
  86. void __iomem *buffers;
  87. int nr_ports;
  88. int tx_mask;
  89. struct pci_dev *dev;
  90. struct atm_dev *atmdev[4];
  91. struct tasklet_struct tlet;
  92. spinlock_t tx_lock;
  93. spinlock_t tx_queue_lock;
  94. spinlock_t cli_queue_lock;
  95. spinlock_t param_queue_lock;
  96. struct list_head param_queue;
  97. struct sk_buff_head tx_queue[4];
  98. struct sk_buff_head cli_queue[4];
  99. struct sk_buff *tx_skb[4];
  100. struct sk_buff *rx_skb[4];
  101. wait_queue_head_t param_wq;
  102. wait_queue_head_t fw_wq;
  103. int using_dma;
  104. };
  105. struct solos_param {
  106. struct list_head list;
  107. pid_t pid;
  108. int port;
  109. struct sk_buff *response;
  110. };
  111. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  112. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  113. MODULE_DESCRIPTION("Solos PCI driver");
  114. MODULE_VERSION(VERSION);
  115. MODULE_LICENSE("GPL");
  116. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  117. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  118. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  119. module_param(atmdebug, int, 0644);
  120. module_param(firmware_upgrade, int, 0444);
  121. module_param(fpga_upgrade, int, 0444);
  122. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  123. struct atm_vcc *vcc);
  124. static uint32_t fpga_tx(struct solos_card *);
  125. static irqreturn_t solos_irq(int irq, void *dev_id);
  126. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  127. static int list_vccs(int vci);
  128. static void release_vccs(struct atm_dev *dev);
  129. static int atm_init(struct solos_card *);
  130. static void atm_remove(struct solos_card *);
  131. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  132. static void solos_bh(unsigned long);
  133. static int print_buffer(struct sk_buff *buf);
  134. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  135. {
  136. if (vcc->pop)
  137. vcc->pop(vcc, skb);
  138. else
  139. dev_kfree_skb_any(skb);
  140. }
  141. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  142. char *buf)
  143. {
  144. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  145. struct solos_card *card = atmdev->dev_data;
  146. struct solos_param prm;
  147. struct sk_buff *skb;
  148. struct pkt_hdr *header;
  149. int buflen;
  150. buflen = strlen(attr->attr.name) + 10;
  151. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  152. if (!skb) {
  153. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  154. return -ENOMEM;
  155. }
  156. header = (void *)skb_put(skb, sizeof(*header));
  157. buflen = snprintf((void *)&header[1], buflen - 1,
  158. "L%05d\n%s\n", current->pid, attr->attr.name);
  159. skb_put(skb, buflen);
  160. header->size = cpu_to_le16(buflen);
  161. header->vpi = cpu_to_le16(0);
  162. header->vci = cpu_to_le16(0);
  163. header->type = cpu_to_le16(PKT_COMMAND);
  164. prm.pid = current->pid;
  165. prm.response = NULL;
  166. prm.port = SOLOS_CHAN(atmdev);
  167. spin_lock_irq(&card->param_queue_lock);
  168. list_add(&prm.list, &card->param_queue);
  169. spin_unlock_irq(&card->param_queue_lock);
  170. fpga_queue(card, prm.port, skb, NULL);
  171. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  172. spin_lock_irq(&card->param_queue_lock);
  173. list_del(&prm.list);
  174. spin_unlock_irq(&card->param_queue_lock);
  175. if (!prm.response)
  176. return -EIO;
  177. buflen = prm.response->len;
  178. memcpy(buf, prm.response->data, buflen);
  179. kfree_skb(prm.response);
  180. return buflen;
  181. }
  182. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  183. const char *buf, size_t count)
  184. {
  185. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  186. struct solos_card *card = atmdev->dev_data;
  187. struct solos_param prm;
  188. struct sk_buff *skb;
  189. struct pkt_hdr *header;
  190. int buflen;
  191. ssize_t ret;
  192. buflen = strlen(attr->attr.name) + 11 + count;
  193. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  194. if (!skb) {
  195. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  196. return -ENOMEM;
  197. }
  198. header = (void *)skb_put(skb, sizeof(*header));
  199. buflen = snprintf((void *)&header[1], buflen - 1,
  200. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  201. skb_put(skb, buflen);
  202. header->size = cpu_to_le16(buflen);
  203. header->vpi = cpu_to_le16(0);
  204. header->vci = cpu_to_le16(0);
  205. header->type = cpu_to_le16(PKT_COMMAND);
  206. prm.pid = current->pid;
  207. prm.response = NULL;
  208. prm.port = SOLOS_CHAN(atmdev);
  209. spin_lock_irq(&card->param_queue_lock);
  210. list_add(&prm.list, &card->param_queue);
  211. spin_unlock_irq(&card->param_queue_lock);
  212. fpga_queue(card, prm.port, skb, NULL);
  213. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  214. spin_lock_irq(&card->param_queue_lock);
  215. list_del(&prm.list);
  216. spin_unlock_irq(&card->param_queue_lock);
  217. skb = prm.response;
  218. if (!skb)
  219. return -EIO;
  220. buflen = skb->len;
  221. /* Sometimes it has a newline, sometimes it doesn't. */
  222. if (skb->data[buflen - 1] == '\n')
  223. buflen--;
  224. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  225. ret = count;
  226. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  227. ret = -EIO;
  228. else {
  229. /* We know we have enough space allocated for this; we allocated
  230. it ourselves */
  231. skb->data[buflen] = 0;
  232. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  233. skb->data);
  234. ret = -EIO;
  235. }
  236. kfree_skb(skb);
  237. return ret;
  238. }
  239. static char *next_string(struct sk_buff *skb)
  240. {
  241. int i = 0;
  242. char *this = skb->data;
  243. for (i = 0; i < skb->len; i++) {
  244. if (this[i] == '\n') {
  245. this[i] = 0;
  246. skb_pull(skb, i + 1);
  247. return this;
  248. }
  249. if (!isprint(this[i]))
  250. return NULL;
  251. }
  252. return NULL;
  253. }
  254. /*
  255. * Status packet has fields separated by \n, starting with a version number
  256. * for the information therein. Fields are....
  257. *
  258. * packet version
  259. * TxBitRate (version >= 1)
  260. * RxBitRate (version >= 1)
  261. * State (version >= 1)
  262. */
  263. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  264. {
  265. char *str, *end, *state_str;
  266. int ver, rate_up, rate_down, state;
  267. if (!card->atmdev[port])
  268. return -ENODEV;
  269. str = next_string(skb);
  270. if (!str)
  271. return -EIO;
  272. ver = simple_strtol(str, NULL, 10);
  273. if (ver < 1) {
  274. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  275. ver);
  276. return -EIO;
  277. }
  278. str = next_string(skb);
  279. if (!str)
  280. return -EIO;
  281. rate_up = simple_strtol(str, &end, 10);
  282. if (*end)
  283. return -EIO;
  284. str = next_string(skb);
  285. if (!str)
  286. return -EIO;
  287. rate_down = simple_strtol(str, &end, 10);
  288. if (*end)
  289. return -EIO;
  290. state_str = next_string(skb);
  291. if (!state_str)
  292. return -EIO;
  293. if (!strcmp(state_str, "Showtime"))
  294. state = ATM_PHY_SIG_FOUND;
  295. else {
  296. state = ATM_PHY_SIG_LOST;
  297. release_vccs(card->atmdev[port]);
  298. }
  299. if (state == ATM_PHY_SIG_LOST) {
  300. dev_info(&card->dev->dev, "Port %d ATM state: %s\n",
  301. port, state_str);
  302. } else {
  303. char *snr, *attn;
  304. snr = next_string(skb);
  305. if (!str)
  306. return -EIO;
  307. attn = next_string(skb);
  308. if (!attn)
  309. return -EIO;
  310. dev_info(&card->dev->dev, "Port %d: %s (%d/%d kb/s%s%s%s%s)\n",
  311. port, state_str, rate_down/1000, rate_up/1000,
  312. snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
  313. }
  314. card->atmdev[port]->link_rate = rate_down / 424;
  315. card->atmdev[port]->signal = state;
  316. return 0;
  317. }
  318. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  319. {
  320. struct solos_param *prm;
  321. unsigned long flags;
  322. int cmdpid;
  323. int found = 0;
  324. if (skb->len < 7)
  325. return 0;
  326. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  327. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  328. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  329. skb->data[6] != '\n')
  330. return 0;
  331. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  332. spin_lock_irqsave(&card->param_queue_lock, flags);
  333. list_for_each_entry(prm, &card->param_queue, list) {
  334. if (prm->port == port && prm->pid == cmdpid) {
  335. prm->response = skb;
  336. skb_pull(skb, 7);
  337. wake_up(&card->param_wq);
  338. found = 1;
  339. break;
  340. }
  341. }
  342. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  343. return found;
  344. }
  345. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  346. char *buf)
  347. {
  348. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  349. struct solos_card *card = atmdev->dev_data;
  350. struct sk_buff *skb;
  351. spin_lock(&card->cli_queue_lock);
  352. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  353. spin_unlock(&card->cli_queue_lock);
  354. if(skb == NULL)
  355. return sprintf(buf, "No data.\n");
  356. memcpy(buf, skb->data, skb->len);
  357. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  358. kfree_skb(skb);
  359. return skb->len;
  360. }
  361. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  362. {
  363. struct sk_buff *skb;
  364. struct pkt_hdr *header;
  365. if (size > (BUF_SIZE - sizeof(*header))) {
  366. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  367. return 0;
  368. }
  369. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  370. if (!skb) {
  371. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  372. return 0;
  373. }
  374. header = (void *)skb_put(skb, sizeof(*header));
  375. header->size = cpu_to_le16(size);
  376. header->vpi = cpu_to_le16(0);
  377. header->vci = cpu_to_le16(0);
  378. header->type = cpu_to_le16(PKT_COMMAND);
  379. memcpy(skb_put(skb, size), buf, size);
  380. fpga_queue(card, dev, skb, NULL);
  381. return 0;
  382. }
  383. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  384. const char *buf, size_t count)
  385. {
  386. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  387. struct solos_card *card = atmdev->dev_data;
  388. int err;
  389. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  390. return err?:count;
  391. }
  392. static DEVICE_ATTR(console, 0644, console_show, console_store);
  393. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  394. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  395. #include "solos-attrlist.c"
  396. #undef SOLOS_ATTR_RO
  397. #undef SOLOS_ATTR_RW
  398. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  399. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  400. static struct attribute *solos_attrs[] = {
  401. #include "solos-attrlist.c"
  402. NULL
  403. };
  404. static struct attribute_group solos_attr_group = {
  405. .attrs = solos_attrs,
  406. .name = "parameters",
  407. };
  408. static int flash_upgrade(struct solos_card *card, int chip)
  409. {
  410. const struct firmware *fw;
  411. const char *fw_name;
  412. uint32_t data32 = 0;
  413. int blocksize = 0;
  414. int numblocks = 0;
  415. int offset;
  416. if (chip == 0) {
  417. fw_name = "solos-FPGA.bin";
  418. blocksize = FPGA_BLOCK;
  419. } else {
  420. fw_name = "solos-Firmware.bin";
  421. blocksize = SOLOS_BLOCK;
  422. }
  423. if (request_firmware(&fw, fw_name, &card->dev->dev))
  424. return -ENOENT;
  425. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  426. numblocks = fw->size / blocksize;
  427. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  428. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  429. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  430. iowrite32(1, card->config_regs + FPGA_MODE);
  431. data32 = ioread32(card->config_regs + FPGA_MODE);
  432. /* Set mode to Chip Erase */
  433. dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n",
  434. chip?"Solos":"FPGA");
  435. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  436. iowrite32(1, card->config_regs + WRITE_FLASH);
  437. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  438. for (offset = 0; offset < fw->size; offset += blocksize) {
  439. int i;
  440. /* Clear write flag */
  441. iowrite32(0, card->config_regs + WRITE_FLASH);
  442. /* Set mode to Block Write */
  443. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  444. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  445. /* Copy block to buffer, swapping each 16 bits */
  446. for(i = 0; i < blocksize; i += 4) {
  447. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  448. iowrite32(word, RX_BUF(card, 3) + i);
  449. }
  450. /* Specify block number and then trigger flash write */
  451. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  452. iowrite32(1, card->config_regs + WRITE_FLASH);
  453. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  454. }
  455. release_firmware(fw);
  456. iowrite32(0, card->config_regs + WRITE_FLASH);
  457. iowrite32(0, card->config_regs + FPGA_MODE);
  458. iowrite32(0, card->config_regs + FLASH_MODE);
  459. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  460. return 0;
  461. }
  462. static irqreturn_t solos_irq(int irq, void *dev_id)
  463. {
  464. struct solos_card *card = dev_id;
  465. int handled = 1;
  466. iowrite32(0, card->config_regs + IRQ_CLEAR);
  467. /* If we're up and running, just kick the tasklet to process TX/RX */
  468. if (card->atmdev[0])
  469. tasklet_schedule(&card->tlet);
  470. else
  471. wake_up(&card->fw_wq);
  472. return IRQ_RETVAL(handled);
  473. }
  474. void solos_bh(unsigned long card_arg)
  475. {
  476. struct solos_card *card = (void *)card_arg;
  477. uint32_t card_flags;
  478. uint32_t rx_done = 0;
  479. int port;
  480. /*
  481. * Since fpga_tx() is going to need to read the flags under its lock,
  482. * it can return them to us so that we don't have to hit PCI MMIO
  483. * again for the same information
  484. */
  485. card_flags = fpga_tx(card);
  486. for (port = 0; port < card->nr_ports; port++) {
  487. if (card_flags & (0x10 << port)) {
  488. struct pkt_hdr _hdr, *header;
  489. struct sk_buff *skb;
  490. struct atm_vcc *vcc;
  491. int size;
  492. if (card->using_dma) {
  493. skb = card->rx_skb[port];
  494. card->rx_skb[port] = NULL;
  495. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  496. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  497. header = (void *)skb->data;
  498. size = le16_to_cpu(header->size);
  499. skb_put(skb, size + sizeof(*header));
  500. skb_pull(skb, sizeof(*header));
  501. } else {
  502. header = &_hdr;
  503. rx_done |= 0x10 << port;
  504. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  505. size = le16_to_cpu(header->size);
  506. skb = alloc_skb(size + 1, GFP_ATOMIC);
  507. if (!skb) {
  508. if (net_ratelimit())
  509. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  510. continue;
  511. }
  512. memcpy_fromio(skb_put(skb, size),
  513. RX_BUF(card, port) + sizeof(*header),
  514. size);
  515. }
  516. if (atmdebug) {
  517. dev_info(&card->dev->dev, "Received: device %d\n", port);
  518. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  519. size, le16_to_cpu(header->vpi),
  520. le16_to_cpu(header->vci));
  521. print_buffer(skb);
  522. }
  523. switch (le16_to_cpu(header->type)) {
  524. case PKT_DATA:
  525. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  526. le16_to_cpu(header->vci));
  527. if (!vcc) {
  528. if (net_ratelimit())
  529. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  530. le16_to_cpu(header->vci), le16_to_cpu(header->vpi),
  531. port);
  532. continue;
  533. }
  534. atm_charge(vcc, skb->truesize);
  535. vcc->push(vcc, skb);
  536. atomic_inc(&vcc->stats->rx);
  537. break;
  538. case PKT_STATUS:
  539. process_status(card, port, skb);
  540. dev_kfree_skb_any(skb);
  541. break;
  542. case PKT_COMMAND:
  543. default: /* FIXME: Not really, surely? */
  544. if (process_command(card, port, skb))
  545. break;
  546. spin_lock(&card->cli_queue_lock);
  547. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  548. if (net_ratelimit())
  549. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  550. port);
  551. dev_kfree_skb_any(skb);
  552. } else
  553. skb_queue_tail(&card->cli_queue[port], skb);
  554. spin_unlock(&card->cli_queue_lock);
  555. break;
  556. }
  557. }
  558. /* Allocate RX skbs for any ports which need them */
  559. if (card->using_dma && card->atmdev[port] &&
  560. !card->rx_skb[port]) {
  561. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  562. if (skb) {
  563. SKB_CB(skb)->dma_addr =
  564. pci_map_single(card->dev, skb->data,
  565. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  566. iowrite32(SKB_CB(skb)->dma_addr,
  567. card->config_regs + RX_DMA_ADDR(port));
  568. card->rx_skb[port] = skb;
  569. } else {
  570. if (net_ratelimit())
  571. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  572. /* We'll have to try again later */
  573. tasklet_schedule(&card->tlet);
  574. }
  575. }
  576. }
  577. if (rx_done)
  578. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  579. return;
  580. }
  581. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  582. {
  583. struct hlist_head *head;
  584. struct atm_vcc *vcc = NULL;
  585. struct hlist_node *node;
  586. struct sock *s;
  587. read_lock(&vcc_sklist_lock);
  588. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  589. sk_for_each(s, node, head) {
  590. vcc = atm_sk(s);
  591. if (vcc->dev == dev && vcc->vci == vci &&
  592. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  593. goto out;
  594. }
  595. vcc = NULL;
  596. out:
  597. read_unlock(&vcc_sklist_lock);
  598. return vcc;
  599. }
  600. static int list_vccs(int vci)
  601. {
  602. struct hlist_head *head;
  603. struct atm_vcc *vcc;
  604. struct hlist_node *node;
  605. struct sock *s;
  606. int num_found = 0;
  607. int i;
  608. read_lock(&vcc_sklist_lock);
  609. if (vci != 0){
  610. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  611. sk_for_each(s, node, head) {
  612. num_found ++;
  613. vcc = atm_sk(s);
  614. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  615. vcc->dev->number,
  616. vcc->vpi,
  617. vcc->vci);
  618. }
  619. } else {
  620. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  621. head = &vcc_hash[i];
  622. sk_for_each(s, node, head) {
  623. num_found ++;
  624. vcc = atm_sk(s);
  625. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  626. vcc->dev->number,
  627. vcc->vpi,
  628. vcc->vci);
  629. }
  630. }
  631. }
  632. read_unlock(&vcc_sklist_lock);
  633. return num_found;
  634. }
  635. static void release_vccs(struct atm_dev *dev)
  636. {
  637. int i;
  638. write_lock_irq(&vcc_sklist_lock);
  639. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  640. struct hlist_head *head = &vcc_hash[i];
  641. struct hlist_node *node, *tmp;
  642. struct sock *s;
  643. struct atm_vcc *vcc;
  644. sk_for_each_safe(s, node, tmp, head) {
  645. vcc = atm_sk(s);
  646. if (vcc->dev == dev) {
  647. vcc_release_async(vcc, -EPIPE);
  648. sk_del_node_init(s);
  649. }
  650. }
  651. }
  652. write_unlock_irq(&vcc_sklist_lock);
  653. }
  654. static int popen(struct atm_vcc *vcc)
  655. {
  656. struct solos_card *card = vcc->dev->dev_data;
  657. struct sk_buff *skb;
  658. struct pkt_hdr *header;
  659. if (vcc->qos.aal != ATM_AAL5) {
  660. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  661. vcc->qos.aal);
  662. return -EINVAL;
  663. }
  664. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  665. if (!skb && net_ratelimit()) {
  666. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  667. return -ENOMEM;
  668. }
  669. header = (void *)skb_put(skb, sizeof(*header));
  670. header->size = cpu_to_le16(0);
  671. header->vpi = cpu_to_le16(vcc->vpi);
  672. header->vci = cpu_to_le16(vcc->vci);
  673. header->type = cpu_to_le16(PKT_POPEN);
  674. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  675. // dev_dbg(&card->dev->dev, "Open for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  676. set_bit(ATM_VF_ADDR, &vcc->flags); // accept the vpi / vci
  677. set_bit(ATM_VF_READY, &vcc->flags);
  678. list_vccs(0);
  679. return 0;
  680. }
  681. static void pclose(struct atm_vcc *vcc)
  682. {
  683. struct solos_card *card = vcc->dev->dev_data;
  684. struct sk_buff *skb;
  685. struct pkt_hdr *header;
  686. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  687. if (!skb) {
  688. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  689. return;
  690. }
  691. header = (void *)skb_put(skb, sizeof(*header));
  692. header->size = cpu_to_le16(0);
  693. header->vpi = cpu_to_le16(vcc->vpi);
  694. header->vci = cpu_to_le16(vcc->vci);
  695. header->type = cpu_to_le16(PKT_PCLOSE);
  696. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  697. // dev_dbg(&card->dev->dev, "Close for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  698. clear_bit(ATM_VF_ADDR, &vcc->flags);
  699. clear_bit(ATM_VF_READY, &vcc->flags);
  700. return;
  701. }
  702. static int print_buffer(struct sk_buff *buf)
  703. {
  704. int len,i;
  705. char msg[500];
  706. char item[10];
  707. len = buf->len;
  708. for (i = 0; i < len; i++){
  709. if(i % 8 == 0)
  710. sprintf(msg, "%02X: ", i);
  711. sprintf(item,"%02X ",*(buf->data + i));
  712. strcat(msg, item);
  713. if(i % 8 == 7) {
  714. sprintf(item, "\n");
  715. strcat(msg, item);
  716. printk(KERN_DEBUG "%s", msg);
  717. }
  718. }
  719. if (i % 8 != 0) {
  720. sprintf(item, "\n");
  721. strcat(msg, item);
  722. printk(KERN_DEBUG "%s", msg);
  723. }
  724. printk(KERN_DEBUG "\n");
  725. return 0;
  726. }
  727. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  728. struct atm_vcc *vcc)
  729. {
  730. int old_len;
  731. unsigned long flags;
  732. SKB_CB(skb)->vcc = vcc;
  733. spin_lock_irqsave(&card->tx_queue_lock, flags);
  734. old_len = skb_queue_len(&card->tx_queue[port]);
  735. skb_queue_tail(&card->tx_queue[port], skb);
  736. if (!old_len)
  737. card->tx_mask |= (1 << port);
  738. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  739. /* Theoretically we could just schedule the tasklet here, but
  740. that introduces latency we don't want -- it's noticeable */
  741. if (!old_len)
  742. fpga_tx(card);
  743. }
  744. static uint32_t fpga_tx(struct solos_card *card)
  745. {
  746. uint32_t tx_pending, card_flags;
  747. uint32_t tx_started = 0;
  748. struct sk_buff *skb;
  749. struct atm_vcc *vcc;
  750. unsigned char port;
  751. unsigned long flags;
  752. spin_lock_irqsave(&card->tx_lock, flags);
  753. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  754. /*
  755. * The queue lock is required for _writing_ to tx_mask, but we're
  756. * OK to read it here without locking. The only potential update
  757. * that we could race with is in fpga_queue() where it sets a bit
  758. * for a new port... but it's going to call this function again if
  759. * it's doing that, anyway.
  760. */
  761. tx_pending = card->tx_mask & ~card_flags;
  762. for (port = 0; tx_pending; tx_pending >>= 1, port++) {
  763. if (tx_pending & 1) {
  764. struct sk_buff *oldskb = card->tx_skb[port];
  765. if (oldskb)
  766. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  767. oldskb->len, PCI_DMA_TODEVICE);
  768. spin_lock(&card->tx_queue_lock);
  769. skb = skb_dequeue(&card->tx_queue[port]);
  770. if (!skb)
  771. card->tx_mask &= ~(1 << port);
  772. spin_unlock(&card->tx_queue_lock);
  773. if (skb && !card->using_dma) {
  774. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  775. tx_started |= 1 << port; //Set TX full flag
  776. oldskb = skb; /* We're done with this skb already */
  777. } else if (skb && card->using_dma) {
  778. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  779. skb->len, PCI_DMA_TODEVICE);
  780. iowrite32(SKB_CB(skb)->dma_addr,
  781. card->config_regs + TX_DMA_ADDR(port));
  782. }
  783. if (!oldskb)
  784. continue;
  785. /* Clean up and free oldskb now it's gone */
  786. if (atmdebug) {
  787. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  788. port);
  789. print_buffer(oldskb);
  790. }
  791. vcc = SKB_CB(oldskb)->vcc;
  792. if (vcc) {
  793. atomic_inc(&vcc->stats->tx);
  794. solos_pop(vcc, oldskb);
  795. } else
  796. dev_kfree_skb_irq(oldskb);
  797. }
  798. }
  799. if (tx_started)
  800. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  801. out:
  802. spin_unlock_irqrestore(&card->tx_lock, flags);
  803. return card_flags;
  804. }
  805. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  806. {
  807. struct solos_card *card = vcc->dev->dev_data;
  808. struct pkt_hdr *header;
  809. int pktlen;
  810. //dev_dbg(&card->dev->dev, "psend called.\n");
  811. //dev_dbg(&card->dev->dev, "dev,vpi,vci = %d,%d,%d\n",SOLOS_CHAN(vcc->dev),vcc->vpi,vcc->vci);
  812. pktlen = skb->len;
  813. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  814. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  815. solos_pop(vcc, skb);
  816. return 0;
  817. }
  818. if (!skb_clone_writable(skb, sizeof(*header))) {
  819. int expand_by = 0;
  820. int ret;
  821. if (skb_headroom(skb) < sizeof(*header))
  822. expand_by = sizeof(*header) - skb_headroom(skb);
  823. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  824. if (ret) {
  825. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  826. solos_pop(vcc, skb);
  827. return ret;
  828. }
  829. }
  830. header = (void *)skb_push(skb, sizeof(*header));
  831. /* This does _not_ include the size of the header */
  832. header->size = cpu_to_le16(pktlen);
  833. header->vpi = cpu_to_le16(vcc->vpi);
  834. header->vci = cpu_to_le16(vcc->vci);
  835. header->type = cpu_to_le16(PKT_DATA);
  836. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  837. return 0;
  838. }
  839. static struct atmdev_ops fpga_ops = {
  840. .open = popen,
  841. .close = pclose,
  842. .ioctl = NULL,
  843. .getsockopt = NULL,
  844. .setsockopt = NULL,
  845. .send = psend,
  846. .send_oam = NULL,
  847. .phy_put = NULL,
  848. .phy_get = NULL,
  849. .change_qos = NULL,
  850. .proc_read = NULL,
  851. .owner = THIS_MODULE
  852. };
  853. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  854. {
  855. int err, i;
  856. uint16_t fpga_ver;
  857. uint8_t major_ver, minor_ver;
  858. uint32_t data32;
  859. struct solos_card *card;
  860. card = kzalloc(sizeof(*card), GFP_KERNEL);
  861. if (!card)
  862. return -ENOMEM;
  863. card->dev = dev;
  864. init_waitqueue_head(&card->fw_wq);
  865. init_waitqueue_head(&card->param_wq);
  866. err = pci_enable_device(dev);
  867. if (err) {
  868. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  869. goto out;
  870. }
  871. err = pci_set_dma_mask(dev, DMA_32BIT_MASK);
  872. if (err) {
  873. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  874. goto out;
  875. }
  876. err = pci_request_regions(dev, "solos");
  877. if (err) {
  878. dev_warn(&dev->dev, "Failed to request regions\n");
  879. goto out;
  880. }
  881. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  882. if (!card->config_regs) {
  883. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  884. goto out_release_regions;
  885. }
  886. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  887. if (!card->buffers) {
  888. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  889. goto out_unmap_config;
  890. }
  891. // for(i=0;i<64 ;i+=4){
  892. // data32=ioread32(card->buffers + i);
  893. // dev_dbg(&card->dev->dev, "%08lX\n",(unsigned long)data32);
  894. // }
  895. //Fill Config Mem with zeros
  896. for(i = 0; i < 128; i += 4)
  897. iowrite32(0, card->config_regs + i);
  898. //Set RX empty flags
  899. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  900. data32 = ioread32(card->config_regs + FPGA_VER);
  901. fpga_ver = (data32 & 0x0000FFFF);
  902. major_ver = ((data32 & 0xFF000000) >> 24);
  903. minor_ver = ((data32 & 0x00FF0000) >> 16);
  904. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  905. major_ver, minor_ver, fpga_ver);
  906. if (fpga_ver > 27)
  907. card->using_dma = 1;
  908. card->nr_ports = 2; /* FIXME: Detect daughterboard */
  909. pci_set_drvdata(dev, card);
  910. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  911. spin_lock_init(&card->tx_lock);
  912. spin_lock_init(&card->tx_queue_lock);
  913. spin_lock_init(&card->cli_queue_lock);
  914. spin_lock_init(&card->param_queue_lock);
  915. INIT_LIST_HEAD(&card->param_queue);
  916. /*
  917. // Set Loopback mode
  918. data32 = 0x00010000;
  919. iowrite32(data32,card->config_regs + FLAGS_ADDR);
  920. */
  921. /*
  922. // Fill Buffers with zeros
  923. for (i = 0; i < BUF_SIZE * 8; i += 4)
  924. iowrite32(0, card->buffers + i);
  925. */
  926. /*
  927. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  928. iowrite32(0x12345678, card->buffers + i + (0*BUF_SIZE));
  929. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  930. iowrite32(0xabcdef98, card->buffers + i + (1*BUF_SIZE));
  931. // Read Config Memory
  932. printk(KERN_DEBUG "Reading Config MEM\n");
  933. i = 0;
  934. for(i = 0; i < 16; i++) {
  935. data32=ioread32(card->buffers + i*(BUF_SIZE/2));
  936. printk(KERN_ALERT "Addr: %lX Data: %08lX\n",
  937. (unsigned long)(addr_start + i*(BUF_SIZE/2)),
  938. (unsigned long)data32);
  939. }
  940. */
  941. //dev_dbg(&card->dev->dev, "Requesting IRQ: %d\n",dev->irq);
  942. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  943. "solos-pci", card);
  944. if (err) {
  945. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  946. goto out_unmap_both;
  947. }
  948. // Enable IRQs
  949. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  950. if (fpga_upgrade)
  951. flash_upgrade(card, 0);
  952. if (firmware_upgrade)
  953. flash_upgrade(card, 1);
  954. err = atm_init(card);
  955. if (err)
  956. goto out_free_irq;
  957. return 0;
  958. out_free_irq:
  959. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  960. free_irq(dev->irq, card);
  961. tasklet_kill(&card->tlet);
  962. out_unmap_both:
  963. pci_set_drvdata(dev, NULL);
  964. pci_iounmap(dev, card->config_regs);
  965. out_unmap_config:
  966. pci_iounmap(dev, card->buffers);
  967. out_release_regions:
  968. pci_release_regions(dev);
  969. out:
  970. return err;
  971. }
  972. static int atm_init(struct solos_card *card)
  973. {
  974. int i;
  975. for (i = 0; i < card->nr_ports; i++) {
  976. struct sk_buff *skb;
  977. struct pkt_hdr *header;
  978. skb_queue_head_init(&card->tx_queue[i]);
  979. skb_queue_head_init(&card->cli_queue[i]);
  980. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  981. if (!card->atmdev[i]) {
  982. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  983. atm_remove(card);
  984. return -ENODEV;
  985. }
  986. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  987. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  988. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  989. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  990. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  991. card->atmdev[i]->ci_range.vpi_bits = 8;
  992. card->atmdev[i]->ci_range.vci_bits = 16;
  993. card->atmdev[i]->dev_data = card;
  994. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  995. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  996. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  997. if (!skb) {
  998. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  999. continue;
  1000. }
  1001. header = (void *)skb_put(skb, sizeof(*header));
  1002. header->size = cpu_to_le16(0);
  1003. header->vpi = cpu_to_le16(0);
  1004. header->vci = cpu_to_le16(0);
  1005. header->type = cpu_to_le16(PKT_STATUS);
  1006. fpga_queue(card, i, skb, NULL);
  1007. }
  1008. return 0;
  1009. }
  1010. static void atm_remove(struct solos_card *card)
  1011. {
  1012. int i;
  1013. for (i = 0; i < card->nr_ports; i++) {
  1014. if (card->atmdev[i]) {
  1015. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1016. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1017. atm_dev_deregister(card->atmdev[i]);
  1018. }
  1019. }
  1020. }
  1021. static void fpga_remove(struct pci_dev *dev)
  1022. {
  1023. struct solos_card *card = pci_get_drvdata(dev);
  1024. atm_remove(card);
  1025. dev_vdbg(&dev->dev, "Freeing IRQ\n");
  1026. // Disable IRQs from FPGA
  1027. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1028. free_irq(dev->irq, card);
  1029. tasklet_kill(&card->tlet);
  1030. // iowrite32(0x01,pciregs);
  1031. dev_vdbg(&dev->dev, "Unmapping PCI resource\n");
  1032. pci_iounmap(dev, card->buffers);
  1033. pci_iounmap(dev, card->config_regs);
  1034. dev_vdbg(&dev->dev, "Releasing PCI Region\n");
  1035. pci_release_regions(dev);
  1036. pci_disable_device(dev);
  1037. pci_set_drvdata(dev, NULL);
  1038. kfree(card);
  1039. // dev_dbg(&card->dev->dev, "fpga_remove\n");
  1040. return;
  1041. }
  1042. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1043. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1044. { 0, }
  1045. };
  1046. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1047. static struct pci_driver fpga_driver = {
  1048. .name = "solos",
  1049. .id_table = fpga_pci_tbl,
  1050. .probe = fpga_probe,
  1051. .remove = fpga_remove,
  1052. };
  1053. static int __init solos_pci_init(void)
  1054. {
  1055. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1056. return pci_register_driver(&fpga_driver);
  1057. }
  1058. static void __exit solos_pci_exit(void)
  1059. {
  1060. pci_unregister_driver(&fpga_driver);
  1061. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1062. }
  1063. module_init(solos_pci_init);
  1064. module_exit(solos_pci_exit);