cputable.c 37 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC32
  30. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  33. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  38. #endif /* CONFIG_PPC32 */
  39. #ifdef CONFIG_PPC64
  40. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  43. extern void __restore_cpu_pa6t(void);
  44. extern void __restore_cpu_ppc970(void);
  45. #endif /* CONFIG_PPC64 */
  46. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  47. * ones as well...
  48. */
  49. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  50. PPC_FEATURE_HAS_MMU)
  51. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  52. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  53. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  54. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  55. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  56. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  57. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  58. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  59. PPC_FEATURE_TRUE_LE)
  60. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  61. PPC_FEATURE_TRUE_LE | \
  62. PPC_FEATURE_HAS_ALTIVEC_COMP)
  63. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  64. PPC_FEATURE_BOOKE)
  65. /* We only set the spe features if the kernel was compiled with
  66. * spe support
  67. */
  68. #ifdef CONFIG_SPE
  69. #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
  70. #else
  71. #define PPC_FEATURE_SPE_COMP 0
  72. #endif
  73. static struct cpu_spec cpu_specs[] = {
  74. #ifdef CONFIG_PPC64
  75. { /* Power3 */
  76. .pvr_mask = 0xffff0000,
  77. .pvr_value = 0x00400000,
  78. .cpu_name = "POWER3 (630)",
  79. .cpu_features = CPU_FTRS_POWER3,
  80. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  81. .icache_bsize = 128,
  82. .dcache_bsize = 128,
  83. .num_pmcs = 8,
  84. .pmc_type = PPC_PMC_IBM,
  85. .oprofile_cpu_type = "ppc64/power3",
  86. .oprofile_type = PPC_OPROFILE_RS64,
  87. .platform = "power3",
  88. },
  89. { /* Power3+ */
  90. .pvr_mask = 0xffff0000,
  91. .pvr_value = 0x00410000,
  92. .cpu_name = "POWER3 (630+)",
  93. .cpu_features = CPU_FTRS_POWER3,
  94. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  95. .icache_bsize = 128,
  96. .dcache_bsize = 128,
  97. .num_pmcs = 8,
  98. .pmc_type = PPC_PMC_IBM,
  99. .oprofile_cpu_type = "ppc64/power3",
  100. .oprofile_type = PPC_OPROFILE_RS64,
  101. .platform = "power3",
  102. },
  103. { /* Northstar */
  104. .pvr_mask = 0xffff0000,
  105. .pvr_value = 0x00330000,
  106. .cpu_name = "RS64-II (northstar)",
  107. .cpu_features = CPU_FTRS_RS64,
  108. .cpu_user_features = COMMON_USER_PPC64,
  109. .icache_bsize = 128,
  110. .dcache_bsize = 128,
  111. .num_pmcs = 8,
  112. .pmc_type = PPC_PMC_IBM,
  113. .oprofile_cpu_type = "ppc64/rs64",
  114. .oprofile_type = PPC_OPROFILE_RS64,
  115. .platform = "rs64",
  116. },
  117. { /* Pulsar */
  118. .pvr_mask = 0xffff0000,
  119. .pvr_value = 0x00340000,
  120. .cpu_name = "RS64-III (pulsar)",
  121. .cpu_features = CPU_FTRS_RS64,
  122. .cpu_user_features = COMMON_USER_PPC64,
  123. .icache_bsize = 128,
  124. .dcache_bsize = 128,
  125. .num_pmcs = 8,
  126. .pmc_type = PPC_PMC_IBM,
  127. .oprofile_cpu_type = "ppc64/rs64",
  128. .oprofile_type = PPC_OPROFILE_RS64,
  129. .platform = "rs64",
  130. },
  131. { /* I-star */
  132. .pvr_mask = 0xffff0000,
  133. .pvr_value = 0x00360000,
  134. .cpu_name = "RS64-III (icestar)",
  135. .cpu_features = CPU_FTRS_RS64,
  136. .cpu_user_features = COMMON_USER_PPC64,
  137. .icache_bsize = 128,
  138. .dcache_bsize = 128,
  139. .num_pmcs = 8,
  140. .pmc_type = PPC_PMC_IBM,
  141. .oprofile_cpu_type = "ppc64/rs64",
  142. .oprofile_type = PPC_OPROFILE_RS64,
  143. .platform = "rs64",
  144. },
  145. { /* S-star */
  146. .pvr_mask = 0xffff0000,
  147. .pvr_value = 0x00370000,
  148. .cpu_name = "RS64-IV (sstar)",
  149. .cpu_features = CPU_FTRS_RS64,
  150. .cpu_user_features = COMMON_USER_PPC64,
  151. .icache_bsize = 128,
  152. .dcache_bsize = 128,
  153. .num_pmcs = 8,
  154. .pmc_type = PPC_PMC_IBM,
  155. .oprofile_cpu_type = "ppc64/rs64",
  156. .oprofile_type = PPC_OPROFILE_RS64,
  157. .platform = "rs64",
  158. },
  159. { /* Power4 */
  160. .pvr_mask = 0xffff0000,
  161. .pvr_value = 0x00350000,
  162. .cpu_name = "POWER4 (gp)",
  163. .cpu_features = CPU_FTRS_POWER4,
  164. .cpu_user_features = COMMON_USER_POWER4,
  165. .icache_bsize = 128,
  166. .dcache_bsize = 128,
  167. .num_pmcs = 8,
  168. .pmc_type = PPC_PMC_IBM,
  169. .oprofile_cpu_type = "ppc64/power4",
  170. .oprofile_type = PPC_OPROFILE_POWER4,
  171. .platform = "power4",
  172. },
  173. { /* Power4+ */
  174. .pvr_mask = 0xffff0000,
  175. .pvr_value = 0x00380000,
  176. .cpu_name = "POWER4+ (gq)",
  177. .cpu_features = CPU_FTRS_POWER4,
  178. .cpu_user_features = COMMON_USER_POWER4,
  179. .icache_bsize = 128,
  180. .dcache_bsize = 128,
  181. .num_pmcs = 8,
  182. .pmc_type = PPC_PMC_IBM,
  183. .oprofile_cpu_type = "ppc64/power4",
  184. .oprofile_type = PPC_OPROFILE_POWER4,
  185. .platform = "power4",
  186. },
  187. { /* PPC970 */
  188. .pvr_mask = 0xffff0000,
  189. .pvr_value = 0x00390000,
  190. .cpu_name = "PPC970",
  191. .cpu_features = CPU_FTRS_PPC970,
  192. .cpu_user_features = COMMON_USER_POWER4 |
  193. PPC_FEATURE_HAS_ALTIVEC_COMP,
  194. .icache_bsize = 128,
  195. .dcache_bsize = 128,
  196. .num_pmcs = 8,
  197. .pmc_type = PPC_PMC_IBM,
  198. .cpu_setup = __setup_cpu_ppc970,
  199. .cpu_restore = __restore_cpu_ppc970,
  200. .oprofile_cpu_type = "ppc64/970",
  201. .oprofile_type = PPC_OPROFILE_POWER4,
  202. .platform = "ppc970",
  203. },
  204. { /* PPC970FX */
  205. .pvr_mask = 0xffff0000,
  206. .pvr_value = 0x003c0000,
  207. .cpu_name = "PPC970FX",
  208. .cpu_features = CPU_FTRS_PPC970,
  209. .cpu_user_features = COMMON_USER_POWER4 |
  210. PPC_FEATURE_HAS_ALTIVEC_COMP,
  211. .icache_bsize = 128,
  212. .dcache_bsize = 128,
  213. .num_pmcs = 8,
  214. .pmc_type = PPC_PMC_IBM,
  215. .cpu_setup = __setup_cpu_ppc970,
  216. .cpu_restore = __restore_cpu_ppc970,
  217. .oprofile_cpu_type = "ppc64/970",
  218. .oprofile_type = PPC_OPROFILE_POWER4,
  219. .platform = "ppc970",
  220. },
  221. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  222. .pvr_mask = 0xffffffff,
  223. .pvr_value = 0x00440100,
  224. .cpu_name = "PPC970MP",
  225. .cpu_features = CPU_FTRS_PPC970,
  226. .cpu_user_features = COMMON_USER_POWER4 |
  227. PPC_FEATURE_HAS_ALTIVEC_COMP,
  228. .icache_bsize = 128,
  229. .dcache_bsize = 128,
  230. .num_pmcs = 8,
  231. .pmc_type = PPC_PMC_IBM,
  232. .cpu_setup = __setup_cpu_ppc970,
  233. .cpu_restore = __restore_cpu_ppc970,
  234. .oprofile_cpu_type = "ppc64/970MP",
  235. .oprofile_type = PPC_OPROFILE_POWER4,
  236. .platform = "ppc970",
  237. },
  238. { /* PPC970MP */
  239. .pvr_mask = 0xffff0000,
  240. .pvr_value = 0x00440000,
  241. .cpu_name = "PPC970MP",
  242. .cpu_features = CPU_FTRS_PPC970,
  243. .cpu_user_features = COMMON_USER_POWER4 |
  244. PPC_FEATURE_HAS_ALTIVEC_COMP,
  245. .icache_bsize = 128,
  246. .dcache_bsize = 128,
  247. .num_pmcs = 8,
  248. .pmc_type = PPC_PMC_IBM,
  249. .cpu_setup = __setup_cpu_ppc970MP,
  250. .cpu_restore = __restore_cpu_ppc970,
  251. .oprofile_cpu_type = "ppc64/970MP",
  252. .oprofile_type = PPC_OPROFILE_POWER4,
  253. .platform = "ppc970",
  254. },
  255. { /* PPC970GX */
  256. .pvr_mask = 0xffff0000,
  257. .pvr_value = 0x00450000,
  258. .cpu_name = "PPC970GX",
  259. .cpu_features = CPU_FTRS_PPC970,
  260. .cpu_user_features = COMMON_USER_POWER4 |
  261. PPC_FEATURE_HAS_ALTIVEC_COMP,
  262. .icache_bsize = 128,
  263. .dcache_bsize = 128,
  264. .num_pmcs = 8,
  265. .pmc_type = PPC_PMC_IBM,
  266. .cpu_setup = __setup_cpu_ppc970,
  267. .oprofile_cpu_type = "ppc64/970",
  268. .oprofile_type = PPC_OPROFILE_POWER4,
  269. .platform = "ppc970",
  270. },
  271. { /* Power5 GR */
  272. .pvr_mask = 0xffff0000,
  273. .pvr_value = 0x003a0000,
  274. .cpu_name = "POWER5 (gr)",
  275. .cpu_features = CPU_FTRS_POWER5,
  276. .cpu_user_features = COMMON_USER_POWER5,
  277. .icache_bsize = 128,
  278. .dcache_bsize = 128,
  279. .num_pmcs = 6,
  280. .pmc_type = PPC_PMC_IBM,
  281. .oprofile_cpu_type = "ppc64/power5",
  282. .oprofile_type = PPC_OPROFILE_POWER4,
  283. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  284. * and above but only works on POWER5 and above
  285. */
  286. .oprofile_mmcra_sihv = MMCRA_SIHV,
  287. .oprofile_mmcra_sipr = MMCRA_SIPR,
  288. .platform = "power5",
  289. },
  290. { /* Power5 GS */
  291. .pvr_mask = 0xffff0000,
  292. .pvr_value = 0x003b0000,
  293. .cpu_name = "POWER5+ (gs)",
  294. .cpu_features = CPU_FTRS_POWER5,
  295. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  296. .icache_bsize = 128,
  297. .dcache_bsize = 128,
  298. .num_pmcs = 6,
  299. .pmc_type = PPC_PMC_IBM,
  300. .oprofile_cpu_type = "ppc64/power5+",
  301. .oprofile_type = PPC_OPROFILE_POWER4,
  302. .oprofile_mmcra_sihv = MMCRA_SIHV,
  303. .oprofile_mmcra_sipr = MMCRA_SIPR,
  304. .platform = "power5+",
  305. },
  306. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  307. .pvr_mask = 0xffffffff,
  308. .pvr_value = 0x0f000001,
  309. .cpu_name = "POWER5+",
  310. .cpu_features = CPU_FTRS_POWER5,
  311. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  312. .icache_bsize = 128,
  313. .dcache_bsize = 128,
  314. .num_pmcs = 6,
  315. .pmc_type = PPC_PMC_IBM,
  316. .oprofile_cpu_type = "ppc64/power6",
  317. .oprofile_type = PPC_OPROFILE_POWER4,
  318. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  319. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  320. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  321. POWER6_MMCRA_OTHER,
  322. .platform = "power5+",
  323. },
  324. { /* Power6 */
  325. .pvr_mask = 0xffff0000,
  326. .pvr_value = 0x003e0000,
  327. .cpu_name = "POWER6 (raw)",
  328. .cpu_features = CPU_FTRS_POWER6,
  329. .cpu_user_features = COMMON_USER_POWER6 |
  330. PPC_FEATURE_POWER6_EXT,
  331. .icache_bsize = 128,
  332. .dcache_bsize = 128,
  333. .num_pmcs = 6,
  334. .pmc_type = PPC_PMC_IBM,
  335. .oprofile_cpu_type = "ppc64/power6",
  336. .oprofile_type = PPC_OPROFILE_POWER4,
  337. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  338. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  339. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  340. POWER6_MMCRA_OTHER,
  341. .platform = "power6x",
  342. },
  343. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  344. .pvr_mask = 0xffffffff,
  345. .pvr_value = 0x0f000002,
  346. .cpu_name = "POWER6 (architected)",
  347. .cpu_features = CPU_FTRS_POWER6,
  348. .cpu_user_features = COMMON_USER_POWER6,
  349. .icache_bsize = 128,
  350. .dcache_bsize = 128,
  351. .num_pmcs = 6,
  352. .pmc_type = PPC_PMC_IBM,
  353. .oprofile_cpu_type = "ppc64/power6",
  354. .oprofile_type = PPC_OPROFILE_POWER4,
  355. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  356. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  357. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  358. POWER6_MMCRA_OTHER,
  359. .platform = "power6",
  360. },
  361. { /* Cell Broadband Engine */
  362. .pvr_mask = 0xffff0000,
  363. .pvr_value = 0x00700000,
  364. .cpu_name = "Cell Broadband Engine",
  365. .cpu_features = CPU_FTRS_CELL,
  366. .cpu_user_features = COMMON_USER_PPC64 |
  367. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  368. PPC_FEATURE_SMT,
  369. .icache_bsize = 128,
  370. .dcache_bsize = 128,
  371. .num_pmcs = 4,
  372. .pmc_type = PPC_PMC_IBM,
  373. .oprofile_cpu_type = "ppc64/cell-be",
  374. .oprofile_type = PPC_OPROFILE_CELL,
  375. .platform = "ppc-cell-be",
  376. },
  377. { /* PA Semi PA6T */
  378. .pvr_mask = 0x7fff0000,
  379. .pvr_value = 0x00900000,
  380. .cpu_name = "PA6T",
  381. .cpu_features = CPU_FTRS_PA6T,
  382. .cpu_user_features = COMMON_USER_PA6T,
  383. .icache_bsize = 64,
  384. .dcache_bsize = 64,
  385. .num_pmcs = 6,
  386. .pmc_type = PPC_PMC_PA6T,
  387. .cpu_setup = __setup_cpu_pa6t,
  388. .cpu_restore = __restore_cpu_pa6t,
  389. .oprofile_cpu_type = "ppc64/pa6t",
  390. .oprofile_type = PPC_OPROFILE_PA6T,
  391. .platform = "pa6t",
  392. },
  393. { /* default match */
  394. .pvr_mask = 0x00000000,
  395. .pvr_value = 0x00000000,
  396. .cpu_name = "POWER4 (compatible)",
  397. .cpu_features = CPU_FTRS_COMPATIBLE,
  398. .cpu_user_features = COMMON_USER_PPC64,
  399. .icache_bsize = 128,
  400. .dcache_bsize = 128,
  401. .num_pmcs = 6,
  402. .pmc_type = PPC_PMC_IBM,
  403. .platform = "power4",
  404. }
  405. #endif /* CONFIG_PPC64 */
  406. #ifdef CONFIG_PPC32
  407. #if CLASSIC_PPC
  408. { /* 601 */
  409. .pvr_mask = 0xffff0000,
  410. .pvr_value = 0x00010000,
  411. .cpu_name = "601",
  412. .cpu_features = CPU_FTRS_PPC601,
  413. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  414. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  415. .icache_bsize = 32,
  416. .dcache_bsize = 32,
  417. .platform = "ppc601",
  418. },
  419. { /* 603 */
  420. .pvr_mask = 0xffff0000,
  421. .pvr_value = 0x00030000,
  422. .cpu_name = "603",
  423. .cpu_features = CPU_FTRS_603,
  424. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  425. .icache_bsize = 32,
  426. .dcache_bsize = 32,
  427. .cpu_setup = __setup_cpu_603,
  428. .platform = "ppc603",
  429. },
  430. { /* 603e */
  431. .pvr_mask = 0xffff0000,
  432. .pvr_value = 0x00060000,
  433. .cpu_name = "603e",
  434. .cpu_features = CPU_FTRS_603,
  435. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  436. .icache_bsize = 32,
  437. .dcache_bsize = 32,
  438. .cpu_setup = __setup_cpu_603,
  439. .platform = "ppc603",
  440. },
  441. { /* 603ev */
  442. .pvr_mask = 0xffff0000,
  443. .pvr_value = 0x00070000,
  444. .cpu_name = "603ev",
  445. .cpu_features = CPU_FTRS_603,
  446. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  447. .icache_bsize = 32,
  448. .dcache_bsize = 32,
  449. .cpu_setup = __setup_cpu_603,
  450. .platform = "ppc603",
  451. },
  452. { /* 604 */
  453. .pvr_mask = 0xffff0000,
  454. .pvr_value = 0x00040000,
  455. .cpu_name = "604",
  456. .cpu_features = CPU_FTRS_604,
  457. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  458. .icache_bsize = 32,
  459. .dcache_bsize = 32,
  460. .num_pmcs = 2,
  461. .cpu_setup = __setup_cpu_604,
  462. .platform = "ppc604",
  463. },
  464. { /* 604e */
  465. .pvr_mask = 0xfffff000,
  466. .pvr_value = 0x00090000,
  467. .cpu_name = "604e",
  468. .cpu_features = CPU_FTRS_604,
  469. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  470. .icache_bsize = 32,
  471. .dcache_bsize = 32,
  472. .num_pmcs = 4,
  473. .cpu_setup = __setup_cpu_604,
  474. .platform = "ppc604",
  475. },
  476. { /* 604r */
  477. .pvr_mask = 0xffff0000,
  478. .pvr_value = 0x00090000,
  479. .cpu_name = "604r",
  480. .cpu_features = CPU_FTRS_604,
  481. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  482. .icache_bsize = 32,
  483. .dcache_bsize = 32,
  484. .num_pmcs = 4,
  485. .cpu_setup = __setup_cpu_604,
  486. .platform = "ppc604",
  487. },
  488. { /* 604ev */
  489. .pvr_mask = 0xffff0000,
  490. .pvr_value = 0x000a0000,
  491. .cpu_name = "604ev",
  492. .cpu_features = CPU_FTRS_604,
  493. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  494. .icache_bsize = 32,
  495. .dcache_bsize = 32,
  496. .num_pmcs = 4,
  497. .cpu_setup = __setup_cpu_604,
  498. .platform = "ppc604",
  499. },
  500. { /* 740/750 (0x4202, don't support TAU ?) */
  501. .pvr_mask = 0xffffffff,
  502. .pvr_value = 0x00084202,
  503. .cpu_name = "740/750",
  504. .cpu_features = CPU_FTRS_740_NOTAU,
  505. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  506. .icache_bsize = 32,
  507. .dcache_bsize = 32,
  508. .num_pmcs = 4,
  509. .cpu_setup = __setup_cpu_750,
  510. .platform = "ppc750",
  511. },
  512. { /* 750CX (80100 and 8010x?) */
  513. .pvr_mask = 0xfffffff0,
  514. .pvr_value = 0x00080100,
  515. .cpu_name = "750CX",
  516. .cpu_features = CPU_FTRS_750,
  517. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  518. .icache_bsize = 32,
  519. .dcache_bsize = 32,
  520. .num_pmcs = 4,
  521. .cpu_setup = __setup_cpu_750cx,
  522. .platform = "ppc750",
  523. },
  524. { /* 750CX (82201 and 82202) */
  525. .pvr_mask = 0xfffffff0,
  526. .pvr_value = 0x00082200,
  527. .cpu_name = "750CX",
  528. .cpu_features = CPU_FTRS_750,
  529. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  530. .icache_bsize = 32,
  531. .dcache_bsize = 32,
  532. .num_pmcs = 4,
  533. .cpu_setup = __setup_cpu_750cx,
  534. .platform = "ppc750",
  535. },
  536. { /* 750CXe (82214) */
  537. .pvr_mask = 0xfffffff0,
  538. .pvr_value = 0x00082210,
  539. .cpu_name = "750CXe",
  540. .cpu_features = CPU_FTRS_750,
  541. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  542. .icache_bsize = 32,
  543. .dcache_bsize = 32,
  544. .num_pmcs = 4,
  545. .cpu_setup = __setup_cpu_750cx,
  546. .platform = "ppc750",
  547. },
  548. { /* 750CXe "Gekko" (83214) */
  549. .pvr_mask = 0xffffffff,
  550. .pvr_value = 0x00083214,
  551. .cpu_name = "750CXe",
  552. .cpu_features = CPU_FTRS_750,
  553. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  554. .icache_bsize = 32,
  555. .dcache_bsize = 32,
  556. .num_pmcs = 4,
  557. .cpu_setup = __setup_cpu_750cx,
  558. .platform = "ppc750",
  559. },
  560. { /* 750CL */
  561. .pvr_mask = 0xfffff0f0,
  562. .pvr_value = 0x00087010,
  563. .cpu_name = "750CL",
  564. .cpu_features = CPU_FTRS_750CL,
  565. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  566. .icache_bsize = 32,
  567. .dcache_bsize = 32,
  568. .num_pmcs = 4,
  569. .cpu_setup = __setup_cpu_750,
  570. .platform = "ppc750",
  571. },
  572. { /* 745/755 */
  573. .pvr_mask = 0xfffff000,
  574. .pvr_value = 0x00083000,
  575. .cpu_name = "745/755",
  576. .cpu_features = CPU_FTRS_750,
  577. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  578. .icache_bsize = 32,
  579. .dcache_bsize = 32,
  580. .num_pmcs = 4,
  581. .cpu_setup = __setup_cpu_750,
  582. .platform = "ppc750",
  583. },
  584. { /* 750FX rev 1.x */
  585. .pvr_mask = 0xffffff00,
  586. .pvr_value = 0x70000100,
  587. .cpu_name = "750FX",
  588. .cpu_features = CPU_FTRS_750FX1,
  589. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  590. .icache_bsize = 32,
  591. .dcache_bsize = 32,
  592. .num_pmcs = 4,
  593. .cpu_setup = __setup_cpu_750,
  594. .platform = "ppc750",
  595. },
  596. { /* 750FX rev 2.0 must disable HID0[DPM] */
  597. .pvr_mask = 0xffffffff,
  598. .pvr_value = 0x70000200,
  599. .cpu_name = "750FX",
  600. .cpu_features = CPU_FTRS_750FX2,
  601. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  602. .icache_bsize = 32,
  603. .dcache_bsize = 32,
  604. .num_pmcs = 4,
  605. .cpu_setup = __setup_cpu_750,
  606. .platform = "ppc750",
  607. },
  608. { /* 750FX (All revs except 2.0) */
  609. .pvr_mask = 0xffff0000,
  610. .pvr_value = 0x70000000,
  611. .cpu_name = "750FX",
  612. .cpu_features = CPU_FTRS_750FX,
  613. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  614. .icache_bsize = 32,
  615. .dcache_bsize = 32,
  616. .num_pmcs = 4,
  617. .cpu_setup = __setup_cpu_750fx,
  618. .platform = "ppc750",
  619. },
  620. { /* 750GX */
  621. .pvr_mask = 0xffff0000,
  622. .pvr_value = 0x70020000,
  623. .cpu_name = "750GX",
  624. .cpu_features = CPU_FTRS_750GX,
  625. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  626. .icache_bsize = 32,
  627. .dcache_bsize = 32,
  628. .num_pmcs = 4,
  629. .cpu_setup = __setup_cpu_750fx,
  630. .platform = "ppc750",
  631. },
  632. { /* 740/750 (L2CR bit need fixup for 740) */
  633. .pvr_mask = 0xffff0000,
  634. .pvr_value = 0x00080000,
  635. .cpu_name = "740/750",
  636. .cpu_features = CPU_FTRS_740,
  637. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  638. .icache_bsize = 32,
  639. .dcache_bsize = 32,
  640. .num_pmcs = 4,
  641. .cpu_setup = __setup_cpu_750,
  642. .platform = "ppc750",
  643. },
  644. { /* 7400 rev 1.1 ? (no TAU) */
  645. .pvr_mask = 0xffffffff,
  646. .pvr_value = 0x000c1101,
  647. .cpu_name = "7400 (1.1)",
  648. .cpu_features = CPU_FTRS_7400_NOTAU,
  649. .cpu_user_features = COMMON_USER |
  650. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  651. .icache_bsize = 32,
  652. .dcache_bsize = 32,
  653. .num_pmcs = 4,
  654. .cpu_setup = __setup_cpu_7400,
  655. .platform = "ppc7400",
  656. },
  657. { /* 7400 */
  658. .pvr_mask = 0xffff0000,
  659. .pvr_value = 0x000c0000,
  660. .cpu_name = "7400",
  661. .cpu_features = CPU_FTRS_7400,
  662. .cpu_user_features = COMMON_USER |
  663. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  664. .icache_bsize = 32,
  665. .dcache_bsize = 32,
  666. .num_pmcs = 4,
  667. .cpu_setup = __setup_cpu_7400,
  668. .platform = "ppc7400",
  669. },
  670. { /* 7410 */
  671. .pvr_mask = 0xffff0000,
  672. .pvr_value = 0x800c0000,
  673. .cpu_name = "7410",
  674. .cpu_features = CPU_FTRS_7400,
  675. .cpu_user_features = COMMON_USER |
  676. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  677. .icache_bsize = 32,
  678. .dcache_bsize = 32,
  679. .num_pmcs = 4,
  680. .cpu_setup = __setup_cpu_7410,
  681. .platform = "ppc7400",
  682. },
  683. { /* 7450 2.0 - no doze/nap */
  684. .pvr_mask = 0xffffffff,
  685. .pvr_value = 0x80000200,
  686. .cpu_name = "7450",
  687. .cpu_features = CPU_FTRS_7450_20,
  688. .cpu_user_features = COMMON_USER |
  689. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  690. .icache_bsize = 32,
  691. .dcache_bsize = 32,
  692. .num_pmcs = 6,
  693. .cpu_setup = __setup_cpu_745x,
  694. .oprofile_cpu_type = "ppc/7450",
  695. .oprofile_type = PPC_OPROFILE_G4,
  696. .platform = "ppc7450",
  697. },
  698. { /* 7450 2.1 */
  699. .pvr_mask = 0xffffffff,
  700. .pvr_value = 0x80000201,
  701. .cpu_name = "7450",
  702. .cpu_features = CPU_FTRS_7450_21,
  703. .cpu_user_features = COMMON_USER |
  704. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  705. .icache_bsize = 32,
  706. .dcache_bsize = 32,
  707. .num_pmcs = 6,
  708. .cpu_setup = __setup_cpu_745x,
  709. .oprofile_cpu_type = "ppc/7450",
  710. .oprofile_type = PPC_OPROFILE_G4,
  711. .platform = "ppc7450",
  712. },
  713. { /* 7450 2.3 and newer */
  714. .pvr_mask = 0xffff0000,
  715. .pvr_value = 0x80000000,
  716. .cpu_name = "7450",
  717. .cpu_features = CPU_FTRS_7450_23,
  718. .cpu_user_features = COMMON_USER |
  719. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  720. .icache_bsize = 32,
  721. .dcache_bsize = 32,
  722. .num_pmcs = 6,
  723. .cpu_setup = __setup_cpu_745x,
  724. .oprofile_cpu_type = "ppc/7450",
  725. .oprofile_type = PPC_OPROFILE_G4,
  726. .platform = "ppc7450",
  727. },
  728. { /* 7455 rev 1.x */
  729. .pvr_mask = 0xffffff00,
  730. .pvr_value = 0x80010100,
  731. .cpu_name = "7455",
  732. .cpu_features = CPU_FTRS_7455_1,
  733. .cpu_user_features = COMMON_USER |
  734. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  735. .icache_bsize = 32,
  736. .dcache_bsize = 32,
  737. .num_pmcs = 6,
  738. .cpu_setup = __setup_cpu_745x,
  739. .oprofile_cpu_type = "ppc/7450",
  740. .oprofile_type = PPC_OPROFILE_G4,
  741. .platform = "ppc7450",
  742. },
  743. { /* 7455 rev 2.0 */
  744. .pvr_mask = 0xffffffff,
  745. .pvr_value = 0x80010200,
  746. .cpu_name = "7455",
  747. .cpu_features = CPU_FTRS_7455_20,
  748. .cpu_user_features = COMMON_USER |
  749. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  750. .icache_bsize = 32,
  751. .dcache_bsize = 32,
  752. .num_pmcs = 6,
  753. .cpu_setup = __setup_cpu_745x,
  754. .oprofile_cpu_type = "ppc/7450",
  755. .oprofile_type = PPC_OPROFILE_G4,
  756. .platform = "ppc7450",
  757. },
  758. { /* 7455 others */
  759. .pvr_mask = 0xffff0000,
  760. .pvr_value = 0x80010000,
  761. .cpu_name = "7455",
  762. .cpu_features = CPU_FTRS_7455,
  763. .cpu_user_features = COMMON_USER |
  764. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  765. .icache_bsize = 32,
  766. .dcache_bsize = 32,
  767. .num_pmcs = 6,
  768. .cpu_setup = __setup_cpu_745x,
  769. .oprofile_cpu_type = "ppc/7450",
  770. .oprofile_type = PPC_OPROFILE_G4,
  771. .platform = "ppc7450",
  772. },
  773. { /* 7447/7457 Rev 1.0 */
  774. .pvr_mask = 0xffffffff,
  775. .pvr_value = 0x80020100,
  776. .cpu_name = "7447/7457",
  777. .cpu_features = CPU_FTRS_7447_10,
  778. .cpu_user_features = COMMON_USER |
  779. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  780. .icache_bsize = 32,
  781. .dcache_bsize = 32,
  782. .num_pmcs = 6,
  783. .cpu_setup = __setup_cpu_745x,
  784. .oprofile_cpu_type = "ppc/7450",
  785. .oprofile_type = PPC_OPROFILE_G4,
  786. .platform = "ppc7450",
  787. },
  788. { /* 7447/7457 Rev 1.1 */
  789. .pvr_mask = 0xffffffff,
  790. .pvr_value = 0x80020101,
  791. .cpu_name = "7447/7457",
  792. .cpu_features = CPU_FTRS_7447_10,
  793. .cpu_user_features = COMMON_USER |
  794. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  795. .icache_bsize = 32,
  796. .dcache_bsize = 32,
  797. .num_pmcs = 6,
  798. .cpu_setup = __setup_cpu_745x,
  799. .oprofile_cpu_type = "ppc/7450",
  800. .oprofile_type = PPC_OPROFILE_G4,
  801. .platform = "ppc7450",
  802. },
  803. { /* 7447/7457 Rev 1.2 and later */
  804. .pvr_mask = 0xffff0000,
  805. .pvr_value = 0x80020000,
  806. .cpu_name = "7447/7457",
  807. .cpu_features = CPU_FTRS_7447,
  808. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  809. .icache_bsize = 32,
  810. .dcache_bsize = 32,
  811. .num_pmcs = 6,
  812. .cpu_setup = __setup_cpu_745x,
  813. .oprofile_cpu_type = "ppc/7450",
  814. .oprofile_type = PPC_OPROFILE_G4,
  815. .platform = "ppc7450",
  816. },
  817. { /* 7447A */
  818. .pvr_mask = 0xffff0000,
  819. .pvr_value = 0x80030000,
  820. .cpu_name = "7447A",
  821. .cpu_features = CPU_FTRS_7447A,
  822. .cpu_user_features = COMMON_USER |
  823. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  824. .icache_bsize = 32,
  825. .dcache_bsize = 32,
  826. .num_pmcs = 6,
  827. .cpu_setup = __setup_cpu_745x,
  828. .oprofile_cpu_type = "ppc/7450",
  829. .oprofile_type = PPC_OPROFILE_G4,
  830. .platform = "ppc7450",
  831. },
  832. { /* 7448 */
  833. .pvr_mask = 0xffff0000,
  834. .pvr_value = 0x80040000,
  835. .cpu_name = "7448",
  836. .cpu_features = CPU_FTRS_7448,
  837. .cpu_user_features = COMMON_USER |
  838. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  839. .icache_bsize = 32,
  840. .dcache_bsize = 32,
  841. .num_pmcs = 6,
  842. .cpu_setup = __setup_cpu_745x,
  843. .oprofile_cpu_type = "ppc/7450",
  844. .oprofile_type = PPC_OPROFILE_G4,
  845. .platform = "ppc7450",
  846. },
  847. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  848. .pvr_mask = 0x7fff0000,
  849. .pvr_value = 0x00810000,
  850. .cpu_name = "82xx",
  851. .cpu_features = CPU_FTRS_82XX,
  852. .cpu_user_features = COMMON_USER,
  853. .icache_bsize = 32,
  854. .dcache_bsize = 32,
  855. .cpu_setup = __setup_cpu_603,
  856. .platform = "ppc603",
  857. },
  858. { /* All G2_LE (603e core, plus some) have the same pvr */
  859. .pvr_mask = 0x7fff0000,
  860. .pvr_value = 0x00820000,
  861. .cpu_name = "G2_LE",
  862. .cpu_features = CPU_FTRS_G2_LE,
  863. .cpu_user_features = COMMON_USER,
  864. .icache_bsize = 32,
  865. .dcache_bsize = 32,
  866. .cpu_setup = __setup_cpu_603,
  867. .platform = "ppc603",
  868. },
  869. { /* e300c1 (a 603e core, plus some) on 83xx */
  870. .pvr_mask = 0x7fff0000,
  871. .pvr_value = 0x00830000,
  872. .cpu_name = "e300c1",
  873. .cpu_features = CPU_FTRS_E300,
  874. .cpu_user_features = COMMON_USER,
  875. .icache_bsize = 32,
  876. .dcache_bsize = 32,
  877. .cpu_setup = __setup_cpu_603,
  878. .platform = "ppc603",
  879. },
  880. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  881. .pvr_mask = 0x7fff0000,
  882. .pvr_value = 0x00840000,
  883. .cpu_name = "e300c2",
  884. .cpu_features = CPU_FTRS_E300C2,
  885. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  886. .icache_bsize = 32,
  887. .dcache_bsize = 32,
  888. .cpu_setup = __setup_cpu_603,
  889. .platform = "ppc603",
  890. },
  891. { /* e300c3 on 83xx */
  892. .pvr_mask = 0x7fff0000,
  893. .pvr_value = 0x00850000,
  894. .cpu_name = "e300c3",
  895. .cpu_features = CPU_FTRS_E300,
  896. .cpu_user_features = COMMON_USER,
  897. .icache_bsize = 32,
  898. .dcache_bsize = 32,
  899. .cpu_setup = __setup_cpu_603,
  900. .platform = "ppc603",
  901. },
  902. { /* default match, we assume split I/D cache & TB (non-601)... */
  903. .pvr_mask = 0x00000000,
  904. .pvr_value = 0x00000000,
  905. .cpu_name = "(generic PPC)",
  906. .cpu_features = CPU_FTRS_CLASSIC32,
  907. .cpu_user_features = COMMON_USER,
  908. .icache_bsize = 32,
  909. .dcache_bsize = 32,
  910. .platform = "ppc603",
  911. },
  912. #endif /* CLASSIC_PPC */
  913. #ifdef CONFIG_8xx
  914. { /* 8xx */
  915. .pvr_mask = 0xffff0000,
  916. .pvr_value = 0x00500000,
  917. .cpu_name = "8xx",
  918. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  919. * if the 8xx code is there.... */
  920. .cpu_features = CPU_FTRS_8XX,
  921. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  922. .icache_bsize = 16,
  923. .dcache_bsize = 16,
  924. .platform = "ppc823",
  925. },
  926. #endif /* CONFIG_8xx */
  927. #ifdef CONFIG_40x
  928. { /* 403GC */
  929. .pvr_mask = 0xffffff00,
  930. .pvr_value = 0x00200200,
  931. .cpu_name = "403GC",
  932. .cpu_features = CPU_FTRS_40X,
  933. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  934. .icache_bsize = 16,
  935. .dcache_bsize = 16,
  936. .platform = "ppc403",
  937. },
  938. { /* 403GCX */
  939. .pvr_mask = 0xffffff00,
  940. .pvr_value = 0x00201400,
  941. .cpu_name = "403GCX",
  942. .cpu_features = CPU_FTRS_40X,
  943. .cpu_user_features = PPC_FEATURE_32 |
  944. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  945. .icache_bsize = 16,
  946. .dcache_bsize = 16,
  947. .platform = "ppc403",
  948. },
  949. { /* 403G ?? */
  950. .pvr_mask = 0xffff0000,
  951. .pvr_value = 0x00200000,
  952. .cpu_name = "403G ??",
  953. .cpu_features = CPU_FTRS_40X,
  954. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  955. .icache_bsize = 16,
  956. .dcache_bsize = 16,
  957. .platform = "ppc403",
  958. },
  959. { /* 405GP */
  960. .pvr_mask = 0xffff0000,
  961. .pvr_value = 0x40110000,
  962. .cpu_name = "405GP",
  963. .cpu_features = CPU_FTRS_40X,
  964. .cpu_user_features = PPC_FEATURE_32 |
  965. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  966. .icache_bsize = 32,
  967. .dcache_bsize = 32,
  968. .platform = "ppc405",
  969. },
  970. { /* STB 03xxx */
  971. .pvr_mask = 0xffff0000,
  972. .pvr_value = 0x40130000,
  973. .cpu_name = "STB03xxx",
  974. .cpu_features = CPU_FTRS_40X,
  975. .cpu_user_features = PPC_FEATURE_32 |
  976. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  977. .icache_bsize = 32,
  978. .dcache_bsize = 32,
  979. .platform = "ppc405",
  980. },
  981. { /* STB 04xxx */
  982. .pvr_mask = 0xffff0000,
  983. .pvr_value = 0x41810000,
  984. .cpu_name = "STB04xxx",
  985. .cpu_features = CPU_FTRS_40X,
  986. .cpu_user_features = PPC_FEATURE_32 |
  987. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  988. .icache_bsize = 32,
  989. .dcache_bsize = 32,
  990. .platform = "ppc405",
  991. },
  992. { /* NP405L */
  993. .pvr_mask = 0xffff0000,
  994. .pvr_value = 0x41610000,
  995. .cpu_name = "NP405L",
  996. .cpu_features = CPU_FTRS_40X,
  997. .cpu_user_features = PPC_FEATURE_32 |
  998. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  999. .icache_bsize = 32,
  1000. .dcache_bsize = 32,
  1001. .platform = "ppc405",
  1002. },
  1003. { /* NP4GS3 */
  1004. .pvr_mask = 0xffff0000,
  1005. .pvr_value = 0x40B10000,
  1006. .cpu_name = "NP4GS3",
  1007. .cpu_features = CPU_FTRS_40X,
  1008. .cpu_user_features = PPC_FEATURE_32 |
  1009. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1010. .icache_bsize = 32,
  1011. .dcache_bsize = 32,
  1012. .platform = "ppc405",
  1013. },
  1014. { /* NP405H */
  1015. .pvr_mask = 0xffff0000,
  1016. .pvr_value = 0x41410000,
  1017. .cpu_name = "NP405H",
  1018. .cpu_features = CPU_FTRS_40X,
  1019. .cpu_user_features = PPC_FEATURE_32 |
  1020. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1021. .icache_bsize = 32,
  1022. .dcache_bsize = 32,
  1023. .platform = "ppc405",
  1024. },
  1025. { /* 405GPr */
  1026. .pvr_mask = 0xffff0000,
  1027. .pvr_value = 0x50910000,
  1028. .cpu_name = "405GPr",
  1029. .cpu_features = CPU_FTRS_40X,
  1030. .cpu_user_features = PPC_FEATURE_32 |
  1031. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1032. .icache_bsize = 32,
  1033. .dcache_bsize = 32,
  1034. .platform = "ppc405",
  1035. },
  1036. { /* STBx25xx */
  1037. .pvr_mask = 0xffff0000,
  1038. .pvr_value = 0x51510000,
  1039. .cpu_name = "STBx25xx",
  1040. .cpu_features = CPU_FTRS_40X,
  1041. .cpu_user_features = PPC_FEATURE_32 |
  1042. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1043. .icache_bsize = 32,
  1044. .dcache_bsize = 32,
  1045. .platform = "ppc405",
  1046. },
  1047. { /* 405LP */
  1048. .pvr_mask = 0xffff0000,
  1049. .pvr_value = 0x41F10000,
  1050. .cpu_name = "405LP",
  1051. .cpu_features = CPU_FTRS_40X,
  1052. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1053. .icache_bsize = 32,
  1054. .dcache_bsize = 32,
  1055. .platform = "ppc405",
  1056. },
  1057. { /* Xilinx Virtex-II Pro */
  1058. .pvr_mask = 0xfffff000,
  1059. .pvr_value = 0x20010000,
  1060. .cpu_name = "Virtex-II Pro",
  1061. .cpu_features = CPU_FTRS_40X,
  1062. .cpu_user_features = PPC_FEATURE_32 |
  1063. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1064. .icache_bsize = 32,
  1065. .dcache_bsize = 32,
  1066. .platform = "ppc405",
  1067. },
  1068. { /* Xilinx Virtex-4 FX */
  1069. .pvr_mask = 0xfffff000,
  1070. .pvr_value = 0x20011000,
  1071. .cpu_name = "Virtex-4 FX",
  1072. .cpu_features = CPU_FTRS_40X,
  1073. .cpu_user_features = PPC_FEATURE_32 |
  1074. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1075. .icache_bsize = 32,
  1076. .dcache_bsize = 32,
  1077. .platform = "ppc405",
  1078. },
  1079. { /* 405EP */
  1080. .pvr_mask = 0xffff0000,
  1081. .pvr_value = 0x51210000,
  1082. .cpu_name = "405EP",
  1083. .cpu_features = CPU_FTRS_40X,
  1084. .cpu_user_features = PPC_FEATURE_32 |
  1085. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1086. .icache_bsize = 32,
  1087. .dcache_bsize = 32,
  1088. .platform = "ppc405",
  1089. },
  1090. #endif /* CONFIG_40x */
  1091. #ifdef CONFIG_44x
  1092. {
  1093. .pvr_mask = 0xf0000fff,
  1094. .pvr_value = 0x40000850,
  1095. .cpu_name = "440EP Rev. A",
  1096. .cpu_features = CPU_FTRS_44X,
  1097. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1098. .icache_bsize = 32,
  1099. .dcache_bsize = 32,
  1100. .platform = "ppc440",
  1101. },
  1102. {
  1103. .pvr_mask = 0xf0000fff,
  1104. .pvr_value = 0x400008d3,
  1105. .cpu_name = "440EP Rev. B",
  1106. .cpu_features = CPU_FTRS_44X,
  1107. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1108. .icache_bsize = 32,
  1109. .dcache_bsize = 32,
  1110. .platform = "ppc440",
  1111. },
  1112. { /* 440GP Rev. B */
  1113. .pvr_mask = 0xf0000fff,
  1114. .pvr_value = 0x40000440,
  1115. .cpu_name = "440GP Rev. B",
  1116. .cpu_features = CPU_FTRS_44X,
  1117. .cpu_user_features = COMMON_USER_BOOKE,
  1118. .icache_bsize = 32,
  1119. .dcache_bsize = 32,
  1120. .platform = "ppc440gp",
  1121. },
  1122. { /* 440GP Rev. C */
  1123. .pvr_mask = 0xf0000fff,
  1124. .pvr_value = 0x40000481,
  1125. .cpu_name = "440GP Rev. C",
  1126. .cpu_features = CPU_FTRS_44X,
  1127. .cpu_user_features = COMMON_USER_BOOKE,
  1128. .icache_bsize = 32,
  1129. .dcache_bsize = 32,
  1130. .platform = "ppc440gp",
  1131. },
  1132. { /* 440GX Rev. A */
  1133. .pvr_mask = 0xf0000fff,
  1134. .pvr_value = 0x50000850,
  1135. .cpu_name = "440GX Rev. A",
  1136. .cpu_features = CPU_FTRS_44X,
  1137. .cpu_user_features = COMMON_USER_BOOKE,
  1138. .icache_bsize = 32,
  1139. .dcache_bsize = 32,
  1140. .platform = "ppc440",
  1141. },
  1142. { /* 440GX Rev. B */
  1143. .pvr_mask = 0xf0000fff,
  1144. .pvr_value = 0x50000851,
  1145. .cpu_name = "440GX Rev. B",
  1146. .cpu_features = CPU_FTRS_44X,
  1147. .cpu_user_features = COMMON_USER_BOOKE,
  1148. .icache_bsize = 32,
  1149. .dcache_bsize = 32,
  1150. .platform = "ppc440",
  1151. },
  1152. { /* 440GX Rev. C */
  1153. .pvr_mask = 0xf0000fff,
  1154. .pvr_value = 0x50000892,
  1155. .cpu_name = "440GX Rev. C",
  1156. .cpu_features = CPU_FTRS_44X,
  1157. .cpu_user_features = COMMON_USER_BOOKE,
  1158. .icache_bsize = 32,
  1159. .dcache_bsize = 32,
  1160. .platform = "ppc440",
  1161. },
  1162. { /* 440GX Rev. F */
  1163. .pvr_mask = 0xf0000fff,
  1164. .pvr_value = 0x50000894,
  1165. .cpu_name = "440GX Rev. F",
  1166. .cpu_features = CPU_FTRS_44X,
  1167. .cpu_user_features = COMMON_USER_BOOKE,
  1168. .icache_bsize = 32,
  1169. .dcache_bsize = 32,
  1170. .platform = "ppc440",
  1171. },
  1172. { /* 440SP Rev. A */
  1173. .pvr_mask = 0xff000fff,
  1174. .pvr_value = 0x53000891,
  1175. .cpu_name = "440SP Rev. A",
  1176. .cpu_features = CPU_FTRS_44X,
  1177. .cpu_user_features = COMMON_USER_BOOKE,
  1178. .icache_bsize = 32,
  1179. .dcache_bsize = 32,
  1180. .platform = "ppc440",
  1181. },
  1182. { /* 440SPe Rev. A */
  1183. .pvr_mask = 0xff000fff,
  1184. .pvr_value = 0x53000890,
  1185. .cpu_name = "440SPe Rev. A",
  1186. .cpu_features = CPU_FTRS_44X,
  1187. .cpu_user_features = COMMON_USER_BOOKE,
  1188. .icache_bsize = 32,
  1189. .dcache_bsize = 32,
  1190. .platform = "ppc440",
  1191. },
  1192. #endif /* CONFIG_44x */
  1193. #ifdef CONFIG_FSL_BOOKE
  1194. { /* e200z5 */
  1195. .pvr_mask = 0xfff00000,
  1196. .pvr_value = 0x81000000,
  1197. .cpu_name = "e200z5",
  1198. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1199. .cpu_features = CPU_FTRS_E200,
  1200. .cpu_user_features = COMMON_USER_BOOKE |
  1201. PPC_FEATURE_HAS_EFP_SINGLE |
  1202. PPC_FEATURE_UNIFIED_CACHE,
  1203. .dcache_bsize = 32,
  1204. .platform = "ppc5554",
  1205. },
  1206. { /* e200z6 */
  1207. .pvr_mask = 0xfff00000,
  1208. .pvr_value = 0x81100000,
  1209. .cpu_name = "e200z6",
  1210. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1211. .cpu_features = CPU_FTRS_E200,
  1212. .cpu_user_features = COMMON_USER_BOOKE |
  1213. PPC_FEATURE_SPE_COMP |
  1214. PPC_FEATURE_HAS_EFP_SINGLE |
  1215. PPC_FEATURE_UNIFIED_CACHE,
  1216. .dcache_bsize = 32,
  1217. .platform = "ppc5554",
  1218. },
  1219. { /* e500 */
  1220. .pvr_mask = 0xffff0000,
  1221. .pvr_value = 0x80200000,
  1222. .cpu_name = "e500",
  1223. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1224. .cpu_features = CPU_FTRS_E500,
  1225. .cpu_user_features = COMMON_USER_BOOKE |
  1226. PPC_FEATURE_SPE_COMP |
  1227. PPC_FEATURE_HAS_EFP_SINGLE,
  1228. .icache_bsize = 32,
  1229. .dcache_bsize = 32,
  1230. .num_pmcs = 4,
  1231. .oprofile_cpu_type = "ppc/e500",
  1232. .oprofile_type = PPC_OPROFILE_BOOKE,
  1233. .platform = "ppc8540",
  1234. },
  1235. { /* e500v2 */
  1236. .pvr_mask = 0xffff0000,
  1237. .pvr_value = 0x80210000,
  1238. .cpu_name = "e500v2",
  1239. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1240. .cpu_features = CPU_FTRS_E500_2,
  1241. .cpu_user_features = COMMON_USER_BOOKE |
  1242. PPC_FEATURE_SPE_COMP |
  1243. PPC_FEATURE_HAS_EFP_SINGLE |
  1244. PPC_FEATURE_HAS_EFP_DOUBLE,
  1245. .icache_bsize = 32,
  1246. .dcache_bsize = 32,
  1247. .num_pmcs = 4,
  1248. .oprofile_cpu_type = "ppc/e500",
  1249. .oprofile_type = PPC_OPROFILE_BOOKE,
  1250. .platform = "ppc8548",
  1251. },
  1252. #endif
  1253. #if !CLASSIC_PPC
  1254. { /* default match */
  1255. .pvr_mask = 0x00000000,
  1256. .pvr_value = 0x00000000,
  1257. .cpu_name = "(generic PPC)",
  1258. .cpu_features = CPU_FTRS_GENERIC_32,
  1259. .cpu_user_features = PPC_FEATURE_32,
  1260. .icache_bsize = 32,
  1261. .dcache_bsize = 32,
  1262. .platform = "powerpc",
  1263. }
  1264. #endif /* !CLASSIC_PPC */
  1265. #endif /* CONFIG_PPC32 */
  1266. };
  1267. struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr)
  1268. {
  1269. struct cpu_spec *s = cpu_specs;
  1270. struct cpu_spec **cur = &cur_cpu_spec;
  1271. int i;
  1272. s = PTRRELOC(s);
  1273. cur = PTRRELOC(cur);
  1274. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++)
  1275. if ((pvr & s->pvr_mask) == s->pvr_value) {
  1276. *cur = cpu_specs + i;
  1277. #ifdef CONFIG_PPC64
  1278. /* ppc64 expects identify_cpu to also call setup_cpu
  1279. * for that processor. I will consolidate that at a
  1280. * later time, for now, just use our friend #ifdef.
  1281. * we also don't need to PTRRELOC the function pointer
  1282. * on ppc64 as we are running at 0 in real mode.
  1283. */
  1284. if (s->cpu_setup) {
  1285. s->cpu_setup(offset, s);
  1286. }
  1287. #endif /* CONFIG_PPC64 */
  1288. return s;
  1289. }
  1290. BUG();
  1291. return NULL;
  1292. }
  1293. void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
  1294. {
  1295. struct fixup_entry {
  1296. unsigned long mask;
  1297. unsigned long value;
  1298. long start_off;
  1299. long end_off;
  1300. } *fcur, *fend;
  1301. fcur = fixup_start;
  1302. fend = fixup_end;
  1303. for (; fcur < fend; fcur++) {
  1304. unsigned int *pstart, *pend, *p;
  1305. if ((value & fcur->mask) == fcur->value)
  1306. continue;
  1307. /* These PTRRELOCs will disappear once the new scheme for
  1308. * modules and vdso is implemented
  1309. */
  1310. pstart = ((unsigned int *)fcur) + (fcur->start_off / 4);
  1311. pend = ((unsigned int *)fcur) + (fcur->end_off / 4);
  1312. for (p = pstart; p < pend; p++) {
  1313. *p = 0x60000000u;
  1314. asm volatile ("dcbst 0, %0" : : "r" (p));
  1315. }
  1316. asm volatile ("sync" : : : "memory");
  1317. for (p = pstart; p < pend; p++)
  1318. asm volatile ("icbi 0,%0" : : "r" (p));
  1319. asm volatile ("sync; isync" : : : "memory");
  1320. }
  1321. }