recv.c 53 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include "ath9k.h"
  18. #include "ar9003_mac.h"
  19. #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
  20. static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
  21. int mindelta, int main_rssi_avg,
  22. int alt_rssi_avg, int pkt_count)
  23. {
  24. return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  25. (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
  26. (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
  27. }
  28. static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
  29. int curr_main_set, int curr_alt_set,
  30. int alt_rssi_avg, int main_rssi_avg)
  31. {
  32. bool result = false;
  33. switch (div_group) {
  34. case 0:
  35. if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
  36. result = true;
  37. break;
  38. case 1:
  39. case 2:
  40. if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
  41. (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
  42. (alt_rssi_avg >= (main_rssi_avg - 5))) ||
  43. ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
  44. (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
  45. (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
  46. (alt_rssi_avg >= 4))
  47. result = true;
  48. else
  49. result = false;
  50. break;
  51. }
  52. return result;
  53. }
  54. static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
  55. {
  56. return sc->ps_enabled &&
  57. (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
  58. }
  59. /*
  60. * Setup and link descriptors.
  61. *
  62. * 11N: we can no longer afford to self link the last descriptor.
  63. * MAC acknowledges BA status as long as it copies frames to host
  64. * buffer (or rx fifo). This can incorrectly acknowledge packets
  65. * to a sender if last desc is self-linked.
  66. */
  67. static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  68. {
  69. struct ath_hw *ah = sc->sc_ah;
  70. struct ath_common *common = ath9k_hw_common(ah);
  71. struct ath_desc *ds;
  72. struct sk_buff *skb;
  73. ATH_RXBUF_RESET(bf);
  74. ds = bf->bf_desc;
  75. ds->ds_link = 0; /* link to null */
  76. ds->ds_data = bf->bf_buf_addr;
  77. /* virtual addr of the beginning of the buffer. */
  78. skb = bf->bf_mpdu;
  79. BUG_ON(skb == NULL);
  80. ds->ds_vdata = skb->data;
  81. /*
  82. * setup rx descriptors. The rx_bufsize here tells the hardware
  83. * how much data it can DMA to us and that we are prepared
  84. * to process
  85. */
  86. ath9k_hw_setuprxdesc(ah, ds,
  87. common->rx_bufsize,
  88. 0);
  89. if (sc->rx.rxlink == NULL)
  90. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  91. else
  92. *sc->rx.rxlink = bf->bf_daddr;
  93. sc->rx.rxlink = &ds->ds_link;
  94. }
  95. static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
  96. {
  97. /* XXX block beacon interrupts */
  98. ath9k_hw_setantenna(sc->sc_ah, antenna);
  99. sc->rx.defant = antenna;
  100. sc->rx.rxotherant = 0;
  101. }
  102. static void ath_opmode_init(struct ath_softc *sc)
  103. {
  104. struct ath_hw *ah = sc->sc_ah;
  105. struct ath_common *common = ath9k_hw_common(ah);
  106. u32 rfilt, mfilt[2];
  107. /* configure rx filter */
  108. rfilt = ath_calcrxfilter(sc);
  109. ath9k_hw_setrxfilter(ah, rfilt);
  110. /* configure bssid mask */
  111. ath_hw_setbssidmask(common);
  112. /* configure operational mode */
  113. ath9k_hw_setopmode(ah);
  114. /* calculate and install multicast filter */
  115. mfilt[0] = mfilt[1] = ~0;
  116. ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
  117. }
  118. static bool ath_rx_edma_buf_link(struct ath_softc *sc,
  119. enum ath9k_rx_qtype qtype)
  120. {
  121. struct ath_hw *ah = sc->sc_ah;
  122. struct ath_rx_edma *rx_edma;
  123. struct sk_buff *skb;
  124. struct ath_buf *bf;
  125. rx_edma = &sc->rx.rx_edma[qtype];
  126. if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
  127. return false;
  128. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  129. list_del_init(&bf->list);
  130. skb = bf->bf_mpdu;
  131. ATH_RXBUF_RESET(bf);
  132. memset(skb->data, 0, ah->caps.rx_status_len);
  133. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  134. ah->caps.rx_status_len, DMA_TO_DEVICE);
  135. SKB_CB_ATHBUF(skb) = bf;
  136. ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
  137. skb_queue_tail(&rx_edma->rx_fifo, skb);
  138. return true;
  139. }
  140. static void ath_rx_addbuffer_edma(struct ath_softc *sc,
  141. enum ath9k_rx_qtype qtype, int size)
  142. {
  143. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  144. u32 nbuf = 0;
  145. if (list_empty(&sc->rx.rxbuf)) {
  146. ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
  147. return;
  148. }
  149. while (!list_empty(&sc->rx.rxbuf)) {
  150. nbuf++;
  151. if (!ath_rx_edma_buf_link(sc, qtype))
  152. break;
  153. if (nbuf >= size)
  154. break;
  155. }
  156. }
  157. static void ath_rx_remove_buffer(struct ath_softc *sc,
  158. enum ath9k_rx_qtype qtype)
  159. {
  160. struct ath_buf *bf;
  161. struct ath_rx_edma *rx_edma;
  162. struct sk_buff *skb;
  163. rx_edma = &sc->rx.rx_edma[qtype];
  164. while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
  165. bf = SKB_CB_ATHBUF(skb);
  166. BUG_ON(!bf);
  167. list_add_tail(&bf->list, &sc->rx.rxbuf);
  168. }
  169. }
  170. static void ath_rx_edma_cleanup(struct ath_softc *sc)
  171. {
  172. struct ath_hw *ah = sc->sc_ah;
  173. struct ath_common *common = ath9k_hw_common(ah);
  174. struct ath_buf *bf;
  175. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
  176. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
  177. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  178. if (bf->bf_mpdu) {
  179. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  180. common->rx_bufsize,
  181. DMA_BIDIRECTIONAL);
  182. dev_kfree_skb_any(bf->bf_mpdu);
  183. bf->bf_buf_addr = 0;
  184. bf->bf_mpdu = NULL;
  185. }
  186. }
  187. INIT_LIST_HEAD(&sc->rx.rxbuf);
  188. kfree(sc->rx.rx_bufptr);
  189. sc->rx.rx_bufptr = NULL;
  190. }
  191. static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
  192. {
  193. skb_queue_head_init(&rx_edma->rx_fifo);
  194. skb_queue_head_init(&rx_edma->rx_buffers);
  195. rx_edma->rx_fifo_hwsize = size;
  196. }
  197. static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
  198. {
  199. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  200. struct ath_hw *ah = sc->sc_ah;
  201. struct sk_buff *skb;
  202. struct ath_buf *bf;
  203. int error = 0, i;
  204. u32 size;
  205. ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
  206. ah->caps.rx_status_len);
  207. ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
  208. ah->caps.rx_lp_qdepth);
  209. ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
  210. ah->caps.rx_hp_qdepth);
  211. size = sizeof(struct ath_buf) * nbufs;
  212. bf = kzalloc(size, GFP_KERNEL);
  213. if (!bf)
  214. return -ENOMEM;
  215. INIT_LIST_HEAD(&sc->rx.rxbuf);
  216. sc->rx.rx_bufptr = bf;
  217. for (i = 0; i < nbufs; i++, bf++) {
  218. skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
  219. if (!skb) {
  220. error = -ENOMEM;
  221. goto rx_init_fail;
  222. }
  223. memset(skb->data, 0, common->rx_bufsize);
  224. bf->bf_mpdu = skb;
  225. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  226. common->rx_bufsize,
  227. DMA_BIDIRECTIONAL);
  228. if (unlikely(dma_mapping_error(sc->dev,
  229. bf->bf_buf_addr))) {
  230. dev_kfree_skb_any(skb);
  231. bf->bf_mpdu = NULL;
  232. bf->bf_buf_addr = 0;
  233. ath_err(common,
  234. "dma_mapping_error() on RX init\n");
  235. error = -ENOMEM;
  236. goto rx_init_fail;
  237. }
  238. list_add_tail(&bf->list, &sc->rx.rxbuf);
  239. }
  240. return 0;
  241. rx_init_fail:
  242. ath_rx_edma_cleanup(sc);
  243. return error;
  244. }
  245. static void ath_edma_start_recv(struct ath_softc *sc)
  246. {
  247. spin_lock_bh(&sc->rx.rxbuflock);
  248. ath9k_hw_rxena(sc->sc_ah);
  249. ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
  250. sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
  251. ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
  252. sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
  253. ath_opmode_init(sc);
  254. ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
  255. spin_unlock_bh(&sc->rx.rxbuflock);
  256. }
  257. static void ath_edma_stop_recv(struct ath_softc *sc)
  258. {
  259. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
  260. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
  261. }
  262. int ath_rx_init(struct ath_softc *sc, int nbufs)
  263. {
  264. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  265. struct sk_buff *skb;
  266. struct ath_buf *bf;
  267. int error = 0;
  268. spin_lock_init(&sc->sc_pcu_lock);
  269. sc->sc_flags &= ~SC_OP_RXFLUSH;
  270. spin_lock_init(&sc->rx.rxbuflock);
  271. common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
  272. sc->sc_ah->caps.rx_status_len;
  273. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  274. return ath_rx_edma_init(sc, nbufs);
  275. } else {
  276. ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
  277. common->cachelsz, common->rx_bufsize);
  278. /* Initialize rx descriptors */
  279. error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
  280. "rx", nbufs, 1, 0);
  281. if (error != 0) {
  282. ath_err(common,
  283. "failed to allocate rx descriptors: %d\n",
  284. error);
  285. goto err;
  286. }
  287. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  288. skb = ath_rxbuf_alloc(common, common->rx_bufsize,
  289. GFP_KERNEL);
  290. if (skb == NULL) {
  291. error = -ENOMEM;
  292. goto err;
  293. }
  294. bf->bf_mpdu = skb;
  295. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  296. common->rx_bufsize,
  297. DMA_FROM_DEVICE);
  298. if (unlikely(dma_mapping_error(sc->dev,
  299. bf->bf_buf_addr))) {
  300. dev_kfree_skb_any(skb);
  301. bf->bf_mpdu = NULL;
  302. bf->bf_buf_addr = 0;
  303. ath_err(common,
  304. "dma_mapping_error() on RX init\n");
  305. error = -ENOMEM;
  306. goto err;
  307. }
  308. }
  309. sc->rx.rxlink = NULL;
  310. }
  311. err:
  312. if (error)
  313. ath_rx_cleanup(sc);
  314. return error;
  315. }
  316. void ath_rx_cleanup(struct ath_softc *sc)
  317. {
  318. struct ath_hw *ah = sc->sc_ah;
  319. struct ath_common *common = ath9k_hw_common(ah);
  320. struct sk_buff *skb;
  321. struct ath_buf *bf;
  322. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  323. ath_rx_edma_cleanup(sc);
  324. return;
  325. } else {
  326. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  327. skb = bf->bf_mpdu;
  328. if (skb) {
  329. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  330. common->rx_bufsize,
  331. DMA_FROM_DEVICE);
  332. dev_kfree_skb(skb);
  333. bf->bf_buf_addr = 0;
  334. bf->bf_mpdu = NULL;
  335. }
  336. }
  337. if (sc->rx.rxdma.dd_desc_len != 0)
  338. ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
  339. }
  340. }
  341. /*
  342. * Calculate the receive filter according to the
  343. * operating mode and state:
  344. *
  345. * o always accept unicast, broadcast, and multicast traffic
  346. * o maintain current state of phy error reception (the hal
  347. * may enable phy error frames for noise immunity work)
  348. * o probe request frames are accepted only when operating in
  349. * hostap, adhoc, or monitor modes
  350. * o enable promiscuous mode according to the interface state
  351. * o accept beacons:
  352. * - when operating in adhoc mode so the 802.11 layer creates
  353. * node table entries for peers,
  354. * - when operating in station mode for collecting rssi data when
  355. * the station is otherwise quiet, or
  356. * - when operating as a repeater so we see repeater-sta beacons
  357. * - when scanning
  358. */
  359. u32 ath_calcrxfilter(struct ath_softc *sc)
  360. {
  361. u32 rfilt;
  362. rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
  363. | ATH9K_RX_FILTER_MCAST;
  364. if (sc->rx.rxfilter & FIF_PROBE_REQ)
  365. rfilt |= ATH9K_RX_FILTER_PROBEREQ;
  366. /*
  367. * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
  368. * mode interface or when in monitor mode. AP mode does not need this
  369. * since it receives all in-BSS frames anyway.
  370. */
  371. if (sc->sc_ah->is_monitoring)
  372. rfilt |= ATH9K_RX_FILTER_PROM;
  373. if (sc->rx.rxfilter & FIF_CONTROL)
  374. rfilt |= ATH9K_RX_FILTER_CONTROL;
  375. if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
  376. (sc->nvifs <= 1) &&
  377. !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
  378. rfilt |= ATH9K_RX_FILTER_MYBEACON;
  379. else
  380. rfilt |= ATH9K_RX_FILTER_BEACON;
  381. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  382. (sc->rx.rxfilter & FIF_PSPOLL))
  383. rfilt |= ATH9K_RX_FILTER_PSPOLL;
  384. if (conf_is_ht(&sc->hw->conf))
  385. rfilt |= ATH9K_RX_FILTER_COMP_BAR;
  386. if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
  387. /* The following may also be needed for other older chips */
  388. if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
  389. rfilt |= ATH9K_RX_FILTER_PROM;
  390. rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
  391. }
  392. return rfilt;
  393. }
  394. int ath_startrecv(struct ath_softc *sc)
  395. {
  396. struct ath_hw *ah = sc->sc_ah;
  397. struct ath_buf *bf, *tbf;
  398. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  399. ath_edma_start_recv(sc);
  400. return 0;
  401. }
  402. spin_lock_bh(&sc->rx.rxbuflock);
  403. if (list_empty(&sc->rx.rxbuf))
  404. goto start_recv;
  405. sc->rx.rxlink = NULL;
  406. list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
  407. ath_rx_buf_link(sc, bf);
  408. }
  409. /* We could have deleted elements so the list may be empty now */
  410. if (list_empty(&sc->rx.rxbuf))
  411. goto start_recv;
  412. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  413. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  414. ath9k_hw_rxena(ah);
  415. start_recv:
  416. ath_opmode_init(sc);
  417. ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
  418. spin_unlock_bh(&sc->rx.rxbuflock);
  419. return 0;
  420. }
  421. bool ath_stoprecv(struct ath_softc *sc)
  422. {
  423. struct ath_hw *ah = sc->sc_ah;
  424. bool stopped, reset = false;
  425. spin_lock_bh(&sc->rx.rxbuflock);
  426. ath9k_hw_abortpcurecv(ah);
  427. ath9k_hw_setrxfilter(ah, 0);
  428. stopped = ath9k_hw_stopdmarecv(ah, &reset);
  429. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  430. ath_edma_stop_recv(sc);
  431. else
  432. sc->rx.rxlink = NULL;
  433. spin_unlock_bh(&sc->rx.rxbuflock);
  434. if (!(ah->ah_flags & AH_UNPLUGGED) &&
  435. unlikely(!stopped)) {
  436. ath_err(ath9k_hw_common(sc->sc_ah),
  437. "Could not stop RX, we could be "
  438. "confusing the DMA engine when we start RX up\n");
  439. ATH_DBG_WARN_ON_ONCE(!stopped);
  440. }
  441. return stopped && !reset;
  442. }
  443. void ath_flushrecv(struct ath_softc *sc)
  444. {
  445. sc->sc_flags |= SC_OP_RXFLUSH;
  446. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  447. ath_rx_tasklet(sc, 1, true);
  448. ath_rx_tasklet(sc, 1, false);
  449. sc->sc_flags &= ~SC_OP_RXFLUSH;
  450. }
  451. static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
  452. {
  453. /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
  454. struct ieee80211_mgmt *mgmt;
  455. u8 *pos, *end, id, elen;
  456. struct ieee80211_tim_ie *tim;
  457. mgmt = (struct ieee80211_mgmt *)skb->data;
  458. pos = mgmt->u.beacon.variable;
  459. end = skb->data + skb->len;
  460. while (pos + 2 < end) {
  461. id = *pos++;
  462. elen = *pos++;
  463. if (pos + elen > end)
  464. break;
  465. if (id == WLAN_EID_TIM) {
  466. if (elen < sizeof(*tim))
  467. break;
  468. tim = (struct ieee80211_tim_ie *) pos;
  469. if (tim->dtim_count != 0)
  470. break;
  471. return tim->bitmap_ctrl & 0x01;
  472. }
  473. pos += elen;
  474. }
  475. return false;
  476. }
  477. static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
  478. {
  479. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  480. if (skb->len < 24 + 8 + 2 + 2)
  481. return;
  482. sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
  483. if (sc->ps_flags & PS_BEACON_SYNC) {
  484. sc->ps_flags &= ~PS_BEACON_SYNC;
  485. ath_dbg(common, ATH_DBG_PS,
  486. "Reconfigure Beacon timers based on timestamp from the AP\n");
  487. ath_set_beacon(sc);
  488. }
  489. if (ath_beacon_dtim_pending_cab(skb)) {
  490. /*
  491. * Remain awake waiting for buffered broadcast/multicast
  492. * frames. If the last broadcast/multicast frame is not
  493. * received properly, the next beacon frame will work as
  494. * a backup trigger for returning into NETWORK SLEEP state,
  495. * so we are waiting for it as well.
  496. */
  497. ath_dbg(common, ATH_DBG_PS,
  498. "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
  499. sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
  500. return;
  501. }
  502. if (sc->ps_flags & PS_WAIT_FOR_CAB) {
  503. /*
  504. * This can happen if a broadcast frame is dropped or the AP
  505. * fails to send a frame indicating that all CAB frames have
  506. * been delivered.
  507. */
  508. sc->ps_flags &= ~PS_WAIT_FOR_CAB;
  509. ath_dbg(common, ATH_DBG_PS,
  510. "PS wait for CAB frames timed out\n");
  511. }
  512. }
  513. static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
  514. {
  515. struct ieee80211_hdr *hdr;
  516. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  517. hdr = (struct ieee80211_hdr *)skb->data;
  518. /* Process Beacon and CAB receive in PS state */
  519. if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
  520. && mybeacon)
  521. ath_rx_ps_beacon(sc, skb);
  522. else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
  523. (ieee80211_is_data(hdr->frame_control) ||
  524. ieee80211_is_action(hdr->frame_control)) &&
  525. is_multicast_ether_addr(hdr->addr1) &&
  526. !ieee80211_has_moredata(hdr->frame_control)) {
  527. /*
  528. * No more broadcast/multicast frames to be received at this
  529. * point.
  530. */
  531. sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
  532. ath_dbg(common, ATH_DBG_PS,
  533. "All PS CAB frames received, back to sleep\n");
  534. } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
  535. !is_multicast_ether_addr(hdr->addr1) &&
  536. !ieee80211_has_morefrags(hdr->frame_control)) {
  537. sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
  538. ath_dbg(common, ATH_DBG_PS,
  539. "Going back to sleep after having received PS-Poll data (0x%lx)\n",
  540. sc->ps_flags & (PS_WAIT_FOR_BEACON |
  541. PS_WAIT_FOR_CAB |
  542. PS_WAIT_FOR_PSPOLL_DATA |
  543. PS_WAIT_FOR_TX_ACK));
  544. }
  545. }
  546. static bool ath_edma_get_buffers(struct ath_softc *sc,
  547. enum ath9k_rx_qtype qtype)
  548. {
  549. struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
  550. struct ath_hw *ah = sc->sc_ah;
  551. struct ath_common *common = ath9k_hw_common(ah);
  552. struct sk_buff *skb;
  553. struct ath_buf *bf;
  554. int ret;
  555. skb = skb_peek(&rx_edma->rx_fifo);
  556. if (!skb)
  557. return false;
  558. bf = SKB_CB_ATHBUF(skb);
  559. BUG_ON(!bf);
  560. dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
  561. common->rx_bufsize, DMA_FROM_DEVICE);
  562. ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
  563. if (ret == -EINPROGRESS) {
  564. /*let device gain the buffer again*/
  565. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  566. common->rx_bufsize, DMA_FROM_DEVICE);
  567. return false;
  568. }
  569. __skb_unlink(skb, &rx_edma->rx_fifo);
  570. if (ret == -EINVAL) {
  571. /* corrupt descriptor, skip this one and the following one */
  572. list_add_tail(&bf->list, &sc->rx.rxbuf);
  573. ath_rx_edma_buf_link(sc, qtype);
  574. skb = skb_peek(&rx_edma->rx_fifo);
  575. if (!skb)
  576. return true;
  577. bf = SKB_CB_ATHBUF(skb);
  578. BUG_ON(!bf);
  579. __skb_unlink(skb, &rx_edma->rx_fifo);
  580. list_add_tail(&bf->list, &sc->rx.rxbuf);
  581. ath_rx_edma_buf_link(sc, qtype);
  582. return true;
  583. }
  584. skb_queue_tail(&rx_edma->rx_buffers, skb);
  585. return true;
  586. }
  587. static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
  588. struct ath_rx_status *rs,
  589. enum ath9k_rx_qtype qtype)
  590. {
  591. struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
  592. struct sk_buff *skb;
  593. struct ath_buf *bf;
  594. while (ath_edma_get_buffers(sc, qtype));
  595. skb = __skb_dequeue(&rx_edma->rx_buffers);
  596. if (!skb)
  597. return NULL;
  598. bf = SKB_CB_ATHBUF(skb);
  599. ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
  600. return bf;
  601. }
  602. static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
  603. struct ath_rx_status *rs)
  604. {
  605. struct ath_hw *ah = sc->sc_ah;
  606. struct ath_common *common = ath9k_hw_common(ah);
  607. struct ath_desc *ds;
  608. struct ath_buf *bf;
  609. int ret;
  610. if (list_empty(&sc->rx.rxbuf)) {
  611. sc->rx.rxlink = NULL;
  612. return NULL;
  613. }
  614. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  615. ds = bf->bf_desc;
  616. /*
  617. * Must provide the virtual address of the current
  618. * descriptor, the physical address, and the virtual
  619. * address of the next descriptor in the h/w chain.
  620. * This allows the HAL to look ahead to see if the
  621. * hardware is done with a descriptor by checking the
  622. * done bit in the following descriptor and the address
  623. * of the current descriptor the DMA engine is working
  624. * on. All this is necessary because of our use of
  625. * a self-linked list to avoid rx overruns.
  626. */
  627. ret = ath9k_hw_rxprocdesc(ah, ds, rs);
  628. if (ret == -EINPROGRESS) {
  629. struct ath_rx_status trs;
  630. struct ath_buf *tbf;
  631. struct ath_desc *tds;
  632. memset(&trs, 0, sizeof(trs));
  633. if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
  634. sc->rx.rxlink = NULL;
  635. return NULL;
  636. }
  637. tbf = list_entry(bf->list.next, struct ath_buf, list);
  638. /*
  639. * On some hardware the descriptor status words could
  640. * get corrupted, including the done bit. Because of
  641. * this, check if the next descriptor's done bit is
  642. * set or not.
  643. *
  644. * If the next descriptor's done bit is set, the current
  645. * descriptor has been corrupted. Force s/w to discard
  646. * this descriptor and continue...
  647. */
  648. tds = tbf->bf_desc;
  649. ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
  650. if (ret == -EINPROGRESS)
  651. return NULL;
  652. }
  653. if (!bf->bf_mpdu)
  654. return bf;
  655. /*
  656. * Synchronize the DMA transfer with CPU before
  657. * 1. accessing the frame
  658. * 2. requeueing the same buffer to h/w
  659. */
  660. dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
  661. common->rx_bufsize,
  662. DMA_FROM_DEVICE);
  663. return bf;
  664. }
  665. /* Assumes you've already done the endian to CPU conversion */
  666. static bool ath9k_rx_accept(struct ath_common *common,
  667. struct ieee80211_hdr *hdr,
  668. struct ieee80211_rx_status *rxs,
  669. struct ath_rx_status *rx_stats,
  670. bool *decrypt_error)
  671. {
  672. struct ath_softc *sc = (struct ath_softc *) common->priv;
  673. bool is_mc, is_valid_tkip, strip_mic, mic_error;
  674. struct ath_hw *ah = common->ah;
  675. __le16 fc;
  676. u8 rx_status_len = ah->caps.rx_status_len;
  677. fc = hdr->frame_control;
  678. is_mc = !!is_multicast_ether_addr(hdr->addr1);
  679. is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
  680. test_bit(rx_stats->rs_keyix, common->tkip_keymap);
  681. strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
  682. !(rx_stats->rs_status &
  683. (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
  684. ATH9K_RXERR_KEYMISS));
  685. if (!rx_stats->rs_datalen)
  686. return false;
  687. /*
  688. * rs_status follows rs_datalen so if rs_datalen is too large
  689. * we can take a hint that hardware corrupted it, so ignore
  690. * those frames.
  691. */
  692. if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
  693. return false;
  694. /* Only use error bits from the last fragment */
  695. if (rx_stats->rs_more)
  696. return true;
  697. mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
  698. !ieee80211_has_morefrags(fc) &&
  699. !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
  700. (rx_stats->rs_status & ATH9K_RXERR_MIC);
  701. /*
  702. * The rx_stats->rs_status will not be set until the end of the
  703. * chained descriptors so it can be ignored if rs_more is set. The
  704. * rs_more will be false at the last element of the chained
  705. * descriptors.
  706. */
  707. if (rx_stats->rs_status != 0) {
  708. u8 status_mask;
  709. if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
  710. rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
  711. mic_error = false;
  712. }
  713. if (rx_stats->rs_status & ATH9K_RXERR_PHY)
  714. return false;
  715. if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
  716. (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
  717. *decrypt_error = true;
  718. mic_error = false;
  719. }
  720. /*
  721. * Reject error frames with the exception of
  722. * decryption and MIC failures. For monitor mode,
  723. * we also ignore the CRC error.
  724. */
  725. status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
  726. ATH9K_RXERR_KEYMISS;
  727. if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
  728. status_mask |= ATH9K_RXERR_CRC;
  729. if (rx_stats->rs_status & ~status_mask)
  730. return false;
  731. }
  732. /*
  733. * For unicast frames the MIC error bit can have false positives,
  734. * so all MIC error reports need to be validated in software.
  735. * False negatives are not common, so skip software verification
  736. * if the hardware considers the MIC valid.
  737. */
  738. if (strip_mic)
  739. rxs->flag |= RX_FLAG_MMIC_STRIPPED;
  740. else if (is_mc && mic_error)
  741. rxs->flag |= RX_FLAG_MMIC_ERROR;
  742. return true;
  743. }
  744. static int ath9k_process_rate(struct ath_common *common,
  745. struct ieee80211_hw *hw,
  746. struct ath_rx_status *rx_stats,
  747. struct ieee80211_rx_status *rxs)
  748. {
  749. struct ieee80211_supported_band *sband;
  750. enum ieee80211_band band;
  751. unsigned int i = 0;
  752. band = hw->conf.channel->band;
  753. sband = hw->wiphy->bands[band];
  754. if (rx_stats->rs_rate & 0x80) {
  755. /* HT rate */
  756. rxs->flag |= RX_FLAG_HT;
  757. if (rx_stats->rs_flags & ATH9K_RX_2040)
  758. rxs->flag |= RX_FLAG_40MHZ;
  759. if (rx_stats->rs_flags & ATH9K_RX_GI)
  760. rxs->flag |= RX_FLAG_SHORT_GI;
  761. rxs->rate_idx = rx_stats->rs_rate & 0x7f;
  762. return 0;
  763. }
  764. for (i = 0; i < sband->n_bitrates; i++) {
  765. if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
  766. rxs->rate_idx = i;
  767. return 0;
  768. }
  769. if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
  770. rxs->flag |= RX_FLAG_SHORTPRE;
  771. rxs->rate_idx = i;
  772. return 0;
  773. }
  774. }
  775. /*
  776. * No valid hardware bitrate found -- we should not get here
  777. * because hardware has already validated this frame as OK.
  778. */
  779. ath_dbg(common, ATH_DBG_ANY,
  780. "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
  781. rx_stats->rs_rate);
  782. return -EINVAL;
  783. }
  784. static void ath9k_process_rssi(struct ath_common *common,
  785. struct ieee80211_hw *hw,
  786. struct ieee80211_hdr *hdr,
  787. struct ath_rx_status *rx_stats)
  788. {
  789. struct ath_softc *sc = hw->priv;
  790. struct ath_hw *ah = common->ah;
  791. int last_rssi;
  792. if (!rx_stats->is_mybeacon ||
  793. ((ah->opmode != NL80211_IFTYPE_STATION) &&
  794. (ah->opmode != NL80211_IFTYPE_ADHOC)))
  795. return;
  796. if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
  797. ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
  798. last_rssi = sc->last_rssi;
  799. if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
  800. rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
  801. ATH_RSSI_EP_MULTIPLIER);
  802. if (rx_stats->rs_rssi < 0)
  803. rx_stats->rs_rssi = 0;
  804. /* Update Beacon RSSI, this is used by ANI. */
  805. ah->stats.avgbrssi = rx_stats->rs_rssi;
  806. }
  807. /*
  808. * For Decrypt or Demic errors, we only mark packet status here and always push
  809. * up the frame up to let mac80211 handle the actual error case, be it no
  810. * decryption key or real decryption error. This let us keep statistics there.
  811. */
  812. static int ath9k_rx_skb_preprocess(struct ath_common *common,
  813. struct ieee80211_hw *hw,
  814. struct ieee80211_hdr *hdr,
  815. struct ath_rx_status *rx_stats,
  816. struct ieee80211_rx_status *rx_status,
  817. bool *decrypt_error)
  818. {
  819. struct ath_hw *ah = common->ah;
  820. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  821. /*
  822. * everything but the rate is checked here, the rate check is done
  823. * separately to avoid doing two lookups for a rate for each frame.
  824. */
  825. if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
  826. return -EINVAL;
  827. /* Only use status info from the last fragment */
  828. if (rx_stats->rs_more)
  829. return 0;
  830. ath9k_process_rssi(common, hw, hdr, rx_stats);
  831. if (ath9k_process_rate(common, hw, rx_stats, rx_status))
  832. return -EINVAL;
  833. rx_status->band = hw->conf.channel->band;
  834. rx_status->freq = hw->conf.channel->center_freq;
  835. rx_status->signal = ah->noise + rx_stats->rs_rssi;
  836. rx_status->antenna = rx_stats->rs_antenna;
  837. rx_status->flag |= RX_FLAG_MACTIME_MPDU;
  838. return 0;
  839. }
  840. static void ath9k_rx_skb_postprocess(struct ath_common *common,
  841. struct sk_buff *skb,
  842. struct ath_rx_status *rx_stats,
  843. struct ieee80211_rx_status *rxs,
  844. bool decrypt_error)
  845. {
  846. struct ath_hw *ah = common->ah;
  847. struct ieee80211_hdr *hdr;
  848. int hdrlen, padpos, padsize;
  849. u8 keyix;
  850. __le16 fc;
  851. /* see if any padding is done by the hw and remove it */
  852. hdr = (struct ieee80211_hdr *) skb->data;
  853. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  854. fc = hdr->frame_control;
  855. padpos = ath9k_cmn_padpos(hdr->frame_control);
  856. /* The MAC header is padded to have 32-bit boundary if the
  857. * packet payload is non-zero. The general calculation for
  858. * padsize would take into account odd header lengths:
  859. * padsize = (4 - padpos % 4) % 4; However, since only
  860. * even-length headers are used, padding can only be 0 or 2
  861. * bytes and we can optimize this a bit. In addition, we must
  862. * not try to remove padding from short control frames that do
  863. * not have payload. */
  864. padsize = padpos & 3;
  865. if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
  866. memmove(skb->data + padsize, skb->data, padpos);
  867. skb_pull(skb, padsize);
  868. }
  869. keyix = rx_stats->rs_keyix;
  870. if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
  871. ieee80211_has_protected(fc)) {
  872. rxs->flag |= RX_FLAG_DECRYPTED;
  873. } else if (ieee80211_has_protected(fc)
  874. && !decrypt_error && skb->len >= hdrlen + 4) {
  875. keyix = skb->data[hdrlen + 3] >> 6;
  876. if (test_bit(keyix, common->keymap))
  877. rxs->flag |= RX_FLAG_DECRYPTED;
  878. }
  879. if (ah->sw_mgmt_crypto &&
  880. (rxs->flag & RX_FLAG_DECRYPTED) &&
  881. ieee80211_is_mgmt(fc))
  882. /* Use software decrypt for management frames. */
  883. rxs->flag &= ~RX_FLAG_DECRYPTED;
  884. }
  885. static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
  886. struct ath_hw_antcomb_conf ant_conf,
  887. int main_rssi_avg)
  888. {
  889. antcomb->quick_scan_cnt = 0;
  890. if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
  891. antcomb->rssi_lna2 = main_rssi_avg;
  892. else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
  893. antcomb->rssi_lna1 = main_rssi_avg;
  894. switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
  895. case 0x10: /* LNA2 A-B */
  896. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  897. antcomb->first_quick_scan_conf =
  898. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  899. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
  900. break;
  901. case 0x20: /* LNA1 A-B */
  902. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  903. antcomb->first_quick_scan_conf =
  904. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  905. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
  906. break;
  907. case 0x21: /* LNA1 LNA2 */
  908. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
  909. antcomb->first_quick_scan_conf =
  910. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  911. antcomb->second_quick_scan_conf =
  912. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  913. break;
  914. case 0x12: /* LNA2 LNA1 */
  915. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
  916. antcomb->first_quick_scan_conf =
  917. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  918. antcomb->second_quick_scan_conf =
  919. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  920. break;
  921. case 0x13: /* LNA2 A+B */
  922. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  923. antcomb->first_quick_scan_conf =
  924. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  925. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
  926. break;
  927. case 0x23: /* LNA1 A+B */
  928. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  929. antcomb->first_quick_scan_conf =
  930. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  931. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
  932. break;
  933. default:
  934. break;
  935. }
  936. }
  937. static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
  938. struct ath_hw_antcomb_conf *div_ant_conf,
  939. int main_rssi_avg, int alt_rssi_avg,
  940. int alt_ratio)
  941. {
  942. /* alt_good */
  943. switch (antcomb->quick_scan_cnt) {
  944. case 0:
  945. /* set alt to main, and alt to first conf */
  946. div_ant_conf->main_lna_conf = antcomb->main_conf;
  947. div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
  948. break;
  949. case 1:
  950. /* set alt to main, and alt to first conf */
  951. div_ant_conf->main_lna_conf = antcomb->main_conf;
  952. div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
  953. antcomb->rssi_first = main_rssi_avg;
  954. antcomb->rssi_second = alt_rssi_avg;
  955. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
  956. /* main is LNA1 */
  957. if (ath_is_alt_ant_ratio_better(alt_ratio,
  958. ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
  959. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  960. main_rssi_avg, alt_rssi_avg,
  961. antcomb->total_pkt_count))
  962. antcomb->first_ratio = true;
  963. else
  964. antcomb->first_ratio = false;
  965. } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
  966. if (ath_is_alt_ant_ratio_better(alt_ratio,
  967. ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
  968. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  969. main_rssi_avg, alt_rssi_avg,
  970. antcomb->total_pkt_count))
  971. antcomb->first_ratio = true;
  972. else
  973. antcomb->first_ratio = false;
  974. } else {
  975. if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  976. (alt_rssi_avg > main_rssi_avg +
  977. ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
  978. (alt_rssi_avg > main_rssi_avg)) &&
  979. (antcomb->total_pkt_count > 50))
  980. antcomb->first_ratio = true;
  981. else
  982. antcomb->first_ratio = false;
  983. }
  984. break;
  985. case 2:
  986. antcomb->alt_good = false;
  987. antcomb->scan_not_start = false;
  988. antcomb->scan = false;
  989. antcomb->rssi_first = main_rssi_avg;
  990. antcomb->rssi_third = alt_rssi_avg;
  991. if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
  992. antcomb->rssi_lna1 = alt_rssi_avg;
  993. else if (antcomb->second_quick_scan_conf ==
  994. ATH_ANT_DIV_COMB_LNA2)
  995. antcomb->rssi_lna2 = alt_rssi_avg;
  996. else if (antcomb->second_quick_scan_conf ==
  997. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
  998. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
  999. antcomb->rssi_lna2 = main_rssi_avg;
  1000. else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
  1001. antcomb->rssi_lna1 = main_rssi_avg;
  1002. }
  1003. if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
  1004. ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
  1005. div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
  1006. else
  1007. div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
  1008. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
  1009. if (ath_is_alt_ant_ratio_better(alt_ratio,
  1010. ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
  1011. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  1012. main_rssi_avg, alt_rssi_avg,
  1013. antcomb->total_pkt_count))
  1014. antcomb->second_ratio = true;
  1015. else
  1016. antcomb->second_ratio = false;
  1017. } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
  1018. if (ath_is_alt_ant_ratio_better(alt_ratio,
  1019. ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
  1020. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  1021. main_rssi_avg, alt_rssi_avg,
  1022. antcomb->total_pkt_count))
  1023. antcomb->second_ratio = true;
  1024. else
  1025. antcomb->second_ratio = false;
  1026. } else {
  1027. if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  1028. (alt_rssi_avg > main_rssi_avg +
  1029. ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
  1030. (alt_rssi_avg > main_rssi_avg)) &&
  1031. (antcomb->total_pkt_count > 50))
  1032. antcomb->second_ratio = true;
  1033. else
  1034. antcomb->second_ratio = false;
  1035. }
  1036. /* set alt to the conf with maximun ratio */
  1037. if (antcomb->first_ratio && antcomb->second_ratio) {
  1038. if (antcomb->rssi_second > antcomb->rssi_third) {
  1039. /* first alt*/
  1040. if ((antcomb->first_quick_scan_conf ==
  1041. ATH_ANT_DIV_COMB_LNA1) ||
  1042. (antcomb->first_quick_scan_conf ==
  1043. ATH_ANT_DIV_COMB_LNA2))
  1044. /* Set alt LNA1 or LNA2*/
  1045. if (div_ant_conf->main_lna_conf ==
  1046. ATH_ANT_DIV_COMB_LNA2)
  1047. div_ant_conf->alt_lna_conf =
  1048. ATH_ANT_DIV_COMB_LNA1;
  1049. else
  1050. div_ant_conf->alt_lna_conf =
  1051. ATH_ANT_DIV_COMB_LNA2;
  1052. else
  1053. /* Set alt to A+B or A-B */
  1054. div_ant_conf->alt_lna_conf =
  1055. antcomb->first_quick_scan_conf;
  1056. } else if ((antcomb->second_quick_scan_conf ==
  1057. ATH_ANT_DIV_COMB_LNA1) ||
  1058. (antcomb->second_quick_scan_conf ==
  1059. ATH_ANT_DIV_COMB_LNA2)) {
  1060. /* Set alt LNA1 or LNA2 */
  1061. if (div_ant_conf->main_lna_conf ==
  1062. ATH_ANT_DIV_COMB_LNA2)
  1063. div_ant_conf->alt_lna_conf =
  1064. ATH_ANT_DIV_COMB_LNA1;
  1065. else
  1066. div_ant_conf->alt_lna_conf =
  1067. ATH_ANT_DIV_COMB_LNA2;
  1068. } else {
  1069. /* Set alt to A+B or A-B */
  1070. div_ant_conf->alt_lna_conf =
  1071. antcomb->second_quick_scan_conf;
  1072. }
  1073. } else if (antcomb->first_ratio) {
  1074. /* first alt */
  1075. if ((antcomb->first_quick_scan_conf ==
  1076. ATH_ANT_DIV_COMB_LNA1) ||
  1077. (antcomb->first_quick_scan_conf ==
  1078. ATH_ANT_DIV_COMB_LNA2))
  1079. /* Set alt LNA1 or LNA2 */
  1080. if (div_ant_conf->main_lna_conf ==
  1081. ATH_ANT_DIV_COMB_LNA2)
  1082. div_ant_conf->alt_lna_conf =
  1083. ATH_ANT_DIV_COMB_LNA1;
  1084. else
  1085. div_ant_conf->alt_lna_conf =
  1086. ATH_ANT_DIV_COMB_LNA2;
  1087. else
  1088. /* Set alt to A+B or A-B */
  1089. div_ant_conf->alt_lna_conf =
  1090. antcomb->first_quick_scan_conf;
  1091. } else if (antcomb->second_ratio) {
  1092. /* second alt */
  1093. if ((antcomb->second_quick_scan_conf ==
  1094. ATH_ANT_DIV_COMB_LNA1) ||
  1095. (antcomb->second_quick_scan_conf ==
  1096. ATH_ANT_DIV_COMB_LNA2))
  1097. /* Set alt LNA1 or LNA2 */
  1098. if (div_ant_conf->main_lna_conf ==
  1099. ATH_ANT_DIV_COMB_LNA2)
  1100. div_ant_conf->alt_lna_conf =
  1101. ATH_ANT_DIV_COMB_LNA1;
  1102. else
  1103. div_ant_conf->alt_lna_conf =
  1104. ATH_ANT_DIV_COMB_LNA2;
  1105. else
  1106. /* Set alt to A+B or A-B */
  1107. div_ant_conf->alt_lna_conf =
  1108. antcomb->second_quick_scan_conf;
  1109. } else {
  1110. /* main is largest */
  1111. if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
  1112. (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
  1113. /* Set alt LNA1 or LNA2 */
  1114. if (div_ant_conf->main_lna_conf ==
  1115. ATH_ANT_DIV_COMB_LNA2)
  1116. div_ant_conf->alt_lna_conf =
  1117. ATH_ANT_DIV_COMB_LNA1;
  1118. else
  1119. div_ant_conf->alt_lna_conf =
  1120. ATH_ANT_DIV_COMB_LNA2;
  1121. else
  1122. /* Set alt to A+B or A-B */
  1123. div_ant_conf->alt_lna_conf = antcomb->main_conf;
  1124. }
  1125. break;
  1126. default:
  1127. break;
  1128. }
  1129. }
  1130. static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
  1131. struct ath_ant_comb *antcomb, int alt_ratio)
  1132. {
  1133. if (ant_conf->div_group == 0) {
  1134. /* Adjust the fast_div_bias based on main and alt lna conf */
  1135. switch ((ant_conf->main_lna_conf << 4) |
  1136. ant_conf->alt_lna_conf) {
  1137. case 0x01: /* A-B LNA2 */
  1138. ant_conf->fast_div_bias = 0x3b;
  1139. break;
  1140. case 0x02: /* A-B LNA1 */
  1141. ant_conf->fast_div_bias = 0x3d;
  1142. break;
  1143. case 0x03: /* A-B A+B */
  1144. ant_conf->fast_div_bias = 0x1;
  1145. break;
  1146. case 0x10: /* LNA2 A-B */
  1147. ant_conf->fast_div_bias = 0x7;
  1148. break;
  1149. case 0x12: /* LNA2 LNA1 */
  1150. ant_conf->fast_div_bias = 0x2;
  1151. break;
  1152. case 0x13: /* LNA2 A+B */
  1153. ant_conf->fast_div_bias = 0x7;
  1154. break;
  1155. case 0x20: /* LNA1 A-B */
  1156. ant_conf->fast_div_bias = 0x6;
  1157. break;
  1158. case 0x21: /* LNA1 LNA2 */
  1159. ant_conf->fast_div_bias = 0x0;
  1160. break;
  1161. case 0x23: /* LNA1 A+B */
  1162. ant_conf->fast_div_bias = 0x6;
  1163. break;
  1164. case 0x30: /* A+B A-B */
  1165. ant_conf->fast_div_bias = 0x1;
  1166. break;
  1167. case 0x31: /* A+B LNA2 */
  1168. ant_conf->fast_div_bias = 0x3b;
  1169. break;
  1170. case 0x32: /* A+B LNA1 */
  1171. ant_conf->fast_div_bias = 0x3d;
  1172. break;
  1173. default:
  1174. break;
  1175. }
  1176. } else if (ant_conf->div_group == 1) {
  1177. /* Adjust the fast_div_bias based on main and alt_lna_conf */
  1178. switch ((ant_conf->main_lna_conf << 4) |
  1179. ant_conf->alt_lna_conf) {
  1180. case 0x01: /* A-B LNA2 */
  1181. ant_conf->fast_div_bias = 0x1;
  1182. ant_conf->main_gaintb = 0;
  1183. ant_conf->alt_gaintb = 0;
  1184. break;
  1185. case 0x02: /* A-B LNA1 */
  1186. ant_conf->fast_div_bias = 0x1;
  1187. ant_conf->main_gaintb = 0;
  1188. ant_conf->alt_gaintb = 0;
  1189. break;
  1190. case 0x03: /* A-B A+B */
  1191. ant_conf->fast_div_bias = 0x1;
  1192. ant_conf->main_gaintb = 0;
  1193. ant_conf->alt_gaintb = 0;
  1194. break;
  1195. case 0x10: /* LNA2 A-B */
  1196. if (!(antcomb->scan) &&
  1197. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1198. ant_conf->fast_div_bias = 0x3f;
  1199. else
  1200. ant_conf->fast_div_bias = 0x1;
  1201. ant_conf->main_gaintb = 0;
  1202. ant_conf->alt_gaintb = 0;
  1203. break;
  1204. case 0x12: /* LNA2 LNA1 */
  1205. ant_conf->fast_div_bias = 0x1;
  1206. ant_conf->main_gaintb = 0;
  1207. ant_conf->alt_gaintb = 0;
  1208. break;
  1209. case 0x13: /* LNA2 A+B */
  1210. if (!(antcomb->scan) &&
  1211. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1212. ant_conf->fast_div_bias = 0x3f;
  1213. else
  1214. ant_conf->fast_div_bias = 0x1;
  1215. ant_conf->main_gaintb = 0;
  1216. ant_conf->alt_gaintb = 0;
  1217. break;
  1218. case 0x20: /* LNA1 A-B */
  1219. if (!(antcomb->scan) &&
  1220. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1221. ant_conf->fast_div_bias = 0x3f;
  1222. else
  1223. ant_conf->fast_div_bias = 0x1;
  1224. ant_conf->main_gaintb = 0;
  1225. ant_conf->alt_gaintb = 0;
  1226. break;
  1227. case 0x21: /* LNA1 LNA2 */
  1228. ant_conf->fast_div_bias = 0x1;
  1229. ant_conf->main_gaintb = 0;
  1230. ant_conf->alt_gaintb = 0;
  1231. break;
  1232. case 0x23: /* LNA1 A+B */
  1233. if (!(antcomb->scan) &&
  1234. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1235. ant_conf->fast_div_bias = 0x3f;
  1236. else
  1237. ant_conf->fast_div_bias = 0x1;
  1238. ant_conf->main_gaintb = 0;
  1239. ant_conf->alt_gaintb = 0;
  1240. break;
  1241. case 0x30: /* A+B A-B */
  1242. ant_conf->fast_div_bias = 0x1;
  1243. ant_conf->main_gaintb = 0;
  1244. ant_conf->alt_gaintb = 0;
  1245. break;
  1246. case 0x31: /* A+B LNA2 */
  1247. ant_conf->fast_div_bias = 0x1;
  1248. ant_conf->main_gaintb = 0;
  1249. ant_conf->alt_gaintb = 0;
  1250. break;
  1251. case 0x32: /* A+B LNA1 */
  1252. ant_conf->fast_div_bias = 0x1;
  1253. ant_conf->main_gaintb = 0;
  1254. ant_conf->alt_gaintb = 0;
  1255. break;
  1256. default:
  1257. break;
  1258. }
  1259. } else if (ant_conf->div_group == 2) {
  1260. /* Adjust the fast_div_bias based on main and alt_lna_conf */
  1261. switch ((ant_conf->main_lna_conf << 4) |
  1262. ant_conf->alt_lna_conf) {
  1263. case 0x01: /* A-B LNA2 */
  1264. ant_conf->fast_div_bias = 0x1;
  1265. ant_conf->main_gaintb = 0;
  1266. ant_conf->alt_gaintb = 0;
  1267. break;
  1268. case 0x02: /* A-B LNA1 */
  1269. ant_conf->fast_div_bias = 0x1;
  1270. ant_conf->main_gaintb = 0;
  1271. ant_conf->alt_gaintb = 0;
  1272. break;
  1273. case 0x03: /* A-B A+B */
  1274. ant_conf->fast_div_bias = 0x1;
  1275. ant_conf->main_gaintb = 0;
  1276. ant_conf->alt_gaintb = 0;
  1277. break;
  1278. case 0x10: /* LNA2 A-B */
  1279. if (!(antcomb->scan) &&
  1280. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1281. ant_conf->fast_div_bias = 0x1;
  1282. else
  1283. ant_conf->fast_div_bias = 0x2;
  1284. ant_conf->main_gaintb = 0;
  1285. ant_conf->alt_gaintb = 0;
  1286. break;
  1287. case 0x12: /* LNA2 LNA1 */
  1288. ant_conf->fast_div_bias = 0x1;
  1289. ant_conf->main_gaintb = 0;
  1290. ant_conf->alt_gaintb = 0;
  1291. break;
  1292. case 0x13: /* LNA2 A+B */
  1293. if (!(antcomb->scan) &&
  1294. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1295. ant_conf->fast_div_bias = 0x1;
  1296. else
  1297. ant_conf->fast_div_bias = 0x2;
  1298. ant_conf->main_gaintb = 0;
  1299. ant_conf->alt_gaintb = 0;
  1300. break;
  1301. case 0x20: /* LNA1 A-B */
  1302. if (!(antcomb->scan) &&
  1303. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1304. ant_conf->fast_div_bias = 0x1;
  1305. else
  1306. ant_conf->fast_div_bias = 0x2;
  1307. ant_conf->main_gaintb = 0;
  1308. ant_conf->alt_gaintb = 0;
  1309. break;
  1310. case 0x21: /* LNA1 LNA2 */
  1311. ant_conf->fast_div_bias = 0x1;
  1312. ant_conf->main_gaintb = 0;
  1313. ant_conf->alt_gaintb = 0;
  1314. break;
  1315. case 0x23: /* LNA1 A+B */
  1316. if (!(antcomb->scan) &&
  1317. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1318. ant_conf->fast_div_bias = 0x1;
  1319. else
  1320. ant_conf->fast_div_bias = 0x2;
  1321. ant_conf->main_gaintb = 0;
  1322. ant_conf->alt_gaintb = 0;
  1323. break;
  1324. case 0x30: /* A+B A-B */
  1325. ant_conf->fast_div_bias = 0x1;
  1326. ant_conf->main_gaintb = 0;
  1327. ant_conf->alt_gaintb = 0;
  1328. break;
  1329. case 0x31: /* A+B LNA2 */
  1330. ant_conf->fast_div_bias = 0x1;
  1331. ant_conf->main_gaintb = 0;
  1332. ant_conf->alt_gaintb = 0;
  1333. break;
  1334. case 0x32: /* A+B LNA1 */
  1335. ant_conf->fast_div_bias = 0x1;
  1336. ant_conf->main_gaintb = 0;
  1337. ant_conf->alt_gaintb = 0;
  1338. break;
  1339. default:
  1340. break;
  1341. }
  1342. }
  1343. }
  1344. /* Antenna diversity and combining */
  1345. static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
  1346. {
  1347. struct ath_hw_antcomb_conf div_ant_conf;
  1348. struct ath_ant_comb *antcomb = &sc->ant_comb;
  1349. int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
  1350. int curr_main_set;
  1351. int main_rssi = rs->rs_rssi_ctl0;
  1352. int alt_rssi = rs->rs_rssi_ctl1;
  1353. int rx_ant_conf, main_ant_conf;
  1354. bool short_scan = false;
  1355. rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
  1356. ATH_ANT_RX_MASK;
  1357. main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
  1358. ATH_ANT_RX_MASK;
  1359. /* Record packet only when both main_rssi and alt_rssi is positive */
  1360. if (main_rssi > 0 && alt_rssi > 0) {
  1361. antcomb->total_pkt_count++;
  1362. antcomb->main_total_rssi += main_rssi;
  1363. antcomb->alt_total_rssi += alt_rssi;
  1364. if (main_ant_conf == rx_ant_conf)
  1365. antcomb->main_recv_cnt++;
  1366. else
  1367. antcomb->alt_recv_cnt++;
  1368. }
  1369. /* Short scan check */
  1370. if (antcomb->scan && antcomb->alt_good) {
  1371. if (time_after(jiffies, antcomb->scan_start_time +
  1372. msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
  1373. short_scan = true;
  1374. else
  1375. if (antcomb->total_pkt_count ==
  1376. ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
  1377. alt_ratio = ((antcomb->alt_recv_cnt * 100) /
  1378. antcomb->total_pkt_count);
  1379. if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
  1380. short_scan = true;
  1381. }
  1382. }
  1383. if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
  1384. rs->rs_moreaggr) && !short_scan)
  1385. return;
  1386. if (antcomb->total_pkt_count) {
  1387. alt_ratio = ((antcomb->alt_recv_cnt * 100) /
  1388. antcomb->total_pkt_count);
  1389. main_rssi_avg = (antcomb->main_total_rssi /
  1390. antcomb->total_pkt_count);
  1391. alt_rssi_avg = (antcomb->alt_total_rssi /
  1392. antcomb->total_pkt_count);
  1393. }
  1394. ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
  1395. curr_alt_set = div_ant_conf.alt_lna_conf;
  1396. curr_main_set = div_ant_conf.main_lna_conf;
  1397. antcomb->count++;
  1398. if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
  1399. if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
  1400. ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
  1401. main_rssi_avg);
  1402. antcomb->alt_good = true;
  1403. } else {
  1404. antcomb->alt_good = false;
  1405. }
  1406. antcomb->count = 0;
  1407. antcomb->scan = true;
  1408. antcomb->scan_not_start = true;
  1409. }
  1410. if (!antcomb->scan) {
  1411. if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
  1412. alt_ratio, curr_main_set, curr_alt_set,
  1413. alt_rssi_avg, main_rssi_avg)) {
  1414. if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
  1415. /* Switch main and alt LNA */
  1416. div_ant_conf.main_lna_conf =
  1417. ATH_ANT_DIV_COMB_LNA2;
  1418. div_ant_conf.alt_lna_conf =
  1419. ATH_ANT_DIV_COMB_LNA1;
  1420. } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
  1421. div_ant_conf.main_lna_conf =
  1422. ATH_ANT_DIV_COMB_LNA1;
  1423. div_ant_conf.alt_lna_conf =
  1424. ATH_ANT_DIV_COMB_LNA2;
  1425. }
  1426. goto div_comb_done;
  1427. } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
  1428. (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
  1429. /* Set alt to another LNA */
  1430. if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
  1431. div_ant_conf.alt_lna_conf =
  1432. ATH_ANT_DIV_COMB_LNA1;
  1433. else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
  1434. div_ant_conf.alt_lna_conf =
  1435. ATH_ANT_DIV_COMB_LNA2;
  1436. goto div_comb_done;
  1437. }
  1438. if ((alt_rssi_avg < (main_rssi_avg +
  1439. div_ant_conf.lna1_lna2_delta)))
  1440. goto div_comb_done;
  1441. }
  1442. if (!antcomb->scan_not_start) {
  1443. switch (curr_alt_set) {
  1444. case ATH_ANT_DIV_COMB_LNA2:
  1445. antcomb->rssi_lna2 = alt_rssi_avg;
  1446. antcomb->rssi_lna1 = main_rssi_avg;
  1447. antcomb->scan = true;
  1448. /* set to A+B */
  1449. div_ant_conf.main_lna_conf =
  1450. ATH_ANT_DIV_COMB_LNA1;
  1451. div_ant_conf.alt_lna_conf =
  1452. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1453. break;
  1454. case ATH_ANT_DIV_COMB_LNA1:
  1455. antcomb->rssi_lna1 = alt_rssi_avg;
  1456. antcomb->rssi_lna2 = main_rssi_avg;
  1457. antcomb->scan = true;
  1458. /* set to A+B */
  1459. div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
  1460. div_ant_conf.alt_lna_conf =
  1461. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1462. break;
  1463. case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
  1464. antcomb->rssi_add = alt_rssi_avg;
  1465. antcomb->scan = true;
  1466. /* set to A-B */
  1467. div_ant_conf.alt_lna_conf =
  1468. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1469. break;
  1470. case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
  1471. antcomb->rssi_sub = alt_rssi_avg;
  1472. antcomb->scan = false;
  1473. if (antcomb->rssi_lna2 >
  1474. (antcomb->rssi_lna1 +
  1475. ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
  1476. /* use LNA2 as main LNA */
  1477. if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
  1478. (antcomb->rssi_add > antcomb->rssi_sub)) {
  1479. /* set to A+B */
  1480. div_ant_conf.main_lna_conf =
  1481. ATH_ANT_DIV_COMB_LNA2;
  1482. div_ant_conf.alt_lna_conf =
  1483. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1484. } else if (antcomb->rssi_sub >
  1485. antcomb->rssi_lna1) {
  1486. /* set to A-B */
  1487. div_ant_conf.main_lna_conf =
  1488. ATH_ANT_DIV_COMB_LNA2;
  1489. div_ant_conf.alt_lna_conf =
  1490. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1491. } else {
  1492. /* set to LNA1 */
  1493. div_ant_conf.main_lna_conf =
  1494. ATH_ANT_DIV_COMB_LNA2;
  1495. div_ant_conf.alt_lna_conf =
  1496. ATH_ANT_DIV_COMB_LNA1;
  1497. }
  1498. } else {
  1499. /* use LNA1 as main LNA */
  1500. if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
  1501. (antcomb->rssi_add > antcomb->rssi_sub)) {
  1502. /* set to A+B */
  1503. div_ant_conf.main_lna_conf =
  1504. ATH_ANT_DIV_COMB_LNA1;
  1505. div_ant_conf.alt_lna_conf =
  1506. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1507. } else if (antcomb->rssi_sub >
  1508. antcomb->rssi_lna1) {
  1509. /* set to A-B */
  1510. div_ant_conf.main_lna_conf =
  1511. ATH_ANT_DIV_COMB_LNA1;
  1512. div_ant_conf.alt_lna_conf =
  1513. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1514. } else {
  1515. /* set to LNA2 */
  1516. div_ant_conf.main_lna_conf =
  1517. ATH_ANT_DIV_COMB_LNA1;
  1518. div_ant_conf.alt_lna_conf =
  1519. ATH_ANT_DIV_COMB_LNA2;
  1520. }
  1521. }
  1522. break;
  1523. default:
  1524. break;
  1525. }
  1526. } else {
  1527. if (!antcomb->alt_good) {
  1528. antcomb->scan_not_start = false;
  1529. /* Set alt to another LNA */
  1530. if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
  1531. div_ant_conf.main_lna_conf =
  1532. ATH_ANT_DIV_COMB_LNA2;
  1533. div_ant_conf.alt_lna_conf =
  1534. ATH_ANT_DIV_COMB_LNA1;
  1535. } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
  1536. div_ant_conf.main_lna_conf =
  1537. ATH_ANT_DIV_COMB_LNA1;
  1538. div_ant_conf.alt_lna_conf =
  1539. ATH_ANT_DIV_COMB_LNA2;
  1540. }
  1541. goto div_comb_done;
  1542. }
  1543. }
  1544. ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
  1545. main_rssi_avg, alt_rssi_avg,
  1546. alt_ratio);
  1547. antcomb->quick_scan_cnt++;
  1548. div_comb_done:
  1549. ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
  1550. ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
  1551. antcomb->scan_start_time = jiffies;
  1552. antcomb->total_pkt_count = 0;
  1553. antcomb->main_total_rssi = 0;
  1554. antcomb->alt_total_rssi = 0;
  1555. antcomb->main_recv_cnt = 0;
  1556. antcomb->alt_recv_cnt = 0;
  1557. }
  1558. int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
  1559. {
  1560. struct ath_buf *bf;
  1561. struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
  1562. struct ieee80211_rx_status *rxs;
  1563. struct ath_hw *ah = sc->sc_ah;
  1564. struct ath_common *common = ath9k_hw_common(ah);
  1565. struct ieee80211_hw *hw = sc->hw;
  1566. struct ieee80211_hdr *hdr;
  1567. int retval;
  1568. bool decrypt_error = false;
  1569. struct ath_rx_status rs;
  1570. enum ath9k_rx_qtype qtype;
  1571. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1572. int dma_type;
  1573. u8 rx_status_len = ah->caps.rx_status_len;
  1574. u64 tsf = 0;
  1575. u32 tsf_lower = 0;
  1576. unsigned long flags;
  1577. if (edma)
  1578. dma_type = DMA_BIDIRECTIONAL;
  1579. else
  1580. dma_type = DMA_FROM_DEVICE;
  1581. qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
  1582. spin_lock_bh(&sc->rx.rxbuflock);
  1583. tsf = ath9k_hw_gettsf64(ah);
  1584. tsf_lower = tsf & 0xffffffff;
  1585. do {
  1586. /* If handling rx interrupt and flush is in progress => exit */
  1587. if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
  1588. break;
  1589. memset(&rs, 0, sizeof(rs));
  1590. if (edma)
  1591. bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
  1592. else
  1593. bf = ath_get_next_rx_buf(sc, &rs);
  1594. if (!bf)
  1595. break;
  1596. skb = bf->bf_mpdu;
  1597. if (!skb)
  1598. continue;
  1599. /*
  1600. * Take frame header from the first fragment and RX status from
  1601. * the last one.
  1602. */
  1603. if (sc->rx.frag)
  1604. hdr_skb = sc->rx.frag;
  1605. else
  1606. hdr_skb = skb;
  1607. hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
  1608. rxs = IEEE80211_SKB_RXCB(hdr_skb);
  1609. if (ieee80211_is_beacon(hdr->frame_control) &&
  1610. !is_zero_ether_addr(common->curbssid) &&
  1611. !compare_ether_addr(hdr->addr3, common->curbssid))
  1612. rs.is_mybeacon = true;
  1613. else
  1614. rs.is_mybeacon = false;
  1615. ath_debug_stat_rx(sc, &rs);
  1616. /*
  1617. * If we're asked to flush receive queue, directly
  1618. * chain it back at the queue without processing it.
  1619. */
  1620. if (sc->sc_flags & SC_OP_RXFLUSH)
  1621. goto requeue_drop_frag;
  1622. rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
  1623. if (rs.rs_tstamp > tsf_lower &&
  1624. unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
  1625. rxs->mactime -= 0x100000000ULL;
  1626. if (rs.rs_tstamp < tsf_lower &&
  1627. unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
  1628. rxs->mactime += 0x100000000ULL;
  1629. retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
  1630. rxs, &decrypt_error);
  1631. if (retval)
  1632. goto requeue_drop_frag;
  1633. /* Ensure we always have an skb to requeue once we are done
  1634. * processing the current buffer's skb */
  1635. requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
  1636. /* If there is no memory we ignore the current RX'd frame,
  1637. * tell hardware it can give us a new frame using the old
  1638. * skb and put it at the tail of the sc->rx.rxbuf list for
  1639. * processing. */
  1640. if (!requeue_skb)
  1641. goto requeue_drop_frag;
  1642. /* Unmap the frame */
  1643. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  1644. common->rx_bufsize,
  1645. dma_type);
  1646. skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
  1647. if (ah->caps.rx_status_len)
  1648. skb_pull(skb, ah->caps.rx_status_len);
  1649. if (!rs.rs_more)
  1650. ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
  1651. rxs, decrypt_error);
  1652. /* We will now give hardware our shiny new allocated skb */
  1653. bf->bf_mpdu = requeue_skb;
  1654. bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
  1655. common->rx_bufsize,
  1656. dma_type);
  1657. if (unlikely(dma_mapping_error(sc->dev,
  1658. bf->bf_buf_addr))) {
  1659. dev_kfree_skb_any(requeue_skb);
  1660. bf->bf_mpdu = NULL;
  1661. bf->bf_buf_addr = 0;
  1662. ath_err(common, "dma_mapping_error() on RX\n");
  1663. ieee80211_rx(hw, skb);
  1664. break;
  1665. }
  1666. if (rs.rs_more) {
  1667. /*
  1668. * rs_more indicates chained descriptors which can be
  1669. * used to link buffers together for a sort of
  1670. * scatter-gather operation.
  1671. */
  1672. if (sc->rx.frag) {
  1673. /* too many fragments - cannot handle frame */
  1674. dev_kfree_skb_any(sc->rx.frag);
  1675. dev_kfree_skb_any(skb);
  1676. skb = NULL;
  1677. }
  1678. sc->rx.frag = skb;
  1679. goto requeue;
  1680. }
  1681. if (sc->rx.frag) {
  1682. int space = skb->len - skb_tailroom(hdr_skb);
  1683. sc->rx.frag = NULL;
  1684. if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
  1685. dev_kfree_skb(skb);
  1686. goto requeue_drop_frag;
  1687. }
  1688. skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
  1689. skb->len);
  1690. dev_kfree_skb_any(skb);
  1691. skb = hdr_skb;
  1692. }
  1693. if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
  1694. /*
  1695. * change the default rx antenna if rx diversity
  1696. * chooses the other antenna 3 times in a row.
  1697. */
  1698. if (sc->rx.defant != rs.rs_antenna) {
  1699. if (++sc->rx.rxotherant >= 3)
  1700. ath_setdefantenna(sc, rs.rs_antenna);
  1701. } else {
  1702. sc->rx.rxotherant = 0;
  1703. }
  1704. }
  1705. if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
  1706. skb_trim(skb, skb->len - 8);
  1707. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1708. if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
  1709. PS_WAIT_FOR_CAB |
  1710. PS_WAIT_FOR_PSPOLL_DATA)) ||
  1711. ath9k_check_auto_sleep(sc))
  1712. ath_rx_ps(sc, skb, rs.is_mybeacon);
  1713. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1714. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
  1715. ath_ant_comb_scan(sc, &rs);
  1716. ieee80211_rx(hw, skb);
  1717. requeue_drop_frag:
  1718. if (sc->rx.frag) {
  1719. dev_kfree_skb_any(sc->rx.frag);
  1720. sc->rx.frag = NULL;
  1721. }
  1722. requeue:
  1723. if (edma) {
  1724. list_add_tail(&bf->list, &sc->rx.rxbuf);
  1725. ath_rx_edma_buf_link(sc, qtype);
  1726. } else {
  1727. list_move_tail(&bf->list, &sc->rx.rxbuf);
  1728. ath_rx_buf_link(sc, bf);
  1729. if (!flush)
  1730. ath9k_hw_rxena(ah);
  1731. }
  1732. } while (1);
  1733. spin_unlock_bh(&sc->rx.rxbuflock);
  1734. if (!(ah->imask & ATH9K_INT_RXEOL)) {
  1735. ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  1736. ath9k_hw_set_interrupts(ah);
  1737. }
  1738. return 0;
  1739. }